Commit | Line | Data |
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caaff562 AN |
1 | /* |
2 | * I2C client/driver for the ST M41T80 family of i2c rtc chips. | |
3 | * | |
4 | * Author: Alexander Bigga <ab@mycable.de> | |
5 | * | |
6 | * Based on m41t00.c by Mark A. Greer <mgreer@mvista.com> | |
7 | * | |
8 | * 2006 (c) mycable GmbH | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | */ | |
15 | ||
a737e835 JP |
16 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
17 | ||
35aa64f3 | 18 | #include <linux/bcd.h> |
1373e77b | 19 | #include <linux/clk-provider.h> |
35aa64f3 | 20 | #include <linux/i2c.h> |
caaff562 | 21 | #include <linux/init.h> |
9fb1f68d | 22 | #include <linux/kernel.h> |
35aa64f3 | 23 | #include <linux/module.h> |
eb235c56 | 24 | #include <linux/of_device.h> |
35aa64f3 | 25 | #include <linux/rtc.h> |
caaff562 | 26 | #include <linux/slab.h> |
613655fa | 27 | #include <linux/mutex.h> |
caaff562 | 28 | #include <linux/string.h> |
617780d2 | 29 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
617780d2 AN |
30 | #include <linux/fs.h> |
31 | #include <linux/ioctl.h> | |
35aa64f3 MR |
32 | #include <linux/miscdevice.h> |
33 | #include <linux/reboot.h> | |
34 | #include <linux/watchdog.h> | |
617780d2 | 35 | #endif |
caaff562 | 36 | |
f2b84ee8 MJ |
37 | #define M41T80_REG_SSEC 0x00 |
38 | #define M41T80_REG_SEC 0x01 | |
39 | #define M41T80_REG_MIN 0x02 | |
40 | #define M41T80_REG_HOUR 0x03 | |
41 | #define M41T80_REG_WDAY 0x04 | |
42 | #define M41T80_REG_DAY 0x05 | |
43 | #define M41T80_REG_MON 0x06 | |
44 | #define M41T80_REG_YEAR 0x07 | |
45 | #define M41T80_REG_ALARM_MON 0x0a | |
46 | #define M41T80_REG_ALARM_DAY 0x0b | |
47 | #define M41T80_REG_ALARM_HOUR 0x0c | |
48 | #define M41T80_REG_ALARM_MIN 0x0d | |
49 | #define M41T80_REG_ALARM_SEC 0x0e | |
50 | #define M41T80_REG_FLAGS 0x0f | |
51 | #define M41T80_REG_SQW 0x13 | |
caaff562 AN |
52 | |
53 | #define M41T80_DATETIME_REG_SIZE (M41T80_REG_YEAR + 1) | |
54 | #define M41T80_ALARM_REG_SIZE \ | |
55 | (M41T80_REG_ALARM_SEC + 1 - M41T80_REG_ALARM_MON) | |
56 | ||
1373e77b GB |
57 | #define M41T80_SQW_MAX_FREQ 32768 |
58 | ||
54339f3b MJ |
59 | #define M41T80_SEC_ST BIT(7) /* ST: Stop Bit */ |
60 | #define M41T80_ALMON_AFE BIT(7) /* AFE: AF Enable Bit */ | |
61 | #define M41T80_ALMON_SQWE BIT(6) /* SQWE: SQW Enable Bit */ | |
62 | #define M41T80_ALHOUR_HT BIT(6) /* HT: Halt Update Bit */ | |
05a7f27a | 63 | #define M41T80_FLAGS_OF BIT(2) /* OF: Oscillator Failure Bit */ |
54339f3b MJ |
64 | #define M41T80_FLAGS_AF BIT(6) /* AF: Alarm Flag Bit */ |
65 | #define M41T80_FLAGS_BATT_LOW BIT(4) /* BL: Battery Low Bit */ | |
66 | #define M41T80_WATCHDOG_RB2 BIT(7) /* RB: Watchdog resolution */ | |
67 | #define M41T80_WATCHDOG_RB1 BIT(1) /* RB: Watchdog resolution */ | |
68 | #define M41T80_WATCHDOG_RB0 BIT(0) /* RB: Watchdog resolution */ | |
caaff562 | 69 | |
54339f3b MJ |
70 | #define M41T80_FEATURE_HT BIT(0) /* Halt feature */ |
71 | #define M41T80_FEATURE_BL BIT(1) /* Battery low indicator */ | |
72 | #define M41T80_FEATURE_SQ BIT(2) /* Squarewave feature */ | |
73 | #define M41T80_FEATURE_WD BIT(3) /* Extra watchdog resolution */ | |
74 | #define M41T80_FEATURE_SQ_ALT BIT(4) /* RSx bits are in reg 4 */ | |
caaff562 | 75 | |
3760f736 | 76 | static const struct i2c_device_id m41t80_id[] = { |
f30281f4 | 77 | { "m41t62", M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT }, |
d3a126fc SF |
78 | { "m41t65", M41T80_FEATURE_HT | M41T80_FEATURE_WD }, |
79 | { "m41t80", M41T80_FEATURE_SQ }, | |
80 | { "m41t81", M41T80_FEATURE_HT | M41T80_FEATURE_SQ}, | |
81 | { "m41t81s", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
82 | { "m41t82", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
83 | { "m41t83", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
84 | { "m41st84", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
85 | { "m41st85", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
86 | { "m41st87", M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ }, | |
6b1a5235 | 87 | { "rv4162", M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT }, |
3760f736 | 88 | { } |
caaff562 | 89 | }; |
3760f736 | 90 | MODULE_DEVICE_TABLE(i2c, m41t80_id); |
caaff562 | 91 | |
eb235c56 JMC |
92 | static const struct of_device_id m41t80_of_match[] = { |
93 | { | |
94 | .compatible = "st,m41t62", | |
95 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_SQ_ALT) | |
96 | }, | |
97 | { | |
98 | .compatible = "st,m41t65", | |
99 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_WD) | |
100 | }, | |
101 | { | |
102 | .compatible = "st,m41t80", | |
103 | .data = (void *)(M41T80_FEATURE_SQ) | |
104 | }, | |
105 | { | |
106 | .compatible = "st,m41t81", | |
107 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_SQ) | |
108 | }, | |
109 | { | |
110 | .compatible = "st,m41t81s", | |
111 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
112 | }, | |
113 | { | |
114 | .compatible = "st,m41t82", | |
115 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
116 | }, | |
117 | { | |
118 | .compatible = "st,m41t83", | |
119 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
120 | }, | |
121 | { | |
122 | .compatible = "st,m41t84", | |
123 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
124 | }, | |
125 | { | |
126 | .compatible = "st,m41t85", | |
127 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
128 | }, | |
129 | { | |
130 | .compatible = "st,m41t87", | |
131 | .data = (void *)(M41T80_FEATURE_HT | M41T80_FEATURE_BL | M41T80_FEATURE_SQ) | |
132 | }, | |
a897bf13 AB |
133 | { |
134 | .compatible = "microcrystal,rv4162", | |
135 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT) | |
136 | }, | |
137 | /* DT compatibility only, do not use compatibles below: */ | |
eb235c56 JMC |
138 | { |
139 | .compatible = "st,rv4162", | |
140 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT) | |
141 | }, | |
142 | { | |
143 | .compatible = "rv4162", | |
144 | .data = (void *)(M41T80_FEATURE_SQ | M41T80_FEATURE_WD | M41T80_FEATURE_SQ_ALT) | |
145 | }, | |
146 | { } | |
147 | }; | |
148 | MODULE_DEVICE_TABLE(of, m41t80_of_match); | |
149 | ||
caaff562 | 150 | struct m41t80_data { |
eb235c56 | 151 | unsigned long features; |
1373e77b | 152 | struct i2c_client *client; |
caaff562 | 153 | struct rtc_device *rtc; |
1373e77b GB |
154 | #ifdef CONFIG_COMMON_CLK |
155 | struct clk_hw sqw; | |
2cb90ed3 | 156 | unsigned long freq; |
13bb1d78 | 157 | unsigned int sqwe; |
1373e77b | 158 | #endif |
caaff562 AN |
159 | }; |
160 | ||
9c6dfed9 MJ |
161 | static irqreturn_t m41t80_handle_irq(int irq, void *dev_id) |
162 | { | |
163 | struct i2c_client *client = dev_id; | |
164 | struct m41t80_data *m41t80 = i2c_get_clientdata(client); | |
165 | struct mutex *lock = &m41t80->rtc->ops_lock; | |
166 | unsigned long events = 0; | |
167 | int flags, flags_afe; | |
168 | ||
169 | mutex_lock(lock); | |
170 | ||
171 | flags_afe = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
172 | if (flags_afe < 0) { | |
173 | mutex_unlock(lock); | |
174 | return IRQ_NONE; | |
175 | } | |
176 | ||
177 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
178 | if (flags <= 0) { | |
179 | mutex_unlock(lock); | |
180 | return IRQ_NONE; | |
181 | } | |
182 | ||
183 | if (flags & M41T80_FLAGS_AF) { | |
184 | flags &= ~M41T80_FLAGS_AF; | |
185 | flags_afe &= ~M41T80_ALMON_AFE; | |
186 | events |= RTC_AF; | |
187 | } | |
188 | ||
189 | if (events) { | |
190 | rtc_update_irq(m41t80->rtc, 1, events); | |
191 | i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, flags); | |
192 | i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
193 | flags_afe); | |
194 | } | |
195 | ||
196 | mutex_unlock(lock); | |
197 | ||
198 | return IRQ_HANDLED; | |
199 | } | |
200 | ||
e2c8e1a9 | 201 | static int m41t80_rtc_read_time(struct device *dev, struct rtc_time *tm) |
caaff562 | 202 | { |
e2c8e1a9 | 203 | struct i2c_client *client = to_i2c_client(dev); |
f2b84ee8 | 204 | unsigned char buf[8]; |
05a7f27a MJ |
205 | int err, flags; |
206 | ||
207 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
208 | if (flags < 0) | |
209 | return flags; | |
210 | ||
211 | if (flags & M41T80_FLAGS_OF) { | |
212 | dev_err(&client->dev, "Oscillator failure, data is invalid.\n"); | |
213 | return -EINVAL; | |
214 | } | |
caaff562 | 215 | |
f2b84ee8 MJ |
216 | err = i2c_smbus_read_i2c_block_data(client, M41T80_REG_SSEC, |
217 | sizeof(buf), buf); | |
218 | if (err < 0) { | |
219 | dev_err(&client->dev, "Unable to read date\n"); | |
caaff562 AN |
220 | return -EIO; |
221 | } | |
222 | ||
fe20ba70 AB |
223 | tm->tm_sec = bcd2bin(buf[M41T80_REG_SEC] & 0x7f); |
224 | tm->tm_min = bcd2bin(buf[M41T80_REG_MIN] & 0x7f); | |
225 | tm->tm_hour = bcd2bin(buf[M41T80_REG_HOUR] & 0x3f); | |
226 | tm->tm_mday = bcd2bin(buf[M41T80_REG_DAY] & 0x3f); | |
caaff562 | 227 | tm->tm_wday = buf[M41T80_REG_WDAY] & 0x07; |
fe20ba70 | 228 | tm->tm_mon = bcd2bin(buf[M41T80_REG_MON] & 0x1f) - 1; |
caaff562 AN |
229 | |
230 | /* assume 20YY not 19YY, and ignore the Century Bit */ | |
fe20ba70 | 231 | tm->tm_year = bcd2bin(buf[M41T80_REG_YEAR]) + 100; |
22652ba7 | 232 | return 0; |
caaff562 AN |
233 | } |
234 | ||
e2c8e1a9 | 235 | static int m41t80_rtc_set_time(struct device *dev, struct rtc_time *tm) |
caaff562 | 236 | { |
e2c8e1a9 | 237 | struct i2c_client *client = to_i2c_client(dev); |
0f546b05 | 238 | struct m41t80_data *clientdata = i2c_get_clientdata(client); |
f2b84ee8 | 239 | unsigned char buf[8]; |
05a7f27a | 240 | int err, flags; |
caaff562 | 241 | |
f2b84ee8 MJ |
242 | if (tm->tm_year < 100 || tm->tm_year > 199) |
243 | return -EINVAL; | |
caaff562 | 244 | |
caaff562 | 245 | buf[M41T80_REG_SSEC] = 0; |
f2b84ee8 MJ |
246 | buf[M41T80_REG_SEC] = bin2bcd(tm->tm_sec); |
247 | buf[M41T80_REG_MIN] = bin2bcd(tm->tm_min); | |
248 | buf[M41T80_REG_HOUR] = bin2bcd(tm->tm_hour); | |
249 | buf[M41T80_REG_DAY] = bin2bcd(tm->tm_mday); | |
250 | buf[M41T80_REG_MON] = bin2bcd(tm->tm_mon + 1); | |
251 | buf[M41T80_REG_YEAR] = bin2bcd(tm->tm_year - 100); | |
252 | buf[M41T80_REG_WDAY] = tm->tm_wday; | |
253 | ||
0f546b05 GB |
254 | /* If the square wave output is controlled in the weekday register */ |
255 | if (clientdata->features & M41T80_FEATURE_SQ_ALT) { | |
256 | int val; | |
257 | ||
258 | val = i2c_smbus_read_byte_data(client, M41T80_REG_WDAY); | |
259 | if (val < 0) | |
260 | return val; | |
261 | ||
262 | buf[M41T80_REG_WDAY] |= (val & 0xf0); | |
263 | } | |
264 | ||
f2b84ee8 MJ |
265 | err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_SSEC, |
266 | sizeof(buf), buf); | |
267 | if (err < 0) { | |
268 | dev_err(&client->dev, "Unable to write to date registers\n"); | |
269 | return err; | |
bcebd81d | 270 | } |
caaff562 | 271 | |
05a7f27a MJ |
272 | /* Clear the OF bit of Flags Register */ |
273 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
274 | if (flags < 0) | |
275 | return flags; | |
276 | ||
277 | if (i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, | |
278 | flags & ~M41T80_FLAGS_OF)) { | |
279 | dev_err(&client->dev, "Unable to write flags register\n"); | |
280 | return -EIO; | |
281 | } | |
282 | ||
f2b84ee8 | 283 | return err; |
caaff562 AN |
284 | } |
285 | ||
caaff562 AN |
286 | static int m41t80_rtc_proc(struct device *dev, struct seq_file *seq) |
287 | { | |
288 | struct i2c_client *client = to_i2c_client(dev); | |
289 | struct m41t80_data *clientdata = i2c_get_clientdata(client); | |
290 | u8 reg; | |
291 | ||
3760f736 | 292 | if (clientdata->features & M41T80_FEATURE_BL) { |
caaff562 AN |
293 | reg = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); |
294 | seq_printf(seq, "battery\t\t: %s\n", | |
295 | (reg & M41T80_FLAGS_BATT_LOW) ? "exhausted" : "ok"); | |
296 | } | |
297 | return 0; | |
298 | } | |
caaff562 | 299 | |
9c6dfed9 MJ |
300 | static int m41t80_alarm_irq_enable(struct device *dev, unsigned int enabled) |
301 | { | |
302 | struct i2c_client *client = to_i2c_client(dev); | |
303 | int flags, retval; | |
304 | ||
305 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
306 | if (flags < 0) | |
307 | return flags; | |
308 | ||
309 | if (enabled) | |
310 | flags |= M41T80_ALMON_AFE; | |
311 | else | |
312 | flags &= ~M41T80_ALMON_AFE; | |
313 | ||
314 | retval = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, flags); | |
315 | if (retval < 0) { | |
e89487fe | 316 | dev_err(dev, "Unable to enable alarm IRQ %d\n", retval); |
9c6dfed9 MJ |
317 | return retval; |
318 | } | |
319 | return 0; | |
320 | } | |
321 | ||
322 | static int m41t80_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
323 | { | |
324 | struct i2c_client *client = to_i2c_client(dev); | |
325 | u8 alarmvals[5]; | |
326 | int ret, err; | |
327 | ||
328 | alarmvals[0] = bin2bcd(alrm->time.tm_mon + 1); | |
329 | alarmvals[1] = bin2bcd(alrm->time.tm_mday); | |
330 | alarmvals[2] = bin2bcd(alrm->time.tm_hour); | |
331 | alarmvals[3] = bin2bcd(alrm->time.tm_min); | |
332 | alarmvals[4] = bin2bcd(alrm->time.tm_sec); | |
333 | ||
334 | /* Clear AF and AFE flags */ | |
335 | ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
336 | if (ret < 0) | |
337 | return ret; | |
338 | err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
339 | ret & ~(M41T80_ALMON_AFE)); | |
340 | if (err < 0) { | |
341 | dev_err(dev, "Unable to clear AFE bit\n"); | |
342 | return err; | |
343 | } | |
344 | ||
2de9261c GB |
345 | /* Keep SQWE bit value */ |
346 | alarmvals[0] |= (ret & M41T80_ALMON_SQWE); | |
347 | ||
9c6dfed9 MJ |
348 | ret = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); |
349 | if (ret < 0) | |
350 | return ret; | |
351 | ||
352 | err = i2c_smbus_write_byte_data(client, M41T80_REG_FLAGS, | |
353 | ret & ~(M41T80_FLAGS_AF)); | |
354 | if (err < 0) { | |
355 | dev_err(dev, "Unable to clear AF bit\n"); | |
356 | return err; | |
357 | } | |
358 | ||
359 | /* Write the alarm */ | |
360 | err = i2c_smbus_write_i2c_block_data(client, M41T80_REG_ALARM_MON, | |
361 | 5, alarmvals); | |
362 | if (err) | |
363 | return err; | |
364 | ||
365 | /* Enable the alarm interrupt */ | |
366 | if (alrm->enabled) { | |
367 | alarmvals[0] |= M41T80_ALMON_AFE; | |
368 | err = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
369 | alarmvals[0]); | |
370 | if (err) | |
371 | return err; | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static int m41t80_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
378 | { | |
379 | struct i2c_client *client = to_i2c_client(dev); | |
380 | u8 alarmvals[5]; | |
381 | int flags, ret; | |
382 | ||
383 | ret = i2c_smbus_read_i2c_block_data(client, M41T80_REG_ALARM_MON, | |
384 | 5, alarmvals); | |
385 | if (ret != 5) | |
386 | return ret < 0 ? ret : -EIO; | |
387 | ||
388 | flags = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); | |
389 | if (flags < 0) | |
390 | return flags; | |
391 | ||
392 | alrm->time.tm_sec = bcd2bin(alarmvals[4] & 0x7f); | |
393 | alrm->time.tm_min = bcd2bin(alarmvals[3] & 0x7f); | |
394 | alrm->time.tm_hour = bcd2bin(alarmvals[2] & 0x3f); | |
9c6dfed9 MJ |
395 | alrm->time.tm_mday = bcd2bin(alarmvals[1] & 0x3f); |
396 | alrm->time.tm_mon = bcd2bin(alarmvals[0] & 0x3f); | |
9c6dfed9 MJ |
397 | |
398 | alrm->enabled = !!(alarmvals[0] & M41T80_ALMON_AFE); | |
399 | alrm->pending = (flags & M41T80_FLAGS_AF) && alrm->enabled; | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
caaff562 AN |
404 | static struct rtc_class_ops m41t80_rtc_ops = { |
405 | .read_time = m41t80_rtc_read_time, | |
406 | .set_time = m41t80_rtc_set_time, | |
caaff562 | 407 | .proc = m41t80_rtc_proc, |
caaff562 AN |
408 | }; |
409 | ||
ae036af8 SC |
410 | #ifdef CONFIG_PM_SLEEP |
411 | static int m41t80_suspend(struct device *dev) | |
412 | { | |
413 | struct i2c_client *client = to_i2c_client(dev); | |
414 | ||
415 | if (client->irq >= 0 && device_may_wakeup(dev)) | |
416 | enable_irq_wake(client->irq); | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | static int m41t80_resume(struct device *dev) | |
422 | { | |
423 | struct i2c_client *client = to_i2c_client(dev); | |
424 | ||
425 | if (client->irq >= 0 && device_may_wakeup(dev)) | |
426 | disable_irq_wake(client->irq); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | #endif | |
431 | ||
432 | static SIMPLE_DEV_PM_OPS(m41t80_pm, m41t80_suspend, m41t80_resume); | |
433 | ||
1373e77b GB |
434 | #ifdef CONFIG_COMMON_CLK |
435 | #define sqw_to_m41t80_data(_hw) container_of(_hw, struct m41t80_data, sqw) | |
436 | ||
2cb90ed3 TK |
437 | static unsigned long m41t80_decode_freq(int setting) |
438 | { | |
439 | return (setting == 0) ? 0 : (setting == 1) ? M41T80_SQW_MAX_FREQ : | |
440 | M41T80_SQW_MAX_FREQ >> setting; | |
441 | } | |
442 | ||
443 | static unsigned long m41t80_get_freq(struct m41t80_data *m41t80) | |
1373e77b | 444 | { |
1373e77b GB |
445 | struct i2c_client *client = m41t80->client; |
446 | int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ? | |
447 | M41T80_REG_WDAY : M41T80_REG_SQW; | |
448 | int ret = i2c_smbus_read_byte_data(client, reg_sqw); | |
1373e77b GB |
449 | |
450 | if (ret < 0) | |
451 | return 0; | |
2cb90ed3 TK |
452 | return m41t80_decode_freq(ret >> 4); |
453 | } | |
1373e77b | 454 | |
2cb90ed3 TK |
455 | static unsigned long m41t80_sqw_recalc_rate(struct clk_hw *hw, |
456 | unsigned long parent_rate) | |
457 | { | |
458 | return sqw_to_m41t80_data(hw)->freq; | |
1373e77b GB |
459 | } |
460 | ||
461 | static long m41t80_sqw_round_rate(struct clk_hw *hw, unsigned long rate, | |
462 | unsigned long *prate) | |
463 | { | |
c8384bb0 TK |
464 | if (rate >= M41T80_SQW_MAX_FREQ) |
465 | return M41T80_SQW_MAX_FREQ; | |
466 | if (rate >= M41T80_SQW_MAX_FREQ / 4) | |
467 | return M41T80_SQW_MAX_FREQ / 4; | |
468 | if (!rate) | |
469 | return 0; | |
470 | return 1 << ilog2(rate); | |
1373e77b GB |
471 | } |
472 | ||
473 | static int m41t80_sqw_set_rate(struct clk_hw *hw, unsigned long rate, | |
474 | unsigned long parent_rate) | |
475 | { | |
476 | struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw); | |
477 | struct i2c_client *client = m41t80->client; | |
478 | int reg_sqw = (m41t80->features & M41T80_FEATURE_SQ_ALT) ? | |
479 | M41T80_REG_WDAY : M41T80_REG_SQW; | |
480 | int reg, ret, val = 0; | |
481 | ||
05a03bf2 TK |
482 | if (rate >= M41T80_SQW_MAX_FREQ) |
483 | val = 1; | |
484 | else if (rate >= M41T80_SQW_MAX_FREQ / 4) | |
485 | val = 2; | |
486 | else if (rate) | |
487 | val = 15 - ilog2(rate); | |
1373e77b GB |
488 | |
489 | reg = i2c_smbus_read_byte_data(client, reg_sqw); | |
490 | if (reg < 0) | |
491 | return reg; | |
492 | ||
493 | reg = (reg & 0x0f) | (val << 4); | |
494 | ||
495 | ret = i2c_smbus_write_byte_data(client, reg_sqw, reg); | |
2cb90ed3 TK |
496 | if (!ret) |
497 | m41t80->freq = m41t80_decode_freq(val); | |
de6042d2 | 498 | return ret; |
1373e77b GB |
499 | } |
500 | ||
501 | static int m41t80_sqw_control(struct clk_hw *hw, bool enable) | |
502 | { | |
503 | struct m41t80_data *m41t80 = sqw_to_m41t80_data(hw); | |
504 | struct i2c_client *client = m41t80->client; | |
505 | int ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
506 | ||
507 | if (ret < 0) | |
508 | return ret; | |
509 | ||
510 | if (enable) | |
511 | ret |= M41T80_ALMON_SQWE; | |
512 | else | |
513 | ret &= ~M41T80_ALMON_SQWE; | |
514 | ||
13bb1d78 TK |
515 | ret = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, ret); |
516 | if (!ret) | |
517 | m41t80->sqwe = enable; | |
518 | return ret; | |
1373e77b GB |
519 | } |
520 | ||
521 | static int m41t80_sqw_prepare(struct clk_hw *hw) | |
522 | { | |
523 | return m41t80_sqw_control(hw, 1); | |
524 | } | |
525 | ||
526 | static void m41t80_sqw_unprepare(struct clk_hw *hw) | |
527 | { | |
528 | m41t80_sqw_control(hw, 0); | |
529 | } | |
530 | ||
531 | static int m41t80_sqw_is_prepared(struct clk_hw *hw) | |
532 | { | |
13bb1d78 | 533 | return sqw_to_m41t80_data(hw)->sqwe; |
1373e77b GB |
534 | } |
535 | ||
536 | static const struct clk_ops m41t80_sqw_ops = { | |
537 | .prepare = m41t80_sqw_prepare, | |
538 | .unprepare = m41t80_sqw_unprepare, | |
539 | .is_prepared = m41t80_sqw_is_prepared, | |
540 | .recalc_rate = m41t80_sqw_recalc_rate, | |
541 | .round_rate = m41t80_sqw_round_rate, | |
542 | .set_rate = m41t80_sqw_set_rate, | |
543 | }; | |
544 | ||
545 | static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80) | |
546 | { | |
547 | struct i2c_client *client = m41t80->client; | |
548 | struct device_node *node = client->dev.of_node; | |
549 | struct clk *clk; | |
550 | struct clk_init_data init; | |
551 | int ret; | |
552 | ||
553 | /* First disable the clock */ | |
554 | ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); | |
555 | if (ret < 0) | |
556 | return ERR_PTR(ret); | |
557 | ret = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_MON, | |
558 | ret & ~(M41T80_ALMON_SQWE)); | |
559 | if (ret < 0) | |
560 | return ERR_PTR(ret); | |
561 | ||
562 | init.name = "m41t80-sqw"; | |
563 | init.ops = &m41t80_sqw_ops; | |
564 | init.flags = 0; | |
565 | init.parent_names = NULL; | |
566 | init.num_parents = 0; | |
567 | m41t80->sqw.init = &init; | |
2cb90ed3 | 568 | m41t80->freq = m41t80_get_freq(m41t80); |
1373e77b GB |
569 | |
570 | /* optional override of the clockname */ | |
571 | of_property_read_string(node, "clock-output-names", &init.name); | |
572 | ||
573 | /* register the clock */ | |
574 | clk = clk_register(&client->dev, &m41t80->sqw); | |
575 | if (!IS_ERR(clk)) | |
576 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
577 | ||
578 | return clk; | |
579 | } | |
580 | #endif | |
581 | ||
617780d2 AN |
582 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
583 | /* | |
584 | ***************************************************************************** | |
585 | * | |
586 | * Watchdog Driver | |
587 | * | |
588 | ***************************************************************************** | |
589 | */ | |
76384f31 | 590 | static DEFINE_MUTEX(m41t80_rtc_mutex); |
617780d2 AN |
591 | static struct i2c_client *save_client; |
592 | ||
593 | /* Default margin */ | |
594 | #define WD_TIMO 60 /* 1..31 seconds */ | |
595 | ||
596 | static int wdt_margin = WD_TIMO; | |
597 | module_param(wdt_margin, int, 0); | |
598 | MODULE_PARM_DESC(wdt_margin, "Watchdog timeout in seconds (default 60s)"); | |
599 | ||
600 | static unsigned long wdt_is_open; | |
601 | static int boot_flag; | |
602 | ||
603 | /** | |
604 | * wdt_ping: | |
605 | * | |
606 | * Reload counter one with the watchdog timeout. We don't bother reloading | |
607 | * the cascade counter. | |
608 | */ | |
609 | static void wdt_ping(void) | |
610 | { | |
611 | unsigned char i2c_data[2]; | |
612 | struct i2c_msg msgs1[1] = { | |
613 | { | |
614 | .addr = save_client->addr, | |
615 | .flags = 0, | |
616 | .len = 2, | |
617 | .buf = i2c_data, | |
618 | }, | |
619 | }; | |
d3a126fc SF |
620 | struct m41t80_data *clientdata = i2c_get_clientdata(save_client); |
621 | ||
617780d2 AN |
622 | i2c_data[0] = 0x09; /* watchdog register */ |
623 | ||
624 | if (wdt_margin > 31) | |
625 | i2c_data[1] = (wdt_margin & 0xFC) | 0x83; /* resolution = 4s */ | |
626 | else | |
627 | /* | |
628 | * WDS = 1 (0x80), mulitplier = WD_TIMO, resolution = 1s (0x02) | |
629 | */ | |
fc99b901 | 630 | i2c_data[1] = wdt_margin << 2 | 0x82; |
617780d2 | 631 | |
d3a126fc SF |
632 | /* |
633 | * M41T65 has three bits for watchdog resolution. Don't set bit 7, as | |
634 | * that would be an invalid resolution. | |
635 | */ | |
636 | if (clientdata->features & M41T80_FEATURE_WD) | |
637 | i2c_data[1] &= ~M41T80_WATCHDOG_RB2; | |
638 | ||
617780d2 AN |
639 | i2c_transfer(save_client->adapter, msgs1, 1); |
640 | } | |
641 | ||
642 | /** | |
643 | * wdt_disable: | |
644 | * | |
645 | * disables watchdog. | |
646 | */ | |
647 | static void wdt_disable(void) | |
648 | { | |
649 | unsigned char i2c_data[2], i2c_buf[0x10]; | |
650 | struct i2c_msg msgs0[2] = { | |
651 | { | |
652 | .addr = save_client->addr, | |
653 | .flags = 0, | |
654 | .len = 1, | |
655 | .buf = i2c_data, | |
656 | }, | |
657 | { | |
658 | .addr = save_client->addr, | |
659 | .flags = I2C_M_RD, | |
660 | .len = 1, | |
661 | .buf = i2c_buf, | |
662 | }, | |
663 | }; | |
664 | struct i2c_msg msgs1[1] = { | |
665 | { | |
666 | .addr = save_client->addr, | |
667 | .flags = 0, | |
668 | .len = 2, | |
669 | .buf = i2c_data, | |
670 | }, | |
671 | }; | |
672 | ||
673 | i2c_data[0] = 0x09; | |
674 | i2c_transfer(save_client->adapter, msgs0, 2); | |
675 | ||
676 | i2c_data[0] = 0x09; | |
677 | i2c_data[1] = 0x00; | |
678 | i2c_transfer(save_client->adapter, msgs1, 1); | |
679 | } | |
680 | ||
681 | /** | |
682 | * wdt_write: | |
683 | * @file: file handle to the watchdog | |
684 | * @buf: buffer to write (unused as data does not matter here | |
685 | * @count: count of bytes | |
686 | * @ppos: pointer to the position to write. No seeks allowed | |
687 | * | |
688 | * A write to a watchdog device is defined as a keepalive signal. Any | |
689 | * write of data will do, as we we don't define content meaning. | |
690 | */ | |
691 | static ssize_t wdt_write(struct file *file, const char __user *buf, | |
692 | size_t count, loff_t *ppos) | |
693 | { | |
617780d2 AN |
694 | if (count) { |
695 | wdt_ping(); | |
696 | return 1; | |
697 | } | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static ssize_t wdt_read(struct file *file, char __user *buf, | |
702 | size_t count, loff_t *ppos) | |
703 | { | |
704 | return 0; | |
705 | } | |
706 | ||
707 | /** | |
708 | * wdt_ioctl: | |
709 | * @inode: inode of the device | |
710 | * @file: file handle to the device | |
711 | * @cmd: watchdog command | |
712 | * @arg: argument pointer | |
713 | * | |
714 | * The watchdog API defines a common set of functions for all watchdogs | |
715 | * according to their available features. We only actually usefully support | |
716 | * querying capabilities and current status. | |
717 | */ | |
55929332 | 718 | static int wdt_ioctl(struct file *file, unsigned int cmd, |
617780d2 AN |
719 | unsigned long arg) |
720 | { | |
721 | int new_margin, rv; | |
722 | static struct watchdog_info ident = { | |
723 | .options = WDIOF_POWERUNDER | WDIOF_KEEPALIVEPING | | |
724 | WDIOF_SETTIMEOUT, | |
725 | .firmware_version = 1, | |
726 | .identity = "M41T80 WTD" | |
727 | }; | |
728 | ||
729 | switch (cmd) { | |
730 | case WDIOC_GETSUPPORT: | |
731 | return copy_to_user((struct watchdog_info __user *)arg, &ident, | |
732 | sizeof(ident)) ? -EFAULT : 0; | |
733 | ||
734 | case WDIOC_GETSTATUS: | |
735 | case WDIOC_GETBOOTSTATUS: | |
736 | return put_user(boot_flag, (int __user *)arg); | |
737 | case WDIOC_KEEPALIVE: | |
738 | wdt_ping(); | |
739 | return 0; | |
740 | case WDIOC_SETTIMEOUT: | |
741 | if (get_user(new_margin, (int __user *)arg)) | |
742 | return -EFAULT; | |
743 | /* Arbitrary, can't find the card's limits */ | |
744 | if (new_margin < 1 || new_margin > 124) | |
745 | return -EINVAL; | |
746 | wdt_margin = new_margin; | |
747 | wdt_ping(); | |
748 | /* Fall */ | |
749 | case WDIOC_GETTIMEOUT: | |
750 | return put_user(wdt_margin, (int __user *)arg); | |
751 | ||
752 | case WDIOC_SETOPTIONS: | |
753 | if (copy_from_user(&rv, (int __user *)arg, sizeof(int))) | |
754 | return -EFAULT; | |
755 | ||
756 | if (rv & WDIOS_DISABLECARD) { | |
a737e835 | 757 | pr_info("disable watchdog\n"); |
617780d2 AN |
758 | wdt_disable(); |
759 | } | |
760 | ||
761 | if (rv & WDIOS_ENABLECARD) { | |
a737e835 | 762 | pr_info("enable watchdog\n"); |
617780d2 AN |
763 | wdt_ping(); |
764 | } | |
765 | ||
766 | return -EINVAL; | |
767 | } | |
768 | return -ENOTTY; | |
769 | } | |
770 | ||
55929332 AB |
771 | static long wdt_unlocked_ioctl(struct file *file, unsigned int cmd, |
772 | unsigned long arg) | |
773 | { | |
774 | int ret; | |
775 | ||
613655fa | 776 | mutex_lock(&m41t80_rtc_mutex); |
55929332 | 777 | ret = wdt_ioctl(file, cmd, arg); |
613655fa | 778 | mutex_unlock(&m41t80_rtc_mutex); |
55929332 AB |
779 | |
780 | return ret; | |
781 | } | |
782 | ||
617780d2 AN |
783 | /** |
784 | * wdt_open: | |
785 | * @inode: inode of device | |
786 | * @file: file handle to device | |
787 | * | |
788 | */ | |
789 | static int wdt_open(struct inode *inode, struct file *file) | |
790 | { | |
791 | if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) { | |
613655fa | 792 | mutex_lock(&m41t80_rtc_mutex); |
41012735 | 793 | if (test_and_set_bit(0, &wdt_is_open)) { |
613655fa | 794 | mutex_unlock(&m41t80_rtc_mutex); |
617780d2 | 795 | return -EBUSY; |
41012735 | 796 | } |
617780d2 AN |
797 | /* |
798 | * Activate | |
799 | */ | |
800 | wdt_is_open = 1; | |
613655fa | 801 | mutex_unlock(&m41t80_rtc_mutex); |
09eeb1f5 | 802 | return nonseekable_open(inode, file); |
617780d2 AN |
803 | } |
804 | return -ENODEV; | |
805 | } | |
806 | ||
807 | /** | |
808 | * wdt_close: | |
809 | * @inode: inode to board | |
810 | * @file: file handle to board | |
811 | * | |
812 | */ | |
813 | static int wdt_release(struct inode *inode, struct file *file) | |
814 | { | |
815 | if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) | |
816 | clear_bit(0, &wdt_is_open); | |
817 | return 0; | |
818 | } | |
819 | ||
820 | /** | |
821 | * notify_sys: | |
822 | * @this: our notifier block | |
823 | * @code: the event being reported | |
824 | * @unused: unused | |
825 | * | |
826 | * Our notifier is called on system shutdowns. We want to turn the card | |
827 | * off at reboot otherwise the machine will reboot again during memory | |
828 | * test or worse yet during the following fsck. This would suck, in fact | |
829 | * trust me - if it happens it does suck. | |
830 | */ | |
831 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | |
832 | void *unused) | |
833 | { | |
834 | if (code == SYS_DOWN || code == SYS_HALT) | |
835 | /* Disable Watchdog */ | |
836 | wdt_disable(); | |
837 | return NOTIFY_DONE; | |
838 | } | |
839 | ||
840 | static const struct file_operations wdt_fops = { | |
841 | .owner = THIS_MODULE, | |
842 | .read = wdt_read, | |
55929332 | 843 | .unlocked_ioctl = wdt_unlocked_ioctl, |
617780d2 AN |
844 | .write = wdt_write, |
845 | .open = wdt_open, | |
846 | .release = wdt_release, | |
6038f373 | 847 | .llseek = no_llseek, |
617780d2 AN |
848 | }; |
849 | ||
850 | static struct miscdevice wdt_dev = { | |
851 | .minor = WATCHDOG_MINOR, | |
852 | .name = "watchdog", | |
853 | .fops = &wdt_fops, | |
854 | }; | |
855 | ||
856 | /* | |
857 | * The WDT card needs to learn about soft shutdowns in order to | |
858 | * turn the timebomb registers off. | |
859 | */ | |
860 | static struct notifier_block wdt_notifier = { | |
861 | .notifier_call = wdt_notify_sys, | |
862 | }; | |
863 | #endif /* CONFIG_RTC_DRV_M41T80_WDT */ | |
864 | ||
caaff562 AN |
865 | /* |
866 | ***************************************************************************** | |
867 | * | |
868 | * Driver Interface | |
869 | * | |
870 | ***************************************************************************** | |
871 | */ | |
ef6b3125 | 872 | |
d2653e92 JD |
873 | static int m41t80_probe(struct i2c_client *client, |
874 | const struct i2c_device_id *id) | |
caaff562 | 875 | { |
f2b84ee8 | 876 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
3760f736 | 877 | int rc = 0; |
caaff562 | 878 | struct rtc_time tm; |
9c6dfed9 | 879 | struct m41t80_data *m41t80_data = NULL; |
d4473b9b | 880 | bool wakeup_source = false; |
caaff562 | 881 | |
f2b84ee8 MJ |
882 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK | |
883 | I2C_FUNC_SMBUS_BYTE_DATA)) { | |
884 | dev_err(&adapter->dev, "doesn't support I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK\n"); | |
c67fedfa | 885 | return -ENODEV; |
f2b84ee8 | 886 | } |
caaff562 | 887 | |
9c6dfed9 MJ |
888 | m41t80_data = devm_kzalloc(&client->dev, sizeof(*m41t80_data), |
889 | GFP_KERNEL); | |
890 | if (!m41t80_data) | |
c67fedfa | 891 | return -ENOMEM; |
caaff562 | 892 | |
1373e77b | 893 | m41t80_data->client = client; |
eb235c56 JMC |
894 | if (client->dev.of_node) |
895 | m41t80_data->features = (unsigned long) | |
896 | of_device_get_match_data(&client->dev); | |
897 | else | |
898 | m41t80_data->features = id->driver_data; | |
9c6dfed9 MJ |
899 | i2c_set_clientdata(client, m41t80_data); |
900 | ||
10d0c768 AB |
901 | m41t80_data->rtc = devm_rtc_allocate_device(&client->dev); |
902 | if (IS_ERR(m41t80_data->rtc)) | |
903 | return PTR_ERR(m41t80_data->rtc); | |
904 | ||
d4473b9b EC |
905 | #ifdef CONFIG_OF |
906 | wakeup_source = of_property_read_bool(client->dev.of_node, | |
907 | "wakeup-source"); | |
908 | #endif | |
9c6dfed9 MJ |
909 | if (client->irq > 0) { |
910 | rc = devm_request_threaded_irq(&client->dev, client->irq, | |
911 | NULL, m41t80_handle_irq, | |
912 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
913 | "m41t80", client); | |
914 | if (rc) { | |
915 | dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n"); | |
916 | client->irq = 0; | |
d4473b9b | 917 | wakeup_source = false; |
9c6dfed9 MJ |
918 | } |
919 | } | |
d4473b9b EC |
920 | if (client->irq > 0 || wakeup_source) { |
921 | m41t80_rtc_ops.read_alarm = m41t80_read_alarm; | |
922 | m41t80_rtc_ops.set_alarm = m41t80_set_alarm; | |
923 | m41t80_rtc_ops.alarm_irq_enable = m41t80_alarm_irq_enable; | |
924 | /* Enable the wakealarm */ | |
925 | device_init_wakeup(&client->dev, true); | |
926 | } | |
a015dbc1 | 927 | |
10d0c768 | 928 | m41t80_data->rtc->ops = &m41t80_rtc_ops; |
caaff562 | 929 | |
d4473b9b EC |
930 | if (client->irq <= 0) { |
931 | /* We cannot support UIE mode if we do not have an IRQ line */ | |
10d0c768 | 932 | m41t80_data->rtc->uie_unsupported = 1; |
d4473b9b | 933 | } |
caaff562 AN |
934 | |
935 | /* Make sure HT (Halt Update) bit is cleared */ | |
936 | rc = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_HOUR); | |
caaff562 | 937 | |
c67fedfa | 938 | if (rc >= 0 && rc & M41T80_ALHOUR_HT) { |
9c6dfed9 | 939 | if (m41t80_data->features & M41T80_FEATURE_HT) { |
e2c8e1a9 | 940 | m41t80_rtc_read_time(&client->dev, &tm); |
caaff562 AN |
941 | dev_info(&client->dev, "HT bit was set!\n"); |
942 | dev_info(&client->dev, | |
fc99b901 | 943 | "Power Down at %04i-%02i-%02i %02i:%02i:%02i\n", |
caaff562 AN |
944 | tm.tm_year + 1900, |
945 | tm.tm_mon + 1, tm.tm_mday, tm.tm_hour, | |
946 | tm.tm_min, tm.tm_sec); | |
947 | } | |
c67fedfa | 948 | rc = i2c_smbus_write_byte_data(client, M41T80_REG_ALARM_HOUR, |
fc99b901 | 949 | rc & ~M41T80_ALHOUR_HT); |
c67fedfa WS |
950 | } |
951 | ||
952 | if (rc < 0) { | |
953 | dev_err(&client->dev, "Can't clear HT bit\n"); | |
85d77047 | 954 | return rc; |
caaff562 AN |
955 | } |
956 | ||
957 | /* Make sure ST (stop) bit is cleared */ | |
958 | rc = i2c_smbus_read_byte_data(client, M41T80_REG_SEC); | |
caaff562 | 959 | |
c67fedfa WS |
960 | if (rc >= 0 && rc & M41T80_SEC_ST) |
961 | rc = i2c_smbus_write_byte_data(client, M41T80_REG_SEC, | |
fc99b901 | 962 | rc & ~M41T80_SEC_ST); |
c67fedfa WS |
963 | if (rc < 0) { |
964 | dev_err(&client->dev, "Can't clear ST bit\n"); | |
85d77047 | 965 | return rc; |
caaff562 AN |
966 | } |
967 | ||
617780d2 | 968 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
9c6dfed9 | 969 | if (m41t80_data->features & M41T80_FEATURE_HT) { |
417607d0 | 970 | save_client = client; |
617780d2 AN |
971 | rc = misc_register(&wdt_dev); |
972 | if (rc) | |
c67fedfa | 973 | return rc; |
617780d2 AN |
974 | rc = register_reboot_notifier(&wdt_notifier); |
975 | if (rc) { | |
976 | misc_deregister(&wdt_dev); | |
c67fedfa | 977 | return rc; |
617780d2 | 978 | } |
617780d2 | 979 | } |
1373e77b GB |
980 | #endif |
981 | #ifdef CONFIG_COMMON_CLK | |
982 | if (m41t80_data->features & M41T80_FEATURE_SQ) | |
983 | m41t80_sqw_register_clk(m41t80_data); | |
617780d2 | 984 | #endif |
10d0c768 AB |
985 | |
986 | rc = rtc_register_device(m41t80_data->rtc); | |
987 | if (rc) | |
988 | return rc; | |
989 | ||
caaff562 | 990 | return 0; |
caaff562 AN |
991 | } |
992 | ||
993 | static int m41t80_remove(struct i2c_client *client) | |
994 | { | |
4ebabb78 | 995 | #ifdef CONFIG_RTC_DRV_M41T80_WDT |
caaff562 | 996 | struct m41t80_data *clientdata = i2c_get_clientdata(client); |
caaff562 | 997 | |
3760f736 | 998 | if (clientdata->features & M41T80_FEATURE_HT) { |
617780d2 AN |
999 | misc_deregister(&wdt_dev); |
1000 | unregister_reboot_notifier(&wdt_notifier); | |
1001 | } | |
1002 | #endif | |
caaff562 AN |
1003 | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | static struct i2c_driver m41t80_driver = { | |
1008 | .driver = { | |
afe1ab4d | 1009 | .name = "rtc-m41t80", |
eb235c56 | 1010 | .of_match_table = of_match_ptr(m41t80_of_match), |
ae036af8 | 1011 | .pm = &m41t80_pm, |
caaff562 AN |
1012 | }, |
1013 | .probe = m41t80_probe, | |
1014 | .remove = m41t80_remove, | |
3760f736 | 1015 | .id_table = m41t80_id, |
caaff562 AN |
1016 | }; |
1017 | ||
0abc9201 | 1018 | module_i2c_driver(m41t80_driver); |
caaff562 AN |
1019 | |
1020 | MODULE_AUTHOR("Alexander Bigga <ab@mycable.de>"); | |
1021 | MODULE_DESCRIPTION("ST Microelectronics M41T80 series RTC I2C Client Driver"); | |
1022 | MODULE_LICENSE("GPL"); |