[linux-2.6-block.git] / drivers / rtc / rtc-jz4740.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
 *	 JZ4740 SoC RTC driver
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/reboot.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define JZ_REG_RTC_CTRL		0x00
#define JZ_REG_RTC_SEC		0x04
#define JZ_REG_RTC_SEC_ALARM	0x08
#define JZ_REG_RTC_REGULATOR	0x0C
#define JZ_REG_RTC_HIBERNATE	0x20
#define JZ_REG_RTC_WAKEUP_FILTER	0x24
#define JZ_REG_RTC_RESET_COUNTER	0x28
#define JZ_REG_RTC_SCRATCHPAD	0x34

/* The following are present on the jz4780 */
#define JZ_REG_RTC_WENR	0x3C
#define JZ_RTC_WENR_WEN	BIT(31)

#define JZ_RTC_CTRL_WRDY	BIT(7)
#define JZ_RTC_CTRL_1HZ		BIT(6)
#define JZ_RTC_CTRL_1HZ_IRQ	BIT(5)
#define JZ_RTC_CTRL_AF		BIT(4)
#define JZ_RTC_CTRL_AF_IRQ	BIT(3)
#define JZ_RTC_CTRL_AE		BIT(2)
#define JZ_RTC_CTRL_ENABLE	BIT(0)

/* Magic value to enable writes on jz4780 */
#define JZ_RTC_WENR_MAGIC	0xA55A

#define JZ_RTC_WAKEUP_FILTER_MASK	0x0000FFE0
#define JZ_RTC_RESET_COUNTER_MASK	0x00000FE0

enum jz4740_rtc_type {
	ID_JZ4740,
	ID_JZ4780,
};

struct jz4740_rtc {
	void __iomem *base;
	enum jz4740_rtc_type type;

	struct rtc_device *rtc;
	struct clk *clk;

	int irq;

	spinlock_t lock;

	unsigned int min_wakeup_pin_assert_time;
	unsigned int reset_pin_assert_time;
};

static struct device *dev_for_power_off;

static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
{
	return readl(rtc->base + reg);
}

static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
{
	uint32_t ctrl;
	int timeout = 10000;

	do {
		ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);

	return timeout ? 0 : -EIO;
}

static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
{
	uint32_t ctrl;
	int ret, timeout = 10000;

	ret = jz4740_rtc_wait_write_ready(rtc);
	if (ret != 0)
		return ret;

	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);

	do {
		ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
	} while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);

	return timeout ? 0 : -EIO;
}

static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
	uint32_t val)
{
	int ret = 0;

	if (rtc->type >= ID_JZ4780)
		ret = jz4780_rtc_enable_write(rtc);
	if (ret == 0)
		ret = jz4740_rtc_wait_write_ready(rtc);
	if (ret == 0)
		writel(val, rtc->base + reg);

	return ret;
}

static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
	bool set)
{
	int ret;
	unsigned long flags;
	uint32_t ctrl;

	spin_lock_irqsave(&rtc->lock, flags);

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	/* Don't clear interrupt flags by accident */
	ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;

	if (set)
		ctrl |= mask;
	else
		ctrl &= ~mask;

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);

	spin_unlock_irqrestore(&rtc->lock, flags);

	return ret;
}

static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs, secs2;
	int timeout = 5;

	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
		return -EINVAL;

	/* If the seconds register is read while it is updated, it can contain a
	 * bogus value. This can be avoided by making sure that two consecutive
	 * reads have the same value.
	 */
	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);

	while (secs != secs2 && --timeout) {
		secs = secs2;
		secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	}

	if (timeout == 0)
		return -EIO;

	rtc_time64_to_tm(secs, time);

	return 0;
}

static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	int ret;

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
	if (ret)
		return ret;

	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
}

static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs;
	uint32_t ctrl;

	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);

	rtc_time64_to_tm(secs, &alrm->time);

	return 0;
}

static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int ret;
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));

	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
	if (!ret)
		ret = jz4740_rtc_ctrl_set_bits(rtc,
			JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);

	return ret;
}

static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
}

static const struct rtc_class_ops jz4740_rtc_ops = {
	.read_time	= jz4740_rtc_read_time,
	.set_time	= jz4740_rtc_set_time,
	.read_alarm	= jz4740_rtc_read_alarm,
	.set_alarm	= jz4740_rtc_set_alarm,
	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
};

static irqreturn_t jz4740_rtc_irq(int irq, void *data)
{
	struct jz4740_rtc *rtc = data;
	uint32_t ctrl;
	unsigned long events = 0;

	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);

	if (ctrl & JZ_RTC_CTRL_1HZ)
		events |= (RTC_UF | RTC_IRQF);

	if (ctrl & JZ_RTC_CTRL_AF)
		events |= (RTC_AF | RTC_IRQF);

	rtc_update_irq(rtc->rtc, 1, events);

	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);

	return IRQ_HANDLED;
}

static void jz4740_rtc_poweroff(struct device *dev)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
}

static void jz4740_rtc_power_off(void)
{
	struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
	unsigned long rtc_rate;
	unsigned long wakeup_filter_ticks;
	unsigned long reset_counter_ticks;

	clk_prepare_enable(rtc->clk);

	rtc_rate = clk_get_rate(rtc->clk);

	/*
	 * Set minimum wakeup pin assertion time: 100 ms.
	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
	 */
	wakeup_filter_ticks =
		(rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
	if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
		wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
	else
		wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
	jz4740_rtc_reg_write(rtc,
			     JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);

	/*
	 * Set reset pin low-level assertion time after wakeup: 60 ms.
	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
	 */
	reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
	if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
		reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
	else
		reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
	jz4740_rtc_reg_write(rtc,
			     JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);

	jz4740_rtc_poweroff(dev_for_power_off);
	kernel_halt();
}

static const struct of_device_id jz4740_rtc_of_match[] = {
	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
	{},
};
MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);

static int jz4740_rtc_probe(struct platform_device *pdev)
{
	int ret;
	struct jz4740_rtc *rtc;
	struct resource *mem;
	const struct platform_device_id *id = platform_get_device_id(pdev);
	const struct of_device_id *of_id = of_match_device(
			jz4740_rtc_of_match, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;

	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
	if (!rtc)
		return -ENOMEM;

	if (of_id)
		rtc->type = (enum jz4740_rtc_type)of_id->data;
	else
		rtc->type = id->driver_data;

	rtc->irq = platform_get_irq(pdev, 0);
	if (rtc->irq < 0) {
		dev_err(&pdev->dev, "Failed to get platform irq\n");
		return -ENOENT;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	rtc->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(rtc->base))
		return PTR_ERR(rtc->base);

	rtc->clk = devm_clk_get(&pdev->dev, "rtc");
	if (IS_ERR(rtc->clk)) {
		dev_err(&pdev->dev, "Failed to get RTC clock\n");
		return PTR_ERR(rtc->clk);
	}

	spin_lock_init(&rtc->lock);

	platform_set_drvdata(pdev, rtc);

	device_init_wakeup(&pdev->dev, 1);

	ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq);
	if (ret) {
		dev_err(&pdev->dev, "Failed to set wake irq: %d\n", ret);
		return ret;
	}

	rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc->rtc)) {
		ret = PTR_ERR(rtc->rtc);
		dev_err(&pdev->dev, "Failed to allocate rtc device: %d\n", ret);
		return ret;
	}

	rtc->rtc->ops = &jz4740_rtc_ops;
	rtc->rtc->range_max = U32_MAX;

	ret = rtc_register_device(rtc->rtc);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
		return ret;
	}

	ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
				pdev->name, rtc);
	if (ret) {
		dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
		return ret;
	}

	if (np && of_device_is_system_power_controller(np)) {
		if (!pm_power_off) {
			/* Default: 60ms */
			rtc->reset_pin_assert_time = 60;
			of_property_read_u32(np, "reset-pin-assert-time-ms",
					     &rtc->reset_pin_assert_time);

			/* Default: 100ms */
			rtc->min_wakeup_pin_assert_time = 100;
			of_property_read_u32(np,
					     "min-wakeup-pin-assert-time-ms",
					     &rtc->min_wakeup_pin_assert_time);

			dev_for_power_off = &pdev->dev;
			pm_power_off = jz4740_rtc_power_off;
		} else {
			dev_warn(&pdev->dev,
				 "Poweroff handler already present!\n");
		}
	}

	return 0;
}

static const struct platform_device_id jz4740_rtc_ids[] = {
	{ "jz4740-rtc", ID_JZ4740 },
	{ "jz4780-rtc", ID_JZ4780 },
	{}
};
MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);

static struct platform_driver jz4740_rtc_driver = {
	.probe	 = jz4740_rtc_probe,
	.driver	 = {
		.name  = "jz4740-rtc",
		.of_match_table = of_match_ptr(jz4740_rtc_of_match),
	},
	.id_table = jz4740_rtc_ids,
};

module_platform_driver(jz4740_rtc_driver);

MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
MODULE_ALIAS("platform:jz4740-rtc");
Commit	Line	Data
86836d64	1	// SPDX-License-Identifier: GPL-2.0+
3bf0eea8 LPC	2	/*
3bf0eea8 LPC	3	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
d0f744c8	4	* Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
3bf0eea8	5	* JZ4740 SoC RTC driver
3bf0eea8 LPC	6	*/
3bf0eea8 LPC	7
f9eb69d1	8	#include <linux/clk.h>
c08ac489	9	#include <linux/io.h>
3bf0eea8	10	#include <linux/kernel.h>
586655d2	11	#include <linux/module.h>
c05229a8	12	#include <linux/of_device.h>
3bf0eea8	13	#include <linux/platform_device.h>
3b2dc19f	14	#include <linux/pm_wakeirq.h>
f9eb69d1	15	#include <linux/reboot.h>
3bf0eea8 LPC	16	#include <linux/rtc.h>
	17	#include <linux/slab.h>
	18	#include <linux/spinlock.h>
	19
	20	#define JZ_REG_RTC_CTRL 0x00
	21	#define JZ_REG_RTC_SEC 0x04
	22	#define JZ_REG_RTC_SEC_ALARM 0x08
	23	#define JZ_REG_RTC_REGULATOR 0x0C
	24	#define JZ_REG_RTC_HIBERNATE 0x20
f9eb69d1 PC	25	#define JZ_REG_RTC_WAKEUP_FILTER 0x24
f9eb69d1 PC	26	#define JZ_REG_RTC_RESET_COUNTER 0x28
3bf0eea8 LPC	27	#define JZ_REG_RTC_SCRATCHPAD 0x34
3bf0eea8 LPC	28
cd563200 PC	29	/* The following are present on the jz4780 */
	30	#define JZ_REG_RTC_WENR 0x3C
	31	#define JZ_RTC_WENR_WEN BIT(31)
	32
3bf0eea8 LPC	33	#define JZ_RTC_CTRL_WRDY BIT(7)
	34	#define JZ_RTC_CTRL_1HZ BIT(6)
	35	#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
	36	#define JZ_RTC_CTRL_AF BIT(4)
	37	#define JZ_RTC_CTRL_AF_IRQ BIT(3)
	38	#define JZ_RTC_CTRL_AE BIT(2)
	39	#define JZ_RTC_CTRL_ENABLE BIT(0)
	40
cd563200 PC	41	/* Magic value to enable writes on jz4780 */
	42	#define JZ_RTC_WENR_MAGIC 0xA55A
	43
f9eb69d1 PC	44	#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
	45	#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
	46
cd563200 PC	47	enum jz4740_rtc_type {
	48	ID_JZ4740,
	49	ID_JZ4780,
	50	};
	51
3bf0eea8	52	struct jz4740_rtc {
3bf0eea8	53	void __iomem *base;
cd563200	54	enum jz4740_rtc_type type;
3bf0eea8 LPC	55
3bf0eea8 LPC	56	struct rtc_device *rtc;
f9eb69d1	57	struct clk *clk;
3bf0eea8	58
7c6a52a0	59	int irq;
3bf0eea8 LPC	60
3bf0eea8 LPC	61	spinlock_t lock;
f9eb69d1 PC	62
	63	unsigned int min_wakeup_pin_assert_time;
	64	unsigned int reset_pin_assert_time;
3bf0eea8 LPC	65	};
3bf0eea8 LPC	66
f9eb69d1 PC	67	static struct device *dev_for_power_off;
f9eb69d1 PC	68
3bf0eea8 LPC	69	static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
	70	{
	71	return readl(rtc->base + reg);
	72	}
	73
	74	static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
	75	{
	76	uint32_t ctrl;
695e38d8	77	int timeout = 10000;
3bf0eea8 LPC	78
	79	do {
	80	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	81	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
	82
	83	return timeout ? 0 : -EIO;
	84	}
	85
cd563200 PC	86	static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
	87	{
	88	uint32_t ctrl;
695e38d8	89	int ret, timeout = 10000;
cd563200 PC	90
	91	ret = jz4740_rtc_wait_write_ready(rtc);
	92	if (ret != 0)
	93	return ret;
	94
	95	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
	96
	97	do {
	98	ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
	99	} while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
	100
	101	return timeout ? 0 : -EIO;
	102	}
	103
3bf0eea8 LPC	104	static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
	105	uint32_t val)
	106	{
cd563200 PC	107	int ret = 0;
	108
	109	if (rtc->type >= ID_JZ4780)
	110	ret = jz4780_rtc_enable_write(rtc);
	111	if (ret == 0)
	112	ret = jz4740_rtc_wait_write_ready(rtc);
3bf0eea8 LPC	113	if (ret == 0)
	114	writel(val, rtc->base + reg);
	115
	116	return ret;
	117	}
	118
	119	static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
	120	bool set)
	121	{
	122	int ret;
	123	unsigned long flags;
	124	uint32_t ctrl;
	125
	126	spin_lock_irqsave(&rtc->lock, flags);
	127
	128	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	129
	130	/* Don't clear interrupt flags by accident */
	131	ctrl \|= JZ_RTC_CTRL_1HZ \| JZ_RTC_CTRL_AF;
	132
	133	if (set)
	134	ctrl \|= mask;
	135	else
	136	ctrl &= ~mask;
	137
	138	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
	139
	140	spin_unlock_irqrestore(&rtc->lock, flags);
	141
	142	return ret;
	143	}
	144
	145	static int jz4740_rtc_read_time(struct device dev, struct rtc_time time)
	146	{
	147	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	148	uint32_t secs, secs2;
	149	int timeout = 5;
	150
7fe8fcee AB	151	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
	152	return -EINVAL;
	153
3bf0eea8 LPC	154	/* If the seconds register is read while it is updated, it can contain a
	155	* bogus value. This can be avoided by making sure that two consecutive
	156	* reads have the same value.
	157	*/
	158	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	159	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	160
	161	while (secs != secs2 && --timeout) {
	162	secs = secs2;
	163	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
	164	}
	165
	166	if (timeout == 0)
	167	return -EIO;
	168
be8dce96	169	rtc_time64_to_tm(secs, time);
3bf0eea8	170
ab62670e	171	return 0;
3bf0eea8 LPC	172	}
3bf0eea8 LPC	173
e72746e7	174	static int jz4740_rtc_set_time(struct device dev, struct rtc_time time)
3bf0eea8 LPC	175	{
3bf0eea8 LPC	176	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
7fe8fcee AB	177	int ret;
	178
	179	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
	180	if (ret)
	181	return ret;
3bf0eea8	182
7fe8fcee	183	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
3bf0eea8 LPC	184	}
	185
	186	static int jz4740_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	187	{
	188	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	189	uint32_t secs;
	190	uint32_t ctrl;
	191
	192	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
	193
	194	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	195
	196	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
	197	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
	198
be8dce96	199	rtc_time64_to_tm(secs, &alrm->time);
3bf0eea8	200
d10dcc95	201	return 0;
3bf0eea8 LPC	202	}
	203
	204	static int jz4740_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	205	{
	206	int ret;
	207	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
be8dce96	208	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
3bf0eea8 LPC	209
	210	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
	211	if (!ret)
d0f744c8 PC	212	ret = jz4740_rtc_ctrl_set_bits(rtc,
d0f744c8 PC	213	JZ_RTC_CTRL_AE \| JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
3bf0eea8 LPC	214
	215	return ret;
	216	}
	217
3bf0eea8 LPC	218	static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
	219	{
	220	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	221	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
	222	}
	223
34c7b3ac	224	static const struct rtc_class_ops jz4740_rtc_ops = {
3bf0eea8	225	.read_time = jz4740_rtc_read_time,
e72746e7	226	.set_time = jz4740_rtc_set_time,
3bf0eea8 LPC	227	.read_alarm = jz4740_rtc_read_alarm,
3bf0eea8 LPC	228	.set_alarm = jz4740_rtc_set_alarm,
3bf0eea8 LPC	229	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
	230	};
	231
	232	static irqreturn_t jz4740_rtc_irq(int irq, void *data)
	233	{
	234	struct jz4740_rtc *rtc = data;
	235	uint32_t ctrl;
	236	unsigned long events = 0;
	237
	238	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
	239
	240	if (ctrl & JZ_RTC_CTRL_1HZ)
	241	events \|= (RTC_UF \| RTC_IRQF);
	242
	243	if (ctrl & JZ_RTC_CTRL_AF)
	244	events \|= (RTC_AF \| RTC_IRQF);
	245
	246	rtc_update_irq(rtc->rtc, 1, events);
	247
	248	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ \| JZ_RTC_CTRL_AF, false);
	249
	250	return IRQ_HANDLED;
	251	}
	252
819c2178	253	static void jz4740_rtc_poweroff(struct device *dev)
3bf0eea8 LPC	254	{
	255	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
	256	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
	257	}
3bf0eea8	258
f9eb69d1 PC	259	static void jz4740_rtc_power_off(void)
	260	{
	261	struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
	262	unsigned long rtc_rate;
	263	unsigned long wakeup_filter_ticks;
	264	unsigned long reset_counter_ticks;
	265
	266	clk_prepare_enable(rtc->clk);
	267
	268	rtc_rate = clk_get_rate(rtc->clk);
	269
	270	/*
	271	* Set minimum wakeup pin assertion time: 100 ms.
	272	* Range is 0 to 2 sec if RTC is clocked at 32 kHz.
	273	*/
	274	wakeup_filter_ticks =
	275	(rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
	276	if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
	277	wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
	278	else
	279	wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
	280	jz4740_rtc_reg_write(rtc,
	281	JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
	282
	283	/*
	284	* Set reset pin low-level assertion time after wakeup: 60 ms.
	285	* Range is 0 to 125 ms if RTC is clocked at 32 kHz.
	286	*/
	287	reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
	288	if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
	289	reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
	290	else
	291	reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
	292	jz4740_rtc_reg_write(rtc,
	293	JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
	294
	295	jz4740_rtc_poweroff(dev_for_power_off);
586655d2	296	kernel_halt();
f9eb69d1 PC	297	}
f9eb69d1 PC	298
c05229a8 PC	299	static const struct of_device_id jz4740_rtc_of_match[] = {
	300	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
	301	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
	302	{},
	303	};
586655d2	304	MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
c05229a8	305
5a167f45	306	static int jz4740_rtc_probe(struct platform_device *pdev)
3bf0eea8 LPC	307	{
	308	int ret;
	309	struct jz4740_rtc *rtc;
3b6aa907	310	struct resource *mem;
cd563200	311	const struct platform_device_id *id = platform_get_device_id(pdev);
c05229a8 PC	312	const struct of_device_id *of_id = of_match_device(
c05229a8 PC	313	jz4740_rtc_of_match, &pdev->dev);
f9eb69d1	314	struct device_node *np = pdev->dev.of_node;
3bf0eea8	315
c08ac489	316	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
3bf0eea8 LPC	317	if (!rtc)
	318	return -ENOMEM;
	319
c05229a8 PC	320	if (of_id)
	321	rtc->type = (enum jz4740_rtc_type)of_id->data;
	322	else
	323	rtc->type = id->driver_data;
cd563200	324
3bf0eea8 LPC	325	rtc->irq = platform_get_irq(pdev, 0);
3bf0eea8 LPC	326	if (rtc->irq < 0) {
3bf0eea8	327	dev_err(&pdev->dev, "Failed to get platform irq\n");
c08ac489	328	return -ENOENT;
3bf0eea8 LPC	329	}
3bf0eea8 LPC	330
3b6aa907 JH	331	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	332	rtc->base = devm_ioremap_resource(&pdev->dev, mem);
	333	if (IS_ERR(rtc->base))
	334	return PTR_ERR(rtc->base);
3bf0eea8	335
f9eb69d1 PC	336	rtc->clk = devm_clk_get(&pdev->dev, "rtc");
	337	if (IS_ERR(rtc->clk)) {
	338	dev_err(&pdev->dev, "Failed to get RTC clock\n");
	339	return PTR_ERR(rtc->clk);
	340	}
	341
3bf0eea8 LPC	342	spin_lock_init(&rtc->lock);
	343
	344	platform_set_drvdata(pdev, rtc);
	345
d0f744c8 PC	346	device_init_wakeup(&pdev->dev, 1);
d0f744c8 PC	347
3b2dc19f AB	348	ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq);
	349	if (ret) {
	350	dev_err(&pdev->dev, "Failed to set wake irq: %d\n", ret);
	351	return ret;
	352	}
	353
a7ab6bed	354	rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
3bf0eea8 LPC	355	if (IS_ERR(rtc->rtc)) {
3bf0eea8 LPC	356	ret = PTR_ERR(rtc->rtc);
a7ab6bed AB	357	dev_err(&pdev->dev, "Failed to allocate rtc device: %d\n", ret);
	358	return ret;
	359	}
	360
	361	rtc->rtc->ops = &jz4740_rtc_ops;
	362	rtc->rtc->range_max = U32_MAX;
	363
	364	ret = rtc_register_device(rtc->rtc);
	365	if (ret) {
3bf0eea8	366	dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
c08ac489	367	return ret;
3bf0eea8 LPC	368	}
3bf0eea8 LPC	369
c08ac489	370	ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
3bf0eea8 LPC	371	pdev->name, rtc);
	372	if (ret) {
	373	dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
c08ac489	374	return ret;
3bf0eea8 LPC	375	}
3bf0eea8 LPC	376
f9eb69d1 PC	377	if (np && of_device_is_system_power_controller(np)) {
	378	if (!pm_power_off) {
	379	/* Default: 60ms */
	380	rtc->reset_pin_assert_time = 60;
	381	of_property_read_u32(np, "reset-pin-assert-time-ms",
	382	&rtc->reset_pin_assert_time);
	383
	384	/* Default: 100ms */
	385	rtc->min_wakeup_pin_assert_time = 100;
	386	of_property_read_u32(np,
	387	"min-wakeup-pin-assert-time-ms",
	388	&rtc->min_wakeup_pin_assert_time);
	389
	390	dev_for_power_off = &pdev->dev;
	391	pm_power_off = jz4740_rtc_power_off;
	392	} else {
	393	dev_warn(&pdev->dev,
	394	"Poweroff handler already present!\n");
	395	}
	396	}
	397
3bf0eea8	398	return 0;
3bf0eea8 LPC	399	}
3bf0eea8 LPC	400
cd563200 PC	401	static const struct platform_device_id jz4740_rtc_ids[] = {
	402	{ "jz4740-rtc", ID_JZ4740 },
	403	{ "jz4780-rtc", ID_JZ4780 },
	404	{}
	405	};
586655d2	406	MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
cd563200	407
681d0378	408	static struct platform_driver jz4740_rtc_driver = {
d0f744c8	409	.probe = jz4740_rtc_probe,
d0f744c8 PC	410	.driver = {
d0f744c8 PC	411	.name = "jz4740-rtc",
c05229a8	412	.of_match_table = of_match_ptr(jz4740_rtc_of_match),
3bf0eea8	413	},
cd563200	414	.id_table = jz4740_rtc_ids,
3bf0eea8 LPC	415	};
3bf0eea8 LPC	416
586655d2 AB	417	module_platform_driver(jz4740_rtc_driver);
	418
	419	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	420	MODULE_LICENSE("GPL");
	421	MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
	422	MODULE_ALIAS("platform:jz4740-rtc");