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c8889bb6 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
eba54546 BS |
2 | /* |
3 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | |
4 | * Copyright 2010 Orex Computed Radiography | |
5 | */ | |
6 | ||
eba54546 BS |
7 | /* |
8 | * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block | |
9 | * to implement a Linux RTC. Times and alarms are truncated to seconds. | |
10 | * Since the RTC framework performs API locking via rtc->ops_lock the | |
11 | * only simultaneous accesses we need to deal with is updating DryIce | |
12 | * registers while servicing an alarm. | |
13 | * | |
14 | * Note that reading the DSR (DryIce Status Register) automatically clears | |
15 | * the WCF (Write Complete Flag). All DryIce writes are synchronized to the | |
16 | * LP (Low Power) domain and set the WCF upon completion. Writes to the | |
17 | * DIER (DryIce Interrupt Enable Register) are the only exception. These | |
18 | * occur at normal bus speeds and do not set WCF. Periodic interrupts are | |
19 | * not supported by the hardware. | |
20 | */ | |
21 | ||
22 | #include <linux/io.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/rtc.h> | |
d4c32f35 | 28 | #include <linux/sched.h> |
ba3f7a17 | 29 | #include <linux/spinlock.h> |
eba54546 | 30 | #include <linux/workqueue.h> |
968d21c2 | 31 | #include <linux/of.h> |
eba54546 BS |
32 | |
33 | /* DryIce Register Definitions */ | |
34 | ||
35 | #define DTCMR 0x00 /* Time Counter MSB Reg */ | |
36 | #define DTCLR 0x04 /* Time Counter LSB Reg */ | |
37 | ||
38 | #define DCAMR 0x08 /* Clock Alarm MSB Reg */ | |
39 | #define DCALR 0x0c /* Clock Alarm LSB Reg */ | |
40 | #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ | |
41 | ||
42 | #define DCR 0x10 /* Control Reg */ | |
46edeffa JB |
43 | #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */ |
44 | #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */ | |
45 | #define DCR_KSSL (1 << 27) /* Key-select soft lock */ | |
46 | #define DCR_MCHL (1 << 20) /* Monotonic-counter hard lock */ | |
47 | #define DCR_MCSL (1 << 19) /* Monotonic-counter soft lock */ | |
48 | #define DCR_TCHL (1 << 18) /* Timer-counter hard lock */ | |
49 | #define DCR_TCSL (1 << 17) /* Timer-counter soft lock */ | |
50 | #define DCR_FSHL (1 << 16) /* Failure state hard lock */ | |
eba54546 | 51 | #define DCR_TCE (1 << 3) /* Time Counter Enable */ |
46edeffa | 52 | #define DCR_MCE (1 << 2) /* Monotonic Counter Enable */ |
eba54546 BS |
53 | |
54 | #define DSR 0x14 /* Status Reg */ | |
46edeffa JB |
55 | #define DSR_WTD (1 << 23) /* Wire-mesh tamper detected */ |
56 | #define DSR_ETBD (1 << 22) /* External tamper B detected */ | |
57 | #define DSR_ETAD (1 << 21) /* External tamper A detected */ | |
58 | #define DSR_EBD (1 << 20) /* External boot detected */ | |
59 | #define DSR_SAD (1 << 19) /* SCC alarm detected */ | |
b88e0ae9 | 60 | #define DSR_TTD (1 << 18) /* Temperature tamper detected */ |
46edeffa JB |
61 | #define DSR_CTD (1 << 17) /* Clock tamper detected */ |
62 | #define DSR_VTD (1 << 16) /* Voltage tamper detected */ | |
63 | #define DSR_WBF (1 << 10) /* Write Busy Flag (synchronous) */ | |
64 | #define DSR_WNF (1 << 9) /* Write Next Flag (synchronous) */ | |
65 | #define DSR_WCF (1 << 8) /* Write Complete Flag (synchronous)*/ | |
eba54546 BS |
66 | #define DSR_WEF (1 << 7) /* Write Error Flag */ |
67 | #define DSR_CAF (1 << 4) /* Clock Alarm Flag */ | |
46edeffa JB |
68 | #define DSR_MCO (1 << 3) /* monotonic counter overflow */ |
69 | #define DSR_TCO (1 << 2) /* time counter overflow */ | |
eba54546 BS |
70 | #define DSR_NVF (1 << 1) /* Non-Valid Flag */ |
71 | #define DSR_SVF (1 << 0) /* Security Violation Flag */ | |
72 | ||
46edeffa | 73 | #define DIER 0x18 /* Interrupt Enable Reg (synchronous) */ |
eba54546 BS |
74 | #define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ |
75 | #define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ | |
76 | #define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ | |
77 | #define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ | |
46edeffa JB |
78 | #define DIER_SVIE (1 << 0) /* Security-violation Interrupt Enable */ |
79 | ||
80 | #define DMCR 0x1c /* DryIce Monotonic Counter Reg */ | |
81 | ||
82 | #define DTCR 0x28 /* DryIce Tamper Configuration Reg */ | |
83 | #define DTCR_MOE (1 << 9) /* monotonic overflow enabled */ | |
84 | #define DTCR_TOE (1 << 8) /* time overflow enabled */ | |
85 | #define DTCR_WTE (1 << 7) /* wire-mesh tamper enabled */ | |
86 | #define DTCR_ETBE (1 << 6) /* external B tamper enabled */ | |
87 | #define DTCR_ETAE (1 << 5) /* external A tamper enabled */ | |
88 | #define DTCR_EBE (1 << 4) /* external boot tamper enabled */ | |
89 | #define DTCR_SAIE (1 << 3) /* SCC enabled */ | |
90 | #define DTCR_TTE (1 << 2) /* temperature tamper enabled */ | |
91 | #define DTCR_CTE (1 << 1) /* clock tamper enabled */ | |
92 | #define DTCR_VTE (1 << 0) /* voltage tamper enabled */ | |
93 | ||
94 | #define DGPR 0x3c /* DryIce General Purpose Reg */ | |
eba54546 BS |
95 | |
96 | /** | |
97 | * struct imxdi_dev - private imxdi rtc data | |
98 | * @pdev: pionter to platform dev | |
99 | * @rtc: pointer to rtc struct | |
100 | * @ioaddr: IO registers pointer | |
eba54546 BS |
101 | * @clk: input reference clock |
102 | * @dsr: copy of the DSR register | |
103 | * @irq_lock: interrupt enable register (DIER) lock | |
104 | * @write_wait: registers write complete queue | |
105 | * @write_mutex: serialize registers write | |
106 | * @work: schedule alarm work | |
107 | */ | |
108 | struct imxdi_dev { | |
109 | struct platform_device *pdev; | |
110 | struct rtc_device *rtc; | |
111 | void __iomem *ioaddr; | |
eba54546 BS |
112 | struct clk *clk; |
113 | u32 dsr; | |
114 | spinlock_t irq_lock; | |
115 | wait_queue_head_t write_wait; | |
116 | struct mutex write_mutex; | |
117 | struct work_struct work; | |
118 | }; | |
119 | ||
3ba3fab7 JB |
120 | /* Some background: |
121 | * | |
122 | * The DryIce unit is a complex security/tamper monitor device. To be able do | |
123 | * its job in a useful manner it runs a bigger statemachine to bring it into | |
124 | * security/tamper failure state and once again to bring it out of this state. | |
125 | * | |
126 | * This unit can be in one of three states: | |
127 | * | |
128 | * - "NON-VALID STATE" | |
129 | * always after the battery power was removed | |
130 | * - "FAILURE STATE" | |
131 | * if one of the enabled security events has happened | |
132 | * - "VALID STATE" | |
133 | * if the unit works as expected | |
134 | * | |
135 | * Everything stops when the unit enters the failure state including the RTC | |
136 | * counter (to be able to detect the time the security event happened). | |
137 | * | |
138 | * The following events (when enabled) let the DryIce unit enter the failure | |
139 | * state: | |
140 | * | |
141 | * - wire-mesh-tamper detect | |
142 | * - external tamper B detect | |
143 | * - external tamper A detect | |
144 | * - temperature tamper detect | |
145 | * - clock tamper detect | |
146 | * - voltage tamper detect | |
147 | * - RTC counter overflow | |
148 | * - monotonic counter overflow | |
149 | * - external boot | |
150 | * | |
151 | * If we find the DryIce unit in "FAILURE STATE" and the TDCHL cleared, we | |
152 | * can only detect this state. In this case the unit is completely locked and | |
153 | * must force a second "SYSTEM POR" to bring the DryIce into the | |
154 | * "NON-VALID STATE" + "FAILURE STATE" where a recovery is possible. | |
155 | * If the TDCHL is set in the "FAILURE STATE" we are out of luck. In this case | |
156 | * a battery power cycle is required. | |
157 | * | |
158 | * In the "NON-VALID STATE" + "FAILURE STATE" we can clear the "FAILURE STATE" | |
159 | * and recover the DryIce unit. By clearing the "NON-VALID STATE" as the last | |
160 | * task, we bring back this unit into life. | |
161 | */ | |
162 | ||
c7e9bbe0 JB |
163 | /* |
164 | * Do a write into the unit without interrupt support. | |
165 | * We do not need to check the WEF here, because the only reason this kind of | |
166 | * write error can happen is if we write to the unit twice within the 122 us | |
167 | * interval. This cannot happen, since we are using this function only while | |
168 | * setting up the unit. | |
169 | */ | |
170 | static void di_write_busy_wait(const struct imxdi_dev *imxdi, u32 val, | |
171 | unsigned reg) | |
172 | { | |
173 | /* do the register write */ | |
174 | writel(val, imxdi->ioaddr + reg); | |
175 | ||
176 | /* | |
177 | * now it takes four 32,768 kHz clock cycles to take | |
178 | * the change into effect = 122 us | |
179 | */ | |
180 | usleep_range(130, 200); | |
181 | } | |
182 | ||
183 | static void di_report_tamper_info(struct imxdi_dev *imxdi, u32 dsr) | |
184 | { | |
185 | u32 dtcr; | |
186 | ||
187 | dtcr = readl(imxdi->ioaddr + DTCR); | |
188 | ||
189 | dev_emerg(&imxdi->pdev->dev, "DryIce tamper event detected\n"); | |
190 | /* the following flags force a transition into the "FAILURE STATE" */ | |
191 | if (dsr & DSR_VTD) | |
192 | dev_emerg(&imxdi->pdev->dev, "%sVoltage Tamper Event\n", | |
193 | dtcr & DTCR_VTE ? "" : "Spurious "); | |
194 | ||
195 | if (dsr & DSR_CTD) | |
196 | dev_emerg(&imxdi->pdev->dev, "%s32768 Hz Clock Tamper Event\n", | |
197 | dtcr & DTCR_CTE ? "" : "Spurious "); | |
198 | ||
199 | if (dsr & DSR_TTD) | |
200 | dev_emerg(&imxdi->pdev->dev, "%sTemperature Tamper Event\n", | |
201 | dtcr & DTCR_TTE ? "" : "Spurious "); | |
202 | ||
203 | if (dsr & DSR_SAD) | |
204 | dev_emerg(&imxdi->pdev->dev, | |
205 | "%sSecure Controller Alarm Event\n", | |
206 | dtcr & DTCR_SAIE ? "" : "Spurious "); | |
207 | ||
208 | if (dsr & DSR_EBD) | |
209 | dev_emerg(&imxdi->pdev->dev, "%sExternal Boot Tamper Event\n", | |
210 | dtcr & DTCR_EBE ? "" : "Spurious "); | |
211 | ||
212 | if (dsr & DSR_ETAD) | |
213 | dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper A Event\n", | |
214 | dtcr & DTCR_ETAE ? "" : "Spurious "); | |
215 | ||
216 | if (dsr & DSR_ETBD) | |
217 | dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper B Event\n", | |
218 | dtcr & DTCR_ETBE ? "" : "Spurious "); | |
219 | ||
220 | if (dsr & DSR_WTD) | |
221 | dev_emerg(&imxdi->pdev->dev, "%sWire-mesh Tamper Event\n", | |
222 | dtcr & DTCR_WTE ? "" : "Spurious "); | |
223 | ||
224 | if (dsr & DSR_MCO) | |
225 | dev_emerg(&imxdi->pdev->dev, | |
226 | "%sMonotonic-counter Overflow Event\n", | |
227 | dtcr & DTCR_MOE ? "" : "Spurious "); | |
228 | ||
229 | if (dsr & DSR_TCO) | |
230 | dev_emerg(&imxdi->pdev->dev, "%sTimer-counter Overflow Event\n", | |
231 | dtcr & DTCR_TOE ? "" : "Spurious "); | |
232 | } | |
233 | ||
234 | static void di_what_is_to_be_done(struct imxdi_dev *imxdi, | |
235 | const char *power_supply) | |
236 | { | |
237 | dev_emerg(&imxdi->pdev->dev, "Please cycle the %s power supply in order to get the DryIce/RTC unit working again\n", | |
238 | power_supply); | |
239 | } | |
240 | ||
241 | static int di_handle_failure_state(struct imxdi_dev *imxdi, u32 dsr) | |
242 | { | |
243 | u32 dcr; | |
244 | ||
245 | dev_dbg(&imxdi->pdev->dev, "DSR register reports: %08X\n", dsr); | |
246 | ||
247 | /* report the cause */ | |
248 | di_report_tamper_info(imxdi, dsr); | |
249 | ||
250 | dcr = readl(imxdi->ioaddr + DCR); | |
251 | ||
252 | if (dcr & DCR_FSHL) { | |
253 | /* we are out of luck */ | |
254 | di_what_is_to_be_done(imxdi, "battery"); | |
255 | return -ENODEV; | |
256 | } | |
257 | /* | |
258 | * with the next SYSTEM POR we will transit from the "FAILURE STATE" | |
259 | * into the "NON-VALID STATE" + "FAILURE STATE" | |
260 | */ | |
261 | di_what_is_to_be_done(imxdi, "main"); | |
262 | ||
263 | return -ENODEV; | |
264 | } | |
265 | ||
266 | static int di_handle_valid_state(struct imxdi_dev *imxdi, u32 dsr) | |
267 | { | |
268 | /* initialize alarm */ | |
269 | di_write_busy_wait(imxdi, DCAMR_UNSET, DCAMR); | |
270 | di_write_busy_wait(imxdi, 0, DCALR); | |
271 | ||
272 | /* clear alarm flag */ | |
273 | if (dsr & DSR_CAF) | |
274 | di_write_busy_wait(imxdi, DSR_CAF, DSR); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | static int di_handle_invalid_state(struct imxdi_dev *imxdi, u32 dsr) | |
280 | { | |
281 | u32 dcr, sec; | |
282 | ||
283 | /* | |
284 | * lets disable all sources which can force the DryIce unit into | |
285 | * the "FAILURE STATE" for now | |
286 | */ | |
287 | di_write_busy_wait(imxdi, 0x00000000, DTCR); | |
288 | /* and lets protect them at runtime from any change */ | |
289 | di_write_busy_wait(imxdi, DCR_TDCSL, DCR); | |
290 | ||
291 | sec = readl(imxdi->ioaddr + DTCMR); | |
292 | if (sec != 0) | |
293 | dev_warn(&imxdi->pdev->dev, | |
d5878a86 | 294 | "The security violation has happened at %u seconds\n", |
c7e9bbe0 JB |
295 | sec); |
296 | /* | |
297 | * the timer cannot be set/modified if | |
298 | * - the TCHL or TCSL bit is set in DCR | |
299 | */ | |
300 | dcr = readl(imxdi->ioaddr + DCR); | |
301 | if (!(dcr & DCR_TCE)) { | |
302 | if (dcr & DCR_TCHL) { | |
303 | /* we are out of luck */ | |
304 | di_what_is_to_be_done(imxdi, "battery"); | |
305 | return -ENODEV; | |
306 | } | |
307 | if (dcr & DCR_TCSL) { | |
308 | di_what_is_to_be_done(imxdi, "main"); | |
309 | return -ENODEV; | |
310 | } | |
311 | } | |
312 | /* | |
313 | * - the timer counter stops/is stopped if | |
314 | * - its overflow flag is set (TCO in DSR) | |
315 | * -> clear overflow bit to make it count again | |
316 | * - NVF is set in DSR | |
317 | * -> clear non-valid bit to make it count again | |
318 | * - its TCE (DCR) is cleared | |
319 | * -> set TCE to make it count | |
320 | * - it was never set before | |
321 | * -> write a time into it (required again if the NVF was set) | |
322 | */ | |
323 | /* state handled */ | |
324 | di_write_busy_wait(imxdi, DSR_NVF, DSR); | |
325 | /* clear overflow flag */ | |
326 | di_write_busy_wait(imxdi, DSR_TCO, DSR); | |
327 | /* enable the counter */ | |
328 | di_write_busy_wait(imxdi, dcr | DCR_TCE, DCR); | |
329 | /* set and trigger it to make it count */ | |
330 | di_write_busy_wait(imxdi, sec, DTCMR); | |
331 | ||
332 | /* now prepare for the valid state */ | |
333 | return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR)); | |
334 | } | |
335 | ||
336 | static int di_handle_invalid_and_failure_state(struct imxdi_dev *imxdi, u32 dsr) | |
337 | { | |
338 | u32 dcr; | |
339 | ||
340 | /* | |
341 | * now we must first remove the tamper sources in order to get the | |
342 | * device out of the "FAILURE STATE" | |
343 | * To disable any of the following sources we need to modify the DTCR | |
344 | */ | |
345 | if (dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD | | |
346 | DSR_TTD | DSR_CTD | DSR_VTD | DSR_MCO | DSR_TCO)) { | |
347 | dcr = __raw_readl(imxdi->ioaddr + DCR); | |
348 | if (dcr & DCR_TDCHL) { | |
349 | /* | |
350 | * the tamper register is locked. We cannot disable the | |
351 | * tamper detection. The TDCHL can only be reset by a | |
352 | * DRYICE POR, but we cannot force a DRYICE POR in | |
353 | * softwere because we are still in "FAILURE STATE". | |
354 | * We need a DRYICE POR via battery power cycling.... | |
355 | */ | |
356 | /* | |
357 | * out of luck! | |
358 | * we cannot disable them without a DRYICE POR | |
359 | */ | |
360 | di_what_is_to_be_done(imxdi, "battery"); | |
361 | return -ENODEV; | |
362 | } | |
363 | if (dcr & DCR_TDCSL) { | |
364 | /* a soft lock can be removed by a SYSTEM POR */ | |
365 | di_what_is_to_be_done(imxdi, "main"); | |
366 | return -ENODEV; | |
367 | } | |
368 | } | |
369 | ||
370 | /* disable all sources */ | |
371 | di_write_busy_wait(imxdi, 0x00000000, DTCR); | |
372 | ||
373 | /* clear the status bits now */ | |
374 | di_write_busy_wait(imxdi, dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD | | |
375 | DSR_EBD | DSR_SAD | DSR_TTD | DSR_CTD | DSR_VTD | | |
376 | DSR_MCO | DSR_TCO), DSR); | |
377 | ||
378 | dsr = readl(imxdi->ioaddr + DSR); | |
379 | if ((dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF | | |
380 | DSR_WCF | DSR_WEF)) != 0) | |
381 | dev_warn(&imxdi->pdev->dev, | |
382 | "There are still some sources of pain in DSR: %08x!\n", | |
383 | dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF | | |
384 | DSR_WCF | DSR_WEF)); | |
385 | ||
386 | /* | |
387 | * now we are trying to clear the "Security-violation flag" to | |
388 | * get the DryIce out of this state | |
389 | */ | |
390 | di_write_busy_wait(imxdi, DSR_SVF, DSR); | |
391 | ||
392 | /* success? */ | |
393 | dsr = readl(imxdi->ioaddr + DSR); | |
394 | if (dsr & DSR_SVF) { | |
395 | dev_crit(&imxdi->pdev->dev, | |
396 | "Cannot clear the security violation flag. We are ending up in an endless loop!\n"); | |
397 | /* last resort */ | |
398 | di_what_is_to_be_done(imxdi, "battery"); | |
399 | return -ENODEV; | |
400 | } | |
401 | ||
402 | /* | |
403 | * now we have left the "FAILURE STATE" and ending up in the | |
404 | * "NON-VALID STATE" time to recover everything | |
405 | */ | |
406 | return di_handle_invalid_state(imxdi, dsr); | |
407 | } | |
408 | ||
409 | static int di_handle_state(struct imxdi_dev *imxdi) | |
410 | { | |
411 | int rc; | |
412 | u32 dsr; | |
413 | ||
414 | dsr = readl(imxdi->ioaddr + DSR); | |
415 | ||
416 | switch (dsr & (DSR_NVF | DSR_SVF)) { | |
417 | case DSR_NVF: | |
418 | dev_warn(&imxdi->pdev->dev, "Invalid stated unit detected\n"); | |
419 | rc = di_handle_invalid_state(imxdi, dsr); | |
420 | break; | |
421 | case DSR_SVF: | |
422 | dev_warn(&imxdi->pdev->dev, "Failure stated unit detected\n"); | |
423 | rc = di_handle_failure_state(imxdi, dsr); | |
424 | break; | |
425 | case DSR_NVF | DSR_SVF: | |
426 | dev_warn(&imxdi->pdev->dev, | |
427 | "Failure+Invalid stated unit detected\n"); | |
428 | rc = di_handle_invalid_and_failure_state(imxdi, dsr); | |
429 | break; | |
430 | default: | |
431 | dev_notice(&imxdi->pdev->dev, "Unlocked unit detected\n"); | |
432 | rc = di_handle_valid_state(imxdi, dsr); | |
433 | } | |
434 | ||
435 | return rc; | |
436 | } | |
437 | ||
eba54546 BS |
438 | /* |
439 | * enable a dryice interrupt | |
440 | */ | |
441 | static void di_int_enable(struct imxdi_dev *imxdi, u32 intr) | |
442 | { | |
443 | unsigned long flags; | |
444 | ||
445 | spin_lock_irqsave(&imxdi->irq_lock, flags); | |
e30d3131 JB |
446 | writel(readl(imxdi->ioaddr + DIER) | intr, |
447 | imxdi->ioaddr + DIER); | |
eba54546 BS |
448 | spin_unlock_irqrestore(&imxdi->irq_lock, flags); |
449 | } | |
450 | ||
451 | /* | |
452 | * disable a dryice interrupt | |
453 | */ | |
454 | static void di_int_disable(struct imxdi_dev *imxdi, u32 intr) | |
455 | { | |
456 | unsigned long flags; | |
457 | ||
458 | spin_lock_irqsave(&imxdi->irq_lock, flags); | |
e30d3131 JB |
459 | writel(readl(imxdi->ioaddr + DIER) & ~intr, |
460 | imxdi->ioaddr + DIER); | |
eba54546 BS |
461 | spin_unlock_irqrestore(&imxdi->irq_lock, flags); |
462 | } | |
463 | ||
464 | /* | |
465 | * This function attempts to clear the dryice write-error flag. | |
466 | * | |
467 | * A dryice write error is similar to a bus fault and should not occur in | |
468 | * normal operation. Clearing the flag requires another write, so the root | |
469 | * cause of the problem may need to be fixed before the flag can be cleared. | |
470 | */ | |
471 | static void clear_write_error(struct imxdi_dev *imxdi) | |
472 | { | |
473 | int cnt; | |
474 | ||
475 | dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n"); | |
476 | ||
477 | /* clear the write error flag */ | |
e30d3131 | 478 | writel(DSR_WEF, imxdi->ioaddr + DSR); |
eba54546 BS |
479 | |
480 | /* wait for it to take effect */ | |
481 | for (cnt = 0; cnt < 1000; cnt++) { | |
e30d3131 | 482 | if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0) |
eba54546 BS |
483 | return; |
484 | udelay(10); | |
485 | } | |
486 | dev_err(&imxdi->pdev->dev, | |
487 | "ERROR: Cannot clear write-error flag!\n"); | |
488 | } | |
489 | ||
490 | /* | |
491 | * Write a dryice register and wait until it completes. | |
492 | * | |
493 | * This function uses interrupts to determine when the | |
494 | * write has completed. | |
495 | */ | |
496 | static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg) | |
497 | { | |
498 | int ret; | |
499 | int rc = 0; | |
500 | ||
501 | /* serialize register writes */ | |
502 | mutex_lock(&imxdi->write_mutex); | |
503 | ||
504 | /* enable the write-complete interrupt */ | |
505 | di_int_enable(imxdi, DIER_WCIE); | |
506 | ||
507 | imxdi->dsr = 0; | |
508 | ||
509 | /* do the register write */ | |
e30d3131 | 510 | writel(val, imxdi->ioaddr + reg); |
eba54546 BS |
511 | |
512 | /* wait for the write to finish */ | |
513 | ret = wait_event_interruptible_timeout(imxdi->write_wait, | |
514 | imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1)); | |
515 | if (ret < 0) { | |
516 | rc = ret; | |
517 | goto out; | |
518 | } else if (ret == 0) { | |
519 | dev_warn(&imxdi->pdev->dev, | |
520 | "Write-wait timeout " | |
521 | "val = 0x%08x reg = 0x%08x\n", val, reg); | |
522 | } | |
523 | ||
524 | /* check for write error */ | |
525 | if (imxdi->dsr & DSR_WEF) { | |
526 | clear_write_error(imxdi); | |
527 | rc = -EIO; | |
528 | } | |
529 | ||
530 | out: | |
531 | mutex_unlock(&imxdi->write_mutex); | |
532 | ||
533 | return rc; | |
534 | } | |
535 | ||
536 | /* | |
537 | * read the seconds portion of the current time from the dryice time counter | |
538 | */ | |
539 | static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
540 | { | |
541 | struct imxdi_dev *imxdi = dev_get_drvdata(dev); | |
542 | unsigned long now; | |
543 | ||
e30d3131 | 544 | now = readl(imxdi->ioaddr + DTCMR); |
93059793 | 545 | rtc_time64_to_tm(now, tm); |
eba54546 BS |
546 | |
547 | return 0; | |
548 | } | |
549 | ||
550 | /* | |
551 | * set the seconds portion of dryice time counter and clear the | |
552 | * fractional part. | |
553 | */ | |
d231d32c | 554 | static int dryice_rtc_set_time(struct device *dev, struct rtc_time *tm) |
eba54546 BS |
555 | { |
556 | struct imxdi_dev *imxdi = dev_get_drvdata(dev); | |
9bb698c6 | 557 | u32 dcr, dsr; |
eba54546 BS |
558 | int rc; |
559 | ||
9bb698c6 JB |
560 | dcr = readl(imxdi->ioaddr + DCR); |
561 | dsr = readl(imxdi->ioaddr + DSR); | |
562 | ||
563 | if (!(dcr & DCR_TCE) || (dsr & DSR_SVF)) { | |
564 | if (dcr & DCR_TCHL) { | |
565 | /* we are even more out of luck */ | |
566 | di_what_is_to_be_done(imxdi, "battery"); | |
567 | return -EPERM; | |
568 | } | |
569 | if ((dcr & DCR_TCSL) || (dsr & DSR_SVF)) { | |
570 | /* we are out of luck for now */ | |
571 | di_what_is_to_be_done(imxdi, "main"); | |
572 | return -EPERM; | |
573 | } | |
574 | } | |
575 | ||
eba54546 BS |
576 | /* zero the fractional part first */ |
577 | rc = di_write_wait(imxdi, 0, DTCLR); | |
9bb698c6 JB |
578 | if (rc != 0) |
579 | return rc; | |
eba54546 | 580 | |
d231d32c | 581 | rc = di_write_wait(imxdi, rtc_tm_to_time64(tm), DTCMR); |
9bb698c6 JB |
582 | if (rc != 0) |
583 | return rc; | |
584 | ||
585 | return di_write_wait(imxdi, readl(imxdi->ioaddr + DCR) | DCR_TCE, DCR); | |
eba54546 BS |
586 | } |
587 | ||
588 | static int dryice_rtc_alarm_irq_enable(struct device *dev, | |
589 | unsigned int enabled) | |
590 | { | |
591 | struct imxdi_dev *imxdi = dev_get_drvdata(dev); | |
592 | ||
593 | if (enabled) | |
594 | di_int_enable(imxdi, DIER_CAIE); | |
595 | else | |
596 | di_int_disable(imxdi, DIER_CAIE); | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | /* | |
602 | * read the seconds portion of the alarm register. | |
603 | * the fractional part of the alarm register is always zero. | |
604 | */ | |
605 | static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
606 | { | |
607 | struct imxdi_dev *imxdi = dev_get_drvdata(dev); | |
608 | u32 dcamr; | |
609 | ||
e30d3131 | 610 | dcamr = readl(imxdi->ioaddr + DCAMR); |
93059793 | 611 | rtc_time64_to_tm(dcamr, &alarm->time); |
eba54546 BS |
612 | |
613 | /* alarm is enabled if the interrupt is enabled */ | |
e30d3131 | 614 | alarm->enabled = (readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0; |
eba54546 BS |
615 | |
616 | /* don't allow the DSR read to mess up DSR_WCF */ | |
617 | mutex_lock(&imxdi->write_mutex); | |
618 | ||
619 | /* alarm is pending if the alarm flag is set */ | |
e30d3131 | 620 | alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0; |
eba54546 BS |
621 | |
622 | mutex_unlock(&imxdi->write_mutex); | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | /* | |
628 | * set the seconds portion of dryice alarm register | |
629 | */ | |
630 | static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
631 | { | |
632 | struct imxdi_dev *imxdi = dev_get_drvdata(dev); | |
eba54546 BS |
633 | int rc; |
634 | ||
eba54546 | 635 | /* write the new alarm time */ |
629d488a | 636 | rc = di_write_wait(imxdi, rtc_tm_to_time64(&alarm->time), DCAMR); |
eba54546 BS |
637 | if (rc) |
638 | return rc; | |
639 | ||
640 | if (alarm->enabled) | |
641 | di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */ | |
642 | else | |
643 | di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */ | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
8bc57e7f | 648 | static const struct rtc_class_ops dryice_rtc_ops = { |
eba54546 | 649 | .read_time = dryice_rtc_read_time, |
d231d32c | 650 | .set_time = dryice_rtc_set_time, |
eba54546 BS |
651 | .alarm_irq_enable = dryice_rtc_alarm_irq_enable, |
652 | .read_alarm = dryice_rtc_read_alarm, | |
653 | .set_alarm = dryice_rtc_set_alarm, | |
654 | }; | |
655 | ||
656 | /* | |
fef1eeb1 | 657 | * interrupt handler for dryice "normal" and security violation interrupt |
eba54546 | 658 | */ |
fef1eeb1 | 659 | static irqreturn_t dryice_irq(int irq, void *dev_id) |
eba54546 BS |
660 | { |
661 | struct imxdi_dev *imxdi = dev_id; | |
662 | u32 dsr, dier; | |
663 | irqreturn_t rc = IRQ_NONE; | |
664 | ||
e30d3131 | 665 | dier = readl(imxdi->ioaddr + DIER); |
a7c535e3 JB |
666 | dsr = readl(imxdi->ioaddr + DSR); |
667 | ||
668 | /* handle the security violation event */ | |
669 | if (dier & DIER_SVIE) { | |
670 | if (dsr & DSR_SVF) { | |
671 | /* | |
672 | * Disable the interrupt when this kind of event has | |
673 | * happened. | |
674 | * There cannot be more than one event of this type, | |
675 | * because it needs a complex state change | |
676 | * including a main power cycle to get again out of | |
677 | * this state. | |
678 | */ | |
679 | di_int_disable(imxdi, DIER_SVIE); | |
680 | /* report the violation */ | |
681 | di_report_tamper_info(imxdi, dsr); | |
682 | rc = IRQ_HANDLED; | |
683 | } | |
684 | } | |
eba54546 BS |
685 | |
686 | /* handle write complete and write error cases */ | |
6df17a65 | 687 | if (dier & DIER_WCIE) { |
eba54546 BS |
688 | /*If the write wait queue is empty then there is no pending |
689 | operations. It means the interrupt is for DryIce -Security. | |
690 | IRQ must be returned as none.*/ | |
2055da97 | 691 | if (list_empty_careful(&imxdi->write_wait.head)) |
eba54546 BS |
692 | return rc; |
693 | ||
694 | /* DSR_WCF clears itself on DSR read */ | |
6df17a65 | 695 | if (dsr & (DSR_WCF | DSR_WEF)) { |
eba54546 BS |
696 | /* mask the interrupt */ |
697 | di_int_disable(imxdi, DIER_WCIE); | |
698 | ||
699 | /* save the dsr value for the wait queue */ | |
700 | imxdi->dsr |= dsr; | |
701 | ||
702 | wake_up_interruptible(&imxdi->write_wait); | |
703 | rc = IRQ_HANDLED; | |
704 | } | |
705 | } | |
706 | ||
707 | /* handle the alarm case */ | |
6df17a65 | 708 | if (dier & DIER_CAIE) { |
eba54546 | 709 | /* DSR_WCF clears itself on DSR read */ |
eba54546 BS |
710 | if (dsr & DSR_CAF) { |
711 | /* mask the interrupt */ | |
712 | di_int_disable(imxdi, DIER_CAIE); | |
713 | ||
714 | /* finish alarm in user context */ | |
715 | schedule_work(&imxdi->work); | |
716 | rc = IRQ_HANDLED; | |
717 | } | |
718 | } | |
719 | return rc; | |
720 | } | |
721 | ||
722 | /* | |
723 | * post the alarm event from user context so it can sleep | |
724 | * on the write completion. | |
725 | */ | |
726 | static void dryice_work(struct work_struct *work) | |
727 | { | |
728 | struct imxdi_dev *imxdi = container_of(work, | |
729 | struct imxdi_dev, work); | |
730 | ||
731 | /* dismiss the interrupt (ignore error) */ | |
732 | di_write_wait(imxdi, DSR_CAF, DSR); | |
733 | ||
734 | /* pass the alarm event to the rtc framework. */ | |
735 | rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF); | |
736 | } | |
737 | ||
738 | /* | |
739 | * probe for dryice rtc device | |
740 | */ | |
5073cba6 | 741 | static int __init dryice_rtc_probe(struct platform_device *pdev) |
eba54546 BS |
742 | { |
743 | struct resource *res; | |
744 | struct imxdi_dev *imxdi; | |
fef1eeb1 | 745 | int norm_irq, sec_irq; |
eba54546 BS |
746 | int rc; |
747 | ||
eba54546 BS |
748 | imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL); |
749 | if (!imxdi) | |
750 | return -ENOMEM; | |
751 | ||
752 | imxdi->pdev = pdev; | |
753 | ||
7c1d69ee JL |
754 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
755 | imxdi->ioaddr = devm_ioremap_resource(&pdev->dev, res); | |
756 | if (IS_ERR(imxdi->ioaddr)) | |
757 | return PTR_ERR(imxdi->ioaddr); | |
eba54546 | 758 | |
fee0de77 JL |
759 | spin_lock_init(&imxdi->irq_lock); |
760 | ||
fef1eeb1 MK |
761 | norm_irq = platform_get_irq(pdev, 0); |
762 | if (norm_irq < 0) | |
763 | return norm_irq; | |
764 | ||
765 | /* the 2nd irq is the security violation irq | |
766 | * make this optional, don't break the device tree ABI | |
767 | */ | |
768 | sec_irq = platform_get_irq(pdev, 1); | |
769 | if (sec_irq <= 0) | |
770 | sec_irq = IRQ_NOTCONNECTED; | |
eba54546 BS |
771 | |
772 | init_waitqueue_head(&imxdi->write_wait); | |
773 | ||
774 | INIT_WORK(&imxdi->work, dryice_work); | |
775 | ||
776 | mutex_init(&imxdi->write_mutex); | |
777 | ||
21c9dfda AB |
778 | imxdi->rtc = devm_rtc_allocate_device(&pdev->dev); |
779 | if (IS_ERR(imxdi->rtc)) | |
780 | return PTR_ERR(imxdi->rtc); | |
781 | ||
9510853c | 782 | imxdi->clk = devm_clk_get(&pdev->dev, NULL); |
eba54546 BS |
783 | if (IS_ERR(imxdi->clk)) |
784 | return PTR_ERR(imxdi->clk); | |
3378f73d FE |
785 | rc = clk_prepare_enable(imxdi->clk); |
786 | if (rc) | |
787 | return rc; | |
eba54546 BS |
788 | |
789 | /* | |
790 | * Initialize dryice hardware | |
791 | */ | |
792 | ||
793 | /* mask all interrupts */ | |
e30d3131 | 794 | writel(0, imxdi->ioaddr + DIER); |
eba54546 | 795 | |
c7e9bbe0 JB |
796 | rc = di_handle_state(imxdi); |
797 | if (rc != 0) | |
798 | goto err; | |
799 | ||
fef1eeb1 MK |
800 | rc = devm_request_irq(&pdev->dev, norm_irq, dryice_irq, |
801 | IRQF_SHARED, pdev->name, imxdi); | |
eba54546 BS |
802 | if (rc) { |
803 | dev_warn(&pdev->dev, "interrupt not available.\n"); | |
804 | goto err; | |
805 | } | |
806 | ||
fef1eeb1 MK |
807 | rc = devm_request_irq(&pdev->dev, sec_irq, dryice_irq, |
808 | IRQF_SHARED, pdev->name, imxdi); | |
809 | if (rc) { | |
810 | dev_warn(&pdev->dev, "security violation interrupt not available.\n"); | |
811 | /* this is not an error, see above */ | |
812 | } | |
813 | ||
eba54546 | 814 | platform_set_drvdata(pdev, imxdi); |
21c9dfda AB |
815 | |
816 | imxdi->rtc->ops = &dryice_rtc_ops; | |
817 | imxdi->rtc->range_max = U32_MAX; | |
818 | ||
819 | rc = rtc_register_device(imxdi->rtc); | |
820 | if (rc) | |
eba54546 | 821 | goto err; |
eba54546 BS |
822 | |
823 | return 0; | |
824 | ||
825 | err: | |
4ec8c7f5 | 826 | clk_disable_unprepare(imxdi->clk); |
eba54546 BS |
827 | |
828 | return rc; | |
829 | } | |
830 | ||
5073cba6 | 831 | static int __exit dryice_rtc_remove(struct platform_device *pdev) |
eba54546 BS |
832 | { |
833 | struct imxdi_dev *imxdi = platform_get_drvdata(pdev); | |
834 | ||
835 | flush_work(&imxdi->work); | |
836 | ||
837 | /* mask all interrupts */ | |
e30d3131 | 838 | writel(0, imxdi->ioaddr + DIER); |
eba54546 | 839 | |
4ec8c7f5 | 840 | clk_disable_unprepare(imxdi->clk); |
eba54546 BS |
841 | |
842 | return 0; | |
843 | } | |
844 | ||
968d21c2 RS |
845 | #ifdef CONFIG_OF |
846 | static const struct of_device_id dryice_dt_ids[] = { | |
847 | { .compatible = "fsl,imx25-rtc" }, | |
848 | { /* sentinel */ } | |
849 | }; | |
850 | ||
851 | MODULE_DEVICE_TABLE(of, dryice_dt_ids); | |
852 | #endif | |
853 | ||
eba54546 BS |
854 | static struct platform_driver dryice_rtc_driver = { |
855 | .driver = { | |
856 | .name = "imxdi_rtc", | |
968d21c2 | 857 | .of_match_table = of_match_ptr(dryice_dt_ids), |
eba54546 | 858 | }, |
5073cba6 | 859 | .remove = __exit_p(dryice_rtc_remove), |
eba54546 BS |
860 | }; |
861 | ||
61534342 | 862 | module_platform_driver_probe(dryice_rtc_driver, dryice_rtc_probe); |
eba54546 BS |
863 | |
864 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
865 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
866 | MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)"); | |
867 | MODULE_LICENSE("GPL"); |