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f22d9cdc MD |
1 | /* drivers/rtc/rtc-goldfish.c |
2 | * | |
3 | * Copyright (C) 2007 Google, Inc. | |
4 | * Copyright (C) 2017 Imagination Technologies Ltd. | |
5 | * | |
6 | * This software is licensed under the terms of the GNU General Public | |
7 | * License version 2, as published by the Free Software Foundation, and | |
8 | * may be copied, distributed, and modified under those terms. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
bd01386e | 17 | #include <linux/io.h> |
f22d9cdc | 18 | #include <linux/module.h> |
6a6ec8c1 | 19 | #include <linux/of.h> |
f22d9cdc MD |
20 | #include <linux/platform_device.h> |
21 | #include <linux/rtc.h> | |
f22d9cdc MD |
22 | |
23 | #define TIMER_TIME_LOW 0x00 /* get low bits of current time */ | |
24 | /* and update TIMER_TIME_HIGH */ | |
25 | #define TIMER_TIME_HIGH 0x04 /* get high bits of time at last */ | |
26 | /* TIMER_TIME_LOW read */ | |
27 | #define TIMER_ALARM_LOW 0x08 /* set low bits of alarm and */ | |
28 | /* activate it */ | |
29 | #define TIMER_ALARM_HIGH 0x0c /* set high bits of next alarm */ | |
30 | #define TIMER_IRQ_ENABLED 0x10 | |
31 | #define TIMER_CLEAR_ALARM 0x14 | |
32 | #define TIMER_ALARM_STATUS 0x18 | |
33 | #define TIMER_CLEAR_INTERRUPT 0x1c | |
34 | ||
35 | struct goldfish_rtc { | |
36 | void __iomem *base; | |
37 | int irq; | |
38 | struct rtc_device *rtc; | |
39 | }; | |
40 | ||
41 | static int goldfish_rtc_read_alarm(struct device *dev, | |
42 | struct rtc_wkalrm *alrm) | |
43 | { | |
44 | u64 rtc_alarm; | |
45 | u64 rtc_alarm_low; | |
46 | u64 rtc_alarm_high; | |
47 | void __iomem *base; | |
48 | struct goldfish_rtc *rtcdrv; | |
49 | ||
50 | rtcdrv = dev_get_drvdata(dev); | |
51 | base = rtcdrv->base; | |
52 | ||
53 | rtc_alarm_low = readl(base + TIMER_ALARM_LOW); | |
54 | rtc_alarm_high = readl(base + TIMER_ALARM_HIGH); | |
55 | rtc_alarm = (rtc_alarm_high << 32) | rtc_alarm_low; | |
56 | ||
57 | do_div(rtc_alarm, NSEC_PER_SEC); | |
58 | memset(alrm, 0, sizeof(struct rtc_wkalrm)); | |
59 | ||
60 | rtc_time_to_tm(rtc_alarm, &alrm->time); | |
61 | ||
62 | if (readl(base + TIMER_ALARM_STATUS)) | |
63 | alrm->enabled = 1; | |
64 | else | |
65 | alrm->enabled = 0; | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | static int goldfish_rtc_set_alarm(struct device *dev, | |
71 | struct rtc_wkalrm *alrm) | |
72 | { | |
73 | struct goldfish_rtc *rtcdrv; | |
74 | unsigned long rtc_alarm; | |
75 | u64 rtc_alarm64; | |
76 | u64 rtc_status_reg; | |
77 | void __iomem *base; | |
78 | int ret = 0; | |
79 | ||
80 | rtcdrv = dev_get_drvdata(dev); | |
81 | base = rtcdrv->base; | |
82 | ||
83 | if (alrm->enabled) { | |
84 | ret = rtc_tm_to_time(&alrm->time, &rtc_alarm); | |
85 | if (ret != 0) | |
86 | return ret; | |
87 | ||
88 | rtc_alarm64 = rtc_alarm * NSEC_PER_SEC; | |
89 | writel((rtc_alarm64 >> 32), base + TIMER_ALARM_HIGH); | |
90 | writel(rtc_alarm64, base + TIMER_ALARM_LOW); | |
91 | } else { | |
92 | /* | |
93 | * if this function was called with enabled=0 | |
94 | * then it could mean that the application is | |
95 | * trying to cancel an ongoing alarm | |
96 | */ | |
97 | rtc_status_reg = readl(base + TIMER_ALARM_STATUS); | |
98 | if (rtc_status_reg) | |
99 | writel(1, base + TIMER_CLEAR_ALARM); | |
100 | } | |
101 | ||
102 | return ret; | |
103 | } | |
104 | ||
105 | static int goldfish_rtc_alarm_irq_enable(struct device *dev, | |
106 | unsigned int enabled) | |
107 | { | |
108 | void __iomem *base; | |
109 | struct goldfish_rtc *rtcdrv; | |
110 | ||
111 | rtcdrv = dev_get_drvdata(dev); | |
112 | base = rtcdrv->base; | |
113 | ||
114 | if (enabled) | |
115 | writel(1, base + TIMER_IRQ_ENABLED); | |
116 | else | |
117 | writel(0, base + TIMER_IRQ_ENABLED); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
122 | static irqreturn_t goldfish_rtc_interrupt(int irq, void *dev_id) | |
123 | { | |
124 | struct goldfish_rtc *rtcdrv = dev_id; | |
125 | void __iomem *base = rtcdrv->base; | |
126 | ||
127 | writel(1, base + TIMER_CLEAR_INTERRUPT); | |
128 | ||
129 | rtc_update_irq(rtcdrv->rtc, 1, RTC_IRQF | RTC_AF); | |
130 | ||
131 | return IRQ_HANDLED; | |
132 | } | |
133 | ||
134 | static int goldfish_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
135 | { | |
136 | struct goldfish_rtc *rtcdrv; | |
137 | void __iomem *base; | |
138 | u64 time_high; | |
139 | u64 time_low; | |
140 | u64 time; | |
141 | ||
142 | rtcdrv = dev_get_drvdata(dev); | |
143 | base = rtcdrv->base; | |
144 | ||
145 | time_low = readl(base + TIMER_TIME_LOW); | |
146 | time_high = readl(base + TIMER_TIME_HIGH); | |
147 | time = (time_high << 32) | time_low; | |
148 | ||
149 | do_div(time, NSEC_PER_SEC); | |
150 | ||
151 | rtc_time_to_tm(time, tm); | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | static int goldfish_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
157 | { | |
158 | struct goldfish_rtc *rtcdrv; | |
159 | void __iomem *base; | |
160 | unsigned long now; | |
161 | u64 now64; | |
162 | int ret; | |
163 | ||
164 | rtcdrv = dev_get_drvdata(dev); | |
165 | base = rtcdrv->base; | |
166 | ||
167 | ret = rtc_tm_to_time(tm, &now); | |
168 | if (ret == 0) { | |
169 | now64 = now * NSEC_PER_SEC; | |
170 | writel((now64 >> 32), base + TIMER_TIME_HIGH); | |
171 | writel(now64, base + TIMER_TIME_LOW); | |
172 | } | |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
177 | static const struct rtc_class_ops goldfish_rtc_ops = { | |
178 | .read_time = goldfish_rtc_read_time, | |
179 | .set_time = goldfish_rtc_set_time, | |
180 | .read_alarm = goldfish_rtc_read_alarm, | |
181 | .set_alarm = goldfish_rtc_set_alarm, | |
182 | .alarm_irq_enable = goldfish_rtc_alarm_irq_enable | |
183 | }; | |
184 | ||
185 | static int goldfish_rtc_probe(struct platform_device *pdev) | |
186 | { | |
187 | struct goldfish_rtc *rtcdrv; | |
188 | struct resource *r; | |
189 | int err; | |
190 | ||
191 | rtcdrv = devm_kzalloc(&pdev->dev, sizeof(*rtcdrv), GFP_KERNEL); | |
192 | if (!rtcdrv) | |
193 | return -ENOMEM; | |
194 | ||
195 | platform_set_drvdata(pdev, rtcdrv); | |
196 | ||
197 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
198 | if (!r) | |
199 | return -ENODEV; | |
200 | ||
201 | rtcdrv->base = devm_ioremap_resource(&pdev->dev, r); | |
202 | if (IS_ERR(rtcdrv->base)) | |
203 | return -ENODEV; | |
204 | ||
205 | rtcdrv->irq = platform_get_irq(pdev, 0); | |
206 | if (rtcdrv->irq < 0) | |
207 | return -ENODEV; | |
208 | ||
409b84e3 | 209 | rtcdrv->rtc = devm_rtc_allocate_device(&pdev->dev); |
f22d9cdc MD |
210 | if (IS_ERR(rtcdrv->rtc)) |
211 | return PTR_ERR(rtcdrv->rtc); | |
212 | ||
409b84e3 | 213 | rtcdrv->rtc->ops = &goldfish_rtc_ops; |
5e2954fd | 214 | rtcdrv->rtc->range_max = U64_MAX / NSEC_PER_SEC; |
409b84e3 | 215 | |
f22d9cdc MD |
216 | err = devm_request_irq(&pdev->dev, rtcdrv->irq, |
217 | goldfish_rtc_interrupt, | |
218 | 0, pdev->name, rtcdrv); | |
219 | if (err) | |
220 | return err; | |
221 | ||
409b84e3 | 222 | return rtc_register_device(rtcdrv->rtc); |
f22d9cdc MD |
223 | } |
224 | ||
225 | static const struct of_device_id goldfish_rtc_of_match[] = { | |
226 | { .compatible = "google,goldfish-rtc", }, | |
227 | {}, | |
228 | }; | |
229 | MODULE_DEVICE_TABLE(of, goldfish_rtc_of_match); | |
230 | ||
231 | static struct platform_driver goldfish_rtc = { | |
232 | .probe = goldfish_rtc_probe, | |
233 | .driver = { | |
234 | .name = "goldfish_rtc", | |
235 | .of_match_table = goldfish_rtc_of_match, | |
236 | } | |
237 | }; | |
238 | ||
239 | module_platform_driver(goldfish_rtc); | |
82d632b8 JH |
240 | |
241 | MODULE_LICENSE("GPL v2"); |