drm/amdgpu: change gfx 11.0.4 external_id range
[linux-block.git] / drivers / rtc / rtc-ds1742.c
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
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2/*
3 * An rtc driver for the Dallas DS1742
4 *
5 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
6 *
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7 * Copyright (C) 2006 Torsten Ertbjerg Rasmussen <tr@newtec.dk>
8 * - nvram size determined from resource
9 * - this ds1742 driver now supports ds1743.
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10 */
11
12#include <linux/bcd.h>
5ec3e4b7 13#include <linux/kernel.h>
5a0e3ad6 14#include <linux/gfp.h>
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15#include <linux/delay.h>
16#include <linux/jiffies.h>
17#include <linux/rtc.h>
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18#include <linux/of.h>
19#include <linux/of_device.h>
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20#include <linux/platform_device.h>
21#include <linux/io.h>
2113852b 22#include <linux/module.h>
5ec3e4b7 23
f9231a0c 24#define RTC_SIZE 8
5ec3e4b7 25
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26#define RTC_CONTROL 0
27#define RTC_CENTURY 0
28#define RTC_SECONDS 1
29#define RTC_MINUTES 2
30#define RTC_HOURS 3
31#define RTC_DAY 4
32#define RTC_DATE 5
33#define RTC_MONTH 6
34#define RTC_YEAR 7
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35
36#define RTC_CENTURY_MASK 0x3f
37#define RTC_SECONDS_MASK 0x7f
38#define RTC_DAY_MASK 0x07
39
40/* Bits in the Control/Century register */
41#define RTC_WRITE 0x80
42#define RTC_READ 0x40
43
44/* Bits in the Seconds register */
45#define RTC_STOP 0x80
46
47/* Bits in the Day register */
48#define RTC_BATT_FLAG 0x80
49
50struct rtc_plat_data {
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51 void __iomem *ioaddr_nvram;
52 void __iomem *ioaddr_rtc;
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53 unsigned long last_jiffies;
54};
55
56static int ds1742_rtc_set_time(struct device *dev, struct rtc_time *tm)
57{
85368bb9 58 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
f9231a0c 59 void __iomem *ioaddr = pdata->ioaddr_rtc;
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60 u8 century;
61
fe20ba70 62 century = bin2bcd((tm->tm_year + 1900) / 100);
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63
64 writeb(RTC_WRITE, ioaddr + RTC_CONTROL);
65
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66 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR);
67 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH);
68 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY);
69 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE);
70 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS);
71 writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES);
72 writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS);
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73
74 /* RTC_CENTURY and RTC_CONTROL share same register */
75 writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr + RTC_CENTURY);
76 writeb(century & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
77 return 0;
78}
79
80static int ds1742_rtc_read_time(struct device *dev, struct rtc_time *tm)
81{
85368bb9 82 struct rtc_plat_data *pdata = dev_get_drvdata(dev);
f9231a0c 83 void __iomem *ioaddr = pdata->ioaddr_rtc;
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84 unsigned int year, month, day, hour, minute, second, week;
85 unsigned int century;
86
87 /* give enough time to update RTC in case of continuous read */
88 if (pdata->last_jiffies == jiffies)
89 msleep(1);
90 pdata->last_jiffies = jiffies;
91 writeb(RTC_READ, ioaddr + RTC_CONTROL);
92 second = readb(ioaddr + RTC_SECONDS) & RTC_SECONDS_MASK;
93 minute = readb(ioaddr + RTC_MINUTES);
94 hour = readb(ioaddr + RTC_HOURS);
95 day = readb(ioaddr + RTC_DATE);
96 week = readb(ioaddr + RTC_DAY) & RTC_DAY_MASK;
97 month = readb(ioaddr + RTC_MONTH);
98 year = readb(ioaddr + RTC_YEAR);
99 century = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
100 writeb(0, ioaddr + RTC_CONTROL);
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101 tm->tm_sec = bcd2bin(second);
102 tm->tm_min = bcd2bin(minute);
103 tm->tm_hour = bcd2bin(hour);
104 tm->tm_mday = bcd2bin(day);
105 tm->tm_wday = bcd2bin(week);
106 tm->tm_mon = bcd2bin(month) - 1;
5ec3e4b7 107 /* year is 1900 + tm->tm_year */
fe20ba70 108 tm->tm_year = bcd2bin(year) + bcd2bin(century) * 100 - 1900;
5ec3e4b7 109
22652ba7 110 return 0;
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111}
112
ff8371ac 113static const struct rtc_class_ops ds1742_rtc_ops = {
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114 .read_time = ds1742_rtc_read_time,
115 .set_time = ds1742_rtc_set_time,
116};
117
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118static int ds1742_nvram_read(void *priv, unsigned int pos, void *val,
119 size_t bytes)
5ec3e4b7 120{
87c78d95 121 struct rtc_plat_data *pdata = priv;
f9231a0c 122 void __iomem *ioaddr = pdata->ioaddr_nvram;
87c78d95 123 u8 *buf = val;
5ec3e4b7 124
87c78d95 125 for (; bytes; bytes--)
5ec3e4b7 126 *buf++ = readb(ioaddr + pos++);
87c78d95 127 return 0;
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128}
129
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130static int ds1742_nvram_write(void *priv, unsigned int pos, void *val,
131 size_t bytes)
5ec3e4b7 132{
87c78d95 133 struct rtc_plat_data *pdata = priv;
f9231a0c 134 void __iomem *ioaddr = pdata->ioaddr_nvram;
87c78d95 135 u8 *buf = val;
5ec3e4b7 136
87c78d95 137 for (; bytes; bytes--)
5ec3e4b7 138 writeb(*buf++, ioaddr + pos++);
87c78d95 139 return 0;
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140}
141
5a167f45 142static int ds1742_rtc_probe(struct platform_device *pdev)
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143{
144 struct rtc_device *rtc;
145 struct resource *res;
146 unsigned int cen, sec;
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147 struct rtc_plat_data *pdata;
148 void __iomem *ioaddr;
5ec3e4b7 149 int ret = 0;
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150 struct nvmem_config nvmem_cfg = {
151 .name = "ds1742_nvram",
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152 .reg_read = ds1742_nvram_read,
153 .reg_write = ds1742_nvram_write,
154 };
155
5ec3e4b7 156
ac18eb62 157 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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158 if (!pdata)
159 return -ENOMEM;
25e2818e 160
e88f319a 161 ioaddr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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162 if (IS_ERR(ioaddr))
163 return PTR_ERR(ioaddr);
ac18eb62 164
f9231a0c 165 pdata->ioaddr_nvram = ioaddr;
87c78d95 166 pdata->ioaddr_rtc = ioaddr + resource_size(res) - RTC_SIZE;
5ec3e4b7 167
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168 nvmem_cfg.size = resource_size(res) - RTC_SIZE;
169 nvmem_cfg.priv = pdata;
3a729700 170
5ec3e4b7 171 /* turn RTC on if it was not on */
f9231a0c 172 ioaddr = pdata->ioaddr_rtc;
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173 sec = readb(ioaddr + RTC_SECONDS);
174 if (sec & RTC_STOP) {
175 sec &= RTC_SECONDS_MASK;
176 cen = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
177 writeb(RTC_WRITE, ioaddr + RTC_CONTROL);
178 writeb(sec, ioaddr + RTC_SECONDS);
179 writeb(cen & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
180 }
391b1fe6 181 if (!(readb(ioaddr + RTC_DAY) & RTC_BATT_FLAG))
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182 dev_warn(&pdev->dev, "voltage-low detected.\n");
183
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184 pdata->last_jiffies = jiffies;
185 platform_set_drvdata(pdev, pdata);
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186
187 rtc = devm_rtc_allocate_device(&pdev->dev);
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188 if (IS_ERR(rtc))
189 return PTR_ERR(rtc);
3a729700 190
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191 rtc->ops = &ds1742_rtc_ops;
192
fdcfd854 193 ret = devm_rtc_register_device(rtc);
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194 if (ret)
195 return ret;
196
6746bc09 197 devm_rtc_nvmem_register(rtc, &nvmem_cfg);
5ec3e4b7 198
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199 return 0;
200}
201
9d203572 202static const struct of_device_id __maybe_unused ds1742_rtc_of_match[] = {
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203 { .compatible = "maxim,ds1742", },
204 { }
205};
206MODULE_DEVICE_TABLE(of, ds1742_rtc_of_match);
207
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208static struct platform_driver ds1742_rtc_driver = {
209 .probe = ds1742_rtc_probe,
5ec3e4b7 210 .driver = {
a95e23a2 211 .name = "rtc-ds1742",
3710f597 212 .of_match_table = of_match_ptr(ds1742_rtc_of_match),
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213 },
214};
215
0c4eae66 216module_platform_driver(ds1742_rtc_driver);
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217
218MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
219MODULE_DESCRIPTION("Dallas DS1742 RTC driver");
220MODULE_LICENSE("GPL");
ad28a07b 221MODULE_ALIAS("platform:rtc-ds1742");