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rtc: ds1685: use generic nvmem
[linux-2.6-block.git] / drivers / rtc / rtc-ds1685.c
CommitLineData
aaaf5fbf
JK		 1/*
2 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
3 * chips.
4 *
5 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
6 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
7 *
8 * References:
9 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
10 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
11 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
12 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
a737e835
JP		 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
aaaf5fbf
JK		 21#include <linux/bcd.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/rtc.h>
27#include <linux/workqueue.h>
28
29#include <linux/rtc/ds1685.h>
30
31#ifdef CONFIG_PROC_FS
32#include <linux/proc_fs.h>
33#endif
34
aaaf5fbf
JK		 35
36/* ----------------------------------------------------------------------- */
37/* Standard read/write functions if platform does not provide overrides */
38
39/**
40 * ds1685_read - read a value from an rtc register.
41 * @rtc: pointer to the ds1685 rtc structure.
42 * @reg: the register address to read.
43 */
44static u8
45ds1685_read(struct ds1685_priv *rtc, int reg)
46{
47 return readb((u8 __iomem *)rtc->regs +
48 (reg * rtc->regstep));
49}
50
51/**
52 * ds1685_write - write a value to an rtc register.
53 * @rtc: pointer to the ds1685 rtc structure.
54 * @reg: the register address to write.
55 * @value: value to write to the register.
56 */
57static void
58ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
59{
60 writeb(value, ((u8 __iomem *)rtc->regs +
61 (reg * rtc->regstep)));
62}
63/* ----------------------------------------------------------------------- */
64
65
66/* ----------------------------------------------------------------------- */
67/* Inlined functions */
68
69/**
70 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
71 * @rtc: pointer to the ds1685 rtc structure.
72 * @val: u8 time value to consider converting.
73 * @bcd_mask: u8 mask value if BCD mode is used.
74 * @bin_mask: u8 mask value if BIN mode is used.
75 *
76 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
77 */
78static inline u8
79ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
80{
81 if (rtc->bcd_mode)
82 return (bcd2bin(val) & bcd_mask);
83
84 return (val & bin_mask);
85}
86
87/**
88 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
89 * @rtc: pointer to the ds1685 rtc structure.
90 * @val: u8 time value to consider converting.
91 * @bin_mask: u8 mask value if BIN mode is used.
92 * @bcd_mask: u8 mask value if BCD mode is used.
93 *
94 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
95 */
96static inline u8
97ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
98{
99 if (rtc->bcd_mode)
100 return (bin2bcd(val) & bcd_mask);
101
102 return (val & bin_mask);
103}
104
c5776dec
HS		 105/**
106 * s1685_rtc_check_mday - check validity of the day of month.
107 * @rtc: pointer to the ds1685 rtc structure.
108 * @mday: day of month.
109 *
110 * Returns -EDOM if the day of month is not within 1..31 range.
111 */
112static inline int
113ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
114{
115 if (rtc->bcd_mode) {
116 if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
117 return -EDOM;
118 } else {
119 if (mday < 1 || mday > 31)
120 return -EDOM;
121 }
122 return 0;
123}
124
aaaf5fbf
JK		 125/**
126 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
127 * @rtc: pointer to the ds1685 rtc structure.
128 */
129static inline void
130ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
131{
132 rtc->write(rtc, RTC_CTRL_A,
133 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
134}
135
136/**
137 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
138 * @rtc: pointer to the ds1685 rtc structure.
139 */
140static inline void
141ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
142{
143 rtc->write(rtc, RTC_CTRL_A,
144 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
145}
146
147/**
148 * ds1685_rtc_begin_data_access - prepare the rtc for data access.
149 * @rtc: pointer to the ds1685 rtc structure.
150 *
151 * This takes several steps to prepare the rtc for access to get/set time
152 * and alarm values from the rtc registers:
153 * - Sets the SET bit in Control Register B.
154 * - Reads Ext Control Register 4A and checks the INCR bit.
155 * - If INCR is active, a short delay is added before Ext Control Register 4A
156 * is read again in a loop until INCR is inactive.
157 * - Switches the rtc to bank 1. This allows access to all relevant
158 * data for normal rtc operation, as bank 0 contains only the nvram.
159 */
160static inline void
161ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
162{
163 /* Set the SET bit in Ctrl B */
164 rtc->write(rtc, RTC_CTRL_B,
165 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
166
167 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
168 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
169 cpu_relax();
170
171 /* Switch to Bank 1 */
172 ds1685_rtc_switch_to_bank1(rtc);
173}
174
175/**
176 * ds1685_rtc_end_data_access - end data access on the rtc.
177 * @rtc: pointer to the ds1685 rtc structure.
178 *
179 * This ends what was started by ds1685_rtc_begin_data_access:
180 * - Switches the rtc back to bank 0.
181 * - Clears the SET bit in Control Register B.
182 */
183static inline void
184ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
185{
186 /* Switch back to Bank 0 */
187 ds1685_rtc_switch_to_bank1(rtc);
188
189 /* Clear the SET bit in Ctrl B */
190 rtc->write(rtc, RTC_CTRL_B,
191 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
192}
193
194/**
195 * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access.
196 * @rtc: pointer to the ds1685 rtc structure.
197 * @flags: irq flags variable for spin_lock_irqsave.
198 *
199 * This takes several steps to prepare the rtc for access to read just the
200 * control registers:
201 * - Sets a spinlock on the rtc IRQ.
202 * - Switches the rtc to bank 1. This allows access to the two extended
203 * control registers.
204 *
205 * Only use this where you are certain another lock will not be held.
206 */
207static inline void
8c09b9fd 208ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long *flags)
aaaf5fbf 209{
8c09b9fd 210 spin_lock_irqsave(&rtc->lock, *flags);
aaaf5fbf
JK		 211 ds1685_rtc_switch_to_bank1(rtc);
212}
213
214/**
215 * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc.
216 * @rtc: pointer to the ds1685 rtc structure.
217 * @flags: irq flags variable for spin_unlock_irqrestore.
218 *
219 * This ends what was started by ds1685_rtc_begin_ctrl_access:
220 * - Switches the rtc back to bank 0.
221 * - Unsets the spinlock on the rtc IRQ.
222 */
223static inline void
224ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
225{
226 ds1685_rtc_switch_to_bank0(rtc);
227 spin_unlock_irqrestore(&rtc->lock, flags);
228}
229
230/**
231 * ds1685_rtc_get_ssn - retrieve the silicon serial number.
232 * @rtc: pointer to the ds1685 rtc structure.
233 * @ssn: u8 array to hold the bits of the silicon serial number.
234 *
235 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
236 * first byte is the model number, the next six bytes are the serial number
237 * digits, and the final byte is a CRC check byte. Together, they form the
238 * silicon serial number.
239 *
240 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
241 * called first before calling this function, else data will be read out of
242 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
243 */
244static inline void
245ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
246{
247 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
248 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
249 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
250 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
251 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
252 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
253 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
254 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
255}
256/* ----------------------------------------------------------------------- */
257
258
259/* ----------------------------------------------------------------------- */
260/* Read/Set Time & Alarm functions */
261
262/**
263 * ds1685_rtc_read_time - reads the time registers.
264 * @dev: pointer to device structure.
265 * @tm: pointer to rtc_time structure.
266 */
267static int
268ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
269{
85368bb9 270 struct ds1685_priv *rtc = dev_get_drvdata(dev);
aaaf5fbf
JK		 271 u8 ctrlb, century;
272 u8 seconds, minutes, hours, wday, mday, month, years;
273
274 /* Fetch the time info from the RTC registers. */
275 ds1685_rtc_begin_data_access(rtc);
276 seconds = rtc->read(rtc, RTC_SECS);
277 minutes = rtc->read(rtc, RTC_MINS);
278 hours = rtc->read(rtc, RTC_HRS);
279 wday = rtc->read(rtc, RTC_WDAY);
280 mday = rtc->read(rtc, RTC_MDAY);
281 month = rtc->read(rtc, RTC_MONTH);
282 years = rtc->read(rtc, RTC_YEAR);
283 century = rtc->read(rtc, RTC_CENTURY);
284 ctrlb = rtc->read(rtc, RTC_CTRL_B);
285 ds1685_rtc_end_data_access(rtc);
286
287 /* bcd2bin if needed, perform fixups, and store to rtc_time. */
288 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
289 RTC_YEAR_BIN_MASK);
290 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
291 RTC_CENTURY_MASK);
292 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
293 RTC_SECS_BIN_MASK);
294 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
295 RTC_MINS_BIN_MASK);
296 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
297 RTC_HRS_24_BIN_MASK);
298 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
299 RTC_WDAY_MASK) - 1);
300 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
301 RTC_MDAY_BIN_MASK);
302 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
303 RTC_MONTH_BIN_MASK) - 1);
304 tm->tm_year = ((years + (century * 100)) - 1900);
305 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
306 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
307
22652ba7 308 return 0;
aaaf5fbf
JK		 309}
310
311/**
312 * ds1685_rtc_set_time - sets the time registers.
313 * @dev: pointer to device structure.
314 * @tm: pointer to rtc_time structure.
315 */
316static int
317ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
318{
85368bb9 319 struct ds1685_priv *rtc = dev_get_drvdata(dev);
aaaf5fbf
JK		 320 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
321
322 /* Fetch the time info from rtc_time. */
323 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
324 RTC_SECS_BCD_MASK);
325 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
326 RTC_MINS_BCD_MASK);
327 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
328 RTC_HRS_24_BCD_MASK);
329 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
330 RTC_WDAY_MASK);
331 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
332 RTC_MDAY_BCD_MASK);
333 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
334 RTC_MONTH_BCD_MASK);
335 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
336 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
337 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
338 RTC_CENTURY_MASK, RTC_CENTURY_MASK);
339
340 /*
341 * Perform Sanity Checks:
342 * - Months: !> 12, Month Day != 0.
343 * - Month Day !> Max days in current month.
344 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
345 */
346 if ((tm->tm_mon > 11) || (mday == 0))
347 return -EDOM;
348
349 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
350 return -EDOM;
351
352 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
353 (tm->tm_sec >= 60) || (wday > 7))
354 return -EDOM;
355
356 /*
357 * Set the data mode to use and store the time values in the
358 * RTC registers.
359 */
360 ds1685_rtc_begin_data_access(rtc);
361 ctrlb = rtc->read(rtc, RTC_CTRL_B);
362 if (rtc->bcd_mode)
363 ctrlb &= ~(RTC_CTRL_B_DM);
364 else
365 ctrlb |= RTC_CTRL_B_DM;
366 rtc->write(rtc, RTC_CTRL_B, ctrlb);
367 rtc->write(rtc, RTC_SECS, seconds);
368 rtc->write(rtc, RTC_MINS, minutes);
369 rtc->write(rtc, RTC_HRS, hours);
370 rtc->write(rtc, RTC_WDAY, wday);
371 rtc->write(rtc, RTC_MDAY, mday);
372 rtc->write(rtc, RTC_MONTH, month);
373 rtc->write(rtc, RTC_YEAR, years);
374 rtc->write(rtc, RTC_CENTURY, century);
375 ds1685_rtc_end_data_access(rtc);
376
377 return 0;
378}
379
380/**
381 * ds1685_rtc_read_alarm - reads the alarm registers.
382 * @dev: pointer to device structure.
383 * @alrm: pointer to rtc_wkalrm structure.
384 *
385 * There are three primary alarm registers: seconds, minutes, and hours.
386 * A fourth alarm register for the month date is also available in bank1 for
387 * kickstart/wakeup features. The DS1685/DS1687 manual states that a
388 * "don't care" value ranging from 0xc0 to 0xff may be written into one or
389 * more of the three alarm bytes to act as a wildcard value. The fourth
390 * byte doesn't support a "don't care" value.
391 */
392static int
393ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
394{
85368bb9 395 struct ds1685_priv *rtc = dev_get_drvdata(dev);
aaaf5fbf 396 u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
c5776dec 397 int ret;
aaaf5fbf
JK		 398
399 /* Fetch the alarm info from the RTC alarm registers. */
400 ds1685_rtc_begin_data_access(rtc);
401 seconds = rtc->read(rtc, RTC_SECS_ALARM);
402 minutes = rtc->read(rtc, RTC_MINS_ALARM);
403 hours = rtc->read(rtc, RTC_HRS_ALARM);
404 mday = rtc->read(rtc, RTC_MDAY_ALARM);
405 ctrlb = rtc->read(rtc, RTC_CTRL_B);
406 ctrlc = rtc->read(rtc, RTC_CTRL_C);
407 ds1685_rtc_end_data_access(rtc);
408
c5776dec
HS		 409 /* Check the month date for validity. */
410 ret = ds1685_rtc_check_mday(rtc, mday);
411 if (ret)
412 return ret;
aaaf5fbf
JK		 413
414 /*
415 * Check the three alarm bytes.
416 *
417 * The Linux RTC system doesn't support the "don't care" capability
418 * of this RTC chip. We check for it anyways in case support is
56d86a7e 419 * added in the future and only assign when we care.
aaaf5fbf 420 */
56d86a7e 421 if (likely(seconds < 0xc0))
aaaf5fbf
JK		 422 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
423 RTC_SECS_BCD_MASK,
424 RTC_SECS_BIN_MASK);
425
56d86a7e 426 if (likely(minutes < 0xc0))
aaaf5fbf
JK		 427 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
428 RTC_MINS_BCD_MASK,
429 RTC_MINS_BIN_MASK);
430
56d86a7e 431 if (likely(hours < 0xc0))
aaaf5fbf
JK		 432 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
433 RTC_HRS_24_BCD_MASK,
434 RTC_HRS_24_BIN_MASK);
435
436 /* Write the data to rtc_wkalrm. */
437 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
438 RTC_MDAY_BIN_MASK);
aaaf5fbf
JK		 439 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
440 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
441
442 return 0;
443}
444
445/**
446 * ds1685_rtc_set_alarm - sets the alarm in registers.
447 * @dev: pointer to device structure.
448 * @alrm: pointer to rtc_wkalrm structure.
449 */
450static int
451ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
452{
85368bb9 453 struct ds1685_priv *rtc = dev_get_drvdata(dev);
aaaf5fbf 454 u8 ctrlb, seconds, minutes, hours, mday;
c5776dec 455 int ret;
aaaf5fbf
JK		 456
457 /* Fetch the alarm info and convert to BCD. */
458 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
459 RTC_SECS_BIN_MASK,
460 RTC_SECS_BCD_MASK);
461 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
462 RTC_MINS_BIN_MASK,
463 RTC_MINS_BCD_MASK);
464 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
465 RTC_HRS_24_BIN_MASK,
466 RTC_HRS_24_BCD_MASK);
467 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
468 RTC_MDAY_BIN_MASK,
469 RTC_MDAY_BCD_MASK);
470
471 /* Check the month date for validity. */
c5776dec
HS		 472 ret = ds1685_rtc_check_mday(rtc, mday);
473 if (ret)
474 return ret;
aaaf5fbf
JK		 475
476 /*
477 * Check the three alarm bytes.
478 *
479 * The Linux RTC system doesn't support the "don't care" capability
480 * of this RTC chip because rtc_valid_tm tries to validate every
481 * field, and we only support four fields. We put the support
482 * here anyways for the future.
483 */
39ea34cc 484 if (unlikely(seconds >= 0xc0))
aaaf5fbf
JK		 485 seconds = 0xff;
486
39ea34cc 487 if (unlikely(minutes >= 0xc0))
aaaf5fbf
JK		 488 minutes = 0xff;
489
39ea34cc 490 if (unlikely(hours >= 0xc0))
aaaf5fbf
JK		 491 hours = 0xff;
492
493 alrm->time.tm_mon = -1;
494 alrm->time.tm_year = -1;
495 alrm->time.tm_wday = -1;
496 alrm->time.tm_yday = -1;
497 alrm->time.tm_isdst = -1;
498
499 /* Disable the alarm interrupt first. */
500 ds1685_rtc_begin_data_access(rtc);
501 ctrlb = rtc->read(rtc, RTC_CTRL_B);
502 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
503
504 /* Read ctrlc to clear RTC_CTRL_C_AF. */
505 rtc->read(rtc, RTC_CTRL_C);
506
507 /*
508 * Set the data mode to use and store the time values in the
509 * RTC registers.
510 */
511 ctrlb = rtc->read(rtc, RTC_CTRL_B);
512 if (rtc->bcd_mode)
513 ctrlb &= ~(RTC_CTRL_B_DM);
514 else
515 ctrlb |= RTC_CTRL_B_DM;
516 rtc->write(rtc, RTC_CTRL_B, ctrlb);
517 rtc->write(rtc, RTC_SECS_ALARM, seconds);
518 rtc->write(rtc, RTC_MINS_ALARM, minutes);
519 rtc->write(rtc, RTC_HRS_ALARM, hours);
520 rtc->write(rtc, RTC_MDAY_ALARM, mday);
521
522 /* Re-enable the alarm if needed. */
523 if (alrm->enabled) {
524 ctrlb = rtc->read(rtc, RTC_CTRL_B);
525 ctrlb |= RTC_CTRL_B_AIE;
526 rtc->write(rtc, RTC_CTRL_B, ctrlb);
527 }
528
529 /* Done! */
530 ds1685_rtc_end_data_access(rtc);
531
532 return 0;
533}
534/* ----------------------------------------------------------------------- */
535
536
537/* ----------------------------------------------------------------------- */
538/* /dev/rtcX Interface functions */
539
aaaf5fbf
JK		 540/**
541 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
542 * @dev: pointer to device structure.
543 * @enabled: flag indicating whether to enable or disable.
544 */
545static int
546ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
547{
548 struct ds1685_priv *rtc = dev_get_drvdata(dev);
549 unsigned long flags = 0;
550
551 /* Enable/disable the Alarm IRQ-Enable flag. */
552 spin_lock_irqsave(&rtc->lock, flags);
553
554 /* Flip the requisite interrupt-enable bit. */
555 if (enabled)
556 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
557 RTC_CTRL_B_AIE));
558 else
559 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
560 ~(RTC_CTRL_B_AIE)));
561
562 /* Read Control C to clear all the flag bits. */
563 rtc->read(rtc, RTC_CTRL_C);
564 spin_unlock_irqrestore(&rtc->lock, flags);
565
566 return 0;
567}
aaaf5fbf
JK		 568/* ----------------------------------------------------------------------- */
569
570
571/* ----------------------------------------------------------------------- */
572/* IRQ handler & workqueue. */
573
574/**
575 * ds1685_rtc_irq_handler - IRQ handler.
576 * @irq: IRQ number.
577 * @dev_id: platform device pointer.
578 */
579static irqreturn_t
580ds1685_rtc_irq_handler(int irq, void *dev_id)
581{
582 struct platform_device *pdev = dev_id;
583 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
584 u8 ctrlb, ctrlc;
585 unsigned long events = 0;
586 u8 num_irqs = 0;
587
588 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
589 if (unlikely(!rtc))
590 return IRQ_HANDLED;
591
592 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
593 spin_lock(&rtc->lock);
594 ctrlb = rtc->read(rtc, RTC_CTRL_B);
595 ctrlc = rtc->read(rtc, RTC_CTRL_C);
596
597 /* Is the IRQF bit set? */
598 if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
599 /*
600 * We need to determine if it was one of the standard
601 * events: PF, AF, or UF. If so, we handle them and
602 * update the RTC core.
603 */
604 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
605 events = RTC_IRQF;
606
607 /* Check for a periodic interrupt. */
608 if ((ctrlb & RTC_CTRL_B_PIE) &&
609 (ctrlc & RTC_CTRL_C_PF)) {
610 events |= RTC_PF;
611 num_irqs++;
612 }
613
614 /* Check for an alarm interrupt. */
615 if ((ctrlb & RTC_CTRL_B_AIE) &&
616 (ctrlc & RTC_CTRL_C_AF)) {
617 events |= RTC_AF;
618 num_irqs++;
619 }
620
621 /* Check for an update interrupt. */
622 if ((ctrlb & RTC_CTRL_B_UIE) &&
623 (ctrlc & RTC_CTRL_C_UF)) {
624 events |= RTC_UF;
625 num_irqs++;
626 }
627
628 rtc_update_irq(rtc->dev, num_irqs, events);
629 } else {
630 /*
631 * One of the "extended" interrupts was received that
632 * is not recognized by the RTC core. These need to
633 * be handled in task context as they can call other
634 * functions and the time spent in irq context needs
635 * to be minimized. Schedule them into a workqueue
636 * and inform the RTC core that the IRQs were handled.
637 */
638 spin_unlock(&rtc->lock);
639 schedule_work(&rtc->work);
640 rtc_update_irq(rtc->dev, 0, 0);
641 return IRQ_HANDLED;
642 }
643 }
644 spin_unlock(&rtc->lock);
645
646 return events ? IRQ_HANDLED : IRQ_NONE;
647}
648
649/**
650 * ds1685_rtc_work_queue - work queue handler.
651 * @work: work_struct containing data to work on in task context.
652 */
653static void
654ds1685_rtc_work_queue(struct work_struct *work)
655{
656 struct ds1685_priv *rtc = container_of(work,
657 struct ds1685_priv, work);
658 struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
659 struct mutex *rtc_mutex = &rtc->dev->ops_lock;
660 u8 ctrl4a, ctrl4b;
661
662 mutex_lock(rtc_mutex);
663
664 ds1685_rtc_switch_to_bank1(rtc);
665 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
666 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
667
668 /*
669 * Check for a kickstart interrupt. With Vcc applied, this
670 * typically means that the power button was pressed, so we
671 * begin the shutdown sequence.
672 */
673 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
674 /* Briefly disable kickstarts to debounce button presses. */
675 rtc->write(rtc, RTC_EXT_CTRL_4B,
676 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
677 ~(RTC_CTRL_4B_KSE)));
678
679 /* Clear the kickstart flag. */
680 rtc->write(rtc, RTC_EXT_CTRL_4A,
681 (ctrl4a & ~(RTC_CTRL_4A_KF)));
682
683
684 /*
685 * Sleep 500ms before re-enabling kickstarts. This allows
686 * adequate time to avoid reading signal jitter as additional
687 * button presses.
688 */
689 msleep(500);
690 rtc->write(rtc, RTC_EXT_CTRL_4B,
691 (rtc->read(rtc, RTC_EXT_CTRL_4B) |
692 RTC_CTRL_4B_KSE));
693
694 /* Call the platform pre-poweroff function. Else, shutdown. */
695 if (rtc->prepare_poweroff != NULL)
696 rtc->prepare_poweroff();
697 else
698 ds1685_rtc_poweroff(pdev);
699 }
700
701 /*
702 * Check for a wake-up interrupt. With Vcc applied, this is
703 * essentially a second alarm interrupt, except it takes into
704 * account the 'date' register in bank1 in addition to the
705 * standard three alarm registers.
706 */
707 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
708 rtc->write(rtc, RTC_EXT_CTRL_4A,
709 (ctrl4a & ~(RTC_CTRL_4A_WF)));
710
711 /* Call the platform wake_alarm function if defined. */
712 if (rtc->wake_alarm != NULL)
713 rtc->wake_alarm();
714 else
715 dev_warn(&pdev->dev,
716 "Wake Alarm IRQ just occurred!\n");
717 }
718
719 /*
720 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
721 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
722 * each byte to a logic 1. This has no effect on any extended
723 * NV-SRAM that might be present, nor on the time/calendar/alarm
724 * registers. After a ram-clear is completed, there is a minimum
725 * recovery time of ~150ms in which all reads/writes are locked out.
726 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
727 * catch this scenario.
728 */
729 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
730 rtc->write(rtc, RTC_EXT_CTRL_4A,
731 (ctrl4a & ~(RTC_CTRL_4A_RF)));
732 msleep(150);
733
734 /* Call the platform post_ram_clear function if defined. */
735 if (rtc->post_ram_clear != NULL)
736 rtc->post_ram_clear();
737 else
738 dev_warn(&pdev->dev,
739 "RAM-Clear IRQ just occurred!\n");
740 }
741 ds1685_rtc_switch_to_bank0(rtc);
742
743 mutex_unlock(rtc_mutex);
744}
745/* ----------------------------------------------------------------------- */
746
747
748/* ----------------------------------------------------------------------- */
749/* ProcFS interface */
750
751#ifdef CONFIG_PROC_FS
752#define NUM_REGS 6 /* Num of control registers. */
753#define NUM_BITS 8 /* Num bits per register. */
754#define NUM_SPACES 4 /* Num spaces between each bit. */
755
756/*
757 * Periodic Interrupt Rates.
758 */
759static const char *ds1685_rtc_pirq_rate[16] = {
760 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
761 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
762 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
763};
764
765/*
766 * Square-Wave Output Frequencies.
767 */
768static const char *ds1685_rtc_sqw_freq[16] = {
769 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
770 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
771};
772
aaaf5fbf
JK		 773/**
774 * ds1685_rtc_proc - procfs access function.
775 * @dev: pointer to device structure.
776 * @seq: pointer to seq_file structure.
777 */
778static int
779ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
780{
781 struct platform_device *pdev = to_platform_device(dev);
782 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
783 u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
52ef84d5 784 char *model;
aaaf5fbf
JK		 785
786 /* Read all the relevant data from the control registers. */
787 ds1685_rtc_switch_to_bank1(rtc);
788 ds1685_rtc_get_ssn(rtc, ssn);
789 ctrla = rtc->read(rtc, RTC_CTRL_A);
790 ctrlb = rtc->read(rtc, RTC_CTRL_B);
791 ctrlc = rtc->read(rtc, RTC_CTRL_C);
792 ctrld = rtc->read(rtc, RTC_CTRL_D);
793 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
794 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
795 ds1685_rtc_switch_to_bank0(rtc);
796
797 /* Determine the RTC model. */
798 switch (ssn[0]) {
799 case RTC_MODEL_DS1685:
800 model = "DS1685/DS1687\0";
801 break;
802 case RTC_MODEL_DS1689:
803 model = "DS1689/DS1693\0";
804 break;
805 case RTC_MODEL_DS17285:
806 model = "DS17285/DS17287\0";
807 break;
808 case RTC_MODEL_DS17485:
809 model = "DS17485/DS17487\0";
810 break;
811 case RTC_MODEL_DS17885:
812 model = "DS17885/DS17887\0";
813 break;
814 default:
815 model = "Unknown\0";
816 break;
817 }
818
819 /* Print out the information. */
820 seq_printf(seq,
821 "Model\t\t: %s\n"
822 "Oscillator\t: %s\n"
823 "12/24hr\t\t: %s\n"
824 "DST\t\t: %s\n"
825 "Data mode\t: %s\n"
826 "Battery\t\t: %s\n"
827 "Aux batt\t: %s\n"
828 "Update IRQ\t: %s\n"
829 "Periodic IRQ\t: %s\n"
830 "Periodic Rate\t: %s\n"
831 "SQW Freq\t: %s\n"
ff67abd2 832 "Serial #\t: %8phC\n",
aaaf5fbf
JK		 833 model,
834 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
835 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
836 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
837 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
838 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
839 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
840 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
841 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
842 (!(ctrl4b & RTC_CTRL_4B_E32K) ?
843 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
844 (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
845 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
ff67abd2 846 ssn);
aaaf5fbf
JK		 847 return 0;
848}
849#else
850#define ds1685_rtc_proc NULL
851#endif /* CONFIG_PROC_FS */
852/* ----------------------------------------------------------------------- */
853
854
855/* ----------------------------------------------------------------------- */
856/* RTC Class operations */
857
858static const struct rtc_class_ops
859ds1685_rtc_ops = {
860 .proc = ds1685_rtc_proc,
861 .read_time = ds1685_rtc_read_time,
862 .set_time = ds1685_rtc_set_time,
863 .read_alarm = ds1685_rtc_read_alarm,
864 .set_alarm = ds1685_rtc_set_alarm,
865 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
866};
867/* ----------------------------------------------------------------------- */
868
482419e1
AB		 869static int ds1685_nvram_read(void *priv, unsigned int pos, void *val,
870 size_t size)
aaaf5fbf 871{
482419e1 872 struct ds1685_priv *rtc = priv;
aaaf5fbf
JK		 873 ssize_t count;
874 unsigned long flags = 0;
482419e1 875 u8 *buf = val;
aaaf5fbf
JK		 876
877 spin_lock_irqsave(&rtc->lock, flags);
878 ds1685_rtc_switch_to_bank0(rtc);
879
880 /* Read NVRAM in time and bank0 registers. */
881 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
882 count++, size--) {
883 if (count < NVRAM_SZ_TIME)
884 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
885 else
886 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
887 }
888
889#ifndef CONFIG_RTC_DRV_DS1689
890 if (size > 0) {
891 ds1685_rtc_switch_to_bank1(rtc);
892
893#ifndef CONFIG_RTC_DRV_DS1685
894 /* Enable burst-mode on DS17x85/DS17x87 */
895 rtc->write(rtc, RTC_EXT_CTRL_4A,
896 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
897 RTC_CTRL_4A_BME));
898
899 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
900 * reading with burst-mode */
901 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
902 (pos - NVRAM_TOTAL_SZ_BANK0));
903#endif
904
905 /* Read NVRAM in bank1 registers. */
906 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
907 count++, size--) {
908#ifdef CONFIG_RTC_DRV_DS1685
909 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
910 * before each read. */
911 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
912 (pos - NVRAM_TOTAL_SZ_BANK0));
913#endif
914 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
915 pos++;
916 }
917
918#ifndef CONFIG_RTC_DRV_DS1685
919 /* Disable burst-mode on DS17x85/DS17x87 */
920 rtc->write(rtc, RTC_EXT_CTRL_4A,
921 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
922 ~(RTC_CTRL_4A_BME)));
923#endif
924 ds1685_rtc_switch_to_bank0(rtc);
925 }
926#endif /* !CONFIG_RTC_DRV_DS1689 */
927 spin_unlock_irqrestore(&rtc->lock, flags);
928
482419e1 929 return 0;
aaaf5fbf
JK		 930}
931
482419e1
AB		 932static int ds1685_nvram_write(void *priv, unsigned int pos, void *val,
933 size_t size)
aaaf5fbf 934{
482419e1 935 struct ds1685_priv *rtc = priv;
aaaf5fbf
JK		 936 ssize_t count;
937 unsigned long flags = 0;
482419e1 938 u8 *buf = val;
aaaf5fbf
JK		 939
940 spin_lock_irqsave(&rtc->lock, flags);
941 ds1685_rtc_switch_to_bank0(rtc);
942
943 /* Write NVRAM in time and bank0 registers. */
944 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
945 count++, size--)
946 if (count < NVRAM_SZ_TIME)
947 rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
948 *buf++);
949 else
950 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
951
952#ifndef CONFIG_RTC_DRV_DS1689
953 if (size > 0) {
954 ds1685_rtc_switch_to_bank1(rtc);
955
956#ifndef CONFIG_RTC_DRV_DS1685
957 /* Enable burst-mode on DS17x85/DS17x87 */
958 rtc->write(rtc, RTC_EXT_CTRL_4A,
959 (rtc->read(rtc, RTC_EXT_CTRL_4A) |
960 RTC_CTRL_4A_BME));
961
962 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
963 * writing with burst-mode */
964 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
965 (pos - NVRAM_TOTAL_SZ_BANK0));
966#endif
967
968 /* Write NVRAM in bank1 registers. */
969 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
970 count++, size--) {
971#ifdef CONFIG_RTC_DRV_DS1685
972 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
973 * before each read. */
974 rtc->write(rtc, RTC_BANK1_RAM_ADDR,
975 (pos - NVRAM_TOTAL_SZ_BANK0));
976#endif
977 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
978 pos++;
979 }
980
981#ifndef CONFIG_RTC_DRV_DS1685
982 /* Disable burst-mode on DS17x85/DS17x87 */
983 rtc->write(rtc, RTC_EXT_CTRL_4A,
984 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
985 ~(RTC_CTRL_4A_BME)));
986#endif
987 ds1685_rtc_switch_to_bank0(rtc);
988 }
989#endif /* !CONFIG_RTC_DRV_DS1689 */
990 spin_unlock_irqrestore(&rtc->lock, flags);
991
482419e1 992 return 0;
aaaf5fbf
JK		 993}
994
482419e1
AB		 995/* ----------------------------------------------------------------------- */
996/* SysFS interface */
aaaf5fbf 997
482419e1 998#ifdef CONFIG_SYSFS
aaaf5fbf
JK		 999/**
1000 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
1001 * @dev: pointer to device structure.
1002 * @attr: pointer to device_attribute structure.
1003 * @buf: pointer to char array to hold the output.
1004 */
1005static ssize_t
1006ds1685_rtc_sysfs_battery_show(struct device *dev,
1007 struct device_attribute *attr, char *buf)
1008{
85368bb9 1009 struct ds1685_priv *rtc = dev_get_drvdata(dev);
aaaf5fbf
JK		 1010 u8 ctrld;
1011
1012 ctrld = rtc->read(rtc, RTC_CTRL_D);
1013
9c25a106 1014 return sprintf(buf, "%s\n",
aaaf5fbf
JK		 1015 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
1016}
1017static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
1018
1019/**
1020 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
1021 * @dev: pointer to device structure.
1022 * @attr: pointer to device_attribute structure.
1023 * @buf: pointer to char array to hold the output.
1024 */
1025static ssize_t
1026ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1027 struct device_attribute *attr, char *buf)
1028{
85368bb9 1029 struct ds1685_priv *rtc = dev_get_drvdata(dev);
aaaf5fbf
JK		 1030 u8 ctrl4a;
1031
1032 ds1685_rtc_switch_to_bank1(rtc);
1033 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1034 ds1685_rtc_switch_to_bank0(rtc);
1035
9c25a106 1036 return sprintf(buf, "%s\n",
aaaf5fbf
JK		 1037 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1038}
1039static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1040
1041/**
1042 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1043 * @dev: pointer to device structure.
1044 * @attr: pointer to device_attribute structure.
1045 * @buf: pointer to char array to hold the output.
1046 */
1047static ssize_t
1048ds1685_rtc_sysfs_serial_show(struct device *dev,
1049 struct device_attribute *attr, char *buf)
1050{
85368bb9 1051 struct ds1685_priv *rtc = dev_get_drvdata(dev);
aaaf5fbf
JK		 1052 u8 ssn[8];
1053
1054 ds1685_rtc_switch_to_bank1(rtc);
1055 ds1685_rtc_get_ssn(rtc, ssn);
1056 ds1685_rtc_switch_to_bank0(rtc);
1057
9c25a106 1058 return sprintf(buf, "%8phC\n", ssn);
aaaf5fbf
JK		 1059}
1060static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1061
1062/**
1063 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1064 */
1065static struct attribute*
1066ds1685_rtc_sysfs_misc_attrs[] = {
1067 &dev_attr_battery.attr,
1068 &dev_attr_auxbatt.attr,
1069 &dev_attr_serial.attr,
1070 NULL,
1071};
1072
1073/**
1074 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1075 */
1076static const struct attribute_group
1077ds1685_rtc_sysfs_misc_grp = {
1078 .name = "misc",
1079 .attrs = ds1685_rtc_sysfs_misc_attrs,
1080};
1081
aaaf5fbf
JK		 1082/**
1083 * ds1685_rtc_sysfs_register - register sysfs files.
1084 * @dev: pointer to device structure.
1085 */
1086static int
1087ds1685_rtc_sysfs_register(struct device *dev)
1088{
1089 int ret = 0;
1090
aaaf5fbf
JK		 1091 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1092 if (ret)
1093 return ret;
1094
aaaf5fbf
JK		 1095 return 0;
1096}
1097
1098/**
1099 * ds1685_rtc_sysfs_unregister - unregister sysfs files.
1100 * @dev: pointer to device structure.
1101 */
1102static int
1103ds1685_rtc_sysfs_unregister(struct device *dev)
1104{
aaaf5fbf
JK		 1105 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp);
1106
aaaf5fbf
JK		 1107 return 0;
1108}
1109#endif /* CONFIG_SYSFS */
1110
1111
1112
1113/* ----------------------------------------------------------------------- */
1114/* Driver Probe/Removal */
1115
1116/**
1117 * ds1685_rtc_probe - initializes rtc driver.
1118 * @pdev: pointer to platform_device structure.
1119 */
1120static int
1121ds1685_rtc_probe(struct platform_device *pdev)
1122{
1123 struct rtc_device *rtc_dev;
1124 struct resource *res;
1125 struct ds1685_priv *rtc;
1126 struct ds1685_rtc_platform_data *pdata;
1127 u8 ctrla, ctrlb, hours;
1128 unsigned char am_pm;
1129 int ret = 0;
482419e1
AB		 1130 struct nvmem_config nvmem_cfg = {
1131 .name = "ds1685_nvram",
1132 .size = NVRAM_TOTAL_SZ,
1133 .reg_read = ds1685_nvram_read,
1134 .reg_write = ds1685_nvram_write,
1135 };
aaaf5fbf
JK		 1136
1137 /* Get the platform data. */
1138 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1139 if (!pdata)
1140 return -ENODEV;
1141
1142 /* Allocate memory for the rtc device. */
1143 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1144 if (!rtc)
1145 return -ENOMEM;
1146
1147 /*
1148 * Allocate/setup any IORESOURCE_MEM resources, if required. Not all
1149 * platforms put the RTC in an easy-access place. Like the SGI Octane,
1150 * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip
1151 * that sits behind the IOC3 PCI metadevice.
1152 */
1153 if (pdata->alloc_io_resources) {
1154 /* Get the platform resources. */
1155 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1156 if (!res)
1157 return -ENXIO;
1158 rtc->size = resource_size(res);
1159
1160 /* Request a memory region. */
1161 /* XXX: mmio-only for now. */
1162 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size,
1163 pdev->name))
1164 return -EBUSY;
1165
1166 /*
1167 * Set the base address for the rtc, and ioremap its
1168 * registers.
1169 */
1170 rtc->baseaddr = res->start;
1171 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size);
1172 if (!rtc->regs)
1173 return -ENOMEM;
1174 }
1175 rtc->alloc_io_resources = pdata->alloc_io_resources;
1176
1177 /* Get the register step size. */
1178 if (pdata->regstep > 0)
1179 rtc->regstep = pdata->regstep;
1180 else
1181 rtc->regstep = 1;
1182
1183 /* Platform read function, else default if mmio setup */
1184 if (pdata->plat_read)
1185 rtc->read = pdata->plat_read;
1186 else
1187 if (pdata->alloc_io_resources)
1188 rtc->read = ds1685_read;
1189 else
1190 return -ENXIO;
1191
1192 /* Platform write function, else default if mmio setup */
1193 if (pdata->plat_write)
1194 rtc->write = pdata->plat_write;
1195 else
1196 if (pdata->alloc_io_resources)
1197 rtc->write = ds1685_write;
1198 else
1199 return -ENXIO;
1200
1201 /* Platform pre-shutdown function, if defined. */
1202 if (pdata->plat_prepare_poweroff)
1203 rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1204
1205 /* Platform wake_alarm function, if defined. */
1206 if (pdata->plat_wake_alarm)
1207 rtc->wake_alarm = pdata->plat_wake_alarm;
1208
1209 /* Platform post_ram_clear function, if defined. */
1210 if (pdata->plat_post_ram_clear)
1211 rtc->post_ram_clear = pdata->plat_post_ram_clear;
1212
1213 /* Init the spinlock, workqueue, & set the driver data. */
1214 spin_lock_init(&rtc->lock);
1215 INIT_WORK(&rtc->work, ds1685_rtc_work_queue);
1216 platform_set_drvdata(pdev, rtc);
1217
1218 /* Turn the oscillator on if is not already on (DV1 = 1). */
1219 ctrla = rtc->read(rtc, RTC_CTRL_A);
1220 if (!(ctrla & RTC_CTRL_A_DV1))
1221 ctrla |= RTC_CTRL_A_DV1;
1222
1223 /* Enable the countdown chain (DV2 = 0) */
1224 ctrla &= ~(RTC_CTRL_A_DV2);
1225
1226 /* Clear RS3-RS0 in Control A. */
1227 ctrla &= ~(RTC_CTRL_A_RS_MASK);
1228
1229 /*
1230 * All done with Control A. Switch to Bank 1 for the remainder of
1231 * the RTC setup so we have access to the extended functions.
1232 */
1233 ctrla |= RTC_CTRL_A_DV0;
1234 rtc->write(rtc, RTC_CTRL_A, ctrla);
1235
1236 /* Default to 32768kHz output. */
1237 rtc->write(rtc, RTC_EXT_CTRL_4B,
1238 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1239
1240 /* Set the SET bit in Control B so we can do some housekeeping. */
1241 rtc->write(rtc, RTC_CTRL_B,
1242 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1243
1244 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1245 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1246 cpu_relax();
1247
1248 /*
1249 * If the platform supports BCD mode, then set DM=0 in Control B.
1250 * Otherwise, set DM=1 for BIN mode.
1251 */
1252 ctrlb = rtc->read(rtc, RTC_CTRL_B);
1253 if (pdata->bcd_mode)
1254 ctrlb &= ~(RTC_CTRL_B_DM);
1255 else
1256 ctrlb |= RTC_CTRL_B_DM;
1257 rtc->bcd_mode = pdata->bcd_mode;
1258
1259 /*
1260 * Disable Daylight Savings Time (DSE = 0).
1261 * The RTC has hardcoded timezone information that is rendered
1262 * obselete. We'll let the OS deal with DST settings instead.
1263 */
1264 if (ctrlb & RTC_CTRL_B_DSE)
1265 ctrlb &= ~(RTC_CTRL_B_DSE);
1266
1267 /* Force 24-hour mode (2412 = 1). */
1268 if (!(ctrlb & RTC_CTRL_B_2412)) {
1269 /* Reinitialize the time hours. */
1270 hours = rtc->read(rtc, RTC_HRS);
1271 am_pm = hours & RTC_HRS_AMPM_MASK;
1272 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1273 RTC_HRS_12_BIN_MASK);
1274 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1275
1276 /* Enable 24-hour mode. */
1277 ctrlb |= RTC_CTRL_B_2412;
1278
1279 /* Write back to Control B, including DM & DSE bits. */
1280 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1281
1282 /* Write the time hours back. */
1283 rtc->write(rtc, RTC_HRS,
1284 ds1685_rtc_bin2bcd(rtc, hours,
1285 RTC_HRS_24_BIN_MASK,
1286 RTC_HRS_24_BCD_MASK));
1287
1288 /* Reinitialize the alarm hours. */
1289 hours = rtc->read(rtc, RTC_HRS_ALARM);
1290 am_pm = hours & RTC_HRS_AMPM_MASK;
1291 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1292 RTC_HRS_12_BIN_MASK);
1293 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1294
1295 /* Write the alarm hours back. */
1296 rtc->write(rtc, RTC_HRS_ALARM,
1297 ds1685_rtc_bin2bcd(rtc, hours,
1298 RTC_HRS_24_BIN_MASK,
1299 RTC_HRS_24_BCD_MASK));
1300 } else {
1301 /* 24-hour mode is already set, so write Control B back. */
1302 rtc->write(rtc, RTC_CTRL_B, ctrlb);
1303 }
1304
1305 /* Unset the SET bit in Control B so the RTC can update. */
1306 rtc->write(rtc, RTC_CTRL_B,
1307 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
1308
1309 /* Check the main battery. */
1310 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
1311 dev_warn(&pdev->dev,
1312 "Main battery is exhausted! RTC may be invalid!\n");
1313
1314 /* Check the auxillary battery. It is optional. */
1315 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
1316 dev_warn(&pdev->dev,
1317 "Aux battery is exhausted or not available.\n");
1318
1319 /* Read Ctrl B and clear PIE/AIE/UIE. */
1320 rtc->write(rtc, RTC_CTRL_B,
1321 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
1322
1323 /* Reading Ctrl C auto-clears PF/AF/UF. */
1324 rtc->read(rtc, RTC_CTRL_C);
1325
1326 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1327 rtc->write(rtc, RTC_EXT_CTRL_4B,
1328 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
1329
1330 /* Clear RF/WF/KF in Ctrl 4A. */
1331 rtc->write(rtc, RTC_EXT_CTRL_4A,
1332 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
1333
1334 /*
1335 * Re-enable KSE to handle power button events. We do not enable
1336 * WIE or RIE by default.
1337 */
1338 rtc->write(rtc, RTC_EXT_CTRL_4B,
1339 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
1340
a2ae8323
AB		 1341 rtc_dev = devm_rtc_allocate_device(&pdev->dev);
1342 if (IS_ERR(rtc_dev))
1343 return PTR_ERR(rtc_dev);
1344
1345 rtc_dev->ops = &ds1685_rtc_ops;
1346
c36b52ed
AB		 1347 /* Century bit is useless because leap year fails in 1900 and 2100 */
1348 rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
1349 rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
1350
a2ae8323
AB		 1351 /* Maximum periodic rate is 8192Hz (0.122070ms). */
1352 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
1353
1354 /* See if the platform doesn't support UIE. */
1355 if (pdata->uie_unsupported)
1356 rtc_dev->uie_unsupported = 1;
1357 rtc->uie_unsupported = pdata->uie_unsupported;
1358
1359 rtc->dev = rtc_dev;
1360
aaaf5fbf
JK		 1361 /*
1362 * Fetch the IRQ and setup the interrupt handler.
1363 *
1364 * Not all platforms have the IRQF pin tied to something. If not, the
1365 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
1366 * there won't be an automatic way of notifying the kernel about it,
1367 * unless ctrlc is explicitly polled.
1368 */
1369 if (!pdata->no_irq) {
1370 ret = platform_get_irq(pdev, 0);
1371 if (ret > 0) {
1372 rtc->irq_num = ret;
1373
1374 /* Request an IRQ. */
1375 ret = devm_request_irq(&pdev->dev, rtc->irq_num,
1376 ds1685_rtc_irq_handler,
1377 IRQF_SHARED, pdev->name, pdev);
1378
1379 /* Check to see if something came back. */
1380 if (unlikely(ret)) {
1381 dev_warn(&pdev->dev,
1382 "RTC interrupt not available\n");
1383 rtc->irq_num = 0;
1384 }
1385 } else
1386 return ret;
1387 }
1388 rtc->no_irq = pdata->no_irq;
1389
1390 /* Setup complete. */
1391 ds1685_rtc_switch_to_bank0(rtc);
1392
aaaf5fbf
JK		 1393#ifdef CONFIG_SYSFS
1394 ret = ds1685_rtc_sysfs_register(&pdev->dev);
1395 if (ret)
a2ae8323 1396 return ret;
aaaf5fbf
JK		 1397#endif
1398
482419e1
AB		 1399 rtc_dev->nvram_old_abi = true;
1400 nvmem_cfg.priv = rtc;
1401 ret = rtc_nvmem_register(rtc_dev, &nvmem_cfg);
1402 if (ret)
1403 return ret;
1404
a2ae8323 1405 return rtc_register_device(rtc_dev);
aaaf5fbf
JK		 1406}
1407
1408/**
1409 * ds1685_rtc_remove - removes rtc driver.
1410 * @pdev: pointer to platform_device structure.
1411 */
1412static int
1413ds1685_rtc_remove(struct platform_device *pdev)
1414{
1415 struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1416
1417#ifdef CONFIG_SYSFS
1418 ds1685_rtc_sysfs_unregister(&pdev->dev);
1419#endif
1420
aaaf5fbf
JK		 1421 /* Read Ctrl B and clear PIE/AIE/UIE. */
1422 rtc->write(rtc, RTC_CTRL_B,
1423 (rtc->read(rtc, RTC_CTRL_B) &
1424 ~(RTC_CTRL_B_PAU_MASK)));
1425
1426 /* Reading Ctrl C auto-clears PF/AF/UF. */
1427 rtc->read(rtc, RTC_CTRL_C);
1428
1429 /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1430 rtc->write(rtc, RTC_EXT_CTRL_4B,
1431 (rtc->read(rtc, RTC_EXT_CTRL_4B) &
1432 ~(RTC_CTRL_4B_RWK_MASK)));
1433
1434 /* Manually clear RF/WF/KF in Ctrl 4A. */
1435 rtc->write(rtc, RTC_EXT_CTRL_4A,
1436 (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1437 ~(RTC_CTRL_4A_RWK_MASK)));
1438
1439 cancel_work_sync(&rtc->work);
1440
1441 return 0;
1442}
1443
1444/**
1445 * ds1685_rtc_driver - rtc driver properties.
1446 */
1447static struct platform_driver ds1685_rtc_driver = {
1448 .driver = {
1449 .name = "rtc-ds1685",
aaaf5fbf
JK		 1450 },
1451 .probe = ds1685_rtc_probe,
1452 .remove = ds1685_rtc_remove,
1453};
508db592 1454module_platform_driver(ds1685_rtc_driver);
aaaf5fbf
JK		 1455/* ----------------------------------------------------------------------- */
1456
1457
1458/* ----------------------------------------------------------------------- */
1459/* Poweroff function */
1460
1461/**
1462 * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
1463 * @pdev: pointer to platform_device structure.
1464 */
52ef84d5 1465void __noreturn
aaaf5fbf
JK		 1466ds1685_rtc_poweroff(struct platform_device *pdev)
1467{
1468 u8 ctrla, ctrl4a, ctrl4b;
1469 struct ds1685_priv *rtc;
1470
1471 /* Check for valid RTC data, else, spin forever. */
1472 if (unlikely(!pdev)) {
a737e835 1473 pr_emerg("platform device data not available, spinning forever ...\n");
361c6ed6 1474 while(1);
aaaf5fbf
JK		 1475 unreachable();
1476 } else {
1477 /* Get the rtc data. */
1478 rtc = platform_get_drvdata(pdev);
1479
1480 /*
1481 * Disable our IRQ. We're powering down, so we're not
1482 * going to worry about cleaning up. Most of that should
1483 * have been taken care of by the shutdown scripts and this
1484 * is the final function call.
1485 */
1486 if (!rtc->no_irq)
1487 disable_irq_nosync(rtc->irq_num);
1488
1489 /* Oscillator must be on and the countdown chain enabled. */
1490 ctrla = rtc->read(rtc, RTC_CTRL_A);
1491 ctrla |= RTC_CTRL_A_DV1;
1492 ctrla &= ~(RTC_CTRL_A_DV2);
1493 rtc->write(rtc, RTC_CTRL_A, ctrla);
1494
1495 /*
1496 * Read Control 4A and check the status of the auxillary
1497 * battery. This must be present and working (VRT2 = 1)
1498 * for wakeup and kickstart functionality to be useful.
1499 */
1500 ds1685_rtc_switch_to_bank1(rtc);
1501 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1502 if (ctrl4a & RTC_CTRL_4A_VRT2) {
1503 /* Clear all of the interrupt flags on Control 4A. */
1504 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
1505 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
1506
1507 /*
1508 * The auxillary battery is present and working.
1509 * Enable extended functions (ABE=1), enable
1510 * wake-up (WIE=1), and enable kickstart (KSE=1)
1511 * in Control 4B.
1512 */
1513 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
1514 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
1515 RTC_CTRL_4B_KSE);
1516 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
1517 }
1518
1519 /* Set PAB to 1 in Control 4A to power the system down. */
1520 dev_warn(&pdev->dev, "Powerdown.\n");
1521 msleep(20);
1522 rtc->write(rtc, RTC_EXT_CTRL_4A,
1523 (ctrl4a | RTC_CTRL_4A_PAB));
1524
1525 /* Spin ... we do not switch back to bank0. */
19105f42 1526 while(1);
aaaf5fbf
JK		 1527 unreachable();
1528 }
1529}
1530EXPORT_SYMBOL(ds1685_rtc_poweroff);
1531/* ----------------------------------------------------------------------- */
1532
1533
1534MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
1535MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
1536MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
1537MODULE_LICENSE("GPL");
aaaf5fbf 1538MODULE_ALIAS("platform:rtc-ds1685");
Linux 6.x block layer and io_uring tree(s)