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aaaf5fbf JK |
1 | /* |
2 | * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time | |
3 | * chips. | |
4 | * | |
5 | * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>. | |
6 | * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>. | |
7 | * | |
8 | * References: | |
9 | * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. | |
10 | * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. | |
11 | * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. | |
12 | * Application Note 90, Using the Multiplex Bus RTC Extended Features. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
a737e835 JP |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
20 | ||
aaaf5fbf JK |
21 | #include <linux/bcd.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/rtc.h> | |
27 | #include <linux/workqueue.h> | |
28 | ||
29 | #include <linux/rtc/ds1685.h> | |
30 | ||
31 | #ifdef CONFIG_PROC_FS | |
32 | #include <linux/proc_fs.h> | |
33 | #endif | |
34 | ||
aaaf5fbf JK |
35 | |
36 | /* ----------------------------------------------------------------------- */ | |
37 | /* Standard read/write functions if platform does not provide overrides */ | |
38 | ||
39 | /** | |
40 | * ds1685_read - read a value from an rtc register. | |
41 | * @rtc: pointer to the ds1685 rtc structure. | |
42 | * @reg: the register address to read. | |
43 | */ | |
44 | static u8 | |
45 | ds1685_read(struct ds1685_priv *rtc, int reg) | |
46 | { | |
47 | return readb((u8 __iomem *)rtc->regs + | |
48 | (reg * rtc->regstep)); | |
49 | } | |
50 | ||
51 | /** | |
52 | * ds1685_write - write a value to an rtc register. | |
53 | * @rtc: pointer to the ds1685 rtc structure. | |
54 | * @reg: the register address to write. | |
55 | * @value: value to write to the register. | |
56 | */ | |
57 | static void | |
58 | ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) | |
59 | { | |
60 | writeb(value, ((u8 __iomem *)rtc->regs + | |
61 | (reg * rtc->regstep))); | |
62 | } | |
63 | /* ----------------------------------------------------------------------- */ | |
64 | ||
65 | ||
66 | /* ----------------------------------------------------------------------- */ | |
67 | /* Inlined functions */ | |
68 | ||
69 | /** | |
70 | * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD. | |
71 | * @rtc: pointer to the ds1685 rtc structure. | |
72 | * @val: u8 time value to consider converting. | |
73 | * @bcd_mask: u8 mask value if BCD mode is used. | |
74 | * @bin_mask: u8 mask value if BIN mode is used. | |
75 | * | |
76 | * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE. | |
77 | */ | |
78 | static inline u8 | |
79 | ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask) | |
80 | { | |
81 | if (rtc->bcd_mode) | |
82 | return (bcd2bin(val) & bcd_mask); | |
83 | ||
84 | return (val & bin_mask); | |
85 | } | |
86 | ||
87 | /** | |
88 | * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD. | |
89 | * @rtc: pointer to the ds1685 rtc structure. | |
90 | * @val: u8 time value to consider converting. | |
91 | * @bin_mask: u8 mask value if BIN mode is used. | |
92 | * @bcd_mask: u8 mask value if BCD mode is used. | |
93 | * | |
94 | * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE. | |
95 | */ | |
96 | static inline u8 | |
97 | ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask) | |
98 | { | |
99 | if (rtc->bcd_mode) | |
100 | return (bin2bcd(val) & bcd_mask); | |
101 | ||
102 | return (val & bin_mask); | |
103 | } | |
104 | ||
c5776dec HS |
105 | /** |
106 | * s1685_rtc_check_mday - check validity of the day of month. | |
107 | * @rtc: pointer to the ds1685 rtc structure. | |
108 | * @mday: day of month. | |
109 | * | |
110 | * Returns -EDOM if the day of month is not within 1..31 range. | |
111 | */ | |
112 | static inline int | |
113 | ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday) | |
114 | { | |
115 | if (rtc->bcd_mode) { | |
116 | if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09) | |
117 | return -EDOM; | |
118 | } else { | |
119 | if (mday < 1 || mday > 31) | |
120 | return -EDOM; | |
121 | } | |
122 | return 0; | |
123 | } | |
124 | ||
aaaf5fbf JK |
125 | /** |
126 | * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0. | |
127 | * @rtc: pointer to the ds1685 rtc structure. | |
128 | */ | |
129 | static inline void | |
130 | ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc) | |
131 | { | |
132 | rtc->write(rtc, RTC_CTRL_A, | |
133 | (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0))); | |
134 | } | |
135 | ||
136 | /** | |
137 | * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1. | |
138 | * @rtc: pointer to the ds1685 rtc structure. | |
139 | */ | |
140 | static inline void | |
141 | ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc) | |
142 | { | |
143 | rtc->write(rtc, RTC_CTRL_A, | |
144 | (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0)); | |
145 | } | |
146 | ||
147 | /** | |
148 | * ds1685_rtc_begin_data_access - prepare the rtc for data access. | |
149 | * @rtc: pointer to the ds1685 rtc structure. | |
150 | * | |
151 | * This takes several steps to prepare the rtc for access to get/set time | |
152 | * and alarm values from the rtc registers: | |
153 | * - Sets the SET bit in Control Register B. | |
154 | * - Reads Ext Control Register 4A and checks the INCR bit. | |
155 | * - If INCR is active, a short delay is added before Ext Control Register 4A | |
156 | * is read again in a loop until INCR is inactive. | |
157 | * - Switches the rtc to bank 1. This allows access to all relevant | |
158 | * data for normal rtc operation, as bank 0 contains only the nvram. | |
159 | */ | |
160 | static inline void | |
161 | ds1685_rtc_begin_data_access(struct ds1685_priv *rtc) | |
162 | { | |
163 | /* Set the SET bit in Ctrl B */ | |
164 | rtc->write(rtc, RTC_CTRL_B, | |
165 | (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); | |
166 | ||
167 | /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ | |
168 | while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) | |
169 | cpu_relax(); | |
170 | ||
171 | /* Switch to Bank 1 */ | |
172 | ds1685_rtc_switch_to_bank1(rtc); | |
173 | } | |
174 | ||
175 | /** | |
176 | * ds1685_rtc_end_data_access - end data access on the rtc. | |
177 | * @rtc: pointer to the ds1685 rtc structure. | |
178 | * | |
179 | * This ends what was started by ds1685_rtc_begin_data_access: | |
180 | * - Switches the rtc back to bank 0. | |
181 | * - Clears the SET bit in Control Register B. | |
182 | */ | |
183 | static inline void | |
184 | ds1685_rtc_end_data_access(struct ds1685_priv *rtc) | |
185 | { | |
186 | /* Switch back to Bank 0 */ | |
187 | ds1685_rtc_switch_to_bank1(rtc); | |
188 | ||
189 | /* Clear the SET bit in Ctrl B */ | |
190 | rtc->write(rtc, RTC_CTRL_B, | |
191 | (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); | |
192 | } | |
193 | ||
194 | /** | |
195 | * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access. | |
196 | * @rtc: pointer to the ds1685 rtc structure. | |
197 | * @flags: irq flags variable for spin_lock_irqsave. | |
198 | * | |
199 | * This takes several steps to prepare the rtc for access to read just the | |
200 | * control registers: | |
201 | * - Sets a spinlock on the rtc IRQ. | |
202 | * - Switches the rtc to bank 1. This allows access to the two extended | |
203 | * control registers. | |
204 | * | |
205 | * Only use this where you are certain another lock will not be held. | |
206 | */ | |
207 | static inline void | |
8c09b9fd | 208 | ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long *flags) |
aaaf5fbf | 209 | { |
8c09b9fd | 210 | spin_lock_irqsave(&rtc->lock, *flags); |
aaaf5fbf JK |
211 | ds1685_rtc_switch_to_bank1(rtc); |
212 | } | |
213 | ||
214 | /** | |
215 | * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc. | |
216 | * @rtc: pointer to the ds1685 rtc structure. | |
217 | * @flags: irq flags variable for spin_unlock_irqrestore. | |
218 | * | |
219 | * This ends what was started by ds1685_rtc_begin_ctrl_access: | |
220 | * - Switches the rtc back to bank 0. | |
221 | * - Unsets the spinlock on the rtc IRQ. | |
222 | */ | |
223 | static inline void | |
224 | ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags) | |
225 | { | |
226 | ds1685_rtc_switch_to_bank0(rtc); | |
227 | spin_unlock_irqrestore(&rtc->lock, flags); | |
228 | } | |
229 | ||
230 | /** | |
231 | * ds1685_rtc_get_ssn - retrieve the silicon serial number. | |
232 | * @rtc: pointer to the ds1685 rtc structure. | |
233 | * @ssn: u8 array to hold the bits of the silicon serial number. | |
234 | * | |
235 | * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The | |
236 | * first byte is the model number, the next six bytes are the serial number | |
237 | * digits, and the final byte is a CRC check byte. Together, they form the | |
238 | * silicon serial number. | |
239 | * | |
240 | * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be | |
241 | * called first before calling this function, else data will be read out of | |
242 | * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done. | |
243 | */ | |
244 | static inline void | |
245 | ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn) | |
246 | { | |
247 | ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL); | |
248 | ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1); | |
249 | ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2); | |
250 | ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3); | |
251 | ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4); | |
252 | ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5); | |
253 | ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6); | |
254 | ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC); | |
255 | } | |
256 | /* ----------------------------------------------------------------------- */ | |
257 | ||
258 | ||
259 | /* ----------------------------------------------------------------------- */ | |
260 | /* Read/Set Time & Alarm functions */ | |
261 | ||
262 | /** | |
263 | * ds1685_rtc_read_time - reads the time registers. | |
264 | * @dev: pointer to device structure. | |
265 | * @tm: pointer to rtc_time structure. | |
266 | */ | |
267 | static int | |
268 | ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
269 | { | |
270 | struct platform_device *pdev = to_platform_device(dev); | |
271 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
272 | u8 ctrlb, century; | |
273 | u8 seconds, minutes, hours, wday, mday, month, years; | |
274 | ||
275 | /* Fetch the time info from the RTC registers. */ | |
276 | ds1685_rtc_begin_data_access(rtc); | |
277 | seconds = rtc->read(rtc, RTC_SECS); | |
278 | minutes = rtc->read(rtc, RTC_MINS); | |
279 | hours = rtc->read(rtc, RTC_HRS); | |
280 | wday = rtc->read(rtc, RTC_WDAY); | |
281 | mday = rtc->read(rtc, RTC_MDAY); | |
282 | month = rtc->read(rtc, RTC_MONTH); | |
283 | years = rtc->read(rtc, RTC_YEAR); | |
284 | century = rtc->read(rtc, RTC_CENTURY); | |
285 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
286 | ds1685_rtc_end_data_access(rtc); | |
287 | ||
288 | /* bcd2bin if needed, perform fixups, and store to rtc_time. */ | |
289 | years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK, | |
290 | RTC_YEAR_BIN_MASK); | |
291 | century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK, | |
292 | RTC_CENTURY_MASK); | |
293 | tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK, | |
294 | RTC_SECS_BIN_MASK); | |
295 | tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK, | |
296 | RTC_MINS_BIN_MASK); | |
297 | tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK, | |
298 | RTC_HRS_24_BIN_MASK); | |
299 | tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK, | |
300 | RTC_WDAY_MASK) - 1); | |
301 | tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, | |
302 | RTC_MDAY_BIN_MASK); | |
303 | tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK, | |
304 | RTC_MONTH_BIN_MASK) - 1); | |
305 | tm->tm_year = ((years + (century * 100)) - 1900); | |
306 | tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); | |
307 | tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */ | |
308 | ||
22652ba7 | 309 | return 0; |
aaaf5fbf JK |
310 | } |
311 | ||
312 | /** | |
313 | * ds1685_rtc_set_time - sets the time registers. | |
314 | * @dev: pointer to device structure. | |
315 | * @tm: pointer to rtc_time structure. | |
316 | */ | |
317 | static int | |
318 | ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
319 | { | |
320 | struct platform_device *pdev = to_platform_device(dev); | |
321 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
322 | u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century; | |
323 | ||
324 | /* Fetch the time info from rtc_time. */ | |
325 | seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK, | |
326 | RTC_SECS_BCD_MASK); | |
327 | minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK, | |
328 | RTC_MINS_BCD_MASK); | |
329 | hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK, | |
330 | RTC_HRS_24_BCD_MASK); | |
331 | wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK, | |
332 | RTC_WDAY_MASK); | |
333 | mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK, | |
334 | RTC_MDAY_BCD_MASK); | |
335 | month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK, | |
336 | RTC_MONTH_BCD_MASK); | |
337 | years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100), | |
338 | RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK); | |
339 | century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100), | |
340 | RTC_CENTURY_MASK, RTC_CENTURY_MASK); | |
341 | ||
342 | /* | |
343 | * Perform Sanity Checks: | |
344 | * - Months: !> 12, Month Day != 0. | |
345 | * - Month Day !> Max days in current month. | |
346 | * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. | |
347 | */ | |
348 | if ((tm->tm_mon > 11) || (mday == 0)) | |
349 | return -EDOM; | |
350 | ||
351 | if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) | |
352 | return -EDOM; | |
353 | ||
354 | if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || | |
355 | (tm->tm_sec >= 60) || (wday > 7)) | |
356 | return -EDOM; | |
357 | ||
358 | /* | |
359 | * Set the data mode to use and store the time values in the | |
360 | * RTC registers. | |
361 | */ | |
362 | ds1685_rtc_begin_data_access(rtc); | |
363 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
364 | if (rtc->bcd_mode) | |
365 | ctrlb &= ~(RTC_CTRL_B_DM); | |
366 | else | |
367 | ctrlb |= RTC_CTRL_B_DM; | |
368 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
369 | rtc->write(rtc, RTC_SECS, seconds); | |
370 | rtc->write(rtc, RTC_MINS, minutes); | |
371 | rtc->write(rtc, RTC_HRS, hours); | |
372 | rtc->write(rtc, RTC_WDAY, wday); | |
373 | rtc->write(rtc, RTC_MDAY, mday); | |
374 | rtc->write(rtc, RTC_MONTH, month); | |
375 | rtc->write(rtc, RTC_YEAR, years); | |
376 | rtc->write(rtc, RTC_CENTURY, century); | |
377 | ds1685_rtc_end_data_access(rtc); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | /** | |
383 | * ds1685_rtc_read_alarm - reads the alarm registers. | |
384 | * @dev: pointer to device structure. | |
385 | * @alrm: pointer to rtc_wkalrm structure. | |
386 | * | |
387 | * There are three primary alarm registers: seconds, minutes, and hours. | |
388 | * A fourth alarm register for the month date is also available in bank1 for | |
389 | * kickstart/wakeup features. The DS1685/DS1687 manual states that a | |
390 | * "don't care" value ranging from 0xc0 to 0xff may be written into one or | |
391 | * more of the three alarm bytes to act as a wildcard value. The fourth | |
392 | * byte doesn't support a "don't care" value. | |
393 | */ | |
394 | static int | |
395 | ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
396 | { | |
397 | struct platform_device *pdev = to_platform_device(dev); | |
398 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
399 | u8 seconds, minutes, hours, mday, ctrlb, ctrlc; | |
c5776dec | 400 | int ret; |
aaaf5fbf JK |
401 | |
402 | /* Fetch the alarm info from the RTC alarm registers. */ | |
403 | ds1685_rtc_begin_data_access(rtc); | |
404 | seconds = rtc->read(rtc, RTC_SECS_ALARM); | |
405 | minutes = rtc->read(rtc, RTC_MINS_ALARM); | |
406 | hours = rtc->read(rtc, RTC_HRS_ALARM); | |
407 | mday = rtc->read(rtc, RTC_MDAY_ALARM); | |
408 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
409 | ctrlc = rtc->read(rtc, RTC_CTRL_C); | |
410 | ds1685_rtc_end_data_access(rtc); | |
411 | ||
c5776dec HS |
412 | /* Check the month date for validity. */ |
413 | ret = ds1685_rtc_check_mday(rtc, mday); | |
414 | if (ret) | |
415 | return ret; | |
aaaf5fbf JK |
416 | |
417 | /* | |
418 | * Check the three alarm bytes. | |
419 | * | |
420 | * The Linux RTC system doesn't support the "don't care" capability | |
421 | * of this RTC chip. We check for it anyways in case support is | |
56d86a7e | 422 | * added in the future and only assign when we care. |
aaaf5fbf | 423 | */ |
56d86a7e | 424 | if (likely(seconds < 0xc0)) |
aaaf5fbf JK |
425 | alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, |
426 | RTC_SECS_BCD_MASK, | |
427 | RTC_SECS_BIN_MASK); | |
428 | ||
56d86a7e | 429 | if (likely(minutes < 0xc0)) |
aaaf5fbf JK |
430 | alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes, |
431 | RTC_MINS_BCD_MASK, | |
432 | RTC_MINS_BIN_MASK); | |
433 | ||
56d86a7e | 434 | if (likely(hours < 0xc0)) |
aaaf5fbf JK |
435 | alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours, |
436 | RTC_HRS_24_BCD_MASK, | |
437 | RTC_HRS_24_BIN_MASK); | |
438 | ||
439 | /* Write the data to rtc_wkalrm. */ | |
440 | alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, | |
441 | RTC_MDAY_BIN_MASK); | |
aaaf5fbf JK |
442 | alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE); |
443 | alrm->pending = !!(ctrlc & RTC_CTRL_C_AF); | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
448 | /** | |
449 | * ds1685_rtc_set_alarm - sets the alarm in registers. | |
450 | * @dev: pointer to device structure. | |
451 | * @alrm: pointer to rtc_wkalrm structure. | |
452 | */ | |
453 | static int | |
454 | ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
455 | { | |
456 | struct platform_device *pdev = to_platform_device(dev); | |
457 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
458 | u8 ctrlb, seconds, minutes, hours, mday; | |
c5776dec | 459 | int ret; |
aaaf5fbf JK |
460 | |
461 | /* Fetch the alarm info and convert to BCD. */ | |
462 | seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec, | |
463 | RTC_SECS_BIN_MASK, | |
464 | RTC_SECS_BCD_MASK); | |
465 | minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min, | |
466 | RTC_MINS_BIN_MASK, | |
467 | RTC_MINS_BCD_MASK); | |
468 | hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour, | |
469 | RTC_HRS_24_BIN_MASK, | |
470 | RTC_HRS_24_BCD_MASK); | |
471 | mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday, | |
472 | RTC_MDAY_BIN_MASK, | |
473 | RTC_MDAY_BCD_MASK); | |
474 | ||
475 | /* Check the month date for validity. */ | |
c5776dec HS |
476 | ret = ds1685_rtc_check_mday(rtc, mday); |
477 | if (ret) | |
478 | return ret; | |
aaaf5fbf JK |
479 | |
480 | /* | |
481 | * Check the three alarm bytes. | |
482 | * | |
483 | * The Linux RTC system doesn't support the "don't care" capability | |
484 | * of this RTC chip because rtc_valid_tm tries to validate every | |
485 | * field, and we only support four fields. We put the support | |
486 | * here anyways for the future. | |
487 | */ | |
39ea34cc | 488 | if (unlikely(seconds >= 0xc0)) |
aaaf5fbf JK |
489 | seconds = 0xff; |
490 | ||
39ea34cc | 491 | if (unlikely(minutes >= 0xc0)) |
aaaf5fbf JK |
492 | minutes = 0xff; |
493 | ||
39ea34cc | 494 | if (unlikely(hours >= 0xc0)) |
aaaf5fbf JK |
495 | hours = 0xff; |
496 | ||
497 | alrm->time.tm_mon = -1; | |
498 | alrm->time.tm_year = -1; | |
499 | alrm->time.tm_wday = -1; | |
500 | alrm->time.tm_yday = -1; | |
501 | alrm->time.tm_isdst = -1; | |
502 | ||
503 | /* Disable the alarm interrupt first. */ | |
504 | ds1685_rtc_begin_data_access(rtc); | |
505 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
506 | rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE))); | |
507 | ||
508 | /* Read ctrlc to clear RTC_CTRL_C_AF. */ | |
509 | rtc->read(rtc, RTC_CTRL_C); | |
510 | ||
511 | /* | |
512 | * Set the data mode to use and store the time values in the | |
513 | * RTC registers. | |
514 | */ | |
515 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
516 | if (rtc->bcd_mode) | |
517 | ctrlb &= ~(RTC_CTRL_B_DM); | |
518 | else | |
519 | ctrlb |= RTC_CTRL_B_DM; | |
520 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
521 | rtc->write(rtc, RTC_SECS_ALARM, seconds); | |
522 | rtc->write(rtc, RTC_MINS_ALARM, minutes); | |
523 | rtc->write(rtc, RTC_HRS_ALARM, hours); | |
524 | rtc->write(rtc, RTC_MDAY_ALARM, mday); | |
525 | ||
526 | /* Re-enable the alarm if needed. */ | |
527 | if (alrm->enabled) { | |
528 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
529 | ctrlb |= RTC_CTRL_B_AIE; | |
530 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
531 | } | |
532 | ||
533 | /* Done! */ | |
534 | ds1685_rtc_end_data_access(rtc); | |
535 | ||
536 | return 0; | |
537 | } | |
538 | /* ----------------------------------------------------------------------- */ | |
539 | ||
540 | ||
541 | /* ----------------------------------------------------------------------- */ | |
542 | /* /dev/rtcX Interface functions */ | |
543 | ||
aaaf5fbf JK |
544 | /** |
545 | * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. | |
546 | * @dev: pointer to device structure. | |
547 | * @enabled: flag indicating whether to enable or disable. | |
548 | */ | |
549 | static int | |
550 | ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
551 | { | |
552 | struct ds1685_priv *rtc = dev_get_drvdata(dev); | |
553 | unsigned long flags = 0; | |
554 | ||
555 | /* Enable/disable the Alarm IRQ-Enable flag. */ | |
556 | spin_lock_irqsave(&rtc->lock, flags); | |
557 | ||
558 | /* Flip the requisite interrupt-enable bit. */ | |
559 | if (enabled) | |
560 | rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) | | |
561 | RTC_CTRL_B_AIE)); | |
562 | else | |
563 | rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) & | |
564 | ~(RTC_CTRL_B_AIE))); | |
565 | ||
566 | /* Read Control C to clear all the flag bits. */ | |
567 | rtc->read(rtc, RTC_CTRL_C); | |
568 | spin_unlock_irqrestore(&rtc->lock, flags); | |
569 | ||
570 | return 0; | |
571 | } | |
aaaf5fbf JK |
572 | /* ----------------------------------------------------------------------- */ |
573 | ||
574 | ||
575 | /* ----------------------------------------------------------------------- */ | |
576 | /* IRQ handler & workqueue. */ | |
577 | ||
578 | /** | |
579 | * ds1685_rtc_irq_handler - IRQ handler. | |
580 | * @irq: IRQ number. | |
581 | * @dev_id: platform device pointer. | |
582 | */ | |
583 | static irqreturn_t | |
584 | ds1685_rtc_irq_handler(int irq, void *dev_id) | |
585 | { | |
586 | struct platform_device *pdev = dev_id; | |
587 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
588 | u8 ctrlb, ctrlc; | |
589 | unsigned long events = 0; | |
590 | u8 num_irqs = 0; | |
591 | ||
592 | /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */ | |
593 | if (unlikely(!rtc)) | |
594 | return IRQ_HANDLED; | |
595 | ||
596 | /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ | |
597 | spin_lock(&rtc->lock); | |
598 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
599 | ctrlc = rtc->read(rtc, RTC_CTRL_C); | |
600 | ||
601 | /* Is the IRQF bit set? */ | |
602 | if (likely(ctrlc & RTC_CTRL_C_IRQF)) { | |
603 | /* | |
604 | * We need to determine if it was one of the standard | |
605 | * events: PF, AF, or UF. If so, we handle them and | |
606 | * update the RTC core. | |
607 | */ | |
608 | if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) { | |
609 | events = RTC_IRQF; | |
610 | ||
611 | /* Check for a periodic interrupt. */ | |
612 | if ((ctrlb & RTC_CTRL_B_PIE) && | |
613 | (ctrlc & RTC_CTRL_C_PF)) { | |
614 | events |= RTC_PF; | |
615 | num_irqs++; | |
616 | } | |
617 | ||
618 | /* Check for an alarm interrupt. */ | |
619 | if ((ctrlb & RTC_CTRL_B_AIE) && | |
620 | (ctrlc & RTC_CTRL_C_AF)) { | |
621 | events |= RTC_AF; | |
622 | num_irqs++; | |
623 | } | |
624 | ||
625 | /* Check for an update interrupt. */ | |
626 | if ((ctrlb & RTC_CTRL_B_UIE) && | |
627 | (ctrlc & RTC_CTRL_C_UF)) { | |
628 | events |= RTC_UF; | |
629 | num_irqs++; | |
630 | } | |
631 | ||
632 | rtc_update_irq(rtc->dev, num_irqs, events); | |
633 | } else { | |
634 | /* | |
635 | * One of the "extended" interrupts was received that | |
636 | * is not recognized by the RTC core. These need to | |
637 | * be handled in task context as they can call other | |
638 | * functions and the time spent in irq context needs | |
639 | * to be minimized. Schedule them into a workqueue | |
640 | * and inform the RTC core that the IRQs were handled. | |
641 | */ | |
642 | spin_unlock(&rtc->lock); | |
643 | schedule_work(&rtc->work); | |
644 | rtc_update_irq(rtc->dev, 0, 0); | |
645 | return IRQ_HANDLED; | |
646 | } | |
647 | } | |
648 | spin_unlock(&rtc->lock); | |
649 | ||
650 | return events ? IRQ_HANDLED : IRQ_NONE; | |
651 | } | |
652 | ||
653 | /** | |
654 | * ds1685_rtc_work_queue - work queue handler. | |
655 | * @work: work_struct containing data to work on in task context. | |
656 | */ | |
657 | static void | |
658 | ds1685_rtc_work_queue(struct work_struct *work) | |
659 | { | |
660 | struct ds1685_priv *rtc = container_of(work, | |
661 | struct ds1685_priv, work); | |
662 | struct platform_device *pdev = to_platform_device(&rtc->dev->dev); | |
663 | struct mutex *rtc_mutex = &rtc->dev->ops_lock; | |
664 | u8 ctrl4a, ctrl4b; | |
665 | ||
666 | mutex_lock(rtc_mutex); | |
667 | ||
668 | ds1685_rtc_switch_to_bank1(rtc); | |
669 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
670 | ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); | |
671 | ||
672 | /* | |
673 | * Check for a kickstart interrupt. With Vcc applied, this | |
674 | * typically means that the power button was pressed, so we | |
675 | * begin the shutdown sequence. | |
676 | */ | |
677 | if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) { | |
678 | /* Briefly disable kickstarts to debounce button presses. */ | |
679 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
680 | (rtc->read(rtc, RTC_EXT_CTRL_4B) & | |
681 | ~(RTC_CTRL_4B_KSE))); | |
682 | ||
683 | /* Clear the kickstart flag. */ | |
684 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
685 | (ctrl4a & ~(RTC_CTRL_4A_KF))); | |
686 | ||
687 | ||
688 | /* | |
689 | * Sleep 500ms before re-enabling kickstarts. This allows | |
690 | * adequate time to avoid reading signal jitter as additional | |
691 | * button presses. | |
692 | */ | |
693 | msleep(500); | |
694 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
695 | (rtc->read(rtc, RTC_EXT_CTRL_4B) | | |
696 | RTC_CTRL_4B_KSE)); | |
697 | ||
698 | /* Call the platform pre-poweroff function. Else, shutdown. */ | |
699 | if (rtc->prepare_poweroff != NULL) | |
700 | rtc->prepare_poweroff(); | |
701 | else | |
702 | ds1685_rtc_poweroff(pdev); | |
703 | } | |
704 | ||
705 | /* | |
706 | * Check for a wake-up interrupt. With Vcc applied, this is | |
707 | * essentially a second alarm interrupt, except it takes into | |
708 | * account the 'date' register in bank1 in addition to the | |
709 | * standard three alarm registers. | |
710 | */ | |
711 | if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) { | |
712 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
713 | (ctrl4a & ~(RTC_CTRL_4A_WF))); | |
714 | ||
715 | /* Call the platform wake_alarm function if defined. */ | |
716 | if (rtc->wake_alarm != NULL) | |
717 | rtc->wake_alarm(); | |
718 | else | |
719 | dev_warn(&pdev->dev, | |
720 | "Wake Alarm IRQ just occurred!\n"); | |
721 | } | |
722 | ||
723 | /* | |
724 | * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0 | |
725 | * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting | |
726 | * each byte to a logic 1. This has no effect on any extended | |
727 | * NV-SRAM that might be present, nor on the time/calendar/alarm | |
728 | * registers. After a ram-clear is completed, there is a minimum | |
729 | * recovery time of ~150ms in which all reads/writes are locked out. | |
730 | * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot | |
731 | * catch this scenario. | |
732 | */ | |
733 | if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) { | |
734 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
735 | (ctrl4a & ~(RTC_CTRL_4A_RF))); | |
736 | msleep(150); | |
737 | ||
738 | /* Call the platform post_ram_clear function if defined. */ | |
739 | if (rtc->post_ram_clear != NULL) | |
740 | rtc->post_ram_clear(); | |
741 | else | |
742 | dev_warn(&pdev->dev, | |
743 | "RAM-Clear IRQ just occurred!\n"); | |
744 | } | |
745 | ds1685_rtc_switch_to_bank0(rtc); | |
746 | ||
747 | mutex_unlock(rtc_mutex); | |
748 | } | |
749 | /* ----------------------------------------------------------------------- */ | |
750 | ||
751 | ||
752 | /* ----------------------------------------------------------------------- */ | |
753 | /* ProcFS interface */ | |
754 | ||
755 | #ifdef CONFIG_PROC_FS | |
756 | #define NUM_REGS 6 /* Num of control registers. */ | |
757 | #define NUM_BITS 8 /* Num bits per register. */ | |
758 | #define NUM_SPACES 4 /* Num spaces between each bit. */ | |
759 | ||
760 | /* | |
761 | * Periodic Interrupt Rates. | |
762 | */ | |
763 | static const char *ds1685_rtc_pirq_rate[16] = { | |
764 | "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms", | |
765 | "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms", | |
766 | "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" | |
767 | }; | |
768 | ||
769 | /* | |
770 | * Square-Wave Output Frequencies. | |
771 | */ | |
772 | static const char *ds1685_rtc_sqw_freq[16] = { | |
773 | "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz", | |
774 | "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz" | |
775 | }; | |
776 | ||
777 | #ifdef CONFIG_RTC_DS1685_PROC_REGS | |
778 | /** | |
779 | * ds1685_rtc_print_regs - helper function to print register values. | |
780 | * @hex: hex byte to convert into binary bits. | |
781 | * @dest: destination char array. | |
782 | * | |
783 | * This is basically a hex->binary function, just with extra spacing between | |
784 | * the digits. It only works on 1-byte values (8 bits). | |
785 | */ | |
786 | static char* | |
787 | ds1685_rtc_print_regs(u8 hex, char *dest) | |
788 | { | |
789 | u32 i, j; | |
790 | char *tmp = dest; | |
791 | ||
792 | for (i = 0; i < NUM_BITS; i++) { | |
793 | *tmp++ = ((hex & 0x80) != 0 ? '1' : '0'); | |
794 | for (j = 0; j < NUM_SPACES; j++) | |
795 | *tmp++ = ' '; | |
796 | hex <<= 1; | |
797 | } | |
798 | *tmp++ = '\0'; | |
799 | ||
800 | return dest; | |
801 | } | |
802 | #endif | |
803 | ||
804 | /** | |
805 | * ds1685_rtc_proc - procfs access function. | |
806 | * @dev: pointer to device structure. | |
807 | * @seq: pointer to seq_file structure. | |
808 | */ | |
809 | static int | |
810 | ds1685_rtc_proc(struct device *dev, struct seq_file *seq) | |
811 | { | |
812 | struct platform_device *pdev = to_platform_device(dev); | |
813 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
814 | u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8]; | |
52ef84d5 | 815 | char *model; |
aaaf5fbf JK |
816 | #ifdef CONFIG_RTC_DS1685_PROC_REGS |
817 | char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1]; | |
818 | #endif | |
819 | ||
820 | /* Read all the relevant data from the control registers. */ | |
821 | ds1685_rtc_switch_to_bank1(rtc); | |
822 | ds1685_rtc_get_ssn(rtc, ssn); | |
823 | ctrla = rtc->read(rtc, RTC_CTRL_A); | |
824 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
825 | ctrlc = rtc->read(rtc, RTC_CTRL_C); | |
826 | ctrld = rtc->read(rtc, RTC_CTRL_D); | |
827 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
828 | ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); | |
829 | ds1685_rtc_switch_to_bank0(rtc); | |
830 | ||
831 | /* Determine the RTC model. */ | |
832 | switch (ssn[0]) { | |
833 | case RTC_MODEL_DS1685: | |
834 | model = "DS1685/DS1687\0"; | |
835 | break; | |
836 | case RTC_MODEL_DS1689: | |
837 | model = "DS1689/DS1693\0"; | |
838 | break; | |
839 | case RTC_MODEL_DS17285: | |
840 | model = "DS17285/DS17287\0"; | |
841 | break; | |
842 | case RTC_MODEL_DS17485: | |
843 | model = "DS17485/DS17487\0"; | |
844 | break; | |
845 | case RTC_MODEL_DS17885: | |
846 | model = "DS17885/DS17887\0"; | |
847 | break; | |
848 | default: | |
849 | model = "Unknown\0"; | |
850 | break; | |
851 | } | |
852 | ||
853 | /* Print out the information. */ | |
854 | seq_printf(seq, | |
855 | "Model\t\t: %s\n" | |
856 | "Oscillator\t: %s\n" | |
857 | "12/24hr\t\t: %s\n" | |
858 | "DST\t\t: %s\n" | |
859 | "Data mode\t: %s\n" | |
860 | "Battery\t\t: %s\n" | |
861 | "Aux batt\t: %s\n" | |
862 | "Update IRQ\t: %s\n" | |
863 | "Periodic IRQ\t: %s\n" | |
864 | "Periodic Rate\t: %s\n" | |
865 | "SQW Freq\t: %s\n" | |
866 | #ifdef CONFIG_RTC_DS1685_PROC_REGS | |
ff67abd2 | 867 | "Serial #\t: %8phC\n" |
aaaf5fbf JK |
868 | "Register Status\t:\n" |
869 | " Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n" | |
870 | "\t\t: %s\n" | |
871 | " Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n" | |
872 | "\t\t: %s\n" | |
873 | " Ctrl C\t: IRQF PF AF UF --- --- --- ---\n" | |
874 | "\t\t: %s\n" | |
875 | " Ctrl D\t: VRT --- --- --- --- --- --- ---\n" | |
876 | "\t\t: %s\n" | |
877 | #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) | |
878 | " Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n" | |
879 | #else | |
880 | " Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n" | |
881 | #endif | |
882 | "\t\t: %s\n" | |
883 | " Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n" | |
884 | "\t\t: %s\n", | |
885 | #else | |
ff67abd2 | 886 | "Serial #\t: %8phC\n", |
aaaf5fbf JK |
887 | #endif |
888 | model, | |
889 | ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), | |
890 | ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), | |
891 | ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), | |
892 | ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), | |
893 | ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), | |
894 | ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), | |
895 | ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"), | |
896 | ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"), | |
897 | (!(ctrl4b & RTC_CTRL_4B_E32K) ? | |
898 | ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"), | |
899 | (!((ctrl4b & RTC_CTRL_4B_E32K)) ? | |
900 | ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"), | |
901 | #ifdef CONFIG_RTC_DS1685_PROC_REGS | |
ff67abd2 | 902 | ssn, |
aaaf5fbf JK |
903 | ds1685_rtc_print_regs(ctrla, bits[0]), |
904 | ds1685_rtc_print_regs(ctrlb, bits[1]), | |
905 | ds1685_rtc_print_regs(ctrlc, bits[2]), | |
906 | ds1685_rtc_print_regs(ctrld, bits[3]), | |
907 | ds1685_rtc_print_regs(ctrl4a, bits[4]), | |
908 | ds1685_rtc_print_regs(ctrl4b, bits[5])); | |
909 | #else | |
ff67abd2 | 910 | ssn); |
aaaf5fbf JK |
911 | #endif |
912 | return 0; | |
913 | } | |
914 | #else | |
915 | #define ds1685_rtc_proc NULL | |
916 | #endif /* CONFIG_PROC_FS */ | |
917 | /* ----------------------------------------------------------------------- */ | |
918 | ||
919 | ||
920 | /* ----------------------------------------------------------------------- */ | |
921 | /* RTC Class operations */ | |
922 | ||
923 | static const struct rtc_class_ops | |
924 | ds1685_rtc_ops = { | |
925 | .proc = ds1685_rtc_proc, | |
926 | .read_time = ds1685_rtc_read_time, | |
927 | .set_time = ds1685_rtc_set_time, | |
928 | .read_alarm = ds1685_rtc_read_alarm, | |
929 | .set_alarm = ds1685_rtc_set_alarm, | |
930 | .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, | |
931 | }; | |
932 | /* ----------------------------------------------------------------------- */ | |
933 | ||
934 | ||
935 | /* ----------------------------------------------------------------------- */ | |
936 | /* SysFS interface */ | |
937 | ||
938 | #ifdef CONFIG_SYSFS | |
939 | /** | |
940 | * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs. | |
941 | * @file: pointer to file structure. | |
942 | * @kobj: pointer to kobject structure. | |
943 | * @bin_attr: pointer to bin_attribute structure. | |
944 | * @buf: pointer to char array to hold the output. | |
945 | * @pos: current file position pointer. | |
946 | * @size: size of the data to read. | |
947 | */ | |
948 | static ssize_t | |
949 | ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj, | |
950 | struct bin_attribute *bin_attr, char *buf, | |
951 | loff_t pos, size_t size) | |
952 | { | |
953 | struct platform_device *pdev = | |
954 | to_platform_device(container_of(kobj, struct device, kobj)); | |
955 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
956 | ssize_t count; | |
957 | unsigned long flags = 0; | |
958 | ||
959 | spin_lock_irqsave(&rtc->lock, flags); | |
960 | ds1685_rtc_switch_to_bank0(rtc); | |
961 | ||
962 | /* Read NVRAM in time and bank0 registers. */ | |
963 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; | |
964 | count++, size--) { | |
965 | if (count < NVRAM_SZ_TIME) | |
966 | *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++)); | |
967 | else | |
968 | *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++)); | |
969 | } | |
970 | ||
971 | #ifndef CONFIG_RTC_DRV_DS1689 | |
972 | if (size > 0) { | |
973 | ds1685_rtc_switch_to_bank1(rtc); | |
974 | ||
975 | #ifndef CONFIG_RTC_DRV_DS1685 | |
976 | /* Enable burst-mode on DS17x85/DS17x87 */ | |
977 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
978 | (rtc->read(rtc, RTC_EXT_CTRL_4A) | | |
979 | RTC_CTRL_4A_BME)); | |
980 | ||
981 | /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start | |
982 | * reading with burst-mode */ | |
983 | rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, | |
984 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
985 | #endif | |
986 | ||
987 | /* Read NVRAM in bank1 registers. */ | |
988 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; | |
989 | count++, size--) { | |
990 | #ifdef CONFIG_RTC_DRV_DS1685 | |
991 | /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR | |
992 | * before each read. */ | |
993 | rtc->write(rtc, RTC_BANK1_RAM_ADDR, | |
994 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
995 | #endif | |
996 | *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT); | |
997 | pos++; | |
998 | } | |
999 | ||
1000 | #ifndef CONFIG_RTC_DRV_DS1685 | |
1001 | /* Disable burst-mode on DS17x85/DS17x87 */ | |
1002 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
1003 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & | |
1004 | ~(RTC_CTRL_4A_BME))); | |
1005 | #endif | |
1006 | ds1685_rtc_switch_to_bank0(rtc); | |
1007 | } | |
1008 | #endif /* !CONFIG_RTC_DRV_DS1689 */ | |
1009 | spin_unlock_irqrestore(&rtc->lock, flags); | |
1010 | ||
1011 | /* | |
1012 | * XXX: Bug? this appears to cause the function to get executed | |
1013 | * several times in succession. But it's the only way to actually get | |
1014 | * data written out to a file. | |
1015 | */ | |
1016 | return count; | |
1017 | } | |
1018 | ||
1019 | /** | |
1020 | * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs. | |
1021 | * @file: pointer to file structure. | |
1022 | * @kobj: pointer to kobject structure. | |
1023 | * @bin_attr: pointer to bin_attribute structure. | |
1024 | * @buf: pointer to char array to hold the input. | |
1025 | * @pos: current file position pointer. | |
1026 | * @size: size of the data to write. | |
1027 | */ | |
1028 | static ssize_t | |
1029 | ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj, | |
1030 | struct bin_attribute *bin_attr, char *buf, | |
1031 | loff_t pos, size_t size) | |
1032 | { | |
1033 | struct platform_device *pdev = | |
1034 | to_platform_device(container_of(kobj, struct device, kobj)); | |
1035 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
1036 | ssize_t count; | |
1037 | unsigned long flags = 0; | |
1038 | ||
1039 | spin_lock_irqsave(&rtc->lock, flags); | |
1040 | ds1685_rtc_switch_to_bank0(rtc); | |
1041 | ||
1042 | /* Write NVRAM in time and bank0 registers. */ | |
1043 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; | |
1044 | count++, size--) | |
1045 | if (count < NVRAM_SZ_TIME) | |
1046 | rtc->write(rtc, (NVRAM_TIME_BASE + pos++), | |
1047 | *buf++); | |
1048 | else | |
1049 | rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++); | |
1050 | ||
1051 | #ifndef CONFIG_RTC_DRV_DS1689 | |
1052 | if (size > 0) { | |
1053 | ds1685_rtc_switch_to_bank1(rtc); | |
1054 | ||
1055 | #ifndef CONFIG_RTC_DRV_DS1685 | |
1056 | /* Enable burst-mode on DS17x85/DS17x87 */ | |
1057 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
1058 | (rtc->read(rtc, RTC_EXT_CTRL_4A) | | |
1059 | RTC_CTRL_4A_BME)); | |
1060 | ||
1061 | /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start | |
1062 | * writing with burst-mode */ | |
1063 | rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, | |
1064 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
1065 | #endif | |
1066 | ||
1067 | /* Write NVRAM in bank1 registers. */ | |
1068 | for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; | |
1069 | count++, size--) { | |
1070 | #ifdef CONFIG_RTC_DRV_DS1685 | |
1071 | /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR | |
1072 | * before each read. */ | |
1073 | rtc->write(rtc, RTC_BANK1_RAM_ADDR, | |
1074 | (pos - NVRAM_TOTAL_SZ_BANK0)); | |
1075 | #endif | |
1076 | rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++); | |
1077 | pos++; | |
1078 | } | |
1079 | ||
1080 | #ifndef CONFIG_RTC_DRV_DS1685 | |
1081 | /* Disable burst-mode on DS17x85/DS17x87 */ | |
1082 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
1083 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & | |
1084 | ~(RTC_CTRL_4A_BME))); | |
1085 | #endif | |
1086 | ds1685_rtc_switch_to_bank0(rtc); | |
1087 | } | |
1088 | #endif /* !CONFIG_RTC_DRV_DS1689 */ | |
1089 | spin_unlock_irqrestore(&rtc->lock, flags); | |
1090 | ||
1091 | return count; | |
1092 | } | |
1093 | ||
1094 | /** | |
1095 | * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram. | |
1096 | * @attr: nvram attributes. | |
1097 | * @read: nvram read function. | |
1098 | * @write: nvram write function. | |
1099 | * @size: nvram total size (bank0 + extended). | |
1100 | */ | |
1101 | static struct bin_attribute | |
1102 | ds1685_rtc_sysfs_nvram_attr = { | |
1103 | .attr = { | |
1104 | .name = "nvram", | |
1105 | .mode = S_IRUGO | S_IWUSR, | |
1106 | }, | |
1107 | .read = ds1685_rtc_sysfs_nvram_read, | |
1108 | .write = ds1685_rtc_sysfs_nvram_write, | |
1109 | .size = NVRAM_TOTAL_SZ | |
1110 | }; | |
1111 | ||
1112 | /** | |
1113 | * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status. | |
1114 | * @dev: pointer to device structure. | |
1115 | * @attr: pointer to device_attribute structure. | |
1116 | * @buf: pointer to char array to hold the output. | |
1117 | */ | |
1118 | static ssize_t | |
1119 | ds1685_rtc_sysfs_battery_show(struct device *dev, | |
1120 | struct device_attribute *attr, char *buf) | |
1121 | { | |
1122 | struct platform_device *pdev = to_platform_device(dev); | |
1123 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
1124 | u8 ctrld; | |
1125 | ||
1126 | ctrld = rtc->read(rtc, RTC_CTRL_D); | |
1127 | ||
9c25a106 | 1128 | return sprintf(buf, "%s\n", |
aaaf5fbf JK |
1129 | (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A"); |
1130 | } | |
1131 | static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL); | |
1132 | ||
1133 | /** | |
1134 | * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status. | |
1135 | * @dev: pointer to device structure. | |
1136 | * @attr: pointer to device_attribute structure. | |
1137 | * @buf: pointer to char array to hold the output. | |
1138 | */ | |
1139 | static ssize_t | |
1140 | ds1685_rtc_sysfs_auxbatt_show(struct device *dev, | |
1141 | struct device_attribute *attr, char *buf) | |
1142 | { | |
1143 | struct platform_device *pdev = to_platform_device(dev); | |
1144 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
1145 | u8 ctrl4a; | |
1146 | ||
1147 | ds1685_rtc_switch_to_bank1(rtc); | |
1148 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
1149 | ds1685_rtc_switch_to_bank0(rtc); | |
1150 | ||
9c25a106 | 1151 | return sprintf(buf, "%s\n", |
aaaf5fbf JK |
1152 | (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A"); |
1153 | } | |
1154 | static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL); | |
1155 | ||
1156 | /** | |
1157 | * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number. | |
1158 | * @dev: pointer to device structure. | |
1159 | * @attr: pointer to device_attribute structure. | |
1160 | * @buf: pointer to char array to hold the output. | |
1161 | */ | |
1162 | static ssize_t | |
1163 | ds1685_rtc_sysfs_serial_show(struct device *dev, | |
1164 | struct device_attribute *attr, char *buf) | |
1165 | { | |
1166 | struct platform_device *pdev = to_platform_device(dev); | |
1167 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
1168 | u8 ssn[8]; | |
1169 | ||
1170 | ds1685_rtc_switch_to_bank1(rtc); | |
1171 | ds1685_rtc_get_ssn(rtc, ssn); | |
1172 | ds1685_rtc_switch_to_bank0(rtc); | |
1173 | ||
9c25a106 | 1174 | return sprintf(buf, "%8phC\n", ssn); |
aaaf5fbf JK |
1175 | } |
1176 | static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL); | |
1177 | ||
1178 | /** | |
1179 | * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features. | |
1180 | */ | |
1181 | static struct attribute* | |
1182 | ds1685_rtc_sysfs_misc_attrs[] = { | |
1183 | &dev_attr_battery.attr, | |
1184 | &dev_attr_auxbatt.attr, | |
1185 | &dev_attr_serial.attr, | |
1186 | NULL, | |
1187 | }; | |
1188 | ||
1189 | /** | |
1190 | * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features. | |
1191 | */ | |
1192 | static const struct attribute_group | |
1193 | ds1685_rtc_sysfs_misc_grp = { | |
1194 | .name = "misc", | |
1195 | .attrs = ds1685_rtc_sysfs_misc_attrs, | |
1196 | }; | |
1197 | ||
1198 | #ifdef CONFIG_RTC_DS1685_SYSFS_REGS | |
1199 | /** | |
1200 | * struct ds1685_rtc_ctrl_regs. | |
1201 | * @name: char pointer for the bit name. | |
1202 | * @reg: control register the bit is in. | |
1203 | * @bit: the bit's offset in the register. | |
1204 | */ | |
1205 | struct ds1685_rtc_ctrl_regs { | |
1206 | const char *name; | |
1207 | const u8 reg; | |
1208 | const u8 bit; | |
1209 | }; | |
1210 | ||
1211 | /* | |
1212 | * Ctrl register bit lookup table. | |
1213 | */ | |
1214 | static const struct ds1685_rtc_ctrl_regs | |
1215 | ds1685_ctrl_regs_table[] = { | |
1216 | { "uip", RTC_CTRL_A, RTC_CTRL_A_UIP }, | |
1217 | { "dv2", RTC_CTRL_A, RTC_CTRL_A_DV2 }, | |
1218 | { "dv1", RTC_CTRL_A, RTC_CTRL_A_DV1 }, | |
1219 | { "dv0", RTC_CTRL_A, RTC_CTRL_A_DV0 }, | |
1220 | { "rs3", RTC_CTRL_A, RTC_CTRL_A_RS3 }, | |
1221 | { "rs2", RTC_CTRL_A, RTC_CTRL_A_RS2 }, | |
1222 | { "rs1", RTC_CTRL_A, RTC_CTRL_A_RS1 }, | |
1223 | { "rs0", RTC_CTRL_A, RTC_CTRL_A_RS0 }, | |
1224 | { "set", RTC_CTRL_B, RTC_CTRL_B_SET }, | |
1225 | { "pie", RTC_CTRL_B, RTC_CTRL_B_PIE }, | |
1226 | { "aie", RTC_CTRL_B, RTC_CTRL_B_AIE }, | |
1227 | { "uie", RTC_CTRL_B, RTC_CTRL_B_UIE }, | |
1228 | { "sqwe", RTC_CTRL_B, RTC_CTRL_B_SQWE }, | |
1229 | { "dm", RTC_CTRL_B, RTC_CTRL_B_DM }, | |
1230 | { "2412", RTC_CTRL_B, RTC_CTRL_B_2412 }, | |
1231 | { "dse", RTC_CTRL_B, RTC_CTRL_B_DSE }, | |
1232 | { "irqf", RTC_CTRL_C, RTC_CTRL_C_IRQF }, | |
1233 | { "pf", RTC_CTRL_C, RTC_CTRL_C_PF }, | |
1234 | { "af", RTC_CTRL_C, RTC_CTRL_C_AF }, | |
1235 | { "uf", RTC_CTRL_C, RTC_CTRL_C_UF }, | |
1236 | { "vrt", RTC_CTRL_D, RTC_CTRL_D_VRT }, | |
1237 | { "vrt2", RTC_EXT_CTRL_4A, RTC_CTRL_4A_VRT2 }, | |
1238 | { "incr", RTC_EXT_CTRL_4A, RTC_CTRL_4A_INCR }, | |
1239 | { "pab", RTC_EXT_CTRL_4A, RTC_CTRL_4A_PAB }, | |
1240 | { "rf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_RF }, | |
1241 | { "wf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_WF }, | |
1242 | { "kf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_KF }, | |
1243 | #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) | |
1244 | { "bme", RTC_EXT_CTRL_4A, RTC_CTRL_4A_BME }, | |
1245 | #endif | |
1246 | { "abe", RTC_EXT_CTRL_4B, RTC_CTRL_4B_ABE }, | |
1247 | { "e32k", RTC_EXT_CTRL_4B, RTC_CTRL_4B_E32K }, | |
1248 | { "cs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_CS }, | |
1249 | { "rce", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RCE }, | |
1250 | { "prs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_PRS }, | |
1251 | { "rie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RIE }, | |
1252 | { "wie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_WIE }, | |
1253 | { "kse", RTC_EXT_CTRL_4B, RTC_CTRL_4B_KSE }, | |
1254 | { NULL, 0, 0 }, | |
1255 | }; | |
1256 | ||
1257 | /** | |
1258 | * ds1685_rtc_sysfs_ctrl_regs_lookup - ctrl register bit lookup function. | |
1259 | * @name: ctrl register bit to look up in ds1685_ctrl_regs_table. | |
1260 | */ | |
1261 | static const struct ds1685_rtc_ctrl_regs* | |
1262 | ds1685_rtc_sysfs_ctrl_regs_lookup(const char *name) | |
1263 | { | |
1264 | const struct ds1685_rtc_ctrl_regs *p = ds1685_ctrl_regs_table; | |
1265 | ||
1266 | for (; p->name != NULL; ++p) | |
1267 | if (strcmp(p->name, name) == 0) | |
1268 | return p; | |
1269 | ||
1270 | return NULL; | |
1271 | } | |
1272 | ||
1273 | /** | |
1274 | * ds1685_rtc_sysfs_ctrl_regs_show - reads a ctrl register bit via sysfs. | |
1275 | * @dev: pointer to device structure. | |
1276 | * @attr: pointer to device_attribute structure. | |
1277 | * @buf: pointer to char array to hold the output. | |
1278 | */ | |
1279 | static ssize_t | |
1280 | ds1685_rtc_sysfs_ctrl_regs_show(struct device *dev, | |
1281 | struct device_attribute *attr, char *buf) | |
1282 | { | |
1283 | u8 tmp; | |
1284 | struct ds1685_priv *rtc = dev_get_drvdata(dev); | |
1285 | const struct ds1685_rtc_ctrl_regs *reg_info = | |
1286 | ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name); | |
1287 | ||
1288 | /* Make sure we actually matched something. */ | |
1289 | if (!reg_info) | |
1290 | return -EINVAL; | |
1291 | ||
1292 | /* No spinlock during a read -- mutex is already held. */ | |
1293 | ds1685_rtc_switch_to_bank1(rtc); | |
1294 | tmp = rtc->read(rtc, reg_info->reg) & reg_info->bit; | |
1295 | ds1685_rtc_switch_to_bank0(rtc); | |
1296 | ||
9c25a106 | 1297 | return sprintf(buf, "%d\n", (tmp ? 1 : 0)); |
aaaf5fbf JK |
1298 | } |
1299 | ||
1300 | /** | |
1301 | * ds1685_rtc_sysfs_ctrl_regs_store - writes a ctrl register bit via sysfs. | |
1302 | * @dev: pointer to device structure. | |
1303 | * @attr: pointer to device_attribute structure. | |
1304 | * @buf: pointer to char array to hold the output. | |
1305 | * @count: number of bytes written. | |
1306 | */ | |
1307 | static ssize_t | |
1308 | ds1685_rtc_sysfs_ctrl_regs_store(struct device *dev, | |
1309 | struct device_attribute *attr, | |
1310 | const char *buf, size_t count) | |
1311 | { | |
1312 | struct ds1685_priv *rtc = dev_get_drvdata(dev); | |
1313 | u8 reg = 0, bit = 0, tmp; | |
8c09b9fd | 1314 | unsigned long flags; |
aaaf5fbf JK |
1315 | long int val = 0; |
1316 | const struct ds1685_rtc_ctrl_regs *reg_info = | |
1317 | ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name); | |
1318 | ||
1319 | /* We only accept numbers. */ | |
1320 | if (kstrtol(buf, 10, &val) < 0) | |
1321 | return -EINVAL; | |
1322 | ||
1323 | /* bits are binary, 0 or 1 only. */ | |
1324 | if ((val != 0) && (val != 1)) | |
1325 | return -ERANGE; | |
1326 | ||
1327 | /* Make sure we actually matched something. */ | |
1328 | if (!reg_info) | |
1329 | return -EINVAL; | |
1330 | ||
1331 | reg = reg_info->reg; | |
1332 | bit = reg_info->bit; | |
1333 | ||
1334 | /* Safe to spinlock during a write. */ | |
8c09b9fd | 1335 | ds1685_rtc_begin_ctrl_access(rtc, &flags); |
aaaf5fbf JK |
1336 | tmp = rtc->read(rtc, reg); |
1337 | rtc->write(rtc, reg, (val ? (tmp | bit) : (tmp & ~(bit)))); | |
1338 | ds1685_rtc_end_ctrl_access(rtc, flags); | |
1339 | ||
1340 | return count; | |
1341 | } | |
1342 | ||
1343 | /** | |
1344 | * DS1685_RTC_SYSFS_CTRL_REG_RO - device_attribute for read-only register bit. | |
1345 | * @bit: bit to read. | |
1346 | */ | |
1347 | #define DS1685_RTC_SYSFS_CTRL_REG_RO(bit) \ | |
1348 | static DEVICE_ATTR(bit, S_IRUGO, \ | |
1349 | ds1685_rtc_sysfs_ctrl_regs_show, NULL) | |
1350 | ||
1351 | /** | |
1352 | * DS1685_RTC_SYSFS_CTRL_REG_RW - device_attribute for read-write register bit. | |
1353 | * @bit: bit to read or write. | |
1354 | */ | |
1355 | #define DS1685_RTC_SYSFS_CTRL_REG_RW(bit) \ | |
1356 | static DEVICE_ATTR(bit, S_IRUGO | S_IWUSR, \ | |
1357 | ds1685_rtc_sysfs_ctrl_regs_show, \ | |
1358 | ds1685_rtc_sysfs_ctrl_regs_store) | |
1359 | ||
1360 | /* | |
1361 | * Control Register A bits. | |
1362 | */ | |
1363 | DS1685_RTC_SYSFS_CTRL_REG_RO(uip); | |
1364 | DS1685_RTC_SYSFS_CTRL_REG_RW(dv2); | |
1365 | DS1685_RTC_SYSFS_CTRL_REG_RW(dv1); | |
1366 | DS1685_RTC_SYSFS_CTRL_REG_RO(dv0); | |
1367 | DS1685_RTC_SYSFS_CTRL_REG_RW(rs3); | |
1368 | DS1685_RTC_SYSFS_CTRL_REG_RW(rs2); | |
1369 | DS1685_RTC_SYSFS_CTRL_REG_RW(rs1); | |
1370 | DS1685_RTC_SYSFS_CTRL_REG_RW(rs0); | |
1371 | ||
1372 | static struct attribute* | |
1373 | ds1685_rtc_sysfs_ctrla_attrs[] = { | |
1374 | &dev_attr_uip.attr, | |
1375 | &dev_attr_dv2.attr, | |
1376 | &dev_attr_dv1.attr, | |
1377 | &dev_attr_dv0.attr, | |
1378 | &dev_attr_rs3.attr, | |
1379 | &dev_attr_rs2.attr, | |
1380 | &dev_attr_rs1.attr, | |
1381 | &dev_attr_rs0.attr, | |
1382 | NULL, | |
1383 | }; | |
1384 | ||
1385 | static const struct attribute_group | |
1386 | ds1685_rtc_sysfs_ctrla_grp = { | |
1387 | .name = "ctrla", | |
1388 | .attrs = ds1685_rtc_sysfs_ctrla_attrs, | |
1389 | }; | |
1390 | ||
1391 | ||
1392 | /* | |
1393 | * Control Register B bits. | |
1394 | */ | |
1395 | DS1685_RTC_SYSFS_CTRL_REG_RO(set); | |
1396 | DS1685_RTC_SYSFS_CTRL_REG_RW(pie); | |
1397 | DS1685_RTC_SYSFS_CTRL_REG_RW(aie); | |
1398 | DS1685_RTC_SYSFS_CTRL_REG_RW(uie); | |
1399 | DS1685_RTC_SYSFS_CTRL_REG_RW(sqwe); | |
1400 | DS1685_RTC_SYSFS_CTRL_REG_RO(dm); | |
1401 | DS1685_RTC_SYSFS_CTRL_REG_RO(2412); | |
1402 | DS1685_RTC_SYSFS_CTRL_REG_RO(dse); | |
1403 | ||
1404 | static struct attribute* | |
1405 | ds1685_rtc_sysfs_ctrlb_attrs[] = { | |
1406 | &dev_attr_set.attr, | |
1407 | &dev_attr_pie.attr, | |
1408 | &dev_attr_aie.attr, | |
1409 | &dev_attr_uie.attr, | |
1410 | &dev_attr_sqwe.attr, | |
1411 | &dev_attr_dm.attr, | |
1412 | &dev_attr_2412.attr, | |
1413 | &dev_attr_dse.attr, | |
1414 | NULL, | |
1415 | }; | |
1416 | ||
1417 | static const struct attribute_group | |
1418 | ds1685_rtc_sysfs_ctrlb_grp = { | |
1419 | .name = "ctrlb", | |
1420 | .attrs = ds1685_rtc_sysfs_ctrlb_attrs, | |
1421 | }; | |
1422 | ||
1423 | /* | |
1424 | * Control Register C bits. | |
1425 | * | |
1426 | * Reading Control C clears these bits! Reading them individually can | |
1427 | * possibly cause an interrupt to be missed. Use the /proc interface | |
1428 | * to see all the bits in this register simultaneously. | |
1429 | */ | |
1430 | DS1685_RTC_SYSFS_CTRL_REG_RO(irqf); | |
1431 | DS1685_RTC_SYSFS_CTRL_REG_RO(pf); | |
1432 | DS1685_RTC_SYSFS_CTRL_REG_RO(af); | |
1433 | DS1685_RTC_SYSFS_CTRL_REG_RO(uf); | |
1434 | ||
1435 | static struct attribute* | |
1436 | ds1685_rtc_sysfs_ctrlc_attrs[] = { | |
1437 | &dev_attr_irqf.attr, | |
1438 | &dev_attr_pf.attr, | |
1439 | &dev_attr_af.attr, | |
1440 | &dev_attr_uf.attr, | |
1441 | NULL, | |
1442 | }; | |
1443 | ||
1444 | static const struct attribute_group | |
1445 | ds1685_rtc_sysfs_ctrlc_grp = { | |
1446 | .name = "ctrlc", | |
1447 | .attrs = ds1685_rtc_sysfs_ctrlc_attrs, | |
1448 | }; | |
1449 | ||
1450 | /* | |
1451 | * Control Register D bits. | |
1452 | */ | |
1453 | DS1685_RTC_SYSFS_CTRL_REG_RO(vrt); | |
1454 | ||
1455 | static struct attribute* | |
1456 | ds1685_rtc_sysfs_ctrld_attrs[] = { | |
1457 | &dev_attr_vrt.attr, | |
1458 | NULL, | |
1459 | }; | |
1460 | ||
1461 | static const struct attribute_group | |
1462 | ds1685_rtc_sysfs_ctrld_grp = { | |
1463 | .name = "ctrld", | |
1464 | .attrs = ds1685_rtc_sysfs_ctrld_attrs, | |
1465 | }; | |
1466 | ||
1467 | /* | |
1468 | * Control Register 4A bits. | |
1469 | */ | |
1470 | DS1685_RTC_SYSFS_CTRL_REG_RO(vrt2); | |
1471 | DS1685_RTC_SYSFS_CTRL_REG_RO(incr); | |
1472 | DS1685_RTC_SYSFS_CTRL_REG_RW(pab); | |
1473 | DS1685_RTC_SYSFS_CTRL_REG_RW(rf); | |
1474 | DS1685_RTC_SYSFS_CTRL_REG_RW(wf); | |
1475 | DS1685_RTC_SYSFS_CTRL_REG_RW(kf); | |
1476 | #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) | |
1477 | DS1685_RTC_SYSFS_CTRL_REG_RO(bme); | |
1478 | #endif | |
1479 | ||
1480 | static struct attribute* | |
1481 | ds1685_rtc_sysfs_ctrl4a_attrs[] = { | |
1482 | &dev_attr_vrt2.attr, | |
1483 | &dev_attr_incr.attr, | |
1484 | &dev_attr_pab.attr, | |
1485 | &dev_attr_rf.attr, | |
1486 | &dev_attr_wf.attr, | |
1487 | &dev_attr_kf.attr, | |
1488 | #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) | |
1489 | &dev_attr_bme.attr, | |
1490 | #endif | |
1491 | NULL, | |
1492 | }; | |
1493 | ||
1494 | static const struct attribute_group | |
1495 | ds1685_rtc_sysfs_ctrl4a_grp = { | |
1496 | .name = "ctrl4a", | |
1497 | .attrs = ds1685_rtc_sysfs_ctrl4a_attrs, | |
1498 | }; | |
1499 | ||
1500 | /* | |
1501 | * Control Register 4B bits. | |
1502 | */ | |
1503 | DS1685_RTC_SYSFS_CTRL_REG_RW(abe); | |
1504 | DS1685_RTC_SYSFS_CTRL_REG_RW(e32k); | |
1505 | DS1685_RTC_SYSFS_CTRL_REG_RO(cs); | |
1506 | DS1685_RTC_SYSFS_CTRL_REG_RW(rce); | |
1507 | DS1685_RTC_SYSFS_CTRL_REG_RW(prs); | |
1508 | DS1685_RTC_SYSFS_CTRL_REG_RW(rie); | |
1509 | DS1685_RTC_SYSFS_CTRL_REG_RW(wie); | |
1510 | DS1685_RTC_SYSFS_CTRL_REG_RW(kse); | |
1511 | ||
1512 | static struct attribute* | |
1513 | ds1685_rtc_sysfs_ctrl4b_attrs[] = { | |
1514 | &dev_attr_abe.attr, | |
1515 | &dev_attr_e32k.attr, | |
1516 | &dev_attr_cs.attr, | |
1517 | &dev_attr_rce.attr, | |
1518 | &dev_attr_prs.attr, | |
1519 | &dev_attr_rie.attr, | |
1520 | &dev_attr_wie.attr, | |
1521 | &dev_attr_kse.attr, | |
1522 | NULL, | |
1523 | }; | |
1524 | ||
1525 | static const struct attribute_group | |
1526 | ds1685_rtc_sysfs_ctrl4b_grp = { | |
1527 | .name = "ctrl4b", | |
1528 | .attrs = ds1685_rtc_sysfs_ctrl4b_attrs, | |
1529 | }; | |
1530 | ||
1531 | ||
1532 | /** | |
1533 | * struct ds1685_rtc_ctrl_regs. | |
1534 | * @name: char pointer for the bit name. | |
1535 | * @reg: control register the bit is in. | |
1536 | * @bit: the bit's offset in the register. | |
1537 | */ | |
1538 | struct ds1685_rtc_time_regs { | |
1539 | const char *name; | |
1540 | const u8 reg; | |
1541 | const u8 mask; | |
1542 | const u8 min; | |
1543 | const u8 max; | |
1544 | }; | |
1545 | ||
1546 | /* | |
1547 | * Time/Date register lookup tables. | |
1548 | */ | |
1549 | static const struct ds1685_rtc_time_regs | |
1550 | ds1685_time_regs_bcd_table[] = { | |
1551 | { "seconds", RTC_SECS, RTC_SECS_BCD_MASK, 0, 59 }, | |
1552 | { "minutes", RTC_MINS, RTC_MINS_BCD_MASK, 0, 59 }, | |
1553 | { "hours", RTC_HRS, RTC_HRS_24_BCD_MASK, 0, 23 }, | |
1554 | { "wday", RTC_WDAY, RTC_WDAY_MASK, 1, 7 }, | |
1555 | { "mday", RTC_MDAY, RTC_MDAY_BCD_MASK, 1, 31 }, | |
1556 | { "month", RTC_MONTH, RTC_MONTH_BCD_MASK, 1, 12 }, | |
1557 | { "year", RTC_YEAR, RTC_YEAR_BCD_MASK, 0, 99 }, | |
1558 | { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0, 99 }, | |
1559 | { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BCD_MASK, 0, 59 }, | |
1560 | { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BCD_MASK, 0, 59 }, | |
1561 | { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BCD_MASK, 0, 23 }, | |
1562 | { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 1, 31 }, | |
1563 | { NULL, 0, 0, 0, 0 }, | |
1564 | }; | |
1565 | ||
1566 | static const struct ds1685_rtc_time_regs | |
1567 | ds1685_time_regs_bin_table[] = { | |
1568 | { "seconds", RTC_SECS, RTC_SECS_BIN_MASK, 0x00, 0x3b }, | |
1569 | { "minutes", RTC_MINS, RTC_MINS_BIN_MASK, 0x00, 0x3b }, | |
1570 | { "hours", RTC_HRS, RTC_HRS_24_BIN_MASK, 0x00, 0x17 }, | |
1571 | { "wday", RTC_WDAY, RTC_WDAY_MASK, 0x01, 0x07 }, | |
1572 | { "mday", RTC_MDAY, RTC_MDAY_BIN_MASK, 0x01, 0x1f }, | |
1573 | { "month", RTC_MONTH, RTC_MONTH_BIN_MASK, 0x01, 0x0c }, | |
1574 | { "year", RTC_YEAR, RTC_YEAR_BIN_MASK, 0x00, 0x63 }, | |
1575 | { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0x00, 0x63 }, | |
1576 | { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BIN_MASK, 0x00, 0x3b }, | |
1577 | { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BIN_MASK, 0x00, 0x3b }, | |
1578 | { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BIN_MASK, 0x00, 0x17 }, | |
1579 | { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 0x01, 0x1f }, | |
1580 | { NULL, 0, 0, 0x00, 0x00 }, | |
1581 | }; | |
1582 | ||
1583 | /** | |
1584 | * ds1685_rtc_sysfs_time_regs_bcd_lookup - time/date reg bit lookup function. | |
1585 | * @name: register bit to look up in ds1685_time_regs_bcd_table. | |
1586 | */ | |
1587 | static const struct ds1685_rtc_time_regs* | |
1588 | ds1685_rtc_sysfs_time_regs_lookup(const char *name, bool bcd_mode) | |
1589 | { | |
1590 | const struct ds1685_rtc_time_regs *p; | |
1591 | ||
1592 | if (bcd_mode) | |
1593 | p = ds1685_time_regs_bcd_table; | |
1594 | else | |
1595 | p = ds1685_time_regs_bin_table; | |
1596 | ||
1597 | for (; p->name != NULL; ++p) | |
1598 | if (strcmp(p->name, name) == 0) | |
1599 | return p; | |
1600 | ||
1601 | return NULL; | |
1602 | } | |
1603 | ||
1604 | /** | |
1605 | * ds1685_rtc_sysfs_time_regs_show - reads a time/date register via sysfs. | |
1606 | * @dev: pointer to device structure. | |
1607 | * @attr: pointer to device_attribute structure. | |
1608 | * @buf: pointer to char array to hold the output. | |
1609 | */ | |
1610 | static ssize_t | |
1611 | ds1685_rtc_sysfs_time_regs_show(struct device *dev, | |
1612 | struct device_attribute *attr, char *buf) | |
1613 | { | |
1614 | u8 tmp; | |
1615 | struct ds1685_priv *rtc = dev_get_drvdata(dev); | |
1616 | const struct ds1685_rtc_time_regs *bcd_reg_info = | |
1617 | ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true); | |
1618 | const struct ds1685_rtc_time_regs *bin_reg_info = | |
1619 | ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false); | |
1620 | ||
1621 | /* Make sure we actually matched something. */ | |
b00eeaed | 1622 | if (!bcd_reg_info || !bin_reg_info) |
aaaf5fbf JK |
1623 | return -EINVAL; |
1624 | ||
1625 | /* bcd_reg_info->reg == bin_reg_info->reg. */ | |
1626 | ds1685_rtc_begin_data_access(rtc); | |
1627 | tmp = rtc->read(rtc, bcd_reg_info->reg); | |
1628 | ds1685_rtc_end_data_access(rtc); | |
1629 | ||
1630 | tmp = ds1685_rtc_bcd2bin(rtc, tmp, bcd_reg_info->mask, | |
1631 | bin_reg_info->mask); | |
1632 | ||
9c25a106 | 1633 | return sprintf(buf, "%d\n", tmp); |
aaaf5fbf JK |
1634 | } |
1635 | ||
1636 | /** | |
1637 | * ds1685_rtc_sysfs_time_regs_store - writes a time/date register via sysfs. | |
1638 | * @dev: pointer to device structure. | |
1639 | * @attr: pointer to device_attribute structure. | |
1640 | * @buf: pointer to char array to hold the output. | |
1641 | * @count: number of bytes written. | |
1642 | */ | |
1643 | static ssize_t | |
1644 | ds1685_rtc_sysfs_time_regs_store(struct device *dev, | |
1645 | struct device_attribute *attr, | |
1646 | const char *buf, size_t count) | |
1647 | { | |
1648 | long int val = 0; | |
1649 | struct ds1685_priv *rtc = dev_get_drvdata(dev); | |
1650 | const struct ds1685_rtc_time_regs *bcd_reg_info = | |
1651 | ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true); | |
1652 | const struct ds1685_rtc_time_regs *bin_reg_info = | |
1653 | ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false); | |
1654 | ||
1655 | /* We only accept numbers. */ | |
1656 | if (kstrtol(buf, 10, &val) < 0) | |
1657 | return -EINVAL; | |
1658 | ||
1659 | /* Make sure we actually matched something. */ | |
b00eeaed | 1660 | if (!bcd_reg_info || !bin_reg_info) |
aaaf5fbf JK |
1661 | return -EINVAL; |
1662 | ||
1663 | /* Check for a valid range. */ | |
1664 | if (rtc->bcd_mode) { | |
1665 | if ((val < bcd_reg_info->min) || (val > bcd_reg_info->max)) | |
1666 | return -ERANGE; | |
1667 | } else { | |
1668 | if ((val < bin_reg_info->min) || (val > bin_reg_info->max)) | |
1669 | return -ERANGE; | |
1670 | } | |
1671 | ||
1672 | val = ds1685_rtc_bin2bcd(rtc, val, bin_reg_info->mask, | |
1673 | bcd_reg_info->mask); | |
1674 | ||
1675 | /* bcd_reg_info->reg == bin_reg_info->reg. */ | |
1676 | ds1685_rtc_begin_data_access(rtc); | |
1677 | rtc->write(rtc, bcd_reg_info->reg, val); | |
1678 | ds1685_rtc_end_data_access(rtc); | |
1679 | ||
1680 | return count; | |
1681 | } | |
1682 | ||
1683 | /** | |
1684 | * DS1685_RTC_SYSFS_REG_RW - device_attribute for a read-write time register. | |
1685 | * @reg: time/date register to read or write. | |
1686 | */ | |
1687 | #define DS1685_RTC_SYSFS_TIME_REG_RW(reg) \ | |
1688 | static DEVICE_ATTR(reg, S_IRUGO | S_IWUSR, \ | |
1689 | ds1685_rtc_sysfs_time_regs_show, \ | |
1690 | ds1685_rtc_sysfs_time_regs_store) | |
1691 | ||
1692 | /* | |
1693 | * Time/Date Register bits. | |
1694 | */ | |
1695 | DS1685_RTC_SYSFS_TIME_REG_RW(seconds); | |
1696 | DS1685_RTC_SYSFS_TIME_REG_RW(minutes); | |
1697 | DS1685_RTC_SYSFS_TIME_REG_RW(hours); | |
1698 | DS1685_RTC_SYSFS_TIME_REG_RW(wday); | |
1699 | DS1685_RTC_SYSFS_TIME_REG_RW(mday); | |
1700 | DS1685_RTC_SYSFS_TIME_REG_RW(month); | |
1701 | DS1685_RTC_SYSFS_TIME_REG_RW(year); | |
1702 | DS1685_RTC_SYSFS_TIME_REG_RW(century); | |
1703 | DS1685_RTC_SYSFS_TIME_REG_RW(alarm_seconds); | |
1704 | DS1685_RTC_SYSFS_TIME_REG_RW(alarm_minutes); | |
1705 | DS1685_RTC_SYSFS_TIME_REG_RW(alarm_hours); | |
1706 | DS1685_RTC_SYSFS_TIME_REG_RW(alarm_mday); | |
1707 | ||
1708 | static struct attribute* | |
1709 | ds1685_rtc_sysfs_time_attrs[] = { | |
1710 | &dev_attr_seconds.attr, | |
1711 | &dev_attr_minutes.attr, | |
1712 | &dev_attr_hours.attr, | |
1713 | &dev_attr_wday.attr, | |
1714 | &dev_attr_mday.attr, | |
1715 | &dev_attr_month.attr, | |
1716 | &dev_attr_year.attr, | |
1717 | &dev_attr_century.attr, | |
1718 | NULL, | |
1719 | }; | |
1720 | ||
1721 | static const struct attribute_group | |
1722 | ds1685_rtc_sysfs_time_grp = { | |
1723 | .name = "datetime", | |
1724 | .attrs = ds1685_rtc_sysfs_time_attrs, | |
1725 | }; | |
1726 | ||
1727 | static struct attribute* | |
1728 | ds1685_rtc_sysfs_alarm_attrs[] = { | |
1729 | &dev_attr_alarm_seconds.attr, | |
1730 | &dev_attr_alarm_minutes.attr, | |
1731 | &dev_attr_alarm_hours.attr, | |
1732 | &dev_attr_alarm_mday.attr, | |
1733 | NULL, | |
1734 | }; | |
1735 | ||
1736 | static const struct attribute_group | |
1737 | ds1685_rtc_sysfs_alarm_grp = { | |
1738 | .name = "alarm", | |
1739 | .attrs = ds1685_rtc_sysfs_alarm_attrs, | |
1740 | }; | |
1741 | #endif /* CONFIG_RTC_DS1685_SYSFS_REGS */ | |
1742 | ||
1743 | ||
1744 | /** | |
1745 | * ds1685_rtc_sysfs_register - register sysfs files. | |
1746 | * @dev: pointer to device structure. | |
1747 | */ | |
1748 | static int | |
1749 | ds1685_rtc_sysfs_register(struct device *dev) | |
1750 | { | |
1751 | int ret = 0; | |
1752 | ||
1753 | sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr); | |
1754 | ret = sysfs_create_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr); | |
1755 | if (ret) | |
1756 | return ret; | |
1757 | ||
1758 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); | |
1759 | if (ret) | |
1760 | return ret; | |
1761 | ||
1762 | #ifdef CONFIG_RTC_DS1685_SYSFS_REGS | |
1763 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); | |
1764 | if (ret) | |
1765 | return ret; | |
1766 | ||
1767 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); | |
1768 | if (ret) | |
1769 | return ret; | |
1770 | ||
1771 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); | |
1772 | if (ret) | |
1773 | return ret; | |
1774 | ||
1775 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); | |
1776 | if (ret) | |
1777 | return ret; | |
1778 | ||
1779 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); | |
1780 | if (ret) | |
1781 | return ret; | |
1782 | ||
1783 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); | |
1784 | if (ret) | |
1785 | return ret; | |
1786 | ||
1787 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp); | |
1788 | if (ret) | |
1789 | return ret; | |
1790 | ||
1791 | ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp); | |
1792 | if (ret) | |
1793 | return ret; | |
1794 | #endif | |
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | /** | |
1799 | * ds1685_rtc_sysfs_unregister - unregister sysfs files. | |
1800 | * @dev: pointer to device structure. | |
1801 | */ | |
1802 | static int | |
1803 | ds1685_rtc_sysfs_unregister(struct device *dev) | |
1804 | { | |
1805 | sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr); | |
1806 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); | |
1807 | ||
1808 | #ifdef CONFIG_RTC_DS1685_SYSFS_REGS | |
1809 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); | |
1810 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); | |
1811 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); | |
1812 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); | |
1813 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); | |
1814 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); | |
1815 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp); | |
1816 | sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp); | |
1817 | #endif | |
1818 | ||
1819 | return 0; | |
1820 | } | |
1821 | #endif /* CONFIG_SYSFS */ | |
1822 | ||
1823 | ||
1824 | ||
1825 | /* ----------------------------------------------------------------------- */ | |
1826 | /* Driver Probe/Removal */ | |
1827 | ||
1828 | /** | |
1829 | * ds1685_rtc_probe - initializes rtc driver. | |
1830 | * @pdev: pointer to platform_device structure. | |
1831 | */ | |
1832 | static int | |
1833 | ds1685_rtc_probe(struct platform_device *pdev) | |
1834 | { | |
1835 | struct rtc_device *rtc_dev; | |
1836 | struct resource *res; | |
1837 | struct ds1685_priv *rtc; | |
1838 | struct ds1685_rtc_platform_data *pdata; | |
1839 | u8 ctrla, ctrlb, hours; | |
1840 | unsigned char am_pm; | |
1841 | int ret = 0; | |
1842 | ||
1843 | /* Get the platform data. */ | |
1844 | pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data; | |
1845 | if (!pdata) | |
1846 | return -ENODEV; | |
1847 | ||
1848 | /* Allocate memory for the rtc device. */ | |
1849 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); | |
1850 | if (!rtc) | |
1851 | return -ENOMEM; | |
1852 | ||
1853 | /* | |
1854 | * Allocate/setup any IORESOURCE_MEM resources, if required. Not all | |
1855 | * platforms put the RTC in an easy-access place. Like the SGI Octane, | |
1856 | * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip | |
1857 | * that sits behind the IOC3 PCI metadevice. | |
1858 | */ | |
1859 | if (pdata->alloc_io_resources) { | |
1860 | /* Get the platform resources. */ | |
1861 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1862 | if (!res) | |
1863 | return -ENXIO; | |
1864 | rtc->size = resource_size(res); | |
1865 | ||
1866 | /* Request a memory region. */ | |
1867 | /* XXX: mmio-only for now. */ | |
1868 | if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size, | |
1869 | pdev->name)) | |
1870 | return -EBUSY; | |
1871 | ||
1872 | /* | |
1873 | * Set the base address for the rtc, and ioremap its | |
1874 | * registers. | |
1875 | */ | |
1876 | rtc->baseaddr = res->start; | |
1877 | rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size); | |
1878 | if (!rtc->regs) | |
1879 | return -ENOMEM; | |
1880 | } | |
1881 | rtc->alloc_io_resources = pdata->alloc_io_resources; | |
1882 | ||
1883 | /* Get the register step size. */ | |
1884 | if (pdata->regstep > 0) | |
1885 | rtc->regstep = pdata->regstep; | |
1886 | else | |
1887 | rtc->regstep = 1; | |
1888 | ||
1889 | /* Platform read function, else default if mmio setup */ | |
1890 | if (pdata->plat_read) | |
1891 | rtc->read = pdata->plat_read; | |
1892 | else | |
1893 | if (pdata->alloc_io_resources) | |
1894 | rtc->read = ds1685_read; | |
1895 | else | |
1896 | return -ENXIO; | |
1897 | ||
1898 | /* Platform write function, else default if mmio setup */ | |
1899 | if (pdata->plat_write) | |
1900 | rtc->write = pdata->plat_write; | |
1901 | else | |
1902 | if (pdata->alloc_io_resources) | |
1903 | rtc->write = ds1685_write; | |
1904 | else | |
1905 | return -ENXIO; | |
1906 | ||
1907 | /* Platform pre-shutdown function, if defined. */ | |
1908 | if (pdata->plat_prepare_poweroff) | |
1909 | rtc->prepare_poweroff = pdata->plat_prepare_poweroff; | |
1910 | ||
1911 | /* Platform wake_alarm function, if defined. */ | |
1912 | if (pdata->plat_wake_alarm) | |
1913 | rtc->wake_alarm = pdata->plat_wake_alarm; | |
1914 | ||
1915 | /* Platform post_ram_clear function, if defined. */ | |
1916 | if (pdata->plat_post_ram_clear) | |
1917 | rtc->post_ram_clear = pdata->plat_post_ram_clear; | |
1918 | ||
1919 | /* Init the spinlock, workqueue, & set the driver data. */ | |
1920 | spin_lock_init(&rtc->lock); | |
1921 | INIT_WORK(&rtc->work, ds1685_rtc_work_queue); | |
1922 | platform_set_drvdata(pdev, rtc); | |
1923 | ||
1924 | /* Turn the oscillator on if is not already on (DV1 = 1). */ | |
1925 | ctrla = rtc->read(rtc, RTC_CTRL_A); | |
1926 | if (!(ctrla & RTC_CTRL_A_DV1)) | |
1927 | ctrla |= RTC_CTRL_A_DV1; | |
1928 | ||
1929 | /* Enable the countdown chain (DV2 = 0) */ | |
1930 | ctrla &= ~(RTC_CTRL_A_DV2); | |
1931 | ||
1932 | /* Clear RS3-RS0 in Control A. */ | |
1933 | ctrla &= ~(RTC_CTRL_A_RS_MASK); | |
1934 | ||
1935 | /* | |
1936 | * All done with Control A. Switch to Bank 1 for the remainder of | |
1937 | * the RTC setup so we have access to the extended functions. | |
1938 | */ | |
1939 | ctrla |= RTC_CTRL_A_DV0; | |
1940 | rtc->write(rtc, RTC_CTRL_A, ctrla); | |
1941 | ||
1942 | /* Default to 32768kHz output. */ | |
1943 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
1944 | (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K)); | |
1945 | ||
1946 | /* Set the SET bit in Control B so we can do some housekeeping. */ | |
1947 | rtc->write(rtc, RTC_CTRL_B, | |
1948 | (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); | |
1949 | ||
1950 | /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ | |
1951 | while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) | |
1952 | cpu_relax(); | |
1953 | ||
1954 | /* | |
1955 | * If the platform supports BCD mode, then set DM=0 in Control B. | |
1956 | * Otherwise, set DM=1 for BIN mode. | |
1957 | */ | |
1958 | ctrlb = rtc->read(rtc, RTC_CTRL_B); | |
1959 | if (pdata->bcd_mode) | |
1960 | ctrlb &= ~(RTC_CTRL_B_DM); | |
1961 | else | |
1962 | ctrlb |= RTC_CTRL_B_DM; | |
1963 | rtc->bcd_mode = pdata->bcd_mode; | |
1964 | ||
1965 | /* | |
1966 | * Disable Daylight Savings Time (DSE = 0). | |
1967 | * The RTC has hardcoded timezone information that is rendered | |
1968 | * obselete. We'll let the OS deal with DST settings instead. | |
1969 | */ | |
1970 | if (ctrlb & RTC_CTRL_B_DSE) | |
1971 | ctrlb &= ~(RTC_CTRL_B_DSE); | |
1972 | ||
1973 | /* Force 24-hour mode (2412 = 1). */ | |
1974 | if (!(ctrlb & RTC_CTRL_B_2412)) { | |
1975 | /* Reinitialize the time hours. */ | |
1976 | hours = rtc->read(rtc, RTC_HRS); | |
1977 | am_pm = hours & RTC_HRS_AMPM_MASK; | |
1978 | hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, | |
1979 | RTC_HRS_12_BIN_MASK); | |
1980 | hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); | |
1981 | ||
1982 | /* Enable 24-hour mode. */ | |
1983 | ctrlb |= RTC_CTRL_B_2412; | |
1984 | ||
1985 | /* Write back to Control B, including DM & DSE bits. */ | |
1986 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
1987 | ||
1988 | /* Write the time hours back. */ | |
1989 | rtc->write(rtc, RTC_HRS, | |
1990 | ds1685_rtc_bin2bcd(rtc, hours, | |
1991 | RTC_HRS_24_BIN_MASK, | |
1992 | RTC_HRS_24_BCD_MASK)); | |
1993 | ||
1994 | /* Reinitialize the alarm hours. */ | |
1995 | hours = rtc->read(rtc, RTC_HRS_ALARM); | |
1996 | am_pm = hours & RTC_HRS_AMPM_MASK; | |
1997 | hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, | |
1998 | RTC_HRS_12_BIN_MASK); | |
1999 | hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); | |
2000 | ||
2001 | /* Write the alarm hours back. */ | |
2002 | rtc->write(rtc, RTC_HRS_ALARM, | |
2003 | ds1685_rtc_bin2bcd(rtc, hours, | |
2004 | RTC_HRS_24_BIN_MASK, | |
2005 | RTC_HRS_24_BCD_MASK)); | |
2006 | } else { | |
2007 | /* 24-hour mode is already set, so write Control B back. */ | |
2008 | rtc->write(rtc, RTC_CTRL_B, ctrlb); | |
2009 | } | |
2010 | ||
2011 | /* Unset the SET bit in Control B so the RTC can update. */ | |
2012 | rtc->write(rtc, RTC_CTRL_B, | |
2013 | (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); | |
2014 | ||
2015 | /* Check the main battery. */ | |
2016 | if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT)) | |
2017 | dev_warn(&pdev->dev, | |
2018 | "Main battery is exhausted! RTC may be invalid!\n"); | |
2019 | ||
2020 | /* Check the auxillary battery. It is optional. */ | |
2021 | if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2)) | |
2022 | dev_warn(&pdev->dev, | |
2023 | "Aux battery is exhausted or not available.\n"); | |
2024 | ||
2025 | /* Read Ctrl B and clear PIE/AIE/UIE. */ | |
2026 | rtc->write(rtc, RTC_CTRL_B, | |
2027 | (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK))); | |
2028 | ||
2029 | /* Reading Ctrl C auto-clears PF/AF/UF. */ | |
2030 | rtc->read(rtc, RTC_CTRL_C); | |
2031 | ||
2032 | /* Read Ctrl 4B and clear RIE/WIE/KSE. */ | |
2033 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
2034 | (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK))); | |
2035 | ||
2036 | /* Clear RF/WF/KF in Ctrl 4A. */ | |
2037 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
2038 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK))); | |
2039 | ||
2040 | /* | |
2041 | * Re-enable KSE to handle power button events. We do not enable | |
2042 | * WIE or RIE by default. | |
2043 | */ | |
2044 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
2045 | (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE)); | |
2046 | ||
2047 | /* | |
2048 | * Fetch the IRQ and setup the interrupt handler. | |
2049 | * | |
2050 | * Not all platforms have the IRQF pin tied to something. If not, the | |
2051 | * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but | |
2052 | * there won't be an automatic way of notifying the kernel about it, | |
2053 | * unless ctrlc is explicitly polled. | |
2054 | */ | |
2055 | if (!pdata->no_irq) { | |
2056 | ret = platform_get_irq(pdev, 0); | |
2057 | if (ret > 0) { | |
2058 | rtc->irq_num = ret; | |
2059 | ||
2060 | /* Request an IRQ. */ | |
2061 | ret = devm_request_irq(&pdev->dev, rtc->irq_num, | |
2062 | ds1685_rtc_irq_handler, | |
2063 | IRQF_SHARED, pdev->name, pdev); | |
2064 | ||
2065 | /* Check to see if something came back. */ | |
2066 | if (unlikely(ret)) { | |
2067 | dev_warn(&pdev->dev, | |
2068 | "RTC interrupt not available\n"); | |
2069 | rtc->irq_num = 0; | |
2070 | } | |
2071 | } else | |
2072 | return ret; | |
2073 | } | |
2074 | rtc->no_irq = pdata->no_irq; | |
2075 | ||
2076 | /* Setup complete. */ | |
2077 | ds1685_rtc_switch_to_bank0(rtc); | |
2078 | ||
2079 | /* Register the device as an RTC. */ | |
2080 | rtc_dev = rtc_device_register(pdev->name, &pdev->dev, | |
2081 | &ds1685_rtc_ops, THIS_MODULE); | |
2082 | ||
2083 | /* Success? */ | |
2084 | if (IS_ERR(rtc_dev)) | |
2085 | return PTR_ERR(rtc_dev); | |
2086 | ||
2087 | /* Maximum periodic rate is 8192Hz (0.122070ms). */ | |
2088 | rtc_dev->max_user_freq = RTC_MAX_USER_FREQ; | |
2089 | ||
2090 | /* See if the platform doesn't support UIE. */ | |
2091 | if (pdata->uie_unsupported) | |
2092 | rtc_dev->uie_unsupported = 1; | |
2093 | rtc->uie_unsupported = pdata->uie_unsupported; | |
2094 | ||
2095 | rtc->dev = rtc_dev; | |
2096 | ||
2097 | #ifdef CONFIG_SYSFS | |
2098 | ret = ds1685_rtc_sysfs_register(&pdev->dev); | |
2099 | if (ret) | |
2100 | rtc_device_unregister(rtc->dev); | |
2101 | #endif | |
2102 | ||
2103 | /* Done! */ | |
2104 | return ret; | |
2105 | } | |
2106 | ||
2107 | /** | |
2108 | * ds1685_rtc_remove - removes rtc driver. | |
2109 | * @pdev: pointer to platform_device structure. | |
2110 | */ | |
2111 | static int | |
2112 | ds1685_rtc_remove(struct platform_device *pdev) | |
2113 | { | |
2114 | struct ds1685_priv *rtc = platform_get_drvdata(pdev); | |
2115 | ||
2116 | #ifdef CONFIG_SYSFS | |
2117 | ds1685_rtc_sysfs_unregister(&pdev->dev); | |
2118 | #endif | |
2119 | ||
2120 | rtc_device_unregister(rtc->dev); | |
2121 | ||
2122 | /* Read Ctrl B and clear PIE/AIE/UIE. */ | |
2123 | rtc->write(rtc, RTC_CTRL_B, | |
2124 | (rtc->read(rtc, RTC_CTRL_B) & | |
2125 | ~(RTC_CTRL_B_PAU_MASK))); | |
2126 | ||
2127 | /* Reading Ctrl C auto-clears PF/AF/UF. */ | |
2128 | rtc->read(rtc, RTC_CTRL_C); | |
2129 | ||
2130 | /* Read Ctrl 4B and clear RIE/WIE/KSE. */ | |
2131 | rtc->write(rtc, RTC_EXT_CTRL_4B, | |
2132 | (rtc->read(rtc, RTC_EXT_CTRL_4B) & | |
2133 | ~(RTC_CTRL_4B_RWK_MASK))); | |
2134 | ||
2135 | /* Manually clear RF/WF/KF in Ctrl 4A. */ | |
2136 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
2137 | (rtc->read(rtc, RTC_EXT_CTRL_4A) & | |
2138 | ~(RTC_CTRL_4A_RWK_MASK))); | |
2139 | ||
2140 | cancel_work_sync(&rtc->work); | |
2141 | ||
2142 | return 0; | |
2143 | } | |
2144 | ||
2145 | /** | |
2146 | * ds1685_rtc_driver - rtc driver properties. | |
2147 | */ | |
2148 | static struct platform_driver ds1685_rtc_driver = { | |
2149 | .driver = { | |
2150 | .name = "rtc-ds1685", | |
aaaf5fbf JK |
2151 | }, |
2152 | .probe = ds1685_rtc_probe, | |
2153 | .remove = ds1685_rtc_remove, | |
2154 | }; | |
508db592 | 2155 | module_platform_driver(ds1685_rtc_driver); |
aaaf5fbf JK |
2156 | /* ----------------------------------------------------------------------- */ |
2157 | ||
2158 | ||
2159 | /* ----------------------------------------------------------------------- */ | |
2160 | /* Poweroff function */ | |
2161 | ||
2162 | /** | |
2163 | * ds1685_rtc_poweroff - uses the RTC chip to power the system off. | |
2164 | * @pdev: pointer to platform_device structure. | |
2165 | */ | |
52ef84d5 | 2166 | void __noreturn |
aaaf5fbf JK |
2167 | ds1685_rtc_poweroff(struct platform_device *pdev) |
2168 | { | |
2169 | u8 ctrla, ctrl4a, ctrl4b; | |
2170 | struct ds1685_priv *rtc; | |
2171 | ||
2172 | /* Check for valid RTC data, else, spin forever. */ | |
2173 | if (unlikely(!pdev)) { | |
a737e835 | 2174 | pr_emerg("platform device data not available, spinning forever ...\n"); |
361c6ed6 | 2175 | while(1); |
aaaf5fbf JK |
2176 | unreachable(); |
2177 | } else { | |
2178 | /* Get the rtc data. */ | |
2179 | rtc = platform_get_drvdata(pdev); | |
2180 | ||
2181 | /* | |
2182 | * Disable our IRQ. We're powering down, so we're not | |
2183 | * going to worry about cleaning up. Most of that should | |
2184 | * have been taken care of by the shutdown scripts and this | |
2185 | * is the final function call. | |
2186 | */ | |
2187 | if (!rtc->no_irq) | |
2188 | disable_irq_nosync(rtc->irq_num); | |
2189 | ||
2190 | /* Oscillator must be on and the countdown chain enabled. */ | |
2191 | ctrla = rtc->read(rtc, RTC_CTRL_A); | |
2192 | ctrla |= RTC_CTRL_A_DV1; | |
2193 | ctrla &= ~(RTC_CTRL_A_DV2); | |
2194 | rtc->write(rtc, RTC_CTRL_A, ctrla); | |
2195 | ||
2196 | /* | |
2197 | * Read Control 4A and check the status of the auxillary | |
2198 | * battery. This must be present and working (VRT2 = 1) | |
2199 | * for wakeup and kickstart functionality to be useful. | |
2200 | */ | |
2201 | ds1685_rtc_switch_to_bank1(rtc); | |
2202 | ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); | |
2203 | if (ctrl4a & RTC_CTRL_4A_VRT2) { | |
2204 | /* Clear all of the interrupt flags on Control 4A. */ | |
2205 | ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK); | |
2206 | rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a); | |
2207 | ||
2208 | /* | |
2209 | * The auxillary battery is present and working. | |
2210 | * Enable extended functions (ABE=1), enable | |
2211 | * wake-up (WIE=1), and enable kickstart (KSE=1) | |
2212 | * in Control 4B. | |
2213 | */ | |
2214 | ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); | |
2215 | ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE | | |
2216 | RTC_CTRL_4B_KSE); | |
2217 | rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b); | |
2218 | } | |
2219 | ||
2220 | /* Set PAB to 1 in Control 4A to power the system down. */ | |
2221 | dev_warn(&pdev->dev, "Powerdown.\n"); | |
2222 | msleep(20); | |
2223 | rtc->write(rtc, RTC_EXT_CTRL_4A, | |
2224 | (ctrl4a | RTC_CTRL_4A_PAB)); | |
2225 | ||
2226 | /* Spin ... we do not switch back to bank0. */ | |
19105f42 | 2227 | while(1); |
aaaf5fbf JK |
2228 | unreachable(); |
2229 | } | |
2230 | } | |
2231 | EXPORT_SYMBOL(ds1685_rtc_poweroff); | |
2232 | /* ----------------------------------------------------------------------- */ | |
2233 | ||
2234 | ||
2235 | MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>"); | |
2236 | MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>"); | |
2237 | MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver"); | |
2238 | MODULE_LICENSE("GPL"); | |
aaaf5fbf | 2239 | MODULE_ALIAS("platform:rtc-ds1685"); |