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1d6316f5 RG |
1 | /* rtc-ds1343.c |
2 | * | |
3 | * Driver for Dallas Semiconductor DS1343 Low Current, SPI Compatible | |
4 | * Real Time Clock | |
5 | * | |
6 | * Author : Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com> | |
571eb883 | 7 | * Ankur Srivastava <sankurece@gmail.com> : DS1343 Nvram Support |
1d6316f5 RG |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/spi/spi.h> | |
20 | #include <linux/regmap.h> | |
21 | #include <linux/rtc.h> | |
22 | #include <linux/bcd.h> | |
23 | #include <linux/pm.h> | |
caff0cc4 | 24 | #include <linux/pm_wakeirq.h> |
1d6316f5 RG |
25 | #include <linux/slab.h> |
26 | ||
1d6316f5 RG |
27 | #define DALLAS_MAXIM_DS1343 0 |
28 | #define DALLAS_MAXIM_DS1344 1 | |
29 | ||
30 | /* RTC DS1343 Registers */ | |
31 | #define DS1343_SECONDS_REG 0x00 | |
32 | #define DS1343_MINUTES_REG 0x01 | |
33 | #define DS1343_HOURS_REG 0x02 | |
34 | #define DS1343_DAY_REG 0x03 | |
35 | #define DS1343_DATE_REG 0x04 | |
36 | #define DS1343_MONTH_REG 0x05 | |
37 | #define DS1343_YEAR_REG 0x06 | |
38 | #define DS1343_ALM0_SEC_REG 0x07 | |
39 | #define DS1343_ALM0_MIN_REG 0x08 | |
40 | #define DS1343_ALM0_HOUR_REG 0x09 | |
41 | #define DS1343_ALM0_DAY_REG 0x0A | |
42 | #define DS1343_ALM1_SEC_REG 0x0B | |
43 | #define DS1343_ALM1_MIN_REG 0x0C | |
44 | #define DS1343_ALM1_HOUR_REG 0x0D | |
45 | #define DS1343_ALM1_DAY_REG 0x0E | |
46 | #define DS1343_CONTROL_REG 0x0F | |
47 | #define DS1343_STATUS_REG 0x10 | |
48 | #define DS1343_TRICKLE_REG 0x11 | |
571eb883 RG |
49 | #define DS1343_NVRAM 0x20 |
50 | ||
51 | #define DS1343_NVRAM_LEN 96 | |
1d6316f5 RG |
52 | |
53 | /* DS1343 Control Registers bits */ | |
54 | #define DS1343_EOSC 0x80 | |
55 | #define DS1343_DOSF 0x20 | |
56 | #define DS1343_EGFIL 0x10 | |
57 | #define DS1343_SQW 0x08 | |
58 | #define DS1343_INTCN 0x04 | |
59 | #define DS1343_A1IE 0x02 | |
60 | #define DS1343_A0IE 0x01 | |
61 | ||
62 | /* DS1343 Status Registers bits */ | |
63 | #define DS1343_OSF 0x80 | |
64 | #define DS1343_IRQF1 0x02 | |
65 | #define DS1343_IRQF0 0x01 | |
66 | ||
67 | /* DS1343 Trickle Charger Registers bits */ | |
68 | #define DS1343_TRICKLE_MAGIC 0xa0 | |
69 | #define DS1343_TRICKLE_DS1 0x08 | |
70 | #define DS1343_TRICKLE_1K 0x01 | |
71 | #define DS1343_TRICKLE_2K 0x02 | |
72 | #define DS1343_TRICKLE_4K 0x03 | |
73 | ||
74 | static const struct spi_device_id ds1343_id[] = { | |
75 | { "ds1343", DALLAS_MAXIM_DS1343 }, | |
76 | { "ds1344", DALLAS_MAXIM_DS1344 }, | |
77 | { } | |
78 | }; | |
79 | MODULE_DEVICE_TABLE(spi, ds1343_id); | |
80 | ||
81 | struct ds1343_priv { | |
82 | struct spi_device *spi; | |
83 | struct rtc_device *rtc; | |
84 | struct regmap *map; | |
85 | struct mutex mutex; | |
86 | unsigned int irqen; | |
10b06b87 | 87 | int irq; |
1d6316f5 RG |
88 | int alarm_sec; |
89 | int alarm_min; | |
90 | int alarm_hour; | |
91 | int alarm_mday; | |
92 | }; | |
93 | ||
94 | static int ds1343_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
95 | { | |
96 | switch (cmd) { | |
97 | #ifdef RTC_SET_CHARGE | |
98 | case RTC_SET_CHARGE: | |
99 | { | |
100 | int val; | |
101 | ||
102 | if (copy_from_user(&val, (int __user *)arg, sizeof(int))) | |
103 | return -EFAULT; | |
104 | ||
105 | return regmap_write(priv->map, DS1343_TRICKLE_REG, val); | |
106 | } | |
107 | break; | |
108 | #endif | |
109 | } | |
110 | ||
111 | return -ENOIOCTLCMD; | |
112 | } | |
113 | ||
114 | static ssize_t ds1343_show_glitchfilter(struct device *dev, | |
115 | struct device_attribute *attr, char *buf) | |
116 | { | |
117 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
118 | int glitch_filt_status, data; | |
119 | ||
120 | regmap_read(priv->map, DS1343_CONTROL_REG, &data); | |
121 | ||
122 | glitch_filt_status = !!(data & DS1343_EGFIL); | |
123 | ||
124 | if (glitch_filt_status) | |
125 | return sprintf(buf, "enabled\n"); | |
126 | else | |
127 | return sprintf(buf, "disabled\n"); | |
128 | } | |
129 | ||
130 | static ssize_t ds1343_store_glitchfilter(struct device *dev, | |
131 | struct device_attribute *attr, | |
132 | const char *buf, size_t count) | |
133 | { | |
134 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
135 | int data; | |
136 | ||
137 | regmap_read(priv->map, DS1343_CONTROL_REG, &data); | |
138 | ||
139 | if (strncmp(buf, "enabled", 7) == 0) | |
140 | data |= DS1343_EGFIL; | |
141 | ||
142 | else if (strncmp(buf, "disabled", 8) == 0) | |
143 | data &= ~(DS1343_EGFIL); | |
144 | ||
145 | else | |
146 | return -EINVAL; | |
147 | ||
148 | regmap_write(priv->map, DS1343_CONTROL_REG, data); | |
149 | ||
150 | return count; | |
151 | } | |
152 | ||
153 | static DEVICE_ATTR(glitch_filter, S_IRUGO | S_IWUSR, ds1343_show_glitchfilter, | |
154 | ds1343_store_glitchfilter); | |
155 | ||
571eb883 RG |
156 | static ssize_t ds1343_nvram_write(struct file *filp, struct kobject *kobj, |
157 | struct bin_attribute *attr, | |
158 | char *buf, loff_t off, size_t count) | |
159 | { | |
160 | int ret; | |
161 | unsigned char address; | |
162 | struct device *dev = kobj_to_dev(kobj); | |
163 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
164 | ||
571eb883 RG |
165 | address = DS1343_NVRAM + off; |
166 | ||
167 | ret = regmap_bulk_write(priv->map, address, buf, count); | |
168 | if (ret < 0) | |
169 | dev_err(&priv->spi->dev, "Error in nvram write %d", ret); | |
170 | ||
171 | return (ret < 0) ? ret : count; | |
172 | } | |
173 | ||
174 | ||
175 | static ssize_t ds1343_nvram_read(struct file *filp, struct kobject *kobj, | |
176 | struct bin_attribute *attr, | |
177 | char *buf, loff_t off, size_t count) | |
178 | { | |
179 | int ret; | |
180 | unsigned char address; | |
181 | struct device *dev = kobj_to_dev(kobj); | |
182 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
183 | ||
571eb883 RG |
184 | address = DS1343_NVRAM + off; |
185 | ||
186 | ret = regmap_bulk_read(priv->map, address, buf, count); | |
187 | if (ret < 0) | |
188 | dev_err(&priv->spi->dev, "Error in nvram read %d\n", ret); | |
189 | ||
190 | return (ret < 0) ? ret : count; | |
191 | } | |
192 | ||
193 | ||
194 | static struct bin_attribute nvram_attr = { | |
195 | .attr.name = "nvram", | |
196 | .attr.mode = S_IRUGO | S_IWUSR, | |
197 | .read = ds1343_nvram_read, | |
198 | .write = ds1343_nvram_write, | |
199 | .size = DS1343_NVRAM_LEN, | |
200 | }; | |
201 | ||
1d6316f5 RG |
202 | static ssize_t ds1343_show_alarmstatus(struct device *dev, |
203 | struct device_attribute *attr, char *buf) | |
204 | { | |
205 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
206 | int alarmstatus, data; | |
207 | ||
208 | regmap_read(priv->map, DS1343_CONTROL_REG, &data); | |
209 | ||
210 | alarmstatus = !!(data & DS1343_A0IE); | |
211 | ||
212 | if (alarmstatus) | |
213 | return sprintf(buf, "enabled\n"); | |
214 | else | |
215 | return sprintf(buf, "disabled\n"); | |
216 | } | |
217 | ||
218 | static DEVICE_ATTR(alarm_status, S_IRUGO, ds1343_show_alarmstatus, NULL); | |
219 | ||
220 | static ssize_t ds1343_show_alarmmode(struct device *dev, | |
221 | struct device_attribute *attr, char *buf) | |
222 | { | |
223 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
224 | int alarm_mode, data; | |
225 | char *alarm_str; | |
226 | ||
227 | regmap_read(priv->map, DS1343_ALM0_SEC_REG, &data); | |
228 | alarm_mode = (data & 0x80) >> 4; | |
229 | ||
230 | regmap_read(priv->map, DS1343_ALM0_MIN_REG, &data); | |
231 | alarm_mode |= (data & 0x80) >> 5; | |
232 | ||
233 | regmap_read(priv->map, DS1343_ALM0_HOUR_REG, &data); | |
234 | alarm_mode |= (data & 0x80) >> 6; | |
235 | ||
236 | regmap_read(priv->map, DS1343_ALM0_DAY_REG, &data); | |
237 | alarm_mode |= (data & 0x80) >> 7; | |
238 | ||
239 | switch (alarm_mode) { | |
240 | case 15: | |
241 | alarm_str = "each second"; | |
242 | break; | |
243 | ||
244 | case 7: | |
245 | alarm_str = "seconds match"; | |
246 | break; | |
247 | ||
248 | case 3: | |
249 | alarm_str = "minutes and seconds match"; | |
250 | break; | |
251 | ||
252 | case 1: | |
253 | alarm_str = "hours, minutes and seconds match"; | |
254 | break; | |
255 | ||
256 | case 0: | |
257 | alarm_str = "day, hours, minutes and seconds match"; | |
258 | break; | |
259 | ||
260 | default: | |
261 | alarm_str = "invalid"; | |
262 | break; | |
263 | } | |
264 | ||
265 | return sprintf(buf, "%s\n", alarm_str); | |
266 | } | |
267 | ||
268 | static DEVICE_ATTR(alarm_mode, S_IRUGO, ds1343_show_alarmmode, NULL); | |
269 | ||
270 | static ssize_t ds1343_show_tricklecharger(struct device *dev, | |
271 | struct device_attribute *attr, char *buf) | |
272 | { | |
273 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
274 | int data; | |
275 | char *diodes = "disabled", *resistors = " "; | |
276 | ||
277 | regmap_read(priv->map, DS1343_TRICKLE_REG, &data); | |
278 | ||
279 | if ((data & 0xf0) == DS1343_TRICKLE_MAGIC) { | |
280 | switch (data & 0x0c) { | |
281 | case DS1343_TRICKLE_DS1: | |
282 | diodes = "one diode,"; | |
283 | break; | |
284 | ||
285 | default: | |
286 | diodes = "no diode,"; | |
287 | break; | |
288 | } | |
289 | ||
290 | switch (data & 0x03) { | |
291 | case DS1343_TRICKLE_1K: | |
292 | resistors = "1k Ohm"; | |
293 | break; | |
294 | ||
295 | case DS1343_TRICKLE_2K: | |
296 | resistors = "2k Ohm"; | |
297 | break; | |
298 | ||
299 | case DS1343_TRICKLE_4K: | |
300 | resistors = "4k Ohm"; | |
301 | break; | |
302 | ||
303 | default: | |
304 | diodes = "disabled"; | |
305 | break; | |
306 | } | |
307 | } | |
308 | ||
309 | return sprintf(buf, "%s %s\n", diodes, resistors); | |
310 | } | |
311 | ||
312 | static DEVICE_ATTR(trickle_charger, S_IRUGO, ds1343_show_tricklecharger, NULL); | |
313 | ||
314 | static int ds1343_sysfs_register(struct device *dev) | |
315 | { | |
10b06b87 | 316 | struct ds1343_priv *priv = dev_get_drvdata(dev); |
1d6316f5 RG |
317 | int err; |
318 | ||
319 | err = device_create_file(dev, &dev_attr_glitch_filter); | |
320 | if (err) | |
321 | return err; | |
322 | ||
10b06b87 | 323 | err = device_create_file(dev, &dev_attr_trickle_charger); |
1d6316f5 RG |
324 | if (err) |
325 | goto error1; | |
326 | ||
571eb883 RG |
327 | err = device_create_bin_file(dev, &nvram_attr); |
328 | if (err) | |
329 | goto error2; | |
330 | ||
10b06b87 RG |
331 | if (priv->irq <= 0) |
332 | return err; | |
333 | ||
1d6316f5 RG |
334 | err = device_create_file(dev, &dev_attr_alarm_mode); |
335 | if (err) | |
571eb883 | 336 | goto error3; |
1d6316f5 | 337 | |
10b06b87 | 338 | err = device_create_file(dev, &dev_attr_alarm_status); |
1d6316f5 RG |
339 | if (!err) |
340 | return err; | |
341 | ||
342 | device_remove_file(dev, &dev_attr_alarm_mode); | |
343 | ||
571eb883 RG |
344 | error3: |
345 | device_remove_bin_file(dev, &nvram_attr); | |
346 | ||
1d6316f5 | 347 | error2: |
10b06b87 | 348 | device_remove_file(dev, &dev_attr_trickle_charger); |
1d6316f5 RG |
349 | |
350 | error1: | |
351 | device_remove_file(dev, &dev_attr_glitch_filter); | |
352 | ||
353 | return err; | |
354 | } | |
355 | ||
356 | static void ds1343_sysfs_unregister(struct device *dev) | |
357 | { | |
10b06b87 RG |
358 | struct ds1343_priv *priv = dev_get_drvdata(dev); |
359 | ||
1d6316f5 | 360 | device_remove_file(dev, &dev_attr_glitch_filter); |
10b06b87 | 361 | device_remove_file(dev, &dev_attr_trickle_charger); |
571eb883 | 362 | device_remove_bin_file(dev, &nvram_attr); |
10b06b87 RG |
363 | |
364 | if (priv->irq <= 0) | |
365 | return; | |
366 | ||
1d6316f5 RG |
367 | device_remove_file(dev, &dev_attr_alarm_status); |
368 | device_remove_file(dev, &dev_attr_alarm_mode); | |
1d6316f5 RG |
369 | } |
370 | ||
371 | static int ds1343_read_time(struct device *dev, struct rtc_time *dt) | |
372 | { | |
373 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
374 | unsigned char buf[7]; | |
375 | int res; | |
376 | ||
377 | res = regmap_bulk_read(priv->map, DS1343_SECONDS_REG, buf, 7); | |
378 | if (res) | |
379 | return res; | |
380 | ||
381 | dt->tm_sec = bcd2bin(buf[0]); | |
382 | dt->tm_min = bcd2bin(buf[1]); | |
383 | dt->tm_hour = bcd2bin(buf[2] & 0x3F); | |
384 | dt->tm_wday = bcd2bin(buf[3]) - 1; | |
385 | dt->tm_mday = bcd2bin(buf[4]); | |
386 | dt->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; | |
387 | dt->tm_year = bcd2bin(buf[6]) + 100; /* year offset from 1900 */ | |
388 | ||
389 | return rtc_valid_tm(dt); | |
390 | } | |
391 | ||
392 | static int ds1343_set_time(struct device *dev, struct rtc_time *dt) | |
393 | { | |
394 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
395 | int res; | |
396 | ||
397 | res = regmap_write(priv->map, DS1343_SECONDS_REG, | |
398 | bin2bcd(dt->tm_sec)); | |
399 | if (res) | |
400 | return res; | |
401 | ||
402 | res = regmap_write(priv->map, DS1343_MINUTES_REG, | |
403 | bin2bcd(dt->tm_min)); | |
404 | if (res) | |
405 | return res; | |
406 | ||
407 | res = regmap_write(priv->map, DS1343_HOURS_REG, | |
408 | bin2bcd(dt->tm_hour) & 0x3F); | |
409 | if (res) | |
410 | return res; | |
411 | ||
412 | res = regmap_write(priv->map, DS1343_DAY_REG, | |
413 | bin2bcd(dt->tm_wday + 1)); | |
414 | if (res) | |
415 | return res; | |
416 | ||
417 | res = regmap_write(priv->map, DS1343_DATE_REG, | |
418 | bin2bcd(dt->tm_mday)); | |
419 | if (res) | |
420 | return res; | |
421 | ||
422 | res = regmap_write(priv->map, DS1343_MONTH_REG, | |
423 | bin2bcd(dt->tm_mon + 1)); | |
424 | if (res) | |
425 | return res; | |
426 | ||
427 | dt->tm_year %= 100; | |
428 | ||
429 | res = regmap_write(priv->map, DS1343_YEAR_REG, | |
430 | bin2bcd(dt->tm_year)); | |
431 | if (res) | |
432 | return res; | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static int ds1343_update_alarm(struct device *dev) | |
438 | { | |
439 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
440 | unsigned int control, stat; | |
441 | unsigned char buf[4]; | |
442 | int res = 0; | |
443 | ||
444 | res = regmap_read(priv->map, DS1343_CONTROL_REG, &control); | |
445 | if (res) | |
446 | return res; | |
447 | ||
448 | res = regmap_read(priv->map, DS1343_STATUS_REG, &stat); | |
449 | if (res) | |
450 | return res; | |
451 | ||
452 | control &= ~(DS1343_A0IE); | |
453 | stat &= ~(DS1343_IRQF0); | |
454 | ||
455 | res = regmap_write(priv->map, DS1343_CONTROL_REG, control); | |
456 | if (res) | |
457 | return res; | |
458 | ||
459 | res = regmap_write(priv->map, DS1343_STATUS_REG, stat); | |
460 | if (res) | |
461 | return res; | |
462 | ||
463 | buf[0] = priv->alarm_sec < 0 || (priv->irqen & RTC_UF) ? | |
464 | 0x80 : bin2bcd(priv->alarm_sec) & 0x7F; | |
465 | buf[1] = priv->alarm_min < 0 || (priv->irqen & RTC_UF) ? | |
466 | 0x80 : bin2bcd(priv->alarm_min) & 0x7F; | |
467 | buf[2] = priv->alarm_hour < 0 || (priv->irqen & RTC_UF) ? | |
468 | 0x80 : bin2bcd(priv->alarm_hour) & 0x3F; | |
469 | buf[3] = priv->alarm_mday < 0 || (priv->irqen & RTC_UF) ? | |
470 | 0x80 : bin2bcd(priv->alarm_mday) & 0x7F; | |
471 | ||
472 | res = regmap_bulk_write(priv->map, DS1343_ALM0_SEC_REG, buf, 4); | |
473 | if (res) | |
474 | return res; | |
475 | ||
476 | if (priv->irqen) { | |
477 | control |= DS1343_A0IE; | |
478 | res = regmap_write(priv->map, DS1343_CONTROL_REG, control); | |
479 | } | |
480 | ||
481 | return res; | |
482 | } | |
483 | ||
484 | static int ds1343_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
485 | { | |
486 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
1d6316f5 RG |
487 | int res = 0; |
488 | unsigned int stat; | |
489 | ||
10b06b87 | 490 | if (priv->irq <= 0) |
1d6316f5 RG |
491 | return -EINVAL; |
492 | ||
493 | mutex_lock(&priv->mutex); | |
494 | ||
495 | res = regmap_read(priv->map, DS1343_STATUS_REG, &stat); | |
496 | if (res) | |
497 | goto out; | |
498 | ||
499 | alarm->enabled = !!(priv->irqen & RTC_AF); | |
500 | alarm->pending = !!(stat & DS1343_IRQF0); | |
501 | ||
502 | alarm->time.tm_sec = priv->alarm_sec < 0 ? 0 : priv->alarm_sec; | |
503 | alarm->time.tm_min = priv->alarm_min < 0 ? 0 : priv->alarm_min; | |
504 | alarm->time.tm_hour = priv->alarm_hour < 0 ? 0 : priv->alarm_hour; | |
505 | alarm->time.tm_mday = priv->alarm_mday < 0 ? 0 : priv->alarm_mday; | |
506 | ||
1d6316f5 RG |
507 | out: |
508 | mutex_unlock(&priv->mutex); | |
509 | return res; | |
510 | } | |
511 | ||
512 | static int ds1343_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
513 | { | |
514 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
1d6316f5 RG |
515 | int res = 0; |
516 | ||
10b06b87 | 517 | if (priv->irq <= 0) |
1d6316f5 RG |
518 | return -EINVAL; |
519 | ||
520 | mutex_lock(&priv->mutex); | |
521 | ||
522 | priv->alarm_sec = alarm->time.tm_sec; | |
523 | priv->alarm_min = alarm->time.tm_min; | |
524 | priv->alarm_hour = alarm->time.tm_hour; | |
525 | priv->alarm_mday = alarm->time.tm_mday; | |
526 | ||
527 | if (alarm->enabled) | |
528 | priv->irqen |= RTC_AF; | |
529 | ||
530 | res = ds1343_update_alarm(dev); | |
531 | ||
532 | mutex_unlock(&priv->mutex); | |
533 | ||
534 | return res; | |
535 | } | |
536 | ||
537 | static int ds1343_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
538 | { | |
539 | struct ds1343_priv *priv = dev_get_drvdata(dev); | |
1d6316f5 RG |
540 | int res = 0; |
541 | ||
10b06b87 | 542 | if (priv->irq <= 0) |
1d6316f5 RG |
543 | return -EINVAL; |
544 | ||
545 | mutex_lock(&priv->mutex); | |
546 | ||
547 | if (enabled) | |
548 | priv->irqen |= RTC_AF; | |
549 | else | |
550 | priv->irqen &= ~RTC_AF; | |
551 | ||
552 | res = ds1343_update_alarm(dev); | |
553 | ||
554 | mutex_unlock(&priv->mutex); | |
555 | ||
556 | return res; | |
557 | } | |
558 | ||
559 | static irqreturn_t ds1343_thread(int irq, void *dev_id) | |
560 | { | |
561 | struct ds1343_priv *priv = dev_id; | |
562 | unsigned int stat, control; | |
563 | int res = 0; | |
564 | ||
565 | mutex_lock(&priv->mutex); | |
566 | ||
567 | res = regmap_read(priv->map, DS1343_STATUS_REG, &stat); | |
568 | if (res) | |
569 | goto out; | |
570 | ||
571 | if (stat & DS1343_IRQF0) { | |
572 | stat &= ~DS1343_IRQF0; | |
573 | regmap_write(priv->map, DS1343_STATUS_REG, stat); | |
574 | ||
575 | res = regmap_read(priv->map, DS1343_CONTROL_REG, &control); | |
576 | if (res) | |
577 | goto out; | |
578 | ||
579 | control &= ~DS1343_A0IE; | |
580 | regmap_write(priv->map, DS1343_CONTROL_REG, control); | |
581 | ||
582 | rtc_update_irq(priv->rtc, 1, RTC_AF | RTC_IRQF); | |
583 | } | |
584 | ||
585 | out: | |
586 | mutex_unlock(&priv->mutex); | |
587 | return IRQ_HANDLED; | |
588 | } | |
589 | ||
590 | static const struct rtc_class_ops ds1343_rtc_ops = { | |
591 | .ioctl = ds1343_ioctl, | |
592 | .read_time = ds1343_read_time, | |
593 | .set_time = ds1343_set_time, | |
594 | .read_alarm = ds1343_read_alarm, | |
595 | .set_alarm = ds1343_set_alarm, | |
596 | .alarm_irq_enable = ds1343_alarm_irq_enable, | |
597 | }; | |
598 | ||
599 | static int ds1343_probe(struct spi_device *spi) | |
600 | { | |
601 | struct ds1343_priv *priv; | |
602 | struct regmap_config config; | |
603 | unsigned int data; | |
604 | int res; | |
605 | ||
606 | memset(&config, 0, sizeof(config)); | |
607 | config.reg_bits = 8; | |
608 | config.val_bits = 8; | |
609 | config.write_flag_mask = 0x80; | |
610 | ||
611 | priv = devm_kzalloc(&spi->dev, sizeof(struct ds1343_priv), GFP_KERNEL); | |
612 | if (!priv) | |
613 | return -ENOMEM; | |
614 | ||
615 | priv->spi = spi; | |
616 | mutex_init(&priv->mutex); | |
617 | ||
618 | /* RTC DS1347 works in spi mode 3 and | |
619 | * its chip select is active high | |
620 | */ | |
621 | spi->mode = SPI_MODE_3 | SPI_CS_HIGH; | |
622 | spi->bits_per_word = 8; | |
623 | res = spi_setup(spi); | |
624 | if (res) | |
625 | return res; | |
626 | ||
627 | spi_set_drvdata(spi, priv); | |
628 | ||
629 | priv->map = devm_regmap_init_spi(spi, &config); | |
630 | ||
631 | if (IS_ERR(priv->map)) { | |
632 | dev_err(&spi->dev, "spi regmap init failed for rtc ds1343\n"); | |
633 | return PTR_ERR(priv->map); | |
634 | } | |
635 | ||
636 | res = regmap_read(priv->map, DS1343_SECONDS_REG, &data); | |
637 | if (res) | |
638 | return res; | |
639 | ||
640 | regmap_read(priv->map, DS1343_CONTROL_REG, &data); | |
641 | data |= DS1343_INTCN; | |
642 | data &= ~(DS1343_EOSC | DS1343_A1IE | DS1343_A0IE); | |
643 | regmap_write(priv->map, DS1343_CONTROL_REG, data); | |
644 | ||
645 | regmap_read(priv->map, DS1343_STATUS_REG, &data); | |
646 | data &= ~(DS1343_OSF | DS1343_IRQF1 | DS1343_IRQF0); | |
647 | regmap_write(priv->map, DS1343_STATUS_REG, data); | |
648 | ||
649 | priv->rtc = devm_rtc_device_register(&spi->dev, "ds1343", | |
650 | &ds1343_rtc_ops, THIS_MODULE); | |
651 | if (IS_ERR(priv->rtc)) { | |
652 | dev_err(&spi->dev, "unable to register rtc ds1343\n"); | |
653 | return PTR_ERR(priv->rtc); | |
654 | } | |
655 | ||
10b06b87 RG |
656 | priv->irq = spi->irq; |
657 | ||
658 | if (priv->irq >= 0) { | |
1d6316f5 | 659 | res = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, |
caff0cc4 | 660 | ds1343_thread, IRQF_ONESHOT, |
1d6316f5 RG |
661 | "ds1343", priv); |
662 | if (res) { | |
10b06b87 | 663 | priv->irq = -1; |
1d6316f5 RG |
664 | dev_err(&spi->dev, |
665 | "unable to request irq for rtc ds1343\n"); | |
10b06b87 | 666 | } else { |
caff0cc4 SH |
667 | device_init_wakeup(&spi->dev, true); |
668 | dev_pm_set_wake_irq(&spi->dev, spi->irq); | |
1d6316f5 | 669 | } |
1d6316f5 RG |
670 | } |
671 | ||
672 | res = ds1343_sysfs_register(&spi->dev); | |
673 | if (res) | |
674 | dev_err(&spi->dev, | |
675 | "unable to create sysfs entries for rtc ds1343\n"); | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | static int ds1343_remove(struct spi_device *spi) | |
681 | { | |
682 | struct ds1343_priv *priv = spi_get_drvdata(spi); | |
683 | ||
684 | if (spi->irq) { | |
685 | mutex_lock(&priv->mutex); | |
686 | priv->irqen &= ~RTC_AF; | |
687 | mutex_unlock(&priv->mutex); | |
688 | ||
caff0cc4 SH |
689 | dev_pm_clear_wake_irq(&spi->dev); |
690 | device_init_wakeup(&spi->dev, false); | |
1d6316f5 RG |
691 | devm_free_irq(&spi->dev, spi->irq, priv); |
692 | } | |
693 | ||
694 | spi_set_drvdata(spi, NULL); | |
695 | ||
696 | ds1343_sysfs_unregister(&spi->dev); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | #ifdef CONFIG_PM_SLEEP | |
702 | ||
703 | static int ds1343_suspend(struct device *dev) | |
704 | { | |
705 | struct spi_device *spi = to_spi_device(dev); | |
706 | ||
707 | if (spi->irq >= 0 && device_may_wakeup(dev)) | |
708 | enable_irq_wake(spi->irq); | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static int ds1343_resume(struct device *dev) | |
714 | { | |
715 | struct spi_device *spi = to_spi_device(dev); | |
716 | ||
717 | if (spi->irq >= 0 && device_may_wakeup(dev)) | |
718 | disable_irq_wake(spi->irq); | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | #endif | |
724 | ||
725 | static SIMPLE_DEV_PM_OPS(ds1343_pm, ds1343_suspend, ds1343_resume); | |
726 | ||
727 | static struct spi_driver ds1343_driver = { | |
728 | .driver = { | |
729 | .name = "ds1343", | |
1d6316f5 RG |
730 | .pm = &ds1343_pm, |
731 | }, | |
732 | .probe = ds1343_probe, | |
733 | .remove = ds1343_remove, | |
734 | .id_table = ds1343_id, | |
735 | }; | |
736 | ||
737 | module_spi_driver(ds1343_driver); | |
738 | ||
739 | MODULE_DESCRIPTION("DS1343 RTC SPI Driver"); | |
571eb883 RG |
740 | MODULE_AUTHOR("Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>," |
741 | "Ankur Srivastava <sankurece@gmail.com>"); | |
1d6316f5 | 742 | MODULE_LICENSE("GPL v2"); |