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rtc: imx-sc: remove .read_alarm
[linux-2.6-block.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1abb0dc9
DB		 2/*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
a2166858 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB		 9 */
10
eac7237f
NM		 11#include <linux/bcd.h>
12#include <linux/i2c.h>
1abb0dc9 13#include <linux/init.h>
698fffc2 14#include <linux/mod_devicetable.h>
eac7237f 15#include <linux/module.h>
227ec129 16#include <linux/property.h>
eac7237f
NM		 17#include <linux/rtc/ds1307.h>
18#include <linux/rtc.h>
1abb0dc9 19#include <linux/slab.h>
1abb0dc9 20#include <linux/string.h>
445c0207
AM		 21#include <linux/hwmon.h>
22#include <linux/hwmon-sysfs.h>
6c6ff145 23#include <linux/clk-provider.h>
11e5890b 24#include <linux/regmap.h>
fd90d48d 25#include <linux/watchdog.h>
1abb0dc9 26
40ce972d
DA		 27/*
28 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB		 29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
1abb0dc9
DB		 32 */
33enum ds_type {
227ec129 34 unknown_ds_type, /* always first and 0 */
045e0e85 35 ds_1307,
300a7735 36 ds_1308,
045e0e85
DB		 37 ds_1337,
38 ds_1338,
39 ds_1339,
40 ds_1340,
0759c886 41 ds_1341,
33df2ee1 42 ds_1388,
97f902b7 43 ds_3231,
8566f70c 44 m41t0,
045e0e85 45 m41t00,
7e580769 46 m41t11,
f4199f85 47 mcp794xx,
a2166858 48 rx_8025,
ee0981be 49 rx_8130,
32d322bc 50 last_ds_type /* always last */
40ce972d 51 /* rs5c372 too? different address... */
1abb0dc9
DB		 52};
53
1abb0dc9
DB		 54/* RTC registers don't differ much, except for the century flag */
55#define DS1307_REG_SECS 0x00 /* 00-59 */
56# define DS1307_BIT_CH 0x80
be5f59f4 57# define DS1340_BIT_nEOSC 0x80
f4199f85 58# define MCP794XX_BIT_ST 0x80
1abb0dc9 59#define DS1307_REG_MIN 0x01 /* 00-59 */
8566f70c 60# define M41T0_BIT_OF 0x80
1abb0dc9 61#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB		 62# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB		 64# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66#define DS1307_REG_WDAY 0x03 /* 01-07 */
f4199f85 67# define MCP794XX_BIT_VBATEN 0x08
1abb0dc9
DB		 68#define DS1307_REG_MDAY 0x04 /* 01-31 */
69#define DS1307_REG_MONTH 0x05 /* 01-12 */
70# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71#define DS1307_REG_YEAR 0x06 /* 00-99 */
72
40ce972d
DA		 73/*
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB		 75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
1abb0dc9 77 */
045e0e85 78#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 79# define DS1307_BIT_OUT 0x80
be5f59f4 80# define DS1338_BIT_OSF 0x20
1abb0dc9
DB		 81# define DS1307_BIT_SQWE 0x10
82# define DS1307_BIT_RS1 0x02
83# define DS1307_BIT_RS0 0x01
84#define DS1337_REG_CONTROL 0x0e
85# define DS1337_BIT_nEOSC 0x80
cb49a5e9 86# define DS1339_BIT_BBSQI 0x20
97f902b7 87# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB		 88# define DS1337_BIT_RS2 0x10
89# define DS1337_BIT_RS1 0x08
90# define DS1337_BIT_INTCN 0x04
91# define DS1337_BIT_A2IE 0x02
92# define DS1337_BIT_A1IE 0x01
045e0e85
DB		 93#define DS1340_REG_CONTROL 0x07
94# define DS1340_BIT_OUT 0x80
95# define DS1340_BIT_FT 0x40
96# define DS1340_BIT_CALIB_SIGN 0x20
97# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG		 98#define DS1340_REG_FLAG 0x09
99# define DS1340_BIT_OSF 0x80
1abb0dc9
DB		 100#define DS1337_REG_STATUS 0x0f
101# define DS1337_BIT_OSF 0x80
6c6ff145 102# define DS3231_BIT_EN32KHZ 0x08
1abb0dc9
DB		 103# define DS1337_BIT_A2I 0x02
104# define DS1337_BIT_A1I 0x01
cb49a5e9 105#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS		 106
107#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 108
a2166858
MF		 109#define RX8025_REG_CTRL1 0x0e
110# define RX8025_BIT_2412 0x20
111#define RX8025_REG_CTRL2 0x0f
112# define RX8025_BIT_PON 0x10
113# define RX8025_BIT_VDET 0x40
114# define RX8025_BIT_XST 0x20
1abb0dc9 115
3ffd4a2f
UKK		 116#define RX8130_REG_ALARM_MIN 0x17
117#define RX8130_REG_ALARM_HOUR 0x18
118#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
119#define RX8130_REG_EXTENSION 0x1c
92cbf12f 120#define RX8130_REG_EXTENSION_WADA BIT(3)
3ffd4a2f
UKK		 121#define RX8130_REG_FLAG 0x1d
122#define RX8130_REG_FLAG_VLF BIT(1)
92cbf12f 123#define RX8130_REG_FLAG_AF BIT(3)
3ffd4a2f 124#define RX8130_REG_CONTROL0 0x1e
92cbf12f 125#define RX8130_REG_CONTROL0_AIE BIT(3)
0026f160
BK		 126#define RX8130_REG_CONTROL1 0x1f
127#define RX8130_REG_CONTROL1_INIEN BIT(4)
128#define RX8130_REG_CONTROL1_CHGEN BIT(5)
92cbf12f
UKK		 129
130#define MCP794XX_REG_CONTROL 0x07
131# define MCP794XX_BIT_ALM0_EN 0x10
132# define MCP794XX_BIT_ALM1_EN 0x20
133#define MCP794XX_REG_ALARM0_BASE 0x0a
134#define MCP794XX_REG_ALARM0_CTRL 0x0d
135#define MCP794XX_REG_ALARM1_BASE 0x11
136#define MCP794XX_REG_ALARM1_CTRL 0x14
137# define MCP794XX_BIT_ALMX_IF BIT(3)
138# define MCP794XX_BIT_ALMX_C0 BIT(4)
139# define MCP794XX_BIT_ALMX_C1 BIT(5)
140# define MCP794XX_BIT_ALMX_C2 BIT(6)
141# define MCP794XX_BIT_ALMX_POL BIT(7)
142# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
143 MCP794XX_BIT_ALMX_C1 | \
144 MCP794XX_BIT_ALMX_C2)
145
79230ff6
GB		 146#define M41TXX_REG_CONTROL 0x07
147# define M41TXX_BIT_OUT BIT(7)
148# define M41TXX_BIT_FT BIT(6)
149# define M41TXX_BIT_CALIB_SIGN BIT(5)
150# define M41TXX_M_CALIBRATION GENMASK(4, 0)
151
fd90d48d
CP		 152#define DS1388_REG_WDOG_HUN_SECS 0x08
153#define DS1388_REG_WDOG_SECS 0x09
df11b323 154#define DS1388_REG_FLAG 0x0b
fd90d48d 155# define DS1388_BIT_WF BIT(6)
df11b323 156# define DS1388_BIT_OSF BIT(7)
fd90d48d
CP		 157#define DS1388_REG_CONTROL 0x0c
158# define DS1388_BIT_RST BIT(0)
159# define DS1388_BIT_WDE BIT(1)
59ed0127 160# define DS1388_BIT_nEOSC BIT(7)
fd90d48d 161
79230ff6
GB		 162/* negative offset step is -2.034ppm */
163#define M41TXX_NEG_OFFSET_STEP_PPB 2034
164/* positive offset step is +4.068ppm */
165#define M41TXX_POS_OFFSET_STEP_PPB 4068
166/* Min and max values supported with 'offset' interface by M41TXX */
167#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
168#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
169
1abb0dc9 170struct ds1307 {
1abb0dc9 171 enum ds_type type;
cb49a5e9
RG		 172 unsigned long flags;
173#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
174#define HAS_ALARM 1 /* bit 1 == irq claimed */
11e5890b
HK		 175 struct device *dev;
176 struct regmap *regmap;
177 const char *name;
1abb0dc9 178 struct rtc_device *rtc;
6c6ff145
AM		 179#ifdef CONFIG_COMMON_CLK
180 struct clk_hw clks[2];
181#endif
1abb0dc9
DB		 182};
183
045e0e85 184struct chip_desc {
045e0e85 185 unsigned alarm:1;
9eab0a78
AB		 186 u16 nvram_offset;
187 u16 nvram_size;
e553170a 188 u8 offset; /* register's offset */
e48585de
HK		 189 u8 century_reg;
190 u8 century_enable_bit;
191 u8 century_bit;
0b6ee805 192 u8 bbsqi_bit;
45947127 193 irq_handler_t irq_handler;
1efb98ba 194 const struct rtc_class_ops *rtc_ops;
eb86c306 195 u16 trickle_charger_reg;
57ec2d95 196 u8 (*do_trickle_setup)(struct ds1307 *, u32,
11e5890b 197 bool);
1b5b6af7
BK		 198 /* Does the RTC require trickle-resistor-ohms to select the value of
199 * the resistor between Vcc and Vbackup?
200 */
201 bool requires_trickle_resistor;
95a74cbb
BK		 202 /* Some RTC's batteries and supercaps were charged by default, others
203 * allow charging but were not configured previously to do so.
204 * Remember this behavior to stay backwards compatible.
205 */
206 bool charge_default;
045e0e85
DB		 207};
208
d0e3f61b 209static const struct chip_desc chips[last_ds_type];
cb49a5e9 210
1abb0dc9
DB		 211static int ds1307_get_time(struct device *dev, struct rtc_time *t)
212{
213 struct ds1307 *ds1307 = dev_get_drvdata(dev);
11e5890b 214 int tmp, ret;
e48585de 215 const struct chip_desc *chip = &chips[ds1307->type];
042fa8c7 216 u8 regs[7];
1abb0dc9 217
501f9826
UKK		 218 if (ds1307->type == rx_8130) {
219 unsigned int regflag;
220 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
221 if (ret) {
222 dev_err(dev, "%s error %d\n", "read", ret);
223 return ret;
224 }
225
226 if (regflag & RX8130_REG_FLAG_VLF) {
227 dev_warn_once(dev, "oscillator failed, set time!\n");
228 return -EINVAL;
229 }
230 }
231
045e0e85 232 /* read the RTC date and time registers all at once */
042fa8c7
AB		 233 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
234 sizeof(regs));
11e5890b
HK		 235 if (ret) {
236 dev_err(dev, "%s error %d\n", "read", ret);
237 return ret;
1abb0dc9
DB		 238 }
239
042fa8c7 240 dev_dbg(dev, "%s: %7ph\n", "read", regs);
1abb0dc9 241
8566f70c
SA		 242 /* if oscillator fail bit is set, no data can be trusted */
243 if (ds1307->type == m41t0 &&
042fa8c7 244 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
8566f70c
SA		 245 dev_warn_once(dev, "oscillator failed, set time!\n");
246 return -EINVAL;
247 }
248
b3a50169
AB		 249 tmp = regs[DS1307_REG_SECS];
250 switch (ds1307->type) {
251 case ds_1307:
252 case m41t0:
253 case m41t00:
254 case m41t11:
255 if (tmp & DS1307_BIT_CH)
256 return -EINVAL;
257 break;
258 case ds_1308:
259 case ds_1338:
260 if (tmp & DS1307_BIT_CH)
261 return -EINVAL;
262
263 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
264 if (ret)
265 return ret;
266 if (tmp & DS1338_BIT_OSF)
267 return -EINVAL;
268 break;
269 case ds_1340:
270 if (tmp & DS1340_BIT_nEOSC)
271 return -EINVAL;
272
273 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
274 if (ret)
275 return ret;
276 if (tmp & DS1340_BIT_OSF)
277 return -EINVAL;
278 break;
df11b323
CP		 279 case ds_1388:
280 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
281 if (ret)
282 return ret;
283 if (tmp & DS1388_BIT_OSF)
284 return -EINVAL;
285 break;
b3a50169
AB		 286 case mcp794xx:
287 if (!(tmp & MCP794XX_BIT_ST))
288 return -EINVAL;
289
290 break;
291 default:
292 break;
293 }
294
042fa8c7
AB		 295 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
296 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
297 tmp = regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70 298 t->tm_hour = bcd2bin(tmp);
042fa8c7
AB		 299 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
300 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
301 tmp = regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 302 t->tm_mon = bcd2bin(tmp) - 1;
042fa8c7 303 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
1abb0dc9 304
042fa8c7 305 if (regs[chip->century_reg] & chip->century_bit &&
e48585de
HK		 306 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
307 t->tm_year += 100;
50d6c0ea 308
1abb0dc9
DB		 309 dev_dbg(dev, "%s secs=%d, mins=%d, "
310 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
311 "read", t->tm_sec, t->tm_min,
312 t->tm_hour, t->tm_mday,
313 t->tm_mon, t->tm_year, t->tm_wday);
314
22652ba7 315 return 0;
1abb0dc9
DB		 316}
317
318static int ds1307_set_time(struct device *dev, struct rtc_time *t)
319{
320 struct ds1307 *ds1307 = dev_get_drvdata(dev);
e48585de 321 const struct chip_desc *chip = &chips[ds1307->type];
1abb0dc9
DB		 322 int result;
323 int tmp;
042fa8c7 324 u8 regs[7];
1abb0dc9
DB		 325
326 dev_dbg(dev, "%s secs=%d, mins=%d, "
327 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG		 328 "write", t->tm_sec, t->tm_min,
329 t->tm_hour, t->tm_mday,
330 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 331
50d6c0ea
AB		 332 if (t->tm_year < 100)
333 return -EINVAL;
334
e48585de
HK		 335#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
336 if (t->tm_year > (chip->century_bit ? 299 : 199))
337 return -EINVAL;
50d6c0ea 338#else
e48585de 339 if (t->tm_year > 199)
50d6c0ea
AB		 340 return -EINVAL;
341#endif
342
042fa8c7
AB		 343 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
344 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
345 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
346 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
347 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
348 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB		 349
350 /* assume 20YY not 19YY */
351 tmp = t->tm_year - 100;
042fa8c7 352 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 353
e48585de 354 if (chip->century_enable_bit)
042fa8c7 355 regs[chip->century_reg] |= chip->century_enable_bit;
e48585de 356 if (t->tm_year > 199 && chip->century_bit)
042fa8c7 357 regs[chip->century_reg] |= chip->century_bit;
e48585de 358
b3a50169
AB		 359 switch (ds1307->type) {
360 case ds_1308:
361 case ds_1338:
362 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
363 DS1338_BIT_OSF, 0);
364 break;
365 case ds_1340:
366 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
367 DS1340_BIT_OSF, 0);
368 break;
f471b05f
CP		 369 case ds_1388:
370 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
371 DS1388_BIT_OSF, 0);
372 break;
b3a50169 373 case mcp794xx:
40ce972d
DA		 374 /*
375 * these bits were cleared when preparing the date/time
376 * values and need to be set again before writing the
042fa8c7 377 * regsfer out to the device.
40ce972d 378 */
042fa8c7
AB		 379 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
380 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
b3a50169
AB		 381 break;
382 default:
383 break;
be5f59f4 384 }
1abb0dc9 385
042fa8c7 386 dev_dbg(dev, "%s: %7ph\n", "write", regs);
1abb0dc9 387
042fa8c7
AB		 388 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
389 sizeof(regs));
11e5890b 390 if (result) {
fed40b73
BS		 391 dev_err(dev, "%s error %d\n", "write", result);
392 return result;
1abb0dc9 393 }
501f9826
UKK		 394
395 if (ds1307->type == rx_8130) {
396 /* clear Voltage Loss Flag as data is available now */
397 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
398 ~(u8)RX8130_REG_FLAG_VLF);
399 if (result) {
400 dev_err(dev, "%s error %d\n", "write", result);
401 return result;
402 }
403 }
404
1abb0dc9
DB		 405 return 0;
406}
407
74d88eb2 408static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 409{
11e5890b 410 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9 411 int ret;
042fa8c7 412 u8 regs[9];
cb49a5e9
RG		 413
414 if (!test_bit(HAS_ALARM, &ds1307->flags))
415 return -EINVAL;
416
417 /* read all ALARM1, ALARM2, and status registers at once */
11e5890b 418 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
042fa8c7 419 regs, sizeof(regs));
11e5890b 420 if (ret) {
cb49a5e9 421 dev_err(dev, "%s error %d\n", "alarm read", ret);
11e5890b 422 return ret;
cb49a5e9
RG		 423 }
424
ff67abd2 425 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
042fa8c7 426 &regs[0], &regs[4], &regs[7]);
cb49a5e9 427
40ce972d
DA		 428 /*
429 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG		 430 * and that all four fields are checked matches
431 */
042fa8c7
AB		 432 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
433 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
434 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
435 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
cb49a5e9
RG		 436
437 /* ... and status */
042fa8c7
AB		 438 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
439 t->pending = !!(regs[8] & DS1337_BIT_A1I);
cb49a5e9
RG		 440
441 dev_dbg(dev, "%s secs=%d, mins=%d, "
442 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
443 "alarm read", t->time.tm_sec, t->time.tm_min,
444 t->time.tm_hour, t->time.tm_mday,
445 t->enabled, t->pending);
446
447 return 0;
448}
449
74d88eb2 450static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 451{
11e5890b 452 struct ds1307 *ds1307 = dev_get_drvdata(dev);
042fa8c7 453 unsigned char regs[9];
cb49a5e9
RG		 454 u8 control, status;
455 int ret;
456
457 if (!test_bit(HAS_ALARM, &ds1307->flags))
458 return -EINVAL;
459
460 dev_dbg(dev, "%s secs=%d, mins=%d, "
461 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
462 "alarm set", t->time.tm_sec, t->time.tm_min,
463 t->time.tm_hour, t->time.tm_mday,
464 t->enabled, t->pending);
465
466 /* read current status of both alarms and the chip */
042fa8c7
AB		 467 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
468 sizeof(regs));
11e5890b 469 if (ret) {
cb49a5e9 470 dev_err(dev, "%s error %d\n", "alarm write", ret);
11e5890b 471 return ret;
cb49a5e9 472 }
042fa8c7
AB		 473 control = regs[7];
474 status = regs[8];
cb49a5e9 475
ff67abd2 476 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
042fa8c7 477 &regs[0], &regs[4], control, status);
cb49a5e9
RG		 478
479 /* set ALARM1, using 24 hour and day-of-month modes */
042fa8c7
AB		 480 regs[0] = bin2bcd(t->time.tm_sec);
481 regs[1] = bin2bcd(t->time.tm_min);
482 regs[2] = bin2bcd(t->time.tm_hour);
483 regs[3] = bin2bcd(t->time.tm_mday);
cb49a5e9
RG		 484
485 /* set ALARM2 to non-garbage */
042fa8c7
AB		 486 regs[4] = 0;
487 regs[5] = 0;
488 regs[6] = 0;
cb49a5e9 489
5919fb97 490 /* disable alarms */
042fa8c7
AB		 491 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
492 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
cb49a5e9 493
042fa8c7
AB		 494 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
495 sizeof(regs));
11e5890b 496 if (ret) {
cb49a5e9 497 dev_err(dev, "can't set alarm time\n");
fed40b73 498 return ret;
cb49a5e9
RG		 499 }
500
5919fb97
NB		 501 /* optionally enable ALARM1 */
502 if (t->enabled) {
503 dev_dbg(dev, "alarm IRQ armed\n");
042fa8c7
AB		 504 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
505 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
5919fb97
NB		 506 }
507
cb49a5e9
RG		 508 return 0;
509}
510
16380c15 511static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9 512{
11e5890b 513 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9 514
16380c15
JS		 515 if (!test_bit(HAS_ALARM, &ds1307->flags))
516 return -ENOTTY;
cb49a5e9 517
078f3f64
HK		 518 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
519 DS1337_BIT_A1IE,
520 enabled ? DS1337_BIT_A1IE : 0);
cb49a5e9
RG		 521}
522
d0e3f61b
UKK		 523static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
524{
525 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
526 DS1307_TRICKLE_CHARGER_NO_DIODE;
682d73f6 527
462eb736
BK		 528 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
529
d0e3f61b
UKK		 530 switch (ohms) {
531 case 250:
532 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
533 break;
534 case 2000:
535 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
536 break;
537 case 4000:
538 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
539 break;
540 default:
541 dev_warn(ds1307->dev,
542 "Unsupported ohm value %u in dt\n", ohms);
543 return 0;
544 }
545 return setup;
546}
ee0981be 547
0026f160
BK		 548static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
549{
550 /* make sure that the backup battery is enabled */
551 u8 setup = RX8130_REG_CONTROL1_INIEN;
552 if (diode)
553 setup |= RX8130_REG_CONTROL1_CHGEN;
554
555 return setup;
556}
557
ee0981be
MV		 558static irqreturn_t rx8130_irq(int irq, void *dev_id)
559{
560 struct ds1307 *ds1307 = dev_id;
ee0981be
MV		 561 u8 ctl[3];
562 int ret;
563
59238192 564 rtc_lock(ds1307->rtc);
ee0981be
MV		 565
566 /* Read control registers. */
f2b48012
AB		 567 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
568 sizeof(ctl));
ee0981be
MV		 569 if (ret < 0)
570 goto out;
571 if (!(ctl[1] & RX8130_REG_FLAG_AF))
572 goto out;
573 ctl[1] &= ~RX8130_REG_FLAG_AF;
574 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
575
f2b48012
AB		 576 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
577 sizeof(ctl));
ee0981be
MV		 578 if (ret < 0)
579 goto out;
580
581 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
582
583out:
59238192 584 rtc_unlock(ds1307->rtc);
ee0981be
MV		 585
586 return IRQ_HANDLED;
587}
588
589static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
590{
591 struct ds1307 *ds1307 = dev_get_drvdata(dev);
592 u8 ald[3], ctl[3];
593 int ret;
594
595 if (!test_bit(HAS_ALARM, &ds1307->flags))
596 return -EINVAL;
597
598 /* Read alarm registers. */
f2b48012
AB		 599 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
600 sizeof(ald));
ee0981be
MV		 601 if (ret < 0)
602 return ret;
603
604 /* Read control registers. */
f2b48012
AB		 605 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
606 sizeof(ctl));
ee0981be
MV		 607 if (ret < 0)
608 return ret;
609
610 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
611 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
612
613 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
614 t->time.tm_sec = -1;
615 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
616 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
617 t->time.tm_wday = -1;
618 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
619 t->time.tm_mon = -1;
620 t->time.tm_year = -1;
621 t->time.tm_yday = -1;
622 t->time.tm_isdst = -1;
623
624 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
625 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
626 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
627
628 return 0;
629}
630
631static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
632{
633 struct ds1307 *ds1307 = dev_get_drvdata(dev);
634 u8 ald[3], ctl[3];
635 int ret;
636
637 if (!test_bit(HAS_ALARM, &ds1307->flags))
638 return -EINVAL;
639
640 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
641 "enabled=%d pending=%d\n", __func__,
642 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
643 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
644 t->enabled, t->pending);
645
646 /* Read control registers. */
f2b48012
AB		 647 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
648 sizeof(ctl));
ee0981be
MV		 649 if (ret < 0)
650 return ret;
651
3f929cad
UKK		 652 ctl[0] &= RX8130_REG_EXTENSION_WADA;
653 ctl[1] &= ~RX8130_REG_FLAG_AF;
ee0981be
MV		 654 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
655
f2b48012
AB		 656 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
657 sizeof(ctl));
ee0981be
MV		 658 if (ret < 0)
659 return ret;
660
661 /* Hardware alarm precision is 1 minute! */
662 ald[0] = bin2bcd(t->time.tm_min);
663 ald[1] = bin2bcd(t->time.tm_hour);
664 ald[2] = bin2bcd(t->time.tm_mday);
665
f2b48012
AB		 666 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
667 sizeof(ald));
ee0981be
MV		 668 if (ret < 0)
669 return ret;
670
671 if (!t->enabled)
672 return 0;
673
674 ctl[2] |= RX8130_REG_CONTROL0_AIE;
675
3f929cad 676 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
ee0981be
MV		 677}
678
d0e3f61b
UKK		 679static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
680{
681 struct ds1307 *ds1307 = dev_get_drvdata(dev);
682 int ret, reg;
683
684 if (!test_bit(HAS_ALARM, &ds1307->flags))
685 return -EINVAL;
686
687 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
688 if (ret < 0)
689 return ret;
690
691 if (enabled)
692 reg |= RX8130_REG_CONTROL0_AIE;
693 else
694 reg &= ~RX8130_REG_CONTROL0_AIE;
695
696 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
697}
698
699static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
700{
701 struct ds1307 *ds1307 = dev_id;
702 struct mutex *lock = &ds1307->rtc->ops_lock;
703 int reg, ret;
704
705 mutex_lock(lock);
706
707 /* Check and clear alarm 0 interrupt flag. */
708 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
709 if (ret)
710 goto out;
711 if (!(reg & MCP794XX_BIT_ALMX_IF))
712 goto out;
713 reg &= ~MCP794XX_BIT_ALMX_IF;
714 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
715 if (ret)
716 goto out;
717
718 /* Disable alarm 0. */
719 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
720 MCP794XX_BIT_ALM0_EN, 0);
721 if (ret)
722 goto out;
723
724 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
725
726out:
727 mutex_unlock(lock);
728
729 return IRQ_HANDLED;
730}
731
732static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
733{
734 struct ds1307 *ds1307 = dev_get_drvdata(dev);
735 u8 regs[10];
736 int ret;
737
738 if (!test_bit(HAS_ALARM, &ds1307->flags))
739 return -EINVAL;
740
741 /* Read control and alarm 0 registers. */
742 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
743 sizeof(regs));
744 if (ret)
745 return ret;
746
747 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
748
749 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
750 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
751 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
752 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
753 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
754 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
755 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
756 t->time.tm_year = -1;
757 t->time.tm_yday = -1;
758 t->time.tm_isdst = -1;
759
760 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
761 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
762 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
763 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
764 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
765 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
766 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
767
768 return 0;
769}
770
771/*
772 * We may have a random RTC weekday, therefore calculate alarm weekday based
773 * on current weekday we read from the RTC timekeeping regs
774 */
775static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
776{
777 struct rtc_time tm_now;
778 int days_now, days_alarm, ret;
779
780 ret = ds1307_get_time(dev, &tm_now);
781 if (ret)
782 return ret;
783
784 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
785 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
786
787 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
788}
789
790static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
791{
792 struct ds1307 *ds1307 = dev_get_drvdata(dev);
793 unsigned char regs[10];
794 int wday, ret;
795
796 if (!test_bit(HAS_ALARM, &ds1307->flags))
797 return -EINVAL;
798
799 wday = mcp794xx_alm_weekday(dev, &t->time);
800 if (wday < 0)
801 return wday;
802
803 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
804 "enabled=%d pending=%d\n", __func__,
805 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
806 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
807 t->enabled, t->pending);
808
809 /* Read control and alarm 0 registers. */
810 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
811 sizeof(regs));
812 if (ret)
813 return ret;
814
815 /* Set alarm 0, using 24-hour and day-of-month modes. */
816 regs[3] = bin2bcd(t->time.tm_sec);
817 regs[4] = bin2bcd(t->time.tm_min);
818 regs[5] = bin2bcd(t->time.tm_hour);
819 regs[6] = wday;
820 regs[7] = bin2bcd(t->time.tm_mday);
821 regs[8] = bin2bcd(t->time.tm_mon + 1);
822
823 /* Clear the alarm 0 interrupt flag. */
824 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
825 /* Set alarm match: second, minute, hour, day, date, month. */
826 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
827 /* Disable interrupt. We will not enable until completely programmed */
828 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
829
830 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
831 sizeof(regs));
832 if (ret)
833 return ret;
834
835 if (!t->enabled)
836 return 0;
837 regs[0] |= MCP794XX_BIT_ALM0_EN;
838 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
839}
840
841static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
ee0981be
MV		 842{
843 struct ds1307 *ds1307 = dev_get_drvdata(dev);
ee0981be
MV		 844
845 if (!test_bit(HAS_ALARM, &ds1307->flags))
846 return -EINVAL;
847
d0e3f61b
UKK		 848 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
849 MCP794XX_BIT_ALM0_EN,
850 enabled ? MCP794XX_BIT_ALM0_EN : 0);
851}
ee0981be 852
d0e3f61b
UKK		 853static int m41txx_rtc_read_offset(struct device *dev, long *offset)
854{
855 struct ds1307 *ds1307 = dev_get_drvdata(dev);
856 unsigned int ctrl_reg;
857 u8 val;
858
859 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
860
861 val = ctrl_reg & M41TXX_M_CALIBRATION;
862
863 /* check if positive */
864 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
865 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
ee0981be 866 else
d0e3f61b 867 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
ee0981be 868
d0e3f61b
UKK		 869 return 0;
870}
871
872static int m41txx_rtc_set_offset(struct device *dev, long offset)
873{
874 struct ds1307 *ds1307 = dev_get_drvdata(dev);
875 unsigned int ctrl_reg;
876
877 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
878 return -ERANGE;
879
880 if (offset >= 0) {
881 ctrl_reg = DIV_ROUND_CLOSEST(offset,
882 M41TXX_POS_OFFSET_STEP_PPB);
883 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
884 } else {
885 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
886 M41TXX_NEG_OFFSET_STEP_PPB);
887 }
888
889 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
890 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
891 ctrl_reg);
ee0981be
MV		 892}
893
fd90d48d
CP		 894#ifdef CONFIG_WATCHDOG_CORE
895static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
896{
897 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
898 u8 regs[2];
899 int ret;
900
901 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
902 DS1388_BIT_WF, 0);
903 if (ret)
904 return ret;
905
906 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
907 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
908 if (ret)
909 return ret;
910
911 /*
912 * watchdog timeouts are measured in seconds. So ignore hundredths of
913 * seconds field.
914 */
915 regs[0] = 0;
916 regs[1] = bin2bcd(wdt_dev->timeout);
917
918 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
919 sizeof(regs));
920 if (ret)
921 return ret;
922
923 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
924 DS1388_BIT_WDE | DS1388_BIT_RST,
925 DS1388_BIT_WDE | DS1388_BIT_RST);
926}
927
928static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
929{
930 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
931
932 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
933 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
934}
935
936static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
937{
938 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
939 u8 regs[2];
940
941 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
942 sizeof(regs));
943}
944
945static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
946 unsigned int val)
947{
948 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
949 u8 regs[2];
950
951 wdt_dev->timeout = val;
952 regs[0] = 0;
953 regs[1] = bin2bcd(wdt_dev->timeout);
954
955 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
956 sizeof(regs));
957}
958#endif
959
d0e3f61b
UKK		 960static const struct rtc_class_ops rx8130_rtc_ops = {
961 .read_time = ds1307_get_time,
962 .set_time = ds1307_set_time,
963 .read_alarm = rx8130_read_alarm,
964 .set_alarm = rx8130_set_alarm,
965 .alarm_irq_enable = rx8130_alarm_irq_enable,
966};
967
968static const struct rtc_class_ops mcp794xx_rtc_ops = {
969 .read_time = ds1307_get_time,
970 .set_time = ds1307_set_time,
971 .read_alarm = mcp794xx_read_alarm,
972 .set_alarm = mcp794xx_set_alarm,
973 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
974};
975
976static const struct rtc_class_ops m41txx_rtc_ops = {
977 .read_time = ds1307_get_time,
978 .set_time = ds1307_set_time,
979 .read_alarm = ds1337_read_alarm,
980 .set_alarm = ds1337_set_alarm,
981 .alarm_irq_enable = ds1307_alarm_irq_enable,
982 .read_offset = m41txx_rtc_read_offset,
983 .set_offset = m41txx_rtc_set_offset,
984};
985
986static const struct chip_desc chips[last_ds_type] = {
987 [ds_1307] = {
988 .nvram_offset = 8,
989 .nvram_size = 56,
990 },
991 [ds_1308] = {
992 .nvram_offset = 8,
993 .nvram_size = 56,
994 },
995 [ds_1337] = {
996 .alarm = 1,
997 .century_reg = DS1307_REG_MONTH,
998 .century_bit = DS1337_BIT_CENTURY,
999 },
1000 [ds_1338] = {
1001 .nvram_offset = 8,
1002 .nvram_size = 56,
1003 },
1004 [ds_1339] = {
1005 .alarm = 1,
1006 .century_reg = DS1307_REG_MONTH,
1007 .century_bit = DS1337_BIT_CENTURY,
1008 .bbsqi_bit = DS1339_BIT_BBSQI,
1009 .trickle_charger_reg = 0x10,
1010 .do_trickle_setup = &do_trickle_setup_ds1339,
1b5b6af7 1011 .requires_trickle_resistor = true,
95a74cbb 1012 .charge_default = true,
d0e3f61b
UKK		 1013 },
1014 [ds_1340] = {
1015 .century_reg = DS1307_REG_HOUR,
1016 .century_enable_bit = DS1340_BIT_CENTURY_EN,
1017 .century_bit = DS1340_BIT_CENTURY,
1018 .do_trickle_setup = &do_trickle_setup_ds1339,
1019 .trickle_charger_reg = 0x08,
1b5b6af7 1020 .requires_trickle_resistor = true,
95a74cbb 1021 .charge_default = true,
d0e3f61b
UKK		 1022 },
1023 [ds_1341] = {
1024 .century_reg = DS1307_REG_MONTH,
1025 .century_bit = DS1337_BIT_CENTURY,
1026 },
1027 [ds_1388] = {
1028 .offset = 1,
1029 .trickle_charger_reg = 0x0a,
1030 },
1031 [ds_3231] = {
1032 .alarm = 1,
1033 .century_reg = DS1307_REG_MONTH,
1034 .century_bit = DS1337_BIT_CENTURY,
1035 .bbsqi_bit = DS3231_BIT_BBSQW,
1036 },
1037 [rx_8130] = {
1038 .alarm = 1,
1039 /* this is battery backed SRAM */
1040 .nvram_offset = 0x20,
1041 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1042 .offset = 0x10,
1043 .irq_handler = rx8130_irq,
1044 .rtc_ops = &rx8130_rtc_ops,
0026f160
BK		 1045 .trickle_charger_reg = RX8130_REG_CONTROL1,
1046 .do_trickle_setup = &do_trickle_setup_rx8130,
d0e3f61b
UKK		 1047 },
1048 [m41t0] = {
1049 .rtc_ops = &m41txx_rtc_ops,
1050 },
1051 [m41t00] = {
1052 .rtc_ops = &m41txx_rtc_ops,
1053 },
1054 [m41t11] = {
1055 /* this is battery backed SRAM */
1056 .nvram_offset = 8,
1057 .nvram_size = 56,
1058 .rtc_ops = &m41txx_rtc_ops,
1059 },
1060 [mcp794xx] = {
1061 .alarm = 1,
1062 /* this is battery backed SRAM */
1063 .nvram_offset = 0x20,
1064 .nvram_size = 0x40,
1065 .irq_handler = mcp794xx_irq,
1066 .rtc_ops = &mcp794xx_rtc_ops,
1067 },
1068};
1069
1070static const struct i2c_device_id ds1307_id[] = {
1071 { "ds1307", ds_1307 },
1072 { "ds1308", ds_1308 },
1073 { "ds1337", ds_1337 },
1074 { "ds1338", ds_1338 },
1075 { "ds1339", ds_1339 },
1076 { "ds1388", ds_1388 },
1077 { "ds1340", ds_1340 },
1078 { "ds1341", ds_1341 },
1079 { "ds3231", ds_3231 },
1080 { "m41t0", m41t0 },
1081 { "m41t00", m41t00 },
1082 { "m41t11", m41t11 },
1083 { "mcp7940x", mcp794xx },
1084 { "mcp7941x", mcp794xx },
1085 { "pt7c4338", ds_1307 },
1086 { "rx8025", rx_8025 },
1087 { "isl12057", ds_1337 },
1088 { "rx8130", rx_8130 },
1089 { }
1090};
1091MODULE_DEVICE_TABLE(i2c, ds1307_id);
1092
d0e3f61b
UKK		 1093static const struct of_device_id ds1307_of_match[] = {
1094 {
1095 .compatible = "dallas,ds1307",
1096 .data = (void *)ds_1307
1097 },
1098 {
1099 .compatible = "dallas,ds1308",
1100 .data = (void *)ds_1308
1101 },
1102 {
1103 .compatible = "dallas,ds1337",
1104 .data = (void *)ds_1337
1105 },
1106 {
1107 .compatible = "dallas,ds1338",
1108 .data = (void *)ds_1338
1109 },
1110 {
1111 .compatible = "dallas,ds1339",
1112 .data = (void *)ds_1339
1113 },
1114 {
1115 .compatible = "dallas,ds1388",
1116 .data = (void *)ds_1388
1117 },
1118 {
1119 .compatible = "dallas,ds1340",
1120 .data = (void *)ds_1340
1121 },
1122 {
1123 .compatible = "dallas,ds1341",
1124 .data = (void *)ds_1341
1125 },
1126 {
1127 .compatible = "maxim,ds3231",
1128 .data = (void *)ds_3231
1129 },
1130 {
1131 .compatible = "st,m41t0",
1132 .data = (void *)m41t0
1133 },
1134 {
1135 .compatible = "st,m41t00",
1136 .data = (void *)m41t00
1137 },
1138 {
1139 .compatible = "st,m41t11",
1140 .data = (void *)m41t11
1141 },
1142 {
1143 .compatible = "microchip,mcp7940x",
1144 .data = (void *)mcp794xx
1145 },
1146 {
1147 .compatible = "microchip,mcp7941x",
1148 .data = (void *)mcp794xx
1149 },
1150 {
1151 .compatible = "pericom,pt7c4338",
1152 .data = (void *)ds_1307
1153 },
1154 {
1155 .compatible = "epson,rx8025",
1156 .data = (void *)rx_8025
1157 },
1158 {
1159 .compatible = "isil,isl12057",
1160 .data = (void *)ds_1337
1161 },
1162 {
1163 .compatible = "epson,rx8130",
1164 .data = (void *)rx_8130
1165 },
1166 { }
1167};
1168MODULE_DEVICE_TABLE(of, ds1307_of_match);
d0e3f61b 1169
1d1945d2 1170/*
d0e3f61b
UKK		 1171 * The ds1337 and ds1339 both have two alarms, but we only use the first
1172 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1173 * signal; ds1339 chips have only one alarm signal.
1d1945d2 1174 */
d0e3f61b 1175static irqreturn_t ds1307_irq(int irq, void *dev_id)
1d1945d2 1176{
d0e3f61b
UKK		 1177 struct ds1307 *ds1307 = dev_id;
1178 struct mutex *lock = &ds1307->rtc->ops_lock;
1179 int stat, ret;
1d1945d2 1180
2fb07a10 1181 mutex_lock(lock);
d0e3f61b 1182 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
11e5890b 1183 if (ret)
1d1945d2
SG		 1184 goto out;
1185
d0e3f61b
UKK		 1186 if (stat & DS1337_BIT_A1I) {
1187 stat &= ~DS1337_BIT_A1I;
1188 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1d1945d2 1189
d0e3f61b
UKK		 1190 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1191 DS1337_BIT_A1IE, 0);
1192 if (ret)
1193 goto out;
1194
1195 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1196 }
1d1945d2
SG		 1197
1198out:
2fb07a10
FB		 1199 mutex_unlock(lock);
1200
1201 return IRQ_HANDLED;
1d1945d2
SG		 1202}
1203
d0e3f61b 1204/*----------------------------------------------------------------------*/
79230ff6 1205
d0e3f61b
UKK		 1206static const struct rtc_class_ops ds13xx_rtc_ops = {
1207 .read_time = ds1307_get_time,
1208 .set_time = ds1307_set_time,
1209 .read_alarm = ds1337_read_alarm,
1210 .set_alarm = ds1337_set_alarm,
1211 .alarm_irq_enable = ds1307_alarm_irq_enable,
1212};
79230ff6 1213
6a5f2a1f
AB		 1214static ssize_t frequency_test_store(struct device *dev,
1215 struct device_attribute *attr,
1216 const char *buf, size_t count)
b41c23e1 1217{
6a5f2a1f 1218 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
b41c23e1
GB		 1219 bool freq_test_en;
1220 int ret;
1221
1222 ret = kstrtobool(buf, &freq_test_en);
1223 if (ret) {
1224 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1225 return ret;
1226 }
1227
1228 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1229 freq_test_en ? M41TXX_BIT_FT : 0);
1230
1231 return count;
1232}
1233
6a5f2a1f
AB		 1234static ssize_t frequency_test_show(struct device *dev,
1235 struct device_attribute *attr,
1236 char *buf)
b41c23e1 1237{
6a5f2a1f 1238 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
b41c23e1
GB		 1239 unsigned int ctrl_reg;
1240
1241 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1242
1243 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1244 "off\n");
1245}
1246
6a5f2a1f 1247static DEVICE_ATTR_RW(frequency_test);
b41c23e1
GB		 1248
1249static struct attribute *rtc_freq_test_attrs[] = {
6a5f2a1f 1250 &dev_attr_frequency_test.attr,
b41c23e1
GB		 1251 NULL,
1252};
1253
1254static const struct attribute_group rtc_freq_test_attr_group = {
1255 .attrs = rtc_freq_test_attrs,
1256};
1257
b41c23e1
GB		 1258static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1259{
1260 int err;
1261
1262 switch (ds1307->type) {
1263 case m41t0:
1264 case m41t00:
1265 case m41t11:
6a5f2a1f
AB		 1266 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1267 if (err)
b41c23e1 1268 return err;
b41c23e1
GB		 1269 break;
1270 default:
1271 break;
1272 }
1273
1274 return 0;
1275}
1276
1d1945d2
SG		 1277/*----------------------------------------------------------------------*/
1278
abc925f7
AB		 1279static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1280 size_t bytes)
682d73f6 1281{
abc925f7 1282 struct ds1307 *ds1307 = priv;
969fa07b 1283 const struct chip_desc *chip = &chips[ds1307->type];
682d73f6 1284
969fa07b 1285 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
abc925f7 1286 val, bytes);
682d73f6
DB		 1287}
1288
abc925f7
AB		 1289static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1290 size_t bytes)
682d73f6 1291{
abc925f7 1292 struct ds1307 *ds1307 = priv;
969fa07b 1293 const struct chip_desc *chip = &chips[ds1307->type];
682d73f6 1294
969fa07b 1295 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
abc925f7 1296 val, bytes);
682d73f6
DB		 1297}
1298
682d73f6
DB		 1299/*----------------------------------------------------------------------*/
1300
d8490fd5 1301static u8 ds1307_trickle_init(struct ds1307 *ds1307,
7624df48 1302 const struct chip_desc *chip)
33b04b7b 1303{
0874734e 1304 u32 ohms, chargeable;
95a74cbb 1305 bool diode = chip->charge_default;
33b04b7b
MV		 1306
1307 if (!chip->do_trickle_setup)
d8490fd5
HK		 1308 return 0;
1309
11e5890b 1310 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1b5b6af7 1311 &ohms) && chip->requires_trickle_resistor)
d8490fd5
HK		 1312 return 0;
1313
0874734e
BK		 1314 /* aux-voltage-chargeable takes precedence over the deprecated
1315 * trickle-diode-disable
1316 */
1317 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1318 &chargeable)) {
1319 switch (chargeable) {
1320 case 0:
1321 diode = false;
1322 break;
1323 case 1:
1324 diode = true;
1325 break;
1326 default:
1327 dev_warn(ds1307->dev,
1328 "unsupported aux-voltage-chargeable value\n");
1329 break;
1330 }
1331 } else if (device_property_read_bool(ds1307->dev,
1332 "trickle-diode-disable")) {
33b04b7b 1333 diode = false;
0874734e 1334 }
d8490fd5
HK		 1335
1336 return chip->do_trickle_setup(ds1307, ohms, diode);
33b04b7b
MV		 1337}
1338
445c0207
AM		 1339/*----------------------------------------------------------------------*/
1340
6b583a64 1341#if IS_REACHABLE(CONFIG_HWMON)
445c0207
AM		 1342
1343/*
1344 * Temperature sensor support for ds3231 devices.
1345 */
1346
1347#define DS3231_REG_TEMPERATURE 0x11
1348
1349/*
1350 * A user-initiated temperature conversion is not started by this function,
1351 * so the temperature is updated once every 64 seconds.
1352 */
9a3dce62 1353static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
445c0207
AM		 1354{
1355 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1356 u8 temp_buf[2];
1357 s16 temp;
1358 int ret;
1359
11e5890b
HK		 1360 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1361 temp_buf, sizeof(temp_buf));
1362 if (ret)
445c0207 1363 return ret;
445c0207
AM		 1364 /*
1365 * Temperature is represented as a 10-bit code with a resolution of
1366 * 0.25 degree celsius and encoded in two's complement format.
1367 */
1368 temp = (temp_buf[0] << 8) | temp_buf[1];
1369 temp >>= 6;
1370 *mC = temp * 250;
1371
1372 return 0;
1373}
1374
1375static ssize_t ds3231_hwmon_show_temp(struct device *dev,
4057a66e 1376 struct device_attribute *attr, char *buf)
445c0207
AM		 1377{
1378 int ret;
9a3dce62 1379 s32 temp;
445c0207
AM		 1380
1381 ret = ds3231_hwmon_read_temp(dev, &temp);
1382 if (ret)
1383 return ret;
1384
1385 return sprintf(buf, "%d\n", temp);
1386}
b4be271c 1387static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
4057a66e 1388 NULL, 0);
445c0207
AM		 1389
1390static struct attribute *ds3231_hwmon_attrs[] = {
1391 &sensor_dev_attr_temp1_input.dev_attr.attr,
1392 NULL,
1393};
1394ATTRIBUTE_GROUPS(ds3231_hwmon);
1395
1396static void ds1307_hwmon_register(struct ds1307 *ds1307)
1397{
1398 struct device *dev;
1399
1400 if (ds1307->type != ds_3231)
1401 return;
1402
11e5890b 1403 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
4057a66e
AB		 1404 ds1307,
1405 ds3231_hwmon_groups);
445c0207 1406 if (IS_ERR(dev)) {
11e5890b
HK		 1407 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1408 PTR_ERR(dev));
445c0207
AM		 1409 }
1410}
1411
1412#else
1413
1414static void ds1307_hwmon_register(struct ds1307 *ds1307)
1415{
1416}
1417
6c6ff145
AM		 1418#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1419
1420/*----------------------------------------------------------------------*/
1421
1422/*
1423 * Square-wave output support for DS3231
1424 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1425 */
1426#ifdef CONFIG_COMMON_CLK
1427
1428enum {
1429 DS3231_CLK_SQW = 0,
1430 DS3231_CLK_32KHZ,
1431};
1432
1433#define clk_sqw_to_ds1307(clk) \
1434 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1435#define clk_32khz_to_ds1307(clk) \
1436 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1437
1438static int ds3231_clk_sqw_rates[] = {
1439 1,
1440 1024,
1441 4096,
1442 8192,
1443};
1444
1445static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1446{
6c6ff145 1447 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1448 int ret;
1449
1450 mutex_lock(lock);
078f3f64
HK		 1451 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1452 mask, value);
6c6ff145
AM		 1453 mutex_unlock(lock);
1454
1455 return ret;
1456}
1457
1458static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1459 unsigned long parent_rate)
1460{
1461 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1462 int control, ret;
6c6ff145
AM		 1463 int rate_sel = 0;
1464
11e5890b
HK		 1465 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1466 if (ret)
1467 return ret;
6c6ff145
AM		 1468 if (control & DS1337_BIT_RS1)
1469 rate_sel += 1;
1470 if (control & DS1337_BIT_RS2)
1471 rate_sel += 2;
1472
1473 return ds3231_clk_sqw_rates[rate_sel];
1474}
1475
1476static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
4057a66e 1477 unsigned long *prate)
6c6ff145
AM		 1478{
1479 int i;
1480
1481 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1482 if (ds3231_clk_sqw_rates[i] <= rate)
1483 return ds3231_clk_sqw_rates[i];
1484 }
1485
1486 return 0;
1487}
1488
1489static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
4057a66e 1490 unsigned long parent_rate)
6c6ff145
AM		 1491{
1492 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1493 int control = 0;
1494 int rate_sel;
1495
1496 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1497 rate_sel++) {
1498 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1499 break;
1500 }
1501
1502 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1503 return -EINVAL;
1504
1505 if (rate_sel & 1)
1506 control |= DS1337_BIT_RS1;
1507 if (rate_sel & 2)
1508 control |= DS1337_BIT_RS2;
1509
1510 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1511 control);
1512}
1513
1514static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1515{
1516 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1517
1518 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1519}
1520
1521static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1522{
1523 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1524
1525 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1526}
1527
1528static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1529{
1530 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1531 int control, ret;
6c6ff145 1532
11e5890b
HK		 1533 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1534 if (ret)
1535 return ret;
6c6ff145
AM		 1536
1537 return !(control & DS1337_BIT_INTCN);
1538}
1539
1540static const struct clk_ops ds3231_clk_sqw_ops = {
1541 .prepare = ds3231_clk_sqw_prepare,
1542 .unprepare = ds3231_clk_sqw_unprepare,
1543 .is_prepared = ds3231_clk_sqw_is_prepared,
1544 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1545 .round_rate = ds3231_clk_sqw_round_rate,
1546 .set_rate = ds3231_clk_sqw_set_rate,
1547};
1548
1549static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
4057a66e 1550 unsigned long parent_rate)
6c6ff145
AM		 1551{
1552 return 32768;
1553}
1554
1555static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1556{
6c6ff145 1557 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1558 int ret;
1559
1560 mutex_lock(lock);
078f3f64
HK		 1561 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1562 DS3231_BIT_EN32KHZ,
1563 enable ? DS3231_BIT_EN32KHZ : 0);
6c6ff145
AM		 1564 mutex_unlock(lock);
1565
1566 return ret;
1567}
1568
1569static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1570{
1571 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1572
1573 return ds3231_clk_32khz_control(ds1307, true);
1574}
1575
1576static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1577{
1578 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1579
1580 ds3231_clk_32khz_control(ds1307, false);
1581}
1582
1583static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1584{
1585 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
11e5890b 1586 int status, ret;
6c6ff145 1587
11e5890b
HK		 1588 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1589 if (ret)
1590 return ret;
6c6ff145
AM		 1591
1592 return !!(status & DS3231_BIT_EN32KHZ);
1593}
1594
1595static const struct clk_ops ds3231_clk_32khz_ops = {
1596 .prepare = ds3231_clk_32khz_prepare,
1597 .unprepare = ds3231_clk_32khz_unprepare,
1598 .is_prepared = ds3231_clk_32khz_is_prepared,
1599 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1600};
1601
227ec129
AS		 1602static const char *ds3231_clks_names[] = {
1603 [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1604 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1605};
1606
6c6ff145
AM		 1607static struct clk_init_data ds3231_clks_init[] = {
1608 [DS3231_CLK_SQW] = {
6c6ff145 1609 .ops = &ds3231_clk_sqw_ops,
6c6ff145
AM		 1610 },
1611 [DS3231_CLK_32KHZ] = {
6c6ff145 1612 .ops = &ds3231_clk_32khz_ops,
6c6ff145
AM		 1613 },
1614};
1615
1616static int ds3231_clks_register(struct ds1307 *ds1307)
1617{
11e5890b 1618 struct device_node *node = ds1307->dev->of_node;
6c6ff145
AM		 1619 struct clk_onecell_data *onecell;
1620 int i;
1621
11e5890b 1622 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
6c6ff145
AM		 1623 if (!onecell)
1624 return -ENOMEM;
1625
1626 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
11e5890b
HK		 1627 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1628 sizeof(onecell->clks[0]), GFP_KERNEL);
6c6ff145
AM		 1629 if (!onecell->clks)
1630 return -ENOMEM;
1631
227ec129
AS		 1632 /* optional override of the clockname */
1633 device_property_read_string_array(ds1307->dev, "clock-output-names",
1634 ds3231_clks_names,
1635 ARRAY_SIZE(ds3231_clks_names));
1636
6c6ff145
AM		 1637 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1638 struct clk_init_data init = ds3231_clks_init[i];
1639
1640 /*
1641 * Interrupt signal due to alarm conditions and square-wave
1642 * output share same pin, so don't initialize both.
1643 */
1644 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1645 continue;
1646
227ec129 1647 init.name = ds3231_clks_names[i];
6c6ff145
AM		 1648 ds1307->clks[i].init = &init;
1649
11e5890b
HK		 1650 onecell->clks[i] = devm_clk_register(ds1307->dev,
1651 &ds1307->clks[i]);
6c6ff145
AM		 1652 if (IS_ERR(onecell->clks[i]))
1653 return PTR_ERR(onecell->clks[i]);
1654 }
1655
227ec129
AS		 1656 if (node)
1657 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
6c6ff145
AM		 1658
1659 return 0;
1660}
1661
1662static void ds1307_clks_register(struct ds1307 *ds1307)
1663{
1664 int ret;
1665
1666 if (ds1307->type != ds_3231)
1667 return;
1668
1669 ret = ds3231_clks_register(ds1307);
1670 if (ret) {
11e5890b
HK		 1671 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1672 ret);
6c6ff145
AM		 1673 }
1674}
1675
1676#else
1677
1678static void ds1307_clks_register(struct ds1307 *ds1307)
1679{
1680}
1681
1682#endif /* CONFIG_COMMON_CLK */
445c0207 1683
fd90d48d
CP		 1684#ifdef CONFIG_WATCHDOG_CORE
1685static const struct watchdog_info ds1388_wdt_info = {
1686 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1687 .identity = "DS1388 watchdog",
1688};
1689
1690static const struct watchdog_ops ds1388_wdt_ops = {
1691 .owner = THIS_MODULE,
1692 .start = ds1388_wdt_start,
1693 .stop = ds1388_wdt_stop,
1694 .ping = ds1388_wdt_ping,
1695 .set_timeout = ds1388_wdt_set_timeout,
1696
1697};
1698
1699static void ds1307_wdt_register(struct ds1307 *ds1307)
1700{
1701 struct watchdog_device *wdt;
9bf13062
CP		 1702 int err;
1703 int val;
fd90d48d
CP		 1704
1705 if (ds1307->type != ds_1388)
1706 return;
1707
1708 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1821b79d
CIK		 1709 if (!wdt)
1710 return;
fd90d48d 1711
9bf13062
CP		 1712 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1713 if (!err && val & DS1388_BIT_WF)
1714 wdt->bootstatus = WDIOF_CARDRESET;
1715
fd90d48d
CP		 1716 wdt->info = &ds1388_wdt_info;
1717 wdt->ops = &ds1388_wdt_ops;
1718 wdt->timeout = 99;
1719 wdt->max_timeout = 99;
1720 wdt->min_timeout = 1;
1721
1722 watchdog_init_timeout(wdt, 0, ds1307->dev);
1723 watchdog_set_drvdata(wdt, ds1307);
1724 devm_watchdog_register_device(ds1307->dev, wdt);
1725}
1726#else
1727static void ds1307_wdt_register(struct ds1307 *ds1307)
1728{
1729}
1730#endif /* CONFIG_WATCHDOG_CORE */
1731
11e5890b
HK		 1732static const struct regmap_config regmap_config = {
1733 .reg_bits = 8,
1734 .val_bits = 8,
11e5890b
HK		 1735};
1736
5a167f45
GKH		 1737static int ds1307_probe(struct i2c_client *client,
1738 const struct i2c_device_id *id)
1abb0dc9
DB		 1739{
1740 struct ds1307 *ds1307;
227ec129 1741 const void *match;
1abb0dc9 1742 int err = -ENODEV;
584ce30c 1743 int tmp;
7624df48 1744 const struct chip_desc *chip;
82e2d43f 1745 bool want_irq;
8bc2a407 1746 bool ds1307_can_wakeup_device = false;
042fa8c7 1747 unsigned char regs[8];
01ce893d 1748 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
d8490fd5 1749 u8 trickle_charger_setup = 0;
1abb0dc9 1750
edca66d2 1751 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 1752 if (!ds1307)
c065f35c 1753 return -ENOMEM;
045e0e85 1754
11e5890b
HK		 1755 dev_set_drvdata(&client->dev, ds1307);
1756 ds1307->dev = &client->dev;
1757 ds1307->name = client->name;
11e5890b
HK		 1758
1759 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1760 if (IS_ERR(ds1307->regmap)) {
1761 dev_err(ds1307->dev, "regmap allocation failed\n");
1762 return PTR_ERR(ds1307->regmap);
1763 }
33df2ee1 1764
11e5890b 1765 i2c_set_clientdata(client, ds1307);
7ef6d2c2 1766
227ec129
AS		 1767 match = device_get_match_data(&client->dev);
1768 if (match) {
1769 ds1307->type = (enum ds_type)match;
7ef6d2c2
JMC		 1770 chip = &chips[ds1307->type];
1771 } else if (id) {
9c19b893
TH		 1772 chip = &chips[id->driver_data];
1773 ds1307->type = id->driver_data;
1774 } else {
a3111118 1775 return -ENODEV;
9c19b893 1776 }
33df2ee1 1777
82e2d43f
HK		 1778 want_irq = client->irq > 0 && chip->alarm;
1779
9c19b893 1780 if (!pdata)
d8490fd5 1781 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
9c19b893 1782 else if (pdata->trickle_charger_setup)
d8490fd5 1783 trickle_charger_setup = pdata->trickle_charger_setup;
33b04b7b 1784
d8490fd5 1785 if (trickle_charger_setup && chip->trickle_charger_reg) {
11e5890b
HK		 1786 dev_dbg(ds1307->dev,
1787 "writing trickle charger info 0x%x to 0x%x\n",
d8490fd5 1788 trickle_charger_setup, chip->trickle_charger_reg);
11e5890b 1789 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
d8490fd5 1790 trickle_charger_setup);
33b04b7b 1791 }
eb86c306 1792
8bc2a407
ML		 1793/*
1794 * For devices with no IRQ directly connected to the SoC, the RTC chip
1795 * can be forced as a wakeup source by stating that explicitly in
1796 * the device's .dts file using the "wakeup-source" boolean property.
1797 * If the "wakeup-source" property is set, don't request an IRQ.
1798 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1799 * if supported by the RTC.
1800 */
227ec129 1801 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
78aaa06d 1802 ds1307_can_wakeup_device = true;
8bc2a407 1803
045e0e85
DB		 1804 switch (ds1307->type) {
1805 case ds_1337:
1806 case ds_1339:
0759c886 1807 case ds_1341:
97f902b7 1808 case ds_3231:
be5f59f4 1809 /* get registers that the "rtc" read below won't read... */
11e5890b 1810 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
042fa8c7 1811 regs, 2);
11e5890b
HK		 1812 if (err) {
1813 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1814 goto exit;
1abb0dc9
DB		 1815 }
1816
be5f59f4 1817 /* oscillator off? turn it on, so clock can tick. */
042fa8c7
AB		 1818 if (regs[0] & DS1337_BIT_nEOSC)
1819 regs[0] &= ~DS1337_BIT_nEOSC;
cb49a5e9 1820
40ce972d 1821 /*
8bc2a407
ML		 1822 * Using IRQ or defined as wakeup-source?
1823 * Disable the square wave and both alarms.
97f902b7
WS		 1824 * For some variants, be sure alarms can trigger when we're
1825 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 1826 */
82e2d43f 1827 if (want_irq || ds1307_can_wakeup_device) {
042fa8c7
AB		 1828 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1829 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
cb49a5e9
RG		 1830 }
1831
11e5890b 1832 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
042fa8c7 1833 regs[0]);
be5f59f4
RG		 1834
1835 /* oscillator fault? clear flag, and warn */
042fa8c7 1836 if (regs[1] & DS1337_BIT_OSF) {
11e5890b 1837 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
042fa8c7 1838 regs[1] & ~DS1337_BIT_OSF);
11e5890b 1839 dev_warn(ds1307->dev, "SET TIME!\n");
1abb0dc9 1840 }
045e0e85 1841 break;
a2166858
MF		 1842
1843 case rx_8025:
11e5890b 1844 err = regmap_bulk_read(ds1307->regmap,
042fa8c7 1845 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
11e5890b
HK		 1846 if (err) {
1847 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1848 goto exit;
a2166858
MF		 1849 }
1850
1851 /* oscillator off? turn it on, so clock can tick. */
042fa8c7
AB		 1852 if (!(regs[1] & RX8025_BIT_XST)) {
1853 regs[1] |= RX8025_BIT_XST;
11e5890b
HK		 1854 regmap_write(ds1307->regmap,
1855 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1856 regs[1]);
11e5890b 1857 dev_warn(ds1307->dev,
a2166858
MF		 1858 "oscillator stop detected - SET TIME!\n");
1859 }
1860
042fa8c7
AB		 1861 if (regs[1] & RX8025_BIT_PON) {
1862 regs[1] &= ~RX8025_BIT_PON;
11e5890b
HK		 1863 regmap_write(ds1307->regmap,
1864 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1865 regs[1]);
11e5890b 1866 dev_warn(ds1307->dev, "power-on detected\n");
a2166858
MF		 1867 }
1868
042fa8c7
AB		 1869 if (regs[1] & RX8025_BIT_VDET) {
1870 regs[1] &= ~RX8025_BIT_VDET;
11e5890b
HK		 1871 regmap_write(ds1307->regmap,
1872 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1873 regs[1]);
11e5890b 1874 dev_warn(ds1307->dev, "voltage drop detected\n");
a2166858
MF		 1875 }
1876
1877 /* make sure we are running in 24hour mode */
042fa8c7 1878 if (!(regs[0] & RX8025_BIT_2412)) {
a2166858
MF		 1879 u8 hour;
1880
1881 /* switch to 24 hour mode */
11e5890b
HK		 1882 regmap_write(ds1307->regmap,
1883 RX8025_REG_CTRL1 << 4 | 0x08,
042fa8c7 1884 regs[0] | RX8025_BIT_2412);
11e5890b
HK		 1885
1886 err = regmap_bulk_read(ds1307->regmap,
1887 RX8025_REG_CTRL1 << 4 | 0x08,
042fa8c7 1888 regs, 2);
11e5890b
HK		 1889 if (err) {
1890 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1891 goto exit;
a2166858
MF		 1892 }
1893
1894 /* correct hour */
042fa8c7 1895 hour = bcd2bin(regs[DS1307_REG_HOUR]);
a2166858
MF		 1896 if (hour == 12)
1897 hour = 0;
042fa8c7 1898 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
a2166858
MF		 1899 hour += 12;
1900
11e5890b
HK		 1901 regmap_write(ds1307->regmap,
1902 DS1307_REG_HOUR << 4 | 0x08, hour);
a2166858
MF		 1903 }
1904 break;
59ed0127
CP		 1905 case ds_1388:
1906 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1907 if (err) {
1908 dev_dbg(ds1307->dev, "read error %d\n", err);
1909 goto exit;
1910 }
1911
1912 /* oscillator off? turn it on, so clock can tick. */
1913 if (tmp & DS1388_BIT_nEOSC) {
1914 tmp &= ~DS1388_BIT_nEOSC;
1915 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1916 }
1917 break;
045e0e85
DB		 1918 default:
1919 break;
1920 }
1abb0dc9 1921
1abb0dc9 1922 /* read RTC registers */
042fa8c7
AB		 1923 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1924 sizeof(regs));
11e5890b
HK		 1925 if (err) {
1926 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1927 goto exit;
1abb0dc9
DB		 1928 }
1929
b3a50169
AB		 1930 if (ds1307->type == mcp794xx &&
1931 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1932 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1933 regs[DS1307_REG_WDAY] |
1934 MCP794XX_BIT_VBATEN);
1abb0dc9 1935 }
045e0e85 1936
042fa8c7 1937 tmp = regs[DS1307_REG_HOUR];
c065f35c
DB		 1938 switch (ds1307->type) {
1939 case ds_1340:
8566f70c 1940 case m41t0:
c065f35c 1941 case m41t00:
7e580769 1942 case m41t11:
40ce972d
DA		 1943 /*
1944 * NOTE: ignores century bits; fix before deploying
c065f35c
DB		 1945 * systems that will run through year 2100.
1946 */
1947 break;
a2166858
MF		 1948 case rx_8025:
1949 break;
c065f35c
DB		 1950 default:
1951 if (!(tmp & DS1307_BIT_12HR))
1952 break;
1953
40ce972d
DA		 1954 /*
1955 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB		 1956 * take note...
1957 */
fe20ba70 1958 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB		 1959 if (tmp == 12)
1960 tmp = 0;
042fa8c7 1961 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
c065f35c 1962 tmp += 12;
e553170a 1963 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
11e5890b 1964 bin2bcd(tmp));
1abb0dc9
DB		 1965 }
1966
82e2d43f 1967 if (want_irq || ds1307_can_wakeup_device) {
11e5890b 1968 device_set_wakeup_capable(ds1307->dev, true);
3abb1ada
SG		 1969 set_bit(HAS_ALARM, &ds1307->flags);
1970 }
69b119a6
AB		 1971
1972 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
e69c0567 1973 if (IS_ERR(ds1307->rtc))
4071ea25 1974 return PTR_ERR(ds1307->rtc);
1abb0dc9 1975
82e2d43f 1976 if (ds1307_can_wakeup_device && !want_irq) {
11e5890b
HK		 1977 dev_info(ds1307->dev,
1978 "'wakeup-source' is set, request for an IRQ is disabled!\n");
8bc2a407
ML		 1979 /* We cannot support UIE mode if we do not have an IRQ line */
1980 ds1307->rtc->uie_unsupported = 1;
1981 }
1982
cb49a5e9 1983 if (want_irq) {
45947127
HK		 1984 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1985 chip->irq_handler ?: ds1307_irq,
c5983191 1986 IRQF_SHARED | IRQF_ONESHOT,
4b9e2a0c 1987 ds1307->name, ds1307);
cb49a5e9 1988 if (err) {
4071ea25 1989 client->irq = 0;
11e5890b 1990 device_set_wakeup_capable(ds1307->dev, false);
3abb1ada 1991 clear_bit(HAS_ALARM, &ds1307->flags);
11e5890b 1992 dev_err(ds1307->dev, "unable to request IRQ!\n");
e69c0567 1993 } else {
11e5890b 1994 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
e69c0567 1995 }
cb49a5e9
RG		 1996 }
1997
e9fb7682 1998 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
6a5f2a1f 1999 err = ds1307_add_frequency_test(ds1307);
e9fb7682
AB		 2000 if (err)
2001 return err;
2002
fdcfd854 2003 err = devm_rtc_register_device(ds1307->rtc);
b41c23e1
GB		 2004 if (err)
2005 return err;
2006
9eab0a78 2007 if (chip->nvram_size) {
409baf17
AB		 2008 struct nvmem_config nvmem_cfg = {
2009 .name = "ds1307_nvram",
2010 .word_size = 1,
2011 .stride = 1,
2012 .size = chip->nvram_size,
2013 .reg_read = ds1307_nvram_read,
2014 .reg_write = ds1307_nvram_write,
2015 .priv = ds1307,
2016 };
abc925f7 2017
3a905c2d 2018 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
682d73f6
DB		 2019 }
2020
445c0207 2021 ds1307_hwmon_register(ds1307);
6c6ff145 2022 ds1307_clks_register(ds1307);
fd90d48d 2023 ds1307_wdt_register(ds1307);
445c0207 2024
1abb0dc9
DB		 2025 return 0;
2026
edca66d2 2027exit:
1abb0dc9
DB		 2028 return err;
2029}
2030
1abb0dc9
DB		 2031static struct i2c_driver ds1307_driver = {
2032 .driver = {
c065f35c 2033 .name = "rtc-ds1307",
698fffc2 2034 .of_match_table = ds1307_of_match,
1abb0dc9 2035 },
c065f35c 2036 .probe = ds1307_probe,
3760f736 2037 .id_table = ds1307_id,
1abb0dc9
DB		 2038};
2039
0abc9201 2040module_i2c_driver(ds1307_driver);
1abb0dc9
DB		 2041
2042MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2043MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)