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rtc: ds1307: remove flags
[linux-2.6-block.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1abb0dc9
DB		 2/*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
a2166858 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB		 9 */
10
eac7237f
NM		 11#include <linux/bcd.h>
12#include <linux/i2c.h>
1abb0dc9 13#include <linux/init.h>
698fffc2 14#include <linux/mod_devicetable.h>
eac7237f 15#include <linux/module.h>
227ec129 16#include <linux/property.h>
eac7237f
NM		 17#include <linux/rtc/ds1307.h>
18#include <linux/rtc.h>
1abb0dc9 19#include <linux/slab.h>
1abb0dc9 20#include <linux/string.h>
445c0207
AM		 21#include <linux/hwmon.h>
22#include <linux/hwmon-sysfs.h>
6c6ff145 23#include <linux/clk-provider.h>
11e5890b 24#include <linux/regmap.h>
fd90d48d 25#include <linux/watchdog.h>
1abb0dc9 26
40ce972d
DA		 27/*
28 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB		 29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
1abb0dc9
DB		 32 */
33enum ds_type {
227ec129 34 unknown_ds_type, /* always first and 0 */
045e0e85 35 ds_1307,
300a7735 36 ds_1308,
045e0e85
DB		 37 ds_1337,
38 ds_1338,
39 ds_1339,
40 ds_1340,
0759c886 41 ds_1341,
33df2ee1 42 ds_1388,
97f902b7 43 ds_3231,
8566f70c 44 m41t0,
045e0e85 45 m41t00,
7e580769 46 m41t11,
f4199f85 47 mcp794xx,
a2166858 48 rx_8025,
ee0981be 49 rx_8130,
32d322bc 50 last_ds_type /* always last */
40ce972d 51 /* rs5c372 too? different address... */
1abb0dc9
DB		 52};
53
1abb0dc9
DB		 54/* RTC registers don't differ much, except for the century flag */
55#define DS1307_REG_SECS 0x00 /* 00-59 */
56# define DS1307_BIT_CH 0x80
be5f59f4 57# define DS1340_BIT_nEOSC 0x80
f4199f85 58# define MCP794XX_BIT_ST 0x80
1abb0dc9 59#define DS1307_REG_MIN 0x01 /* 00-59 */
8566f70c 60# define M41T0_BIT_OF 0x80
1abb0dc9 61#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB		 62# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
63# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB		 64# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
65# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
66#define DS1307_REG_WDAY 0x03 /* 01-07 */
f4199f85 67# define MCP794XX_BIT_VBATEN 0x08
1abb0dc9
DB		 68#define DS1307_REG_MDAY 0x04 /* 01-31 */
69#define DS1307_REG_MONTH 0x05 /* 01-12 */
70# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
71#define DS1307_REG_YEAR 0x06 /* 00-99 */
72
40ce972d
DA		 73/*
74 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB		 75 * start at 7, and they differ a LOT. Only control and status matter for
76 * basic RTC date and time functionality; be careful using them.
1abb0dc9 77 */
045e0e85 78#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 79# define DS1307_BIT_OUT 0x80
be5f59f4 80# define DS1338_BIT_OSF 0x20
1abb0dc9
DB		 81# define DS1307_BIT_SQWE 0x10
82# define DS1307_BIT_RS1 0x02
83# define DS1307_BIT_RS0 0x01
84#define DS1337_REG_CONTROL 0x0e
85# define DS1337_BIT_nEOSC 0x80
cb49a5e9 86# define DS1339_BIT_BBSQI 0x20
97f902b7 87# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB		 88# define DS1337_BIT_RS2 0x10
89# define DS1337_BIT_RS1 0x08
90# define DS1337_BIT_INTCN 0x04
91# define DS1337_BIT_A2IE 0x02
92# define DS1337_BIT_A1IE 0x01
045e0e85
DB		 93#define DS1340_REG_CONTROL 0x07
94# define DS1340_BIT_OUT 0x80
95# define DS1340_BIT_FT 0x40
96# define DS1340_BIT_CALIB_SIGN 0x20
97# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG		 98#define DS1340_REG_FLAG 0x09
99# define DS1340_BIT_OSF 0x80
1abb0dc9
DB		 100#define DS1337_REG_STATUS 0x0f
101# define DS1337_BIT_OSF 0x80
6c6ff145 102# define DS3231_BIT_EN32KHZ 0x08
1abb0dc9
DB		 103# define DS1337_BIT_A2I 0x02
104# define DS1337_BIT_A1I 0x01
cb49a5e9 105#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS		 106
107#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 108
a2166858
MF		 109#define RX8025_REG_CTRL1 0x0e
110# define RX8025_BIT_2412 0x20
111#define RX8025_REG_CTRL2 0x0f
112# define RX8025_BIT_PON 0x10
113# define RX8025_BIT_VDET 0x40
114# define RX8025_BIT_XST 0x20
1abb0dc9 115
3ffd4a2f
UKK		 116#define RX8130_REG_ALARM_MIN 0x17
117#define RX8130_REG_ALARM_HOUR 0x18
118#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
119#define RX8130_REG_EXTENSION 0x1c
92cbf12f 120#define RX8130_REG_EXTENSION_WADA BIT(3)
3ffd4a2f
UKK		 121#define RX8130_REG_FLAG 0x1d
122#define RX8130_REG_FLAG_VLF BIT(1)
92cbf12f 123#define RX8130_REG_FLAG_AF BIT(3)
3ffd4a2f 124#define RX8130_REG_CONTROL0 0x1e
92cbf12f 125#define RX8130_REG_CONTROL0_AIE BIT(3)
0026f160
BK		 126#define RX8130_REG_CONTROL1 0x1f
127#define RX8130_REG_CONTROL1_INIEN BIT(4)
128#define RX8130_REG_CONTROL1_CHGEN BIT(5)
92cbf12f
UKK		 129
130#define MCP794XX_REG_CONTROL 0x07
131# define MCP794XX_BIT_ALM0_EN 0x10
132# define MCP794XX_BIT_ALM1_EN 0x20
133#define MCP794XX_REG_ALARM0_BASE 0x0a
134#define MCP794XX_REG_ALARM0_CTRL 0x0d
135#define MCP794XX_REG_ALARM1_BASE 0x11
136#define MCP794XX_REG_ALARM1_CTRL 0x14
137# define MCP794XX_BIT_ALMX_IF BIT(3)
138# define MCP794XX_BIT_ALMX_C0 BIT(4)
139# define MCP794XX_BIT_ALMX_C1 BIT(5)
140# define MCP794XX_BIT_ALMX_C2 BIT(6)
141# define MCP794XX_BIT_ALMX_POL BIT(7)
142# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
143 MCP794XX_BIT_ALMX_C1 | \
144 MCP794XX_BIT_ALMX_C2)
145
79230ff6
GB		 146#define M41TXX_REG_CONTROL 0x07
147# define M41TXX_BIT_OUT BIT(7)
148# define M41TXX_BIT_FT BIT(6)
149# define M41TXX_BIT_CALIB_SIGN BIT(5)
150# define M41TXX_M_CALIBRATION GENMASK(4, 0)
151
fd90d48d
CP		 152#define DS1388_REG_WDOG_HUN_SECS 0x08
153#define DS1388_REG_WDOG_SECS 0x09
df11b323 154#define DS1388_REG_FLAG 0x0b
fd90d48d 155# define DS1388_BIT_WF BIT(6)
df11b323 156# define DS1388_BIT_OSF BIT(7)
fd90d48d
CP		 157#define DS1388_REG_CONTROL 0x0c
158# define DS1388_BIT_RST BIT(0)
159# define DS1388_BIT_WDE BIT(1)
59ed0127 160# define DS1388_BIT_nEOSC BIT(7)
fd90d48d 161
79230ff6
GB		 162/* negative offset step is -2.034ppm */
163#define M41TXX_NEG_OFFSET_STEP_PPB 2034
164/* positive offset step is +4.068ppm */
165#define M41TXX_POS_OFFSET_STEP_PPB 4068
166/* Min and max values supported with 'offset' interface by M41TXX */
167#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
168#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
169
1abb0dc9 170struct ds1307 {
1abb0dc9 171 enum ds_type type;
11e5890b
HK		 172 struct device *dev;
173 struct regmap *regmap;
174 const char *name;
1abb0dc9 175 struct rtc_device *rtc;
6c6ff145
AM		 176#ifdef CONFIG_COMMON_CLK
177 struct clk_hw clks[2];
178#endif
1abb0dc9
DB		 179};
180
045e0e85 181struct chip_desc {
045e0e85 182 unsigned alarm:1;
9eab0a78
AB		 183 u16 nvram_offset;
184 u16 nvram_size;
e553170a 185 u8 offset; /* register's offset */
e48585de
HK		 186 u8 century_reg;
187 u8 century_enable_bit;
188 u8 century_bit;
0b6ee805 189 u8 bbsqi_bit;
45947127 190 irq_handler_t irq_handler;
1efb98ba 191 const struct rtc_class_ops *rtc_ops;
eb86c306 192 u16 trickle_charger_reg;
57ec2d95 193 u8 (*do_trickle_setup)(struct ds1307 *, u32,
11e5890b 194 bool);
1b5b6af7
BK		 195 /* Does the RTC require trickle-resistor-ohms to select the value of
196 * the resistor between Vcc and Vbackup?
197 */
198 bool requires_trickle_resistor;
95a74cbb
BK		 199 /* Some RTC's batteries and supercaps were charged by default, others
200 * allow charging but were not configured previously to do so.
201 * Remember this behavior to stay backwards compatible.
202 */
203 bool charge_default;
045e0e85
DB		 204};
205
d0e3f61b 206static const struct chip_desc chips[last_ds_type];
cb49a5e9 207
1abb0dc9
DB		 208static int ds1307_get_time(struct device *dev, struct rtc_time *t)
209{
210 struct ds1307 *ds1307 = dev_get_drvdata(dev);
11e5890b 211 int tmp, ret;
e48585de 212 const struct chip_desc *chip = &chips[ds1307->type];
042fa8c7 213 u8 regs[7];
1abb0dc9 214
501f9826
UKK		 215 if (ds1307->type == rx_8130) {
216 unsigned int regflag;
217 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
218 if (ret) {
219 dev_err(dev, "%s error %d\n", "read", ret);
220 return ret;
221 }
222
223 if (regflag & RX8130_REG_FLAG_VLF) {
224 dev_warn_once(dev, "oscillator failed, set time!\n");
225 return -EINVAL;
226 }
227 }
228
045e0e85 229 /* read the RTC date and time registers all at once */
042fa8c7
AB		 230 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
231 sizeof(regs));
11e5890b
HK		 232 if (ret) {
233 dev_err(dev, "%s error %d\n", "read", ret);
234 return ret;
1abb0dc9
DB		 235 }
236
042fa8c7 237 dev_dbg(dev, "%s: %7ph\n", "read", regs);
1abb0dc9 238
8566f70c
SA		 239 /* if oscillator fail bit is set, no data can be trusted */
240 if (ds1307->type == m41t0 &&
042fa8c7 241 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
8566f70c
SA		 242 dev_warn_once(dev, "oscillator failed, set time!\n");
243 return -EINVAL;
244 }
245
b3a50169
AB		 246 tmp = regs[DS1307_REG_SECS];
247 switch (ds1307->type) {
248 case ds_1307:
249 case m41t0:
250 case m41t00:
251 case m41t11:
252 if (tmp & DS1307_BIT_CH)
253 return -EINVAL;
254 break;
255 case ds_1308:
256 case ds_1338:
257 if (tmp & DS1307_BIT_CH)
258 return -EINVAL;
259
260 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
261 if (ret)
262 return ret;
263 if (tmp & DS1338_BIT_OSF)
264 return -EINVAL;
265 break;
266 case ds_1340:
267 if (tmp & DS1340_BIT_nEOSC)
268 return -EINVAL;
269
270 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
271 if (ret)
272 return ret;
273 if (tmp & DS1340_BIT_OSF)
274 return -EINVAL;
275 break;
df11b323
CP		 276 case ds_1388:
277 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
278 if (ret)
279 return ret;
280 if (tmp & DS1388_BIT_OSF)
281 return -EINVAL;
282 break;
b3a50169
AB		 283 case mcp794xx:
284 if (!(tmp & MCP794XX_BIT_ST))
285 return -EINVAL;
286
287 break;
288 default:
289 break;
290 }
291
042fa8c7
AB		 292 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
293 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
294 tmp = regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70 295 t->tm_hour = bcd2bin(tmp);
042fa8c7
AB		 296 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
297 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
298 tmp = regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 299 t->tm_mon = bcd2bin(tmp) - 1;
042fa8c7 300 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
1abb0dc9 301
042fa8c7 302 if (regs[chip->century_reg] & chip->century_bit &&
e48585de
HK		 303 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
304 t->tm_year += 100;
50d6c0ea 305
1abb0dc9
DB		 306 dev_dbg(dev, "%s secs=%d, mins=%d, "
307 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
308 "read", t->tm_sec, t->tm_min,
309 t->tm_hour, t->tm_mday,
310 t->tm_mon, t->tm_year, t->tm_wday);
311
22652ba7 312 return 0;
1abb0dc9
DB		 313}
314
315static int ds1307_set_time(struct device *dev, struct rtc_time *t)
316{
317 struct ds1307 *ds1307 = dev_get_drvdata(dev);
e48585de 318 const struct chip_desc *chip = &chips[ds1307->type];
1abb0dc9
DB		 319 int result;
320 int tmp;
042fa8c7 321 u8 regs[7];
1abb0dc9
DB		 322
323 dev_dbg(dev, "%s secs=%d, mins=%d, "
324 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG		 325 "write", t->tm_sec, t->tm_min,
326 t->tm_hour, t->tm_mday,
327 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 328
50d6c0ea
AB		 329 if (t->tm_year < 100)
330 return -EINVAL;
331
e48585de
HK		 332#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
333 if (t->tm_year > (chip->century_bit ? 299 : 199))
334 return -EINVAL;
50d6c0ea 335#else
e48585de 336 if (t->tm_year > 199)
50d6c0ea
AB		 337 return -EINVAL;
338#endif
339
042fa8c7
AB		 340 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
341 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
342 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
343 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
344 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
345 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB		 346
347 /* assume 20YY not 19YY */
348 tmp = t->tm_year - 100;
042fa8c7 349 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 350
e48585de 351 if (chip->century_enable_bit)
042fa8c7 352 regs[chip->century_reg] |= chip->century_enable_bit;
e48585de 353 if (t->tm_year > 199 && chip->century_bit)
042fa8c7 354 regs[chip->century_reg] |= chip->century_bit;
e48585de 355
b3a50169
AB		 356 switch (ds1307->type) {
357 case ds_1308:
358 case ds_1338:
359 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
360 DS1338_BIT_OSF, 0);
361 break;
362 case ds_1340:
363 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
364 DS1340_BIT_OSF, 0);
365 break;
f471b05f
CP		 366 case ds_1388:
367 regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
368 DS1388_BIT_OSF, 0);
369 break;
b3a50169 370 case mcp794xx:
40ce972d
DA		 371 /*
372 * these bits were cleared when preparing the date/time
373 * values and need to be set again before writing the
042fa8c7 374 * regsfer out to the device.
40ce972d 375 */
042fa8c7
AB		 376 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
377 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
b3a50169
AB		 378 break;
379 default:
380 break;
be5f59f4 381 }
1abb0dc9 382
042fa8c7 383 dev_dbg(dev, "%s: %7ph\n", "write", regs);
1abb0dc9 384
042fa8c7
AB		 385 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
386 sizeof(regs));
11e5890b 387 if (result) {
fed40b73
BS		 388 dev_err(dev, "%s error %d\n", "write", result);
389 return result;
1abb0dc9 390 }
501f9826
UKK		 391
392 if (ds1307->type == rx_8130) {
393 /* clear Voltage Loss Flag as data is available now */
394 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
395 ~(u8)RX8130_REG_FLAG_VLF);
396 if (result) {
397 dev_err(dev, "%s error %d\n", "write", result);
398 return result;
399 }
400 }
401
1abb0dc9
DB		 402 return 0;
403}
404
74d88eb2 405static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 406{
11e5890b 407 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9 408 int ret;
042fa8c7 409 u8 regs[9];
cb49a5e9 410
cb49a5e9 411 /* read all ALARM1, ALARM2, and status registers at once */
11e5890b 412 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
042fa8c7 413 regs, sizeof(regs));
11e5890b 414 if (ret) {
cb49a5e9 415 dev_err(dev, "%s error %d\n", "alarm read", ret);
11e5890b 416 return ret;
cb49a5e9
RG		 417 }
418
ff67abd2 419 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
042fa8c7 420 &regs[0], &regs[4], &regs[7]);
cb49a5e9 421
40ce972d
DA		 422 /*
423 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG		 424 * and that all four fields are checked matches
425 */
042fa8c7
AB		 426 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
427 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
428 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
429 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
cb49a5e9
RG		 430
431 /* ... and status */
042fa8c7
AB		 432 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
433 t->pending = !!(regs[8] & DS1337_BIT_A1I);
cb49a5e9
RG		 434
435 dev_dbg(dev, "%s secs=%d, mins=%d, "
436 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
437 "alarm read", t->time.tm_sec, t->time.tm_min,
438 t->time.tm_hour, t->time.tm_mday,
439 t->enabled, t->pending);
440
441 return 0;
442}
443
74d88eb2 444static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 445{
11e5890b 446 struct ds1307 *ds1307 = dev_get_drvdata(dev);
042fa8c7 447 unsigned char regs[9];
cb49a5e9
RG		 448 u8 control, status;
449 int ret;
450
cb49a5e9
RG		 451 dev_dbg(dev, "%s secs=%d, mins=%d, "
452 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
453 "alarm set", t->time.tm_sec, t->time.tm_min,
454 t->time.tm_hour, t->time.tm_mday,
455 t->enabled, t->pending);
456
457 /* read current status of both alarms and the chip */
042fa8c7
AB		 458 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
459 sizeof(regs));
11e5890b 460 if (ret) {
cb49a5e9 461 dev_err(dev, "%s error %d\n", "alarm write", ret);
11e5890b 462 return ret;
cb49a5e9 463 }
042fa8c7
AB		 464 control = regs[7];
465 status = regs[8];
cb49a5e9 466
ff67abd2 467 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
042fa8c7 468 &regs[0], &regs[4], control, status);
cb49a5e9
RG		 469
470 /* set ALARM1, using 24 hour and day-of-month modes */
042fa8c7
AB		 471 regs[0] = bin2bcd(t->time.tm_sec);
472 regs[1] = bin2bcd(t->time.tm_min);
473 regs[2] = bin2bcd(t->time.tm_hour);
474 regs[3] = bin2bcd(t->time.tm_mday);
cb49a5e9
RG		 475
476 /* set ALARM2 to non-garbage */
042fa8c7
AB		 477 regs[4] = 0;
478 regs[5] = 0;
479 regs[6] = 0;
cb49a5e9 480
5919fb97 481 /* disable alarms */
042fa8c7
AB		 482 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
483 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
cb49a5e9 484
042fa8c7
AB		 485 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
486 sizeof(regs));
11e5890b 487 if (ret) {
cb49a5e9 488 dev_err(dev, "can't set alarm time\n");
fed40b73 489 return ret;
cb49a5e9
RG		 490 }
491
5919fb97
NB		 492 /* optionally enable ALARM1 */
493 if (t->enabled) {
494 dev_dbg(dev, "alarm IRQ armed\n");
042fa8c7
AB		 495 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
496 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
5919fb97
NB		 497 }
498
cb49a5e9
RG		 499 return 0;
500}
501
16380c15 502static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9 503{
11e5890b 504 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9 505
078f3f64
HK		 506 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
507 DS1337_BIT_A1IE,
508 enabled ? DS1337_BIT_A1IE : 0);
cb49a5e9
RG		 509}
510
d0e3f61b
UKK		 511static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
512{
513 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
514 DS1307_TRICKLE_CHARGER_NO_DIODE;
682d73f6 515
462eb736
BK		 516 setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
517
d0e3f61b
UKK		 518 switch (ohms) {
519 case 250:
520 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
521 break;
522 case 2000:
523 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
524 break;
525 case 4000:
526 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
527 break;
528 default:
529 dev_warn(ds1307->dev,
530 "Unsupported ohm value %u in dt\n", ohms);
531 return 0;
532 }
533 return setup;
534}
ee0981be 535
0026f160
BK		 536static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
537{
538 /* make sure that the backup battery is enabled */
539 u8 setup = RX8130_REG_CONTROL1_INIEN;
540 if (diode)
541 setup |= RX8130_REG_CONTROL1_CHGEN;
542
543 return setup;
544}
545
ee0981be
MV		 546static irqreturn_t rx8130_irq(int irq, void *dev_id)
547{
548 struct ds1307 *ds1307 = dev_id;
ee0981be
MV		 549 u8 ctl[3];
550 int ret;
551
59238192 552 rtc_lock(ds1307->rtc);
ee0981be
MV		 553
554 /* Read control registers. */
f2b48012
AB		 555 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
556 sizeof(ctl));
ee0981be
MV		 557 if (ret < 0)
558 goto out;
559 if (!(ctl[1] & RX8130_REG_FLAG_AF))
560 goto out;
561 ctl[1] &= ~RX8130_REG_FLAG_AF;
562 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
563
f2b48012
AB		 564 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
565 sizeof(ctl));
ee0981be
MV		 566 if (ret < 0)
567 goto out;
568
569 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
570
571out:
59238192 572 rtc_unlock(ds1307->rtc);
ee0981be
MV		 573
574 return IRQ_HANDLED;
575}
576
577static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
578{
579 struct ds1307 *ds1307 = dev_get_drvdata(dev);
580 u8 ald[3], ctl[3];
581 int ret;
582
ee0981be 583 /* Read alarm registers. */
f2b48012
AB		 584 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
585 sizeof(ald));
ee0981be
MV		 586 if (ret < 0)
587 return ret;
588
589 /* Read control registers. */
f2b48012
AB		 590 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
591 sizeof(ctl));
ee0981be
MV		 592 if (ret < 0)
593 return ret;
594
595 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
596 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
597
598 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
599 t->time.tm_sec = -1;
600 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
601 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
602 t->time.tm_wday = -1;
603 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
604 t->time.tm_mon = -1;
605 t->time.tm_year = -1;
606 t->time.tm_yday = -1;
607 t->time.tm_isdst = -1;
608
609 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
610 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
611 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
612
613 return 0;
614}
615
616static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
617{
618 struct ds1307 *ds1307 = dev_get_drvdata(dev);
619 u8 ald[3], ctl[3];
620 int ret;
621
ee0981be
MV		 622 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
623 "enabled=%d pending=%d\n", __func__,
624 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
625 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
626 t->enabled, t->pending);
627
628 /* Read control registers. */
f2b48012
AB		 629 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
630 sizeof(ctl));
ee0981be
MV		 631 if (ret < 0)
632 return ret;
633
3f929cad
UKK		 634 ctl[0] &= RX8130_REG_EXTENSION_WADA;
635 ctl[1] &= ~RX8130_REG_FLAG_AF;
ee0981be
MV		 636 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
637
f2b48012
AB		 638 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
639 sizeof(ctl));
ee0981be
MV		 640 if (ret < 0)
641 return ret;
642
643 /* Hardware alarm precision is 1 minute! */
644 ald[0] = bin2bcd(t->time.tm_min);
645 ald[1] = bin2bcd(t->time.tm_hour);
646 ald[2] = bin2bcd(t->time.tm_mday);
647
f2b48012
AB		 648 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
649 sizeof(ald));
ee0981be
MV		 650 if (ret < 0)
651 return ret;
652
653 if (!t->enabled)
654 return 0;
655
656 ctl[2] |= RX8130_REG_CONTROL0_AIE;
657
3f929cad 658 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
ee0981be
MV		 659}
660
d0e3f61b
UKK		 661static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
662{
663 struct ds1307 *ds1307 = dev_get_drvdata(dev);
664 int ret, reg;
665
d0e3f61b
UKK		 666 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
667 if (ret < 0)
668 return ret;
669
670 if (enabled)
671 reg |= RX8130_REG_CONTROL0_AIE;
672 else
673 reg &= ~RX8130_REG_CONTROL0_AIE;
674
675 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
676}
677
678static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
679{
680 struct ds1307 *ds1307 = dev_id;
681 struct mutex *lock = &ds1307->rtc->ops_lock;
682 int reg, ret;
683
684 mutex_lock(lock);
685
686 /* Check and clear alarm 0 interrupt flag. */
687 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
688 if (ret)
689 goto out;
690 if (!(reg & MCP794XX_BIT_ALMX_IF))
691 goto out;
692 reg &= ~MCP794XX_BIT_ALMX_IF;
693 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
694 if (ret)
695 goto out;
696
697 /* Disable alarm 0. */
698 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
699 MCP794XX_BIT_ALM0_EN, 0);
700 if (ret)
701 goto out;
702
703 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
704
705out:
706 mutex_unlock(lock);
707
708 return IRQ_HANDLED;
709}
710
711static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
712{
713 struct ds1307 *ds1307 = dev_get_drvdata(dev);
714 u8 regs[10];
715 int ret;
716
d0e3f61b
UKK		 717 /* Read control and alarm 0 registers. */
718 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
719 sizeof(regs));
720 if (ret)
721 return ret;
722
723 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
724
725 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
726 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
727 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
728 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
729 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
730 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
731 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
732 t->time.tm_year = -1;
733 t->time.tm_yday = -1;
734 t->time.tm_isdst = -1;
735
736 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
737 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
738 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
739 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
740 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
741 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
742 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
743
744 return 0;
745}
746
747/*
748 * We may have a random RTC weekday, therefore calculate alarm weekday based
749 * on current weekday we read from the RTC timekeeping regs
750 */
751static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
752{
753 struct rtc_time tm_now;
754 int days_now, days_alarm, ret;
755
756 ret = ds1307_get_time(dev, &tm_now);
757 if (ret)
758 return ret;
759
760 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
761 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
762
763 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
764}
765
766static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
767{
768 struct ds1307 *ds1307 = dev_get_drvdata(dev);
769 unsigned char regs[10];
770 int wday, ret;
771
d0e3f61b
UKK		 772 wday = mcp794xx_alm_weekday(dev, &t->time);
773 if (wday < 0)
774 return wday;
775
776 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
777 "enabled=%d pending=%d\n", __func__,
778 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
779 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
780 t->enabled, t->pending);
781
782 /* Read control and alarm 0 registers. */
783 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
784 sizeof(regs));
785 if (ret)
786 return ret;
787
788 /* Set alarm 0, using 24-hour and day-of-month modes. */
789 regs[3] = bin2bcd(t->time.tm_sec);
790 regs[4] = bin2bcd(t->time.tm_min);
791 regs[5] = bin2bcd(t->time.tm_hour);
792 regs[6] = wday;
793 regs[7] = bin2bcd(t->time.tm_mday);
794 regs[8] = bin2bcd(t->time.tm_mon + 1);
795
796 /* Clear the alarm 0 interrupt flag. */
797 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
798 /* Set alarm match: second, minute, hour, day, date, month. */
799 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
800 /* Disable interrupt. We will not enable until completely programmed */
801 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
802
803 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
804 sizeof(regs));
805 if (ret)
806 return ret;
807
808 if (!t->enabled)
809 return 0;
810 regs[0] |= MCP794XX_BIT_ALM0_EN;
811 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
812}
813
814static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
ee0981be
MV		 815{
816 struct ds1307 *ds1307 = dev_get_drvdata(dev);
ee0981be 817
d0e3f61b
UKK		 818 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
819 MCP794XX_BIT_ALM0_EN,
820 enabled ? MCP794XX_BIT_ALM0_EN : 0);
821}
ee0981be 822
d0e3f61b
UKK		 823static int m41txx_rtc_read_offset(struct device *dev, long *offset)
824{
825 struct ds1307 *ds1307 = dev_get_drvdata(dev);
826 unsigned int ctrl_reg;
827 u8 val;
828
829 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
830
831 val = ctrl_reg & M41TXX_M_CALIBRATION;
832
833 /* check if positive */
834 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
835 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
ee0981be 836 else
d0e3f61b 837 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
ee0981be 838
d0e3f61b
UKK		 839 return 0;
840}
841
842static int m41txx_rtc_set_offset(struct device *dev, long offset)
843{
844 struct ds1307 *ds1307 = dev_get_drvdata(dev);
845 unsigned int ctrl_reg;
846
847 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
848 return -ERANGE;
849
850 if (offset >= 0) {
851 ctrl_reg = DIV_ROUND_CLOSEST(offset,
852 M41TXX_POS_OFFSET_STEP_PPB);
853 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
854 } else {
855 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
856 M41TXX_NEG_OFFSET_STEP_PPB);
857 }
858
859 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
860 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
861 ctrl_reg);
ee0981be
MV		 862}
863
fd90d48d
CP		 864#ifdef CONFIG_WATCHDOG_CORE
865static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
866{
867 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
868 u8 regs[2];
869 int ret;
870
871 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
872 DS1388_BIT_WF, 0);
873 if (ret)
874 return ret;
875
876 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
877 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
878 if (ret)
879 return ret;
880
881 /*
882 * watchdog timeouts are measured in seconds. So ignore hundredths of
883 * seconds field.
884 */
885 regs[0] = 0;
886 regs[1] = bin2bcd(wdt_dev->timeout);
887
888 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
889 sizeof(regs));
890 if (ret)
891 return ret;
892
893 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
894 DS1388_BIT_WDE | DS1388_BIT_RST,
895 DS1388_BIT_WDE | DS1388_BIT_RST);
896}
897
898static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
899{
900 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
901
902 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
903 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
904}
905
906static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
907{
908 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
909 u8 regs[2];
910
911 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
912 sizeof(regs));
913}
914
915static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
916 unsigned int val)
917{
918 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
919 u8 regs[2];
920
921 wdt_dev->timeout = val;
922 regs[0] = 0;
923 regs[1] = bin2bcd(wdt_dev->timeout);
924
925 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
926 sizeof(regs));
927}
928#endif
929
d0e3f61b
UKK		 930static const struct rtc_class_ops rx8130_rtc_ops = {
931 .read_time = ds1307_get_time,
932 .set_time = ds1307_set_time,
933 .read_alarm = rx8130_read_alarm,
934 .set_alarm = rx8130_set_alarm,
935 .alarm_irq_enable = rx8130_alarm_irq_enable,
936};
937
938static const struct rtc_class_ops mcp794xx_rtc_ops = {
939 .read_time = ds1307_get_time,
940 .set_time = ds1307_set_time,
941 .read_alarm = mcp794xx_read_alarm,
942 .set_alarm = mcp794xx_set_alarm,
943 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
944};
945
946static const struct rtc_class_ops m41txx_rtc_ops = {
947 .read_time = ds1307_get_time,
948 .set_time = ds1307_set_time,
949 .read_alarm = ds1337_read_alarm,
950 .set_alarm = ds1337_set_alarm,
951 .alarm_irq_enable = ds1307_alarm_irq_enable,
952 .read_offset = m41txx_rtc_read_offset,
953 .set_offset = m41txx_rtc_set_offset,
954};
955
956static const struct chip_desc chips[last_ds_type] = {
957 [ds_1307] = {
958 .nvram_offset = 8,
959 .nvram_size = 56,
960 },
961 [ds_1308] = {
962 .nvram_offset = 8,
963 .nvram_size = 56,
964 },
965 [ds_1337] = {
966 .alarm = 1,
967 .century_reg = DS1307_REG_MONTH,
968 .century_bit = DS1337_BIT_CENTURY,
969 },
970 [ds_1338] = {
971 .nvram_offset = 8,
972 .nvram_size = 56,
973 },
974 [ds_1339] = {
975 .alarm = 1,
976 .century_reg = DS1307_REG_MONTH,
977 .century_bit = DS1337_BIT_CENTURY,
978 .bbsqi_bit = DS1339_BIT_BBSQI,
979 .trickle_charger_reg = 0x10,
980 .do_trickle_setup = &do_trickle_setup_ds1339,
1b5b6af7 981 .requires_trickle_resistor = true,
95a74cbb 982 .charge_default = true,
d0e3f61b
UKK		 983 },
984 [ds_1340] = {
985 .century_reg = DS1307_REG_HOUR,
986 .century_enable_bit = DS1340_BIT_CENTURY_EN,
987 .century_bit = DS1340_BIT_CENTURY,
988 .do_trickle_setup = &do_trickle_setup_ds1339,
989 .trickle_charger_reg = 0x08,
1b5b6af7 990 .requires_trickle_resistor = true,
95a74cbb 991 .charge_default = true,
d0e3f61b
UKK		 992 },
993 [ds_1341] = {
994 .century_reg = DS1307_REG_MONTH,
995 .century_bit = DS1337_BIT_CENTURY,
996 },
997 [ds_1388] = {
998 .offset = 1,
999 .trickle_charger_reg = 0x0a,
1000 },
1001 [ds_3231] = {
1002 .alarm = 1,
1003 .century_reg = DS1307_REG_MONTH,
1004 .century_bit = DS1337_BIT_CENTURY,
1005 .bbsqi_bit = DS3231_BIT_BBSQW,
1006 },
1007 [rx_8130] = {
1008 .alarm = 1,
1009 /* this is battery backed SRAM */
1010 .nvram_offset = 0x20,
1011 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1012 .offset = 0x10,
1013 .irq_handler = rx8130_irq,
1014 .rtc_ops = &rx8130_rtc_ops,
0026f160
BK		 1015 .trickle_charger_reg = RX8130_REG_CONTROL1,
1016 .do_trickle_setup = &do_trickle_setup_rx8130,
d0e3f61b
UKK		 1017 },
1018 [m41t0] = {
1019 .rtc_ops = &m41txx_rtc_ops,
1020 },
1021 [m41t00] = {
1022 .rtc_ops = &m41txx_rtc_ops,
1023 },
1024 [m41t11] = {
1025 /* this is battery backed SRAM */
1026 .nvram_offset = 8,
1027 .nvram_size = 56,
1028 .rtc_ops = &m41txx_rtc_ops,
1029 },
1030 [mcp794xx] = {
1031 .alarm = 1,
1032 /* this is battery backed SRAM */
1033 .nvram_offset = 0x20,
1034 .nvram_size = 0x40,
1035 .irq_handler = mcp794xx_irq,
1036 .rtc_ops = &mcp794xx_rtc_ops,
1037 },
1038};
1039
1040static const struct i2c_device_id ds1307_id[] = {
1041 { "ds1307", ds_1307 },
1042 { "ds1308", ds_1308 },
1043 { "ds1337", ds_1337 },
1044 { "ds1338", ds_1338 },
1045 { "ds1339", ds_1339 },
1046 { "ds1388", ds_1388 },
1047 { "ds1340", ds_1340 },
1048 { "ds1341", ds_1341 },
1049 { "ds3231", ds_3231 },
1050 { "m41t0", m41t0 },
1051 { "m41t00", m41t00 },
1052 { "m41t11", m41t11 },
1053 { "mcp7940x", mcp794xx },
1054 { "mcp7941x", mcp794xx },
1055 { "pt7c4338", ds_1307 },
1056 { "rx8025", rx_8025 },
1057 { "isl12057", ds_1337 },
1058 { "rx8130", rx_8130 },
1059 { }
1060};
1061MODULE_DEVICE_TABLE(i2c, ds1307_id);
1062
d0e3f61b
UKK		 1063static const struct of_device_id ds1307_of_match[] = {
1064 {
1065 .compatible = "dallas,ds1307",
1066 .data = (void *)ds_1307
1067 },
1068 {
1069 .compatible = "dallas,ds1308",
1070 .data = (void *)ds_1308
1071 },
1072 {
1073 .compatible = "dallas,ds1337",
1074 .data = (void *)ds_1337
1075 },
1076 {
1077 .compatible = "dallas,ds1338",
1078 .data = (void *)ds_1338
1079 },
1080 {
1081 .compatible = "dallas,ds1339",
1082 .data = (void *)ds_1339
1083 },
1084 {
1085 .compatible = "dallas,ds1388",
1086 .data = (void *)ds_1388
1087 },
1088 {
1089 .compatible = "dallas,ds1340",
1090 .data = (void *)ds_1340
1091 },
1092 {
1093 .compatible = "dallas,ds1341",
1094 .data = (void *)ds_1341
1095 },
1096 {
1097 .compatible = "maxim,ds3231",
1098 .data = (void *)ds_3231
1099 },
1100 {
1101 .compatible = "st,m41t0",
1102 .data = (void *)m41t0
1103 },
1104 {
1105 .compatible = "st,m41t00",
1106 .data = (void *)m41t00
1107 },
1108 {
1109 .compatible = "st,m41t11",
1110 .data = (void *)m41t11
1111 },
1112 {
1113 .compatible = "microchip,mcp7940x",
1114 .data = (void *)mcp794xx
1115 },
1116 {
1117 .compatible = "microchip,mcp7941x",
1118 .data = (void *)mcp794xx
1119 },
1120 {
1121 .compatible = "pericom,pt7c4338",
1122 .data = (void *)ds_1307
1123 },
1124 {
1125 .compatible = "epson,rx8025",
1126 .data = (void *)rx_8025
1127 },
1128 {
1129 .compatible = "isil,isl12057",
1130 .data = (void *)ds_1337
1131 },
1132 {
1133 .compatible = "epson,rx8130",
1134 .data = (void *)rx_8130
1135 },
1136 { }
1137};
1138MODULE_DEVICE_TABLE(of, ds1307_of_match);
d0e3f61b 1139
1d1945d2 1140/*
d0e3f61b
UKK		 1141 * The ds1337 and ds1339 both have two alarms, but we only use the first
1142 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1143 * signal; ds1339 chips have only one alarm signal.
1d1945d2 1144 */
d0e3f61b 1145static irqreturn_t ds1307_irq(int irq, void *dev_id)
1d1945d2 1146{
d0e3f61b
UKK		 1147 struct ds1307 *ds1307 = dev_id;
1148 struct mutex *lock = &ds1307->rtc->ops_lock;
1149 int stat, ret;
1d1945d2 1150
2fb07a10 1151 mutex_lock(lock);
d0e3f61b 1152 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
11e5890b 1153 if (ret)
1d1945d2
SG		 1154 goto out;
1155
d0e3f61b
UKK		 1156 if (stat & DS1337_BIT_A1I) {
1157 stat &= ~DS1337_BIT_A1I;
1158 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1d1945d2 1159
d0e3f61b
UKK		 1160 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1161 DS1337_BIT_A1IE, 0);
1162 if (ret)
1163 goto out;
1164
1165 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1166 }
1d1945d2
SG		 1167
1168out:
2fb07a10
FB		 1169 mutex_unlock(lock);
1170
1171 return IRQ_HANDLED;
1d1945d2
SG		 1172}
1173
d0e3f61b 1174/*----------------------------------------------------------------------*/
79230ff6 1175
d0e3f61b
UKK		 1176static const struct rtc_class_ops ds13xx_rtc_ops = {
1177 .read_time = ds1307_get_time,
1178 .set_time = ds1307_set_time,
1179 .read_alarm = ds1337_read_alarm,
1180 .set_alarm = ds1337_set_alarm,
1181 .alarm_irq_enable = ds1307_alarm_irq_enable,
1182};
79230ff6 1183
6a5f2a1f
AB		 1184static ssize_t frequency_test_store(struct device *dev,
1185 struct device_attribute *attr,
1186 const char *buf, size_t count)
b41c23e1 1187{
6a5f2a1f 1188 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
b41c23e1
GB		 1189 bool freq_test_en;
1190 int ret;
1191
1192 ret = kstrtobool(buf, &freq_test_en);
1193 if (ret) {
1194 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1195 return ret;
1196 }
1197
1198 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1199 freq_test_en ? M41TXX_BIT_FT : 0);
1200
1201 return count;
1202}
1203
6a5f2a1f
AB		 1204static ssize_t frequency_test_show(struct device *dev,
1205 struct device_attribute *attr,
1206 char *buf)
b41c23e1 1207{
6a5f2a1f 1208 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
b41c23e1
GB		 1209 unsigned int ctrl_reg;
1210
1211 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1212
1213 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1214 "off\n");
1215}
1216
6a5f2a1f 1217static DEVICE_ATTR_RW(frequency_test);
b41c23e1
GB		 1218
1219static struct attribute *rtc_freq_test_attrs[] = {
6a5f2a1f 1220 &dev_attr_frequency_test.attr,
b41c23e1
GB		 1221 NULL,
1222};
1223
1224static const struct attribute_group rtc_freq_test_attr_group = {
1225 .attrs = rtc_freq_test_attrs,
1226};
1227
b41c23e1
GB		 1228static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1229{
1230 int err;
1231
1232 switch (ds1307->type) {
1233 case m41t0:
1234 case m41t00:
1235 case m41t11:
6a5f2a1f
AB		 1236 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1237 if (err)
b41c23e1 1238 return err;
b41c23e1
GB		 1239 break;
1240 default:
1241 break;
1242 }
1243
1244 return 0;
1245}
1246
1d1945d2
SG		 1247/*----------------------------------------------------------------------*/
1248
abc925f7
AB		 1249static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1250 size_t bytes)
682d73f6 1251{
abc925f7 1252 struct ds1307 *ds1307 = priv;
969fa07b 1253 const struct chip_desc *chip = &chips[ds1307->type];
682d73f6 1254
969fa07b 1255 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
abc925f7 1256 val, bytes);
682d73f6
DB		 1257}
1258
abc925f7
AB		 1259static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1260 size_t bytes)
682d73f6 1261{
abc925f7 1262 struct ds1307 *ds1307 = priv;
969fa07b 1263 const struct chip_desc *chip = &chips[ds1307->type];
682d73f6 1264
969fa07b 1265 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
abc925f7 1266 val, bytes);
682d73f6
DB		 1267}
1268
682d73f6
DB		 1269/*----------------------------------------------------------------------*/
1270
d8490fd5 1271static u8 ds1307_trickle_init(struct ds1307 *ds1307,
7624df48 1272 const struct chip_desc *chip)
33b04b7b 1273{
0874734e 1274 u32 ohms, chargeable;
95a74cbb 1275 bool diode = chip->charge_default;
33b04b7b
MV		 1276
1277 if (!chip->do_trickle_setup)
d8490fd5
HK		 1278 return 0;
1279
11e5890b 1280 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1b5b6af7 1281 &ohms) && chip->requires_trickle_resistor)
d8490fd5
HK		 1282 return 0;
1283
0874734e
BK		 1284 /* aux-voltage-chargeable takes precedence over the deprecated
1285 * trickle-diode-disable
1286 */
1287 if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1288 &chargeable)) {
1289 switch (chargeable) {
1290 case 0:
1291 diode = false;
1292 break;
1293 case 1:
1294 diode = true;
1295 break;
1296 default:
1297 dev_warn(ds1307->dev,
1298 "unsupported aux-voltage-chargeable value\n");
1299 break;
1300 }
1301 } else if (device_property_read_bool(ds1307->dev,
1302 "trickle-diode-disable")) {
33b04b7b 1303 diode = false;
0874734e 1304 }
d8490fd5
HK		 1305
1306 return chip->do_trickle_setup(ds1307, ohms, diode);
33b04b7b
MV		 1307}
1308
445c0207
AM		 1309/*----------------------------------------------------------------------*/
1310
6b583a64 1311#if IS_REACHABLE(CONFIG_HWMON)
445c0207
AM		 1312
1313/*
1314 * Temperature sensor support for ds3231 devices.
1315 */
1316
1317#define DS3231_REG_TEMPERATURE 0x11
1318
1319/*
1320 * A user-initiated temperature conversion is not started by this function,
1321 * so the temperature is updated once every 64 seconds.
1322 */
9a3dce62 1323static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
445c0207
AM		 1324{
1325 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1326 u8 temp_buf[2];
1327 s16 temp;
1328 int ret;
1329
11e5890b
HK		 1330 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1331 temp_buf, sizeof(temp_buf));
1332 if (ret)
445c0207 1333 return ret;
445c0207
AM		 1334 /*
1335 * Temperature is represented as a 10-bit code with a resolution of
1336 * 0.25 degree celsius and encoded in two's complement format.
1337 */
1338 temp = (temp_buf[0] << 8) | temp_buf[1];
1339 temp >>= 6;
1340 *mC = temp * 250;
1341
1342 return 0;
1343}
1344
1345static ssize_t ds3231_hwmon_show_temp(struct device *dev,
4057a66e 1346 struct device_attribute *attr, char *buf)
445c0207
AM		 1347{
1348 int ret;
9a3dce62 1349 s32 temp;
445c0207
AM		 1350
1351 ret = ds3231_hwmon_read_temp(dev, &temp);
1352 if (ret)
1353 return ret;
1354
1355 return sprintf(buf, "%d\n", temp);
1356}
b4be271c 1357static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
4057a66e 1358 NULL, 0);
445c0207
AM		 1359
1360static struct attribute *ds3231_hwmon_attrs[] = {
1361 &sensor_dev_attr_temp1_input.dev_attr.attr,
1362 NULL,
1363};
1364ATTRIBUTE_GROUPS(ds3231_hwmon);
1365
1366static void ds1307_hwmon_register(struct ds1307 *ds1307)
1367{
1368 struct device *dev;
1369
1370 if (ds1307->type != ds_3231)
1371 return;
1372
11e5890b 1373 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
4057a66e
AB		 1374 ds1307,
1375 ds3231_hwmon_groups);
445c0207 1376 if (IS_ERR(dev)) {
11e5890b
HK		 1377 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1378 PTR_ERR(dev));
445c0207
AM		 1379 }
1380}
1381
1382#else
1383
1384static void ds1307_hwmon_register(struct ds1307 *ds1307)
1385{
1386}
1387
6c6ff145
AM		 1388#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1389
1390/*----------------------------------------------------------------------*/
1391
1392/*
1393 * Square-wave output support for DS3231
1394 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1395 */
1396#ifdef CONFIG_COMMON_CLK
1397
1398enum {
1399 DS3231_CLK_SQW = 0,
1400 DS3231_CLK_32KHZ,
1401};
1402
1403#define clk_sqw_to_ds1307(clk) \
1404 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1405#define clk_32khz_to_ds1307(clk) \
1406 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1407
1408static int ds3231_clk_sqw_rates[] = {
1409 1,
1410 1024,
1411 4096,
1412 8192,
1413};
1414
1415static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1416{
6c6ff145 1417 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1418 int ret;
1419
1420 mutex_lock(lock);
078f3f64
HK		 1421 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1422 mask, value);
6c6ff145
AM		 1423 mutex_unlock(lock);
1424
1425 return ret;
1426}
1427
1428static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1429 unsigned long parent_rate)
1430{
1431 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1432 int control, ret;
6c6ff145
AM		 1433 int rate_sel = 0;
1434
11e5890b
HK		 1435 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1436 if (ret)
1437 return ret;
6c6ff145
AM		 1438 if (control & DS1337_BIT_RS1)
1439 rate_sel += 1;
1440 if (control & DS1337_BIT_RS2)
1441 rate_sel += 2;
1442
1443 return ds3231_clk_sqw_rates[rate_sel];
1444}
1445
1446static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
4057a66e 1447 unsigned long *prate)
6c6ff145
AM		 1448{
1449 int i;
1450
1451 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1452 if (ds3231_clk_sqw_rates[i] <= rate)
1453 return ds3231_clk_sqw_rates[i];
1454 }
1455
1456 return 0;
1457}
1458
1459static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
4057a66e 1460 unsigned long parent_rate)
6c6ff145
AM		 1461{
1462 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1463 int control = 0;
1464 int rate_sel;
1465
1466 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1467 rate_sel++) {
1468 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1469 break;
1470 }
1471
1472 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1473 return -EINVAL;
1474
1475 if (rate_sel & 1)
1476 control |= DS1337_BIT_RS1;
1477 if (rate_sel & 2)
1478 control |= DS1337_BIT_RS2;
1479
1480 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1481 control);
1482}
1483
1484static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1485{
1486 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1487
1488 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1489}
1490
1491static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1492{
1493 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1494
1495 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1496}
1497
1498static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1499{
1500 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1501 int control, ret;
6c6ff145 1502
11e5890b
HK		 1503 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1504 if (ret)
1505 return ret;
6c6ff145
AM		 1506
1507 return !(control & DS1337_BIT_INTCN);
1508}
1509
1510static const struct clk_ops ds3231_clk_sqw_ops = {
1511 .prepare = ds3231_clk_sqw_prepare,
1512 .unprepare = ds3231_clk_sqw_unprepare,
1513 .is_prepared = ds3231_clk_sqw_is_prepared,
1514 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1515 .round_rate = ds3231_clk_sqw_round_rate,
1516 .set_rate = ds3231_clk_sqw_set_rate,
1517};
1518
1519static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
4057a66e 1520 unsigned long parent_rate)
6c6ff145
AM		 1521{
1522 return 32768;
1523}
1524
1525static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1526{
6c6ff145 1527 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1528 int ret;
1529
1530 mutex_lock(lock);
078f3f64
HK		 1531 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1532 DS3231_BIT_EN32KHZ,
1533 enable ? DS3231_BIT_EN32KHZ : 0);
6c6ff145
AM		 1534 mutex_unlock(lock);
1535
1536 return ret;
1537}
1538
1539static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1540{
1541 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1542
1543 return ds3231_clk_32khz_control(ds1307, true);
1544}
1545
1546static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1547{
1548 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1549
1550 ds3231_clk_32khz_control(ds1307, false);
1551}
1552
1553static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1554{
1555 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
11e5890b 1556 int status, ret;
6c6ff145 1557
11e5890b
HK		 1558 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1559 if (ret)
1560 return ret;
6c6ff145
AM		 1561
1562 return !!(status & DS3231_BIT_EN32KHZ);
1563}
1564
1565static const struct clk_ops ds3231_clk_32khz_ops = {
1566 .prepare = ds3231_clk_32khz_prepare,
1567 .unprepare = ds3231_clk_32khz_unprepare,
1568 .is_prepared = ds3231_clk_32khz_is_prepared,
1569 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1570};
1571
227ec129
AS		 1572static const char *ds3231_clks_names[] = {
1573 [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1574 [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1575};
1576
6c6ff145
AM		 1577static struct clk_init_data ds3231_clks_init[] = {
1578 [DS3231_CLK_SQW] = {
6c6ff145 1579 .ops = &ds3231_clk_sqw_ops,
6c6ff145
AM		 1580 },
1581 [DS3231_CLK_32KHZ] = {
6c6ff145 1582 .ops = &ds3231_clk_32khz_ops,
6c6ff145
AM		 1583 },
1584};
1585
1586static int ds3231_clks_register(struct ds1307 *ds1307)
1587{
11e5890b 1588 struct device_node *node = ds1307->dev->of_node;
6c6ff145
AM		 1589 struct clk_onecell_data *onecell;
1590 int i;
1591
11e5890b 1592 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
6c6ff145
AM		 1593 if (!onecell)
1594 return -ENOMEM;
1595
1596 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
11e5890b
HK		 1597 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1598 sizeof(onecell->clks[0]), GFP_KERNEL);
6c6ff145
AM		 1599 if (!onecell->clks)
1600 return -ENOMEM;
1601
227ec129
AS		 1602 /* optional override of the clockname */
1603 device_property_read_string_array(ds1307->dev, "clock-output-names",
1604 ds3231_clks_names,
1605 ARRAY_SIZE(ds3231_clks_names));
1606
6c6ff145
AM		 1607 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1608 struct clk_init_data init = ds3231_clks_init[i];
1609
1610 /*
1611 * Interrupt signal due to alarm conditions and square-wave
1612 * output share same pin, so don't initialize both.
1613 */
64e9d8e4 1614 if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features))
6c6ff145
AM		 1615 continue;
1616
227ec129 1617 init.name = ds3231_clks_names[i];
6c6ff145
AM		 1618 ds1307->clks[i].init = &init;
1619
11e5890b
HK		 1620 onecell->clks[i] = devm_clk_register(ds1307->dev,
1621 &ds1307->clks[i]);
6c6ff145
AM		 1622 if (IS_ERR(onecell->clks[i]))
1623 return PTR_ERR(onecell->clks[i]);
1624 }
1625
227ec129
AS		 1626 if (node)
1627 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
6c6ff145
AM		 1628
1629 return 0;
1630}
1631
1632static void ds1307_clks_register(struct ds1307 *ds1307)
1633{
1634 int ret;
1635
1636 if (ds1307->type != ds_3231)
1637 return;
1638
1639 ret = ds3231_clks_register(ds1307);
1640 if (ret) {
11e5890b
HK		 1641 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1642 ret);
6c6ff145
AM		 1643 }
1644}
1645
1646#else
1647
1648static void ds1307_clks_register(struct ds1307 *ds1307)
1649{
1650}
1651
1652#endif /* CONFIG_COMMON_CLK */
445c0207 1653
fd90d48d
CP		 1654#ifdef CONFIG_WATCHDOG_CORE
1655static const struct watchdog_info ds1388_wdt_info = {
1656 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1657 .identity = "DS1388 watchdog",
1658};
1659
1660static const struct watchdog_ops ds1388_wdt_ops = {
1661 .owner = THIS_MODULE,
1662 .start = ds1388_wdt_start,
1663 .stop = ds1388_wdt_stop,
1664 .ping = ds1388_wdt_ping,
1665 .set_timeout = ds1388_wdt_set_timeout,
1666
1667};
1668
1669static void ds1307_wdt_register(struct ds1307 *ds1307)
1670{
1671 struct watchdog_device *wdt;
9bf13062
CP		 1672 int err;
1673 int val;
fd90d48d
CP		 1674
1675 if (ds1307->type != ds_1388)
1676 return;
1677
1678 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1821b79d
CIK		 1679 if (!wdt)
1680 return;
fd90d48d 1681
9bf13062
CP		 1682 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1683 if (!err && val & DS1388_BIT_WF)
1684 wdt->bootstatus = WDIOF_CARDRESET;
1685
fd90d48d
CP		 1686 wdt->info = &ds1388_wdt_info;
1687 wdt->ops = &ds1388_wdt_ops;
1688 wdt->timeout = 99;
1689 wdt->max_timeout = 99;
1690 wdt->min_timeout = 1;
1691
1692 watchdog_init_timeout(wdt, 0, ds1307->dev);
1693 watchdog_set_drvdata(wdt, ds1307);
1694 devm_watchdog_register_device(ds1307->dev, wdt);
1695}
1696#else
1697static void ds1307_wdt_register(struct ds1307 *ds1307)
1698{
1699}
1700#endif /* CONFIG_WATCHDOG_CORE */
1701
11e5890b
HK		 1702static const struct regmap_config regmap_config = {
1703 .reg_bits = 8,
1704 .val_bits = 8,
11e5890b
HK		 1705};
1706
5a167f45
GKH		 1707static int ds1307_probe(struct i2c_client *client,
1708 const struct i2c_device_id *id)
1abb0dc9
DB		 1709{
1710 struct ds1307 *ds1307;
227ec129 1711 const void *match;
1abb0dc9 1712 int err = -ENODEV;
584ce30c 1713 int tmp;
7624df48 1714 const struct chip_desc *chip;
82e2d43f 1715 bool want_irq;
8bc2a407 1716 bool ds1307_can_wakeup_device = false;
042fa8c7 1717 unsigned char regs[8];
01ce893d 1718 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
d8490fd5 1719 u8 trickle_charger_setup = 0;
1abb0dc9 1720
edca66d2 1721 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 1722 if (!ds1307)
c065f35c 1723 return -ENOMEM;
045e0e85 1724
11e5890b
HK		 1725 dev_set_drvdata(&client->dev, ds1307);
1726 ds1307->dev = &client->dev;
1727 ds1307->name = client->name;
11e5890b
HK		 1728
1729 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1730 if (IS_ERR(ds1307->regmap)) {
1731 dev_err(ds1307->dev, "regmap allocation failed\n");
1732 return PTR_ERR(ds1307->regmap);
1733 }
33df2ee1 1734
11e5890b 1735 i2c_set_clientdata(client, ds1307);
7ef6d2c2 1736
227ec129
AS		 1737 match = device_get_match_data(&client->dev);
1738 if (match) {
1739 ds1307->type = (enum ds_type)match;
7ef6d2c2
JMC		 1740 chip = &chips[ds1307->type];
1741 } else if (id) {
9c19b893
TH		 1742 chip = &chips[id->driver_data];
1743 ds1307->type = id->driver_data;
1744 } else {
a3111118 1745 return -ENODEV;
9c19b893 1746 }
33df2ee1 1747
82e2d43f
HK		 1748 want_irq = client->irq > 0 && chip->alarm;
1749
9c19b893 1750 if (!pdata)
d8490fd5 1751 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
9c19b893 1752 else if (pdata->trickle_charger_setup)
d8490fd5 1753 trickle_charger_setup = pdata->trickle_charger_setup;
33b04b7b 1754
d8490fd5 1755 if (trickle_charger_setup && chip->trickle_charger_reg) {
11e5890b
HK		 1756 dev_dbg(ds1307->dev,
1757 "writing trickle charger info 0x%x to 0x%x\n",
d8490fd5 1758 trickle_charger_setup, chip->trickle_charger_reg);
11e5890b 1759 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
d8490fd5 1760 trickle_charger_setup);
33b04b7b 1761 }
eb86c306 1762
8bc2a407
ML		 1763/*
1764 * For devices with no IRQ directly connected to the SoC, the RTC chip
1765 * can be forced as a wakeup source by stating that explicitly in
1766 * the device's .dts file using the "wakeup-source" boolean property.
1767 * If the "wakeup-source" property is set, don't request an IRQ.
1768 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1769 * if supported by the RTC.
1770 */
227ec129 1771 if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
78aaa06d 1772 ds1307_can_wakeup_device = true;
8bc2a407 1773
045e0e85
DB		 1774 switch (ds1307->type) {
1775 case ds_1337:
1776 case ds_1339:
0759c886 1777 case ds_1341:
97f902b7 1778 case ds_3231:
be5f59f4 1779 /* get registers that the "rtc" read below won't read... */
11e5890b 1780 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
042fa8c7 1781 regs, 2);
11e5890b
HK		 1782 if (err) {
1783 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1784 goto exit;
1abb0dc9
DB		 1785 }
1786
be5f59f4 1787 /* oscillator off? turn it on, so clock can tick. */
042fa8c7
AB		 1788 if (regs[0] & DS1337_BIT_nEOSC)
1789 regs[0] &= ~DS1337_BIT_nEOSC;
cb49a5e9 1790
40ce972d 1791 /*
8bc2a407
ML		 1792 * Using IRQ or defined as wakeup-source?
1793 * Disable the square wave and both alarms.
97f902b7
WS		 1794 * For some variants, be sure alarms can trigger when we're
1795 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 1796 */
82e2d43f 1797 if (want_irq || ds1307_can_wakeup_device) {
042fa8c7
AB		 1798 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1799 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
cb49a5e9
RG		 1800 }
1801
11e5890b 1802 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
042fa8c7 1803 regs[0]);
be5f59f4
RG		 1804
1805 /* oscillator fault? clear flag, and warn */
042fa8c7 1806 if (regs[1] & DS1337_BIT_OSF) {
11e5890b 1807 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
042fa8c7 1808 regs[1] & ~DS1337_BIT_OSF);
11e5890b 1809 dev_warn(ds1307->dev, "SET TIME!\n");
1abb0dc9 1810 }
045e0e85 1811 break;
a2166858
MF		 1812
1813 case rx_8025:
11e5890b 1814 err = regmap_bulk_read(ds1307->regmap,
042fa8c7 1815 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
11e5890b
HK		 1816 if (err) {
1817 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1818 goto exit;
a2166858
MF		 1819 }
1820
1821 /* oscillator off? turn it on, so clock can tick. */
042fa8c7
AB		 1822 if (!(regs[1] & RX8025_BIT_XST)) {
1823 regs[1] |= RX8025_BIT_XST;
11e5890b
HK		 1824 regmap_write(ds1307->regmap,
1825 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1826 regs[1]);
11e5890b 1827 dev_warn(ds1307->dev,
a2166858
MF		 1828 "oscillator stop detected - SET TIME!\n");
1829 }
1830
042fa8c7
AB		 1831 if (regs[1] & RX8025_BIT_PON) {
1832 regs[1] &= ~RX8025_BIT_PON;
11e5890b
HK		 1833 regmap_write(ds1307->regmap,
1834 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1835 regs[1]);
11e5890b 1836 dev_warn(ds1307->dev, "power-on detected\n");
a2166858
MF		 1837 }
1838
042fa8c7
AB		 1839 if (regs[1] & RX8025_BIT_VDET) {
1840 regs[1] &= ~RX8025_BIT_VDET;
11e5890b
HK		 1841 regmap_write(ds1307->regmap,
1842 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1843 regs[1]);
11e5890b 1844 dev_warn(ds1307->dev, "voltage drop detected\n");
a2166858
MF		 1845 }
1846
1847 /* make sure we are running in 24hour mode */
042fa8c7 1848 if (!(regs[0] & RX8025_BIT_2412)) {
a2166858
MF		 1849 u8 hour;
1850
1851 /* switch to 24 hour mode */
11e5890b
HK		 1852 regmap_write(ds1307->regmap,
1853 RX8025_REG_CTRL1 << 4 | 0x08,
042fa8c7 1854 regs[0] | RX8025_BIT_2412);
11e5890b
HK		 1855
1856 err = regmap_bulk_read(ds1307->regmap,
1857 RX8025_REG_CTRL1 << 4 | 0x08,
042fa8c7 1858 regs, 2);
11e5890b
HK		 1859 if (err) {
1860 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1861 goto exit;
a2166858
MF		 1862 }
1863
1864 /* correct hour */
042fa8c7 1865 hour = bcd2bin(regs[DS1307_REG_HOUR]);
a2166858
MF		 1866 if (hour == 12)
1867 hour = 0;
042fa8c7 1868 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
a2166858
MF		 1869 hour += 12;
1870
11e5890b
HK		 1871 regmap_write(ds1307->regmap,
1872 DS1307_REG_HOUR << 4 | 0x08, hour);
a2166858
MF		 1873 }
1874 break;
59ed0127
CP		 1875 case ds_1388:
1876 err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1877 if (err) {
1878 dev_dbg(ds1307->dev, "read error %d\n", err);
1879 goto exit;
1880 }
1881
1882 /* oscillator off? turn it on, so clock can tick. */
1883 if (tmp & DS1388_BIT_nEOSC) {
1884 tmp &= ~DS1388_BIT_nEOSC;
1885 regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1886 }
1887 break;
045e0e85
DB		 1888 default:
1889 break;
1890 }
1abb0dc9 1891
1abb0dc9 1892 /* read RTC registers */
042fa8c7
AB		 1893 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1894 sizeof(regs));
11e5890b
HK		 1895 if (err) {
1896 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1897 goto exit;
1abb0dc9
DB		 1898 }
1899
b3a50169
AB		 1900 if (ds1307->type == mcp794xx &&
1901 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1902 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1903 regs[DS1307_REG_WDAY] |
1904 MCP794XX_BIT_VBATEN);
1abb0dc9 1905 }
045e0e85 1906
042fa8c7 1907 tmp = regs[DS1307_REG_HOUR];
c065f35c
DB		 1908 switch (ds1307->type) {
1909 case ds_1340:
8566f70c 1910 case m41t0:
c065f35c 1911 case m41t00:
7e580769 1912 case m41t11:
40ce972d
DA		 1913 /*
1914 * NOTE: ignores century bits; fix before deploying
c065f35c
DB		 1915 * systems that will run through year 2100.
1916 */
1917 break;
a2166858
MF		 1918 case rx_8025:
1919 break;
c065f35c
DB		 1920 default:
1921 if (!(tmp & DS1307_BIT_12HR))
1922 break;
1923
40ce972d
DA		 1924 /*
1925 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB		 1926 * take note...
1927 */
fe20ba70 1928 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB		 1929 if (tmp == 12)
1930 tmp = 0;
042fa8c7 1931 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
c065f35c 1932 tmp += 12;
e553170a 1933 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
11e5890b 1934 bin2bcd(tmp));
1abb0dc9
DB		 1935 }
1936
69b119a6 1937 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
e69c0567 1938 if (IS_ERR(ds1307->rtc))
4071ea25 1939 return PTR_ERR(ds1307->rtc);
1abb0dc9 1940
64e9d8e4
AB		 1941 if (want_irq || ds1307_can_wakeup_device)
1942 device_set_wakeup_capable(ds1307->dev, true);
1943 else
1944 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
1945
82e2d43f 1946 if (ds1307_can_wakeup_device && !want_irq) {
11e5890b
HK		 1947 dev_info(ds1307->dev,
1948 "'wakeup-source' is set, request for an IRQ is disabled!\n");
8bc2a407
ML		 1949 /* We cannot support UIE mode if we do not have an IRQ line */
1950 ds1307->rtc->uie_unsupported = 1;
1951 }
1952
cb49a5e9 1953 if (want_irq) {
45947127
HK		 1954 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1955 chip->irq_handler ?: ds1307_irq,
c5983191 1956 IRQF_SHARED | IRQF_ONESHOT,
4b9e2a0c 1957 ds1307->name, ds1307);
cb49a5e9 1958 if (err) {
4071ea25 1959 client->irq = 0;
11e5890b 1960 device_set_wakeup_capable(ds1307->dev, false);
64e9d8e4 1961 clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
11e5890b 1962 dev_err(ds1307->dev, "unable to request IRQ!\n");
e69c0567 1963 } else {
11e5890b 1964 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
e69c0567 1965 }
cb49a5e9
RG		 1966 }
1967
e9fb7682 1968 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
6a5f2a1f 1969 err = ds1307_add_frequency_test(ds1307);
e9fb7682
AB		 1970 if (err)
1971 return err;
1972
fdcfd854 1973 err = devm_rtc_register_device(ds1307->rtc);
b41c23e1
GB		 1974 if (err)
1975 return err;
1976
9eab0a78 1977 if (chip->nvram_size) {
409baf17
AB		 1978 struct nvmem_config nvmem_cfg = {
1979 .name = "ds1307_nvram",
1980 .word_size = 1,
1981 .stride = 1,
1982 .size = chip->nvram_size,
1983 .reg_read = ds1307_nvram_read,
1984 .reg_write = ds1307_nvram_write,
1985 .priv = ds1307,
1986 };
abc925f7 1987
3a905c2d 1988 devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
682d73f6
DB		 1989 }
1990
445c0207 1991 ds1307_hwmon_register(ds1307);
6c6ff145 1992 ds1307_clks_register(ds1307);
fd90d48d 1993 ds1307_wdt_register(ds1307);
445c0207 1994
1abb0dc9
DB		 1995 return 0;
1996
edca66d2 1997exit:
1abb0dc9
DB		 1998 return err;
1999}
2000
1abb0dc9
DB		 2001static struct i2c_driver ds1307_driver = {
2002 .driver = {
c065f35c 2003 .name = "rtc-ds1307",
698fffc2 2004 .of_match_table = ds1307_of_match,
1abb0dc9 2005 },
c065f35c 2006 .probe = ds1307_probe,
3760f736 2007 .id_table = ds1307_id,
1abb0dc9
DB		 2008};
2009
0abc9201 2010module_i2c_driver(ds1307_driver);
1abb0dc9
DB		 2011
2012MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2013MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)