Commit | Line | Data |
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1abb0dc9 DB |
1 | /* |
2 | * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. | |
3 | * | |
4 | * Copyright (C) 2005 James Chapman (ds1337 core) | |
5 | * Copyright (C) 2006 David Brownell | |
a2166858 | 6 | * Copyright (C) 2009 Matthias Fuchs (rx8025 support) |
1abb0dc9 DB |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/i2c.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/rtc.h> | |
19 | #include <linux/bcd.h> | |
20 | ||
21 | ||
22 | ||
23 | /* We can't determine type by probing, but if we expect pre-Linux code | |
24 | * to have set the chip up as a clock (turning on the oscillator and | |
25 | * setting the date and time), Linux can ignore the non-clock features. | |
26 | * That's a natural job for a factory or repair bench. | |
1abb0dc9 DB |
27 | */ |
28 | enum ds_type { | |
045e0e85 DB |
29 | ds_1307, |
30 | ds_1337, | |
31 | ds_1338, | |
32 | ds_1339, | |
33 | ds_1340, | |
33df2ee1 | 34 | ds_1388, |
97f902b7 | 35 | ds_3231, |
045e0e85 | 36 | m41t00, |
a2166858 | 37 | rx_8025, |
1abb0dc9 DB |
38 | // rs5c372 too? different address... |
39 | }; | |
40 | ||
1abb0dc9 DB |
41 | |
42 | /* RTC registers don't differ much, except for the century flag */ | |
43 | #define DS1307_REG_SECS 0x00 /* 00-59 */ | |
44 | # define DS1307_BIT_CH 0x80 | |
be5f59f4 | 45 | # define DS1340_BIT_nEOSC 0x80 |
1abb0dc9 DB |
46 | #define DS1307_REG_MIN 0x01 /* 00-59 */ |
47 | #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ | |
c065f35c DB |
48 | # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ |
49 | # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ | |
1abb0dc9 DB |
50 | # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ |
51 | # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ | |
52 | #define DS1307_REG_WDAY 0x03 /* 01-07 */ | |
53 | #define DS1307_REG_MDAY 0x04 /* 01-31 */ | |
54 | #define DS1307_REG_MONTH 0x05 /* 01-12 */ | |
55 | # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ | |
56 | #define DS1307_REG_YEAR 0x06 /* 00-99 */ | |
57 | ||
58 | /* Other registers (control, status, alarms, trickle charge, NVRAM, etc) | |
045e0e85 DB |
59 | * start at 7, and they differ a LOT. Only control and status matter for |
60 | * basic RTC date and time functionality; be careful using them. | |
1abb0dc9 | 61 | */ |
045e0e85 | 62 | #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ |
1abb0dc9 | 63 | # define DS1307_BIT_OUT 0x80 |
be5f59f4 | 64 | # define DS1338_BIT_OSF 0x20 |
1abb0dc9 DB |
65 | # define DS1307_BIT_SQWE 0x10 |
66 | # define DS1307_BIT_RS1 0x02 | |
67 | # define DS1307_BIT_RS0 0x01 | |
68 | #define DS1337_REG_CONTROL 0x0e | |
69 | # define DS1337_BIT_nEOSC 0x80 | |
cb49a5e9 | 70 | # define DS1339_BIT_BBSQI 0x20 |
97f902b7 | 71 | # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ |
1abb0dc9 DB |
72 | # define DS1337_BIT_RS2 0x10 |
73 | # define DS1337_BIT_RS1 0x08 | |
74 | # define DS1337_BIT_INTCN 0x04 | |
75 | # define DS1337_BIT_A2IE 0x02 | |
76 | # define DS1337_BIT_A1IE 0x01 | |
045e0e85 DB |
77 | #define DS1340_REG_CONTROL 0x07 |
78 | # define DS1340_BIT_OUT 0x80 | |
79 | # define DS1340_BIT_FT 0x40 | |
80 | # define DS1340_BIT_CALIB_SIGN 0x20 | |
81 | # define DS1340_M_CALIBRATION 0x1f | |
be5f59f4 RG |
82 | #define DS1340_REG_FLAG 0x09 |
83 | # define DS1340_BIT_OSF 0x80 | |
1abb0dc9 DB |
84 | #define DS1337_REG_STATUS 0x0f |
85 | # define DS1337_BIT_OSF 0x80 | |
86 | # define DS1337_BIT_A2I 0x02 | |
87 | # define DS1337_BIT_A1I 0x01 | |
cb49a5e9 | 88 | #define DS1339_REG_ALARM1_SECS 0x07 |
1abb0dc9 DB |
89 | #define DS1339_REG_TRICKLE 0x10 |
90 | ||
a2166858 MF |
91 | #define RX8025_REG_CTRL1 0x0e |
92 | # define RX8025_BIT_2412 0x20 | |
93 | #define RX8025_REG_CTRL2 0x0f | |
94 | # define RX8025_BIT_PON 0x10 | |
95 | # define RX8025_BIT_VDET 0x40 | |
96 | # define RX8025_BIT_XST 0x20 | |
1abb0dc9 DB |
97 | |
98 | ||
99 | struct ds1307 { | |
33df2ee1 | 100 | u8 offset; /* register's offset */ |
cb49a5e9 | 101 | u8 regs[11]; |
1abb0dc9 | 102 | enum ds_type type; |
cb49a5e9 RG |
103 | unsigned long flags; |
104 | #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ | |
105 | #define HAS_ALARM 1 /* bit 1 == irq claimed */ | |
045e0e85 | 106 | struct i2c_client *client; |
1abb0dc9 | 107 | struct rtc_device *rtc; |
cb49a5e9 | 108 | struct work_struct work; |
30e7b039 ES |
109 | s32 (*read_block_data)(struct i2c_client *client, u8 command, |
110 | u8 length, u8 *values); | |
111 | s32 (*write_block_data)(struct i2c_client *client, u8 command, | |
112 | u8 length, const u8 *values); | |
1abb0dc9 DB |
113 | }; |
114 | ||
045e0e85 | 115 | struct chip_desc { |
045e0e85 DB |
116 | unsigned nvram56:1; |
117 | unsigned alarm:1; | |
045e0e85 DB |
118 | }; |
119 | ||
3760f736 JD |
120 | static const struct chip_desc chips[] = { |
121 | [ds_1307] = { | |
045e0e85 | 122 | .nvram56 = 1, |
3760f736 JD |
123 | }, |
124 | [ds_1337] = { | |
045e0e85 | 125 | .alarm = 1, |
3760f736 JD |
126 | }, |
127 | [ds_1338] = { | |
045e0e85 | 128 | .nvram56 = 1, |
3760f736 JD |
129 | }, |
130 | [ds_1339] = { | |
045e0e85 | 131 | .alarm = 1, |
3760f736 JD |
132 | }, |
133 | [ds_1340] = { | |
134 | }, | |
97f902b7 WS |
135 | [ds_3231] = { |
136 | .alarm = 1, | |
137 | }, | |
3760f736 | 138 | [m41t00] = { |
a2166858 MF |
139 | }, |
140 | [rx_8025] = { | |
045e0e85 DB |
141 | }, }; |
142 | ||
3760f736 JD |
143 | static const struct i2c_device_id ds1307_id[] = { |
144 | { "ds1307", ds_1307 }, | |
145 | { "ds1337", ds_1337 }, | |
146 | { "ds1338", ds_1338 }, | |
147 | { "ds1339", ds_1339 }, | |
33df2ee1 | 148 | { "ds1388", ds_1388 }, |
3760f736 | 149 | { "ds1340", ds_1340 }, |
97f902b7 | 150 | { "ds3231", ds_3231 }, |
3760f736 | 151 | { "m41t00", m41t00 }, |
a2166858 | 152 | { "rx8025", rx_8025 }, |
3760f736 JD |
153 | { } |
154 | }; | |
155 | MODULE_DEVICE_TABLE(i2c, ds1307_id); | |
1abb0dc9 | 156 | |
cb49a5e9 RG |
157 | /*----------------------------------------------------------------------*/ |
158 | ||
30e7b039 ES |
159 | #define BLOCK_DATA_MAX_TRIES 10 |
160 | ||
161 | static s32 ds1307_read_block_data_once(struct i2c_client *client, u8 command, | |
162 | u8 length, u8 *values) | |
163 | { | |
164 | s32 i, data; | |
165 | ||
166 | for (i = 0; i < length; i++) { | |
167 | data = i2c_smbus_read_byte_data(client, command + i); | |
168 | if (data < 0) | |
169 | return data; | |
170 | values[i] = data; | |
171 | } | |
172 | return i; | |
173 | } | |
174 | ||
175 | static s32 ds1307_read_block_data(struct i2c_client *client, u8 command, | |
176 | u8 length, u8 *values) | |
177 | { | |
178 | u8 oldvalues[I2C_SMBUS_BLOCK_MAX]; | |
179 | s32 ret; | |
180 | int tries = 0; | |
181 | ||
182 | dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length); | |
183 | ret = ds1307_read_block_data_once(client, command, length, values); | |
184 | if (ret < 0) | |
185 | return ret; | |
186 | do { | |
187 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
188 | dev_err(&client->dev, | |
189 | "ds1307_read_block_data failed\n"); | |
190 | return -EIO; | |
191 | } | |
192 | memcpy(oldvalues, values, length); | |
193 | ret = ds1307_read_block_data_once(client, command, length, | |
194 | values); | |
195 | if (ret < 0) | |
196 | return ret; | |
197 | } while (memcmp(oldvalues, values, length)); | |
198 | return length; | |
199 | } | |
200 | ||
201 | static s32 ds1307_write_block_data(struct i2c_client *client, u8 command, | |
202 | u8 length, const u8 *values) | |
203 | { | |
204 | u8 currvalues[I2C_SMBUS_BLOCK_MAX]; | |
205 | int tries = 0; | |
206 | ||
207 | dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length); | |
208 | do { | |
209 | s32 i, ret; | |
210 | ||
211 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
212 | dev_err(&client->dev, | |
213 | "ds1307_write_block_data failed\n"); | |
214 | return -EIO; | |
215 | } | |
216 | for (i = 0; i < length; i++) { | |
217 | ret = i2c_smbus_write_byte_data(client, command + i, | |
218 | values[i]); | |
219 | if (ret < 0) | |
220 | return ret; | |
221 | } | |
222 | ret = ds1307_read_block_data_once(client, command, length, | |
223 | currvalues); | |
224 | if (ret < 0) | |
225 | return ret; | |
226 | } while (memcmp(currvalues, values, length)); | |
227 | return length; | |
228 | } | |
229 | ||
230 | /*----------------------------------------------------------------------*/ | |
231 | ||
cb49a5e9 RG |
232 | /* |
233 | * The IRQ logic includes a "real" handler running in IRQ context just | |
234 | * long enough to schedule this workqueue entry. We need a task context | |
235 | * to talk to the RTC, since I2C I/O calls require that; and disable the | |
236 | * IRQ until we clear its status on the chip, so that this handler can | |
237 | * work with any type of triggering (not just falling edge). | |
238 | * | |
239 | * The ds1337 and ds1339 both have two alarms, but we only use the first | |
240 | * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm | |
241 | * signal; ds1339 chips have only one alarm signal. | |
242 | */ | |
243 | static void ds1307_work(struct work_struct *work) | |
244 | { | |
245 | struct ds1307 *ds1307; | |
246 | struct i2c_client *client; | |
247 | struct mutex *lock; | |
248 | int stat, control; | |
249 | ||
250 | ds1307 = container_of(work, struct ds1307, work); | |
251 | client = ds1307->client; | |
252 | lock = &ds1307->rtc->ops_lock; | |
253 | ||
254 | mutex_lock(lock); | |
255 | stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS); | |
256 | if (stat < 0) | |
257 | goto out; | |
258 | ||
259 | if (stat & DS1337_BIT_A1I) { | |
260 | stat &= ~DS1337_BIT_A1I; | |
261 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat); | |
262 | ||
263 | control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); | |
264 | if (control < 0) | |
265 | goto out; | |
266 | ||
267 | control &= ~DS1337_BIT_A1IE; | |
268 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control); | |
269 | ||
cb49a5e9 | 270 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); |
cb49a5e9 RG |
271 | } |
272 | ||
273 | out: | |
274 | if (test_bit(HAS_ALARM, &ds1307->flags)) | |
275 | enable_irq(client->irq); | |
276 | mutex_unlock(lock); | |
277 | } | |
278 | ||
279 | static irqreturn_t ds1307_irq(int irq, void *dev_id) | |
280 | { | |
281 | struct i2c_client *client = dev_id; | |
282 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
283 | ||
284 | disable_irq_nosync(irq); | |
285 | schedule_work(&ds1307->work); | |
286 | return IRQ_HANDLED; | |
287 | } | |
288 | ||
289 | /*----------------------------------------------------------------------*/ | |
290 | ||
1abb0dc9 DB |
291 | static int ds1307_get_time(struct device *dev, struct rtc_time *t) |
292 | { | |
293 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
294 | int tmp; | |
295 | ||
045e0e85 | 296 | /* read the RTC date and time registers all at once */ |
30e7b039 | 297 | tmp = ds1307->read_block_data(ds1307->client, |
33df2ee1 | 298 | ds1307->offset, 7, ds1307->regs); |
fed40b73 | 299 | if (tmp != 7) { |
1abb0dc9 DB |
300 | dev_err(dev, "%s error %d\n", "read", tmp); |
301 | return -EIO; | |
302 | } | |
303 | ||
304 | dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n", | |
305 | "read", | |
306 | ds1307->regs[0], ds1307->regs[1], | |
307 | ds1307->regs[2], ds1307->regs[3], | |
308 | ds1307->regs[4], ds1307->regs[5], | |
309 | ds1307->regs[6]); | |
310 | ||
fe20ba70 AB |
311 | t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f); |
312 | t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f); | |
1abb0dc9 | 313 | tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f; |
fe20ba70 AB |
314 | t->tm_hour = bcd2bin(tmp); |
315 | t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1; | |
316 | t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f); | |
1abb0dc9 | 317 | tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f; |
fe20ba70 | 318 | t->tm_mon = bcd2bin(tmp) - 1; |
1abb0dc9 DB |
319 | |
320 | /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */ | |
fe20ba70 | 321 | t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100; |
1abb0dc9 DB |
322 | |
323 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
324 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
325 | "read", t->tm_sec, t->tm_min, | |
326 | t->tm_hour, t->tm_mday, | |
327 | t->tm_mon, t->tm_year, t->tm_wday); | |
328 | ||
045e0e85 DB |
329 | /* initial clock setting can be undefined */ |
330 | return rtc_valid_tm(t); | |
1abb0dc9 DB |
331 | } |
332 | ||
333 | static int ds1307_set_time(struct device *dev, struct rtc_time *t) | |
334 | { | |
335 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
336 | int result; | |
337 | int tmp; | |
338 | u8 *buf = ds1307->regs; | |
339 | ||
340 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
341 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
11966adc JG |
342 | "write", t->tm_sec, t->tm_min, |
343 | t->tm_hour, t->tm_mday, | |
344 | t->tm_mon, t->tm_year, t->tm_wday); | |
1abb0dc9 | 345 | |
fe20ba70 AB |
346 | buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec); |
347 | buf[DS1307_REG_MIN] = bin2bcd(t->tm_min); | |
348 | buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); | |
349 | buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); | |
350 | buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); | |
351 | buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); | |
1abb0dc9 DB |
352 | |
353 | /* assume 20YY not 19YY */ | |
354 | tmp = t->tm_year - 100; | |
fe20ba70 | 355 | buf[DS1307_REG_YEAR] = bin2bcd(tmp); |
1abb0dc9 | 356 | |
be5f59f4 RG |
357 | switch (ds1307->type) { |
358 | case ds_1337: | |
359 | case ds_1339: | |
97f902b7 | 360 | case ds_3231: |
1abb0dc9 | 361 | buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY; |
be5f59f4 RG |
362 | break; |
363 | case ds_1340: | |
1abb0dc9 DB |
364 | buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN |
365 | | DS1340_BIT_CENTURY; | |
be5f59f4 RG |
366 | break; |
367 | default: | |
368 | break; | |
369 | } | |
1abb0dc9 | 370 | |
1abb0dc9 DB |
371 | dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n", |
372 | "write", buf[0], buf[1], buf[2], buf[3], | |
373 | buf[4], buf[5], buf[6]); | |
374 | ||
33df2ee1 JT |
375 | result = ds1307->write_block_data(ds1307->client, |
376 | ds1307->offset, 7, buf); | |
fed40b73 BS |
377 | if (result < 0) { |
378 | dev_err(dev, "%s error %d\n", "write", result); | |
379 | return result; | |
1abb0dc9 DB |
380 | } |
381 | return 0; | |
382 | } | |
383 | ||
74d88eb2 | 384 | static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 RG |
385 | { |
386 | struct i2c_client *client = to_i2c_client(dev); | |
387 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
388 | int ret; | |
389 | ||
390 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
391 | return -EINVAL; | |
392 | ||
393 | /* read all ALARM1, ALARM2, and status registers at once */ | |
30e7b039 | 394 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
395 | DS1339_REG_ALARM1_SECS, 9, ds1307->regs); |
396 | if (ret != 9) { | |
cb49a5e9 RG |
397 | dev_err(dev, "%s error %d\n", "alarm read", ret); |
398 | return -EIO; | |
399 | } | |
400 | ||
401 | dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n", | |
402 | "alarm read", | |
403 | ds1307->regs[0], ds1307->regs[1], | |
404 | ds1307->regs[2], ds1307->regs[3], | |
405 | ds1307->regs[4], ds1307->regs[5], | |
406 | ds1307->regs[6], ds1307->regs[7], | |
407 | ds1307->regs[8]); | |
408 | ||
409 | /* report alarm time (ALARM1); assume 24 hour and day-of-month modes, | |
410 | * and that all four fields are checked matches | |
411 | */ | |
412 | t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f); | |
413 | t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f); | |
414 | t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f); | |
415 | t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f); | |
416 | t->time.tm_mon = -1; | |
417 | t->time.tm_year = -1; | |
418 | t->time.tm_wday = -1; | |
419 | t->time.tm_yday = -1; | |
420 | t->time.tm_isdst = -1; | |
421 | ||
422 | /* ... and status */ | |
423 | t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE); | |
424 | t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I); | |
425 | ||
426 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
427 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
428 | "alarm read", t->time.tm_sec, t->time.tm_min, | |
429 | t->time.tm_hour, t->time.tm_mday, | |
430 | t->enabled, t->pending); | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
74d88eb2 | 435 | static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 RG |
436 | { |
437 | struct i2c_client *client = to_i2c_client(dev); | |
438 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
439 | unsigned char *buf = ds1307->regs; | |
440 | u8 control, status; | |
441 | int ret; | |
442 | ||
443 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
444 | return -EINVAL; | |
445 | ||
446 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
447 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
448 | "alarm set", t->time.tm_sec, t->time.tm_min, | |
449 | t->time.tm_hour, t->time.tm_mday, | |
450 | t->enabled, t->pending); | |
451 | ||
452 | /* read current status of both alarms and the chip */ | |
30e7b039 | 453 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
454 | DS1339_REG_ALARM1_SECS, 9, buf); |
455 | if (ret != 9) { | |
cb49a5e9 RG |
456 | dev_err(dev, "%s error %d\n", "alarm write", ret); |
457 | return -EIO; | |
458 | } | |
459 | control = ds1307->regs[7]; | |
460 | status = ds1307->regs[8]; | |
461 | ||
462 | dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n", | |
463 | "alarm set (old status)", | |
464 | ds1307->regs[0], ds1307->regs[1], | |
465 | ds1307->regs[2], ds1307->regs[3], | |
466 | ds1307->regs[4], ds1307->regs[5], | |
467 | ds1307->regs[6], control, status); | |
468 | ||
469 | /* set ALARM1, using 24 hour and day-of-month modes */ | |
cb49a5e9 RG |
470 | buf[0] = bin2bcd(t->time.tm_sec); |
471 | buf[1] = bin2bcd(t->time.tm_min); | |
472 | buf[2] = bin2bcd(t->time.tm_hour); | |
473 | buf[3] = bin2bcd(t->time.tm_mday); | |
474 | ||
475 | /* set ALARM2 to non-garbage */ | |
476 | buf[4] = 0; | |
477 | buf[5] = 0; | |
478 | buf[6] = 0; | |
479 | ||
480 | /* optionally enable ALARM1 */ | |
481 | buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); | |
482 | if (t->enabled) { | |
483 | dev_dbg(dev, "alarm IRQ armed\n"); | |
484 | buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ | |
485 | } | |
486 | buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); | |
487 | ||
30e7b039 | 488 | ret = ds1307->write_block_data(client, |
fed40b73 BS |
489 | DS1339_REG_ALARM1_SECS, 9, buf); |
490 | if (ret < 0) { | |
cb49a5e9 | 491 | dev_err(dev, "can't set alarm time\n"); |
fed40b73 | 492 | return ret; |
cb49a5e9 RG |
493 | } |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | static int ds1307_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
499 | { | |
500 | struct i2c_client *client = to_i2c_client(dev); | |
501 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
502 | int ret; | |
503 | ||
504 | switch (cmd) { | |
505 | case RTC_AIE_OFF: | |
506 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
507 | return -ENOTTY; | |
508 | ||
509 | ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); | |
510 | if (ret < 0) | |
511 | return ret; | |
512 | ||
513 | ret &= ~DS1337_BIT_A1IE; | |
514 | ||
515 | ret = i2c_smbus_write_byte_data(client, | |
516 | DS1337_REG_CONTROL, ret); | |
517 | if (ret < 0) | |
518 | return ret; | |
519 | ||
520 | break; | |
521 | ||
522 | case RTC_AIE_ON: | |
523 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
524 | return -ENOTTY; | |
525 | ||
526 | ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); | |
527 | if (ret < 0) | |
528 | return ret; | |
529 | ||
530 | ret |= DS1337_BIT_A1IE; | |
531 | ||
532 | ret = i2c_smbus_write_byte_data(client, | |
533 | DS1337_REG_CONTROL, ret); | |
534 | if (ret < 0) | |
535 | return ret; | |
536 | ||
537 | break; | |
538 | ||
539 | default: | |
540 | return -ENOIOCTLCMD; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
ff8371ac | 546 | static const struct rtc_class_ops ds13xx_rtc_ops = { |
1abb0dc9 DB |
547 | .read_time = ds1307_get_time, |
548 | .set_time = ds1307_set_time, | |
74d88eb2 JR |
549 | .read_alarm = ds1337_read_alarm, |
550 | .set_alarm = ds1337_set_alarm, | |
cb49a5e9 | 551 | .ioctl = ds1307_ioctl, |
1abb0dc9 DB |
552 | }; |
553 | ||
682d73f6 DB |
554 | /*----------------------------------------------------------------------*/ |
555 | ||
556 | #define NVRAM_SIZE 56 | |
557 | ||
558 | static ssize_t | |
559 | ds1307_nvram_read(struct kobject *kobj, struct bin_attribute *attr, | |
560 | char *buf, loff_t off, size_t count) | |
561 | { | |
562 | struct i2c_client *client; | |
563 | struct ds1307 *ds1307; | |
682d73f6 DB |
564 | int result; |
565 | ||
fcd8db00 | 566 | client = kobj_to_i2c_client(kobj); |
682d73f6 DB |
567 | ds1307 = i2c_get_clientdata(client); |
568 | ||
569 | if (unlikely(off >= NVRAM_SIZE)) | |
570 | return 0; | |
571 | if ((off + count) > NVRAM_SIZE) | |
572 | count = NVRAM_SIZE - off; | |
573 | if (unlikely(!count)) | |
574 | return count; | |
575 | ||
30e7b039 | 576 | result = ds1307->read_block_data(client, 8 + off, count, buf); |
fed40b73 | 577 | if (result < 0) |
682d73f6 | 578 | dev_err(&client->dev, "%s error %d\n", "nvram read", result); |
fed40b73 | 579 | return result; |
682d73f6 DB |
580 | } |
581 | ||
582 | static ssize_t | |
583 | ds1307_nvram_write(struct kobject *kobj, struct bin_attribute *attr, | |
584 | char *buf, loff_t off, size_t count) | |
585 | { | |
586 | struct i2c_client *client; | |
30e7b039 | 587 | struct ds1307 *ds1307; |
fed40b73 | 588 | int result; |
682d73f6 | 589 | |
fcd8db00 | 590 | client = kobj_to_i2c_client(kobj); |
30e7b039 | 591 | ds1307 = i2c_get_clientdata(client); |
682d73f6 DB |
592 | |
593 | if (unlikely(off >= NVRAM_SIZE)) | |
594 | return -EFBIG; | |
595 | if ((off + count) > NVRAM_SIZE) | |
596 | count = NVRAM_SIZE - off; | |
597 | if (unlikely(!count)) | |
598 | return count; | |
599 | ||
30e7b039 | 600 | result = ds1307->write_block_data(client, 8 + off, count, buf); |
fed40b73 BS |
601 | if (result < 0) { |
602 | dev_err(&client->dev, "%s error %d\n", "nvram write", result); | |
603 | return result; | |
604 | } | |
605 | return count; | |
682d73f6 DB |
606 | } |
607 | ||
608 | static struct bin_attribute nvram = { | |
609 | .attr = { | |
610 | .name = "nvram", | |
611 | .mode = S_IRUGO | S_IWUSR, | |
682d73f6 DB |
612 | }, |
613 | ||
614 | .read = ds1307_nvram_read, | |
615 | .write = ds1307_nvram_write, | |
616 | .size = NVRAM_SIZE, | |
617 | }; | |
618 | ||
619 | /*----------------------------------------------------------------------*/ | |
620 | ||
1abb0dc9 DB |
621 | static struct i2c_driver ds1307_driver; |
622 | ||
d2653e92 JD |
623 | static int __devinit ds1307_probe(struct i2c_client *client, |
624 | const struct i2c_device_id *id) | |
1abb0dc9 DB |
625 | { |
626 | struct ds1307 *ds1307; | |
627 | int err = -ENODEV; | |
1abb0dc9 | 628 | int tmp; |
3760f736 | 629 | const struct chip_desc *chip = &chips[id->driver_data]; |
c065f35c | 630 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
cb49a5e9 | 631 | int want_irq = false; |
fed40b73 | 632 | unsigned char *buf; |
97f902b7 WS |
633 | static const int bbsqi_bitpos[] = { |
634 | [ds_1337] = 0, | |
635 | [ds_1339] = DS1339_BIT_BBSQI, | |
636 | [ds_3231] = DS3231_BIT_BBSQW, | |
637 | }; | |
1abb0dc9 | 638 | |
30e7b039 ES |
639 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA) |
640 | && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) | |
c065f35c DB |
641 | return -EIO; |
642 | ||
643 | if (!(ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL))) | |
644 | return -ENOMEM; | |
045e0e85 | 645 | |
1abb0dc9 | 646 | i2c_set_clientdata(client, ds1307); |
33df2ee1 JT |
647 | |
648 | ds1307->client = client; | |
649 | ds1307->type = id->driver_data; | |
650 | ds1307->offset = 0; | |
651 | ||
fed40b73 | 652 | buf = ds1307->regs; |
30e7b039 ES |
653 | if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) { |
654 | ds1307->read_block_data = i2c_smbus_read_i2c_block_data; | |
655 | ds1307->write_block_data = i2c_smbus_write_i2c_block_data; | |
656 | } else { | |
657 | ds1307->read_block_data = ds1307_read_block_data; | |
658 | ds1307->write_block_data = ds1307_write_block_data; | |
659 | } | |
045e0e85 DB |
660 | |
661 | switch (ds1307->type) { | |
662 | case ds_1337: | |
663 | case ds_1339: | |
97f902b7 | 664 | case ds_3231: |
cb49a5e9 RG |
665 | /* has IRQ? */ |
666 | if (ds1307->client->irq > 0 && chip->alarm) { | |
667 | INIT_WORK(&ds1307->work, ds1307_work); | |
668 | want_irq = true; | |
669 | } | |
be5f59f4 | 670 | /* get registers that the "rtc" read below won't read... */ |
30e7b039 | 671 | tmp = ds1307->read_block_data(ds1307->client, |
fed40b73 | 672 | DS1337_REG_CONTROL, 2, buf); |
1abb0dc9 DB |
673 | if (tmp != 2) { |
674 | pr_debug("read error %d\n", tmp); | |
675 | err = -EIO; | |
676 | goto exit_free; | |
677 | } | |
678 | ||
be5f59f4 RG |
679 | /* oscillator off? turn it on, so clock can tick. */ |
680 | if (ds1307->regs[0] & DS1337_BIT_nEOSC) | |
cb49a5e9 RG |
681 | ds1307->regs[0] &= ~DS1337_BIT_nEOSC; |
682 | ||
683 | /* Using IRQ? Disable the square wave and both alarms. | |
97f902b7 WS |
684 | * For some variants, be sure alarms can trigger when we're |
685 | * running on Vbackup (BBSQI/BBSQW) | |
cb49a5e9 RG |
686 | */ |
687 | if (want_irq) { | |
97f902b7 WS |
688 | ds1307->regs[0] |= DS1337_BIT_INTCN |
689 | | bbsqi_bitpos[ds1307->type]; | |
cb49a5e9 RG |
690 | ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); |
691 | } | |
692 | ||
693 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, | |
694 | ds1307->regs[0]); | |
be5f59f4 RG |
695 | |
696 | /* oscillator fault? clear flag, and warn */ | |
697 | if (ds1307->regs[1] & DS1337_BIT_OSF) { | |
698 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, | |
699 | ds1307->regs[1] & ~DS1337_BIT_OSF); | |
700 | dev_warn(&client->dev, "SET TIME!\n"); | |
1abb0dc9 | 701 | } |
045e0e85 | 702 | break; |
a2166858 MF |
703 | |
704 | case rx_8025: | |
705 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
706 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
707 | if (tmp != 2) { | |
708 | pr_debug("read error %d\n", tmp); | |
709 | err = -EIO; | |
710 | goto exit_free; | |
711 | } | |
712 | ||
713 | /* oscillator off? turn it on, so clock can tick. */ | |
714 | if (!(ds1307->regs[1] & RX8025_BIT_XST)) { | |
715 | ds1307->regs[1] |= RX8025_BIT_XST; | |
716 | i2c_smbus_write_byte_data(client, | |
717 | RX8025_REG_CTRL2 << 4 | 0x08, | |
718 | ds1307->regs[1]); | |
719 | dev_warn(&client->dev, | |
720 | "oscillator stop detected - SET TIME!\n"); | |
721 | } | |
722 | ||
723 | if (ds1307->regs[1] & RX8025_BIT_PON) { | |
724 | ds1307->regs[1] &= ~RX8025_BIT_PON; | |
725 | i2c_smbus_write_byte_data(client, | |
726 | RX8025_REG_CTRL2 << 4 | 0x08, | |
727 | ds1307->regs[1]); | |
728 | dev_warn(&client->dev, "power-on detected\n"); | |
729 | } | |
730 | ||
731 | if (ds1307->regs[1] & RX8025_BIT_VDET) { | |
732 | ds1307->regs[1] &= ~RX8025_BIT_VDET; | |
733 | i2c_smbus_write_byte_data(client, | |
734 | RX8025_REG_CTRL2 << 4 | 0x08, | |
735 | ds1307->regs[1]); | |
736 | dev_warn(&client->dev, "voltage drop detected\n"); | |
737 | } | |
738 | ||
739 | /* make sure we are running in 24hour mode */ | |
740 | if (!(ds1307->regs[0] & RX8025_BIT_2412)) { | |
741 | u8 hour; | |
742 | ||
743 | /* switch to 24 hour mode */ | |
744 | i2c_smbus_write_byte_data(client, | |
745 | RX8025_REG_CTRL1 << 4 | 0x08, | |
746 | ds1307->regs[0] | | |
747 | RX8025_BIT_2412); | |
748 | ||
749 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
750 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
751 | if (tmp != 2) { | |
752 | pr_debug("read error %d\n", tmp); | |
753 | err = -EIO; | |
754 | goto exit_free; | |
755 | } | |
756 | ||
757 | /* correct hour */ | |
758 | hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]); | |
759 | if (hour == 12) | |
760 | hour = 0; | |
761 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
762 | hour += 12; | |
763 | ||
764 | i2c_smbus_write_byte_data(client, | |
765 | DS1307_REG_HOUR << 4 | 0x08, | |
766 | hour); | |
767 | } | |
768 | break; | |
33df2ee1 JT |
769 | case ds_1388: |
770 | ds1307->offset = 1; /* Seconds starts at 1 */ | |
771 | break; | |
045e0e85 DB |
772 | default: |
773 | break; | |
774 | } | |
1abb0dc9 DB |
775 | |
776 | read_rtc: | |
777 | /* read RTC registers */ | |
30e7b039 | 778 | tmp = ds1307->read_block_data(ds1307->client, 0, 8, buf); |
fed40b73 | 779 | if (tmp != 8) { |
1abb0dc9 DB |
780 | pr_debug("read error %d\n", tmp); |
781 | err = -EIO; | |
782 | goto exit_free; | |
783 | } | |
784 | ||
785 | /* minimal sanity checking; some chips (like DS1340) don't | |
786 | * specify the extra bits as must-be-zero, but there are | |
787 | * still a few values that are clearly out-of-range. | |
788 | */ | |
789 | tmp = ds1307->regs[DS1307_REG_SECS]; | |
045e0e85 DB |
790 | switch (ds1307->type) { |
791 | case ds_1307: | |
045e0e85 | 792 | case m41t00: |
be5f59f4 | 793 | /* clock halted? turn it on, so clock can tick. */ |
045e0e85 | 794 | if (tmp & DS1307_BIT_CH) { |
be5f59f4 RG |
795 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
796 | dev_warn(&client->dev, "SET TIME!\n"); | |
045e0e85 | 797 | goto read_rtc; |
1abb0dc9 | 798 | } |
045e0e85 | 799 | break; |
be5f59f4 RG |
800 | case ds_1338: |
801 | /* clock halted? turn it on, so clock can tick. */ | |
045e0e85 | 802 | if (tmp & DS1307_BIT_CH) |
be5f59f4 RG |
803 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
804 | ||
805 | /* oscillator fault? clear flag, and warn */ | |
806 | if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { | |
807 | i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL, | |
bd16f9eb | 808 | ds1307->regs[DS1307_REG_CONTROL] |
be5f59f4 RG |
809 | & ~DS1338_BIT_OSF); |
810 | dev_warn(&client->dev, "SET TIME!\n"); | |
811 | goto read_rtc; | |
812 | } | |
045e0e85 | 813 | break; |
fcd8db00 R |
814 | case ds_1340: |
815 | /* clock halted? turn it on, so clock can tick. */ | |
816 | if (tmp & DS1340_BIT_nEOSC) | |
817 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); | |
818 | ||
819 | tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG); | |
820 | if (tmp < 0) { | |
821 | pr_debug("read error %d\n", tmp); | |
822 | err = -EIO; | |
823 | goto exit_free; | |
824 | } | |
825 | ||
826 | /* oscillator fault? clear flag, and warn */ | |
827 | if (tmp & DS1340_BIT_OSF) { | |
828 | i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0); | |
829 | dev_warn(&client->dev, "SET TIME!\n"); | |
830 | } | |
831 | break; | |
a2166858 | 832 | case rx_8025: |
c065f35c DB |
833 | case ds_1337: |
834 | case ds_1339: | |
33df2ee1 | 835 | case ds_1388: |
97f902b7 | 836 | case ds_3231: |
045e0e85 | 837 | break; |
1abb0dc9 | 838 | } |
045e0e85 | 839 | |
1abb0dc9 | 840 | tmp = ds1307->regs[DS1307_REG_HOUR]; |
c065f35c DB |
841 | switch (ds1307->type) { |
842 | case ds_1340: | |
843 | case m41t00: | |
844 | /* NOTE: ignores century bits; fix before deploying | |
845 | * systems that will run through year 2100. | |
846 | */ | |
847 | break; | |
a2166858 MF |
848 | case rx_8025: |
849 | break; | |
c065f35c DB |
850 | default: |
851 | if (!(tmp & DS1307_BIT_12HR)) | |
852 | break; | |
853 | ||
854 | /* Be sure we're in 24 hour mode. Multi-master systems | |
855 | * take note... | |
856 | */ | |
fe20ba70 | 857 | tmp = bcd2bin(tmp & 0x1f); |
c065f35c DB |
858 | if (tmp == 12) |
859 | tmp = 0; | |
860 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
861 | tmp += 12; | |
1abb0dc9 DB |
862 | i2c_smbus_write_byte_data(client, |
863 | DS1307_REG_HOUR, | |
fe20ba70 | 864 | bin2bcd(tmp)); |
1abb0dc9 DB |
865 | } |
866 | ||
1abb0dc9 DB |
867 | ds1307->rtc = rtc_device_register(client->name, &client->dev, |
868 | &ds13xx_rtc_ops, THIS_MODULE); | |
869 | if (IS_ERR(ds1307->rtc)) { | |
870 | err = PTR_ERR(ds1307->rtc); | |
871 | dev_err(&client->dev, | |
872 | "unable to register the class device\n"); | |
c065f35c | 873 | goto exit_free; |
1abb0dc9 DB |
874 | } |
875 | ||
cb49a5e9 RG |
876 | if (want_irq) { |
877 | err = request_irq(client->irq, ds1307_irq, 0, | |
878 | ds1307->rtc->name, client); | |
879 | if (err) { | |
880 | dev_err(&client->dev, | |
881 | "unable to request IRQ!\n"); | |
882 | goto exit_irq; | |
883 | } | |
884 | set_bit(HAS_ALARM, &ds1307->flags); | |
885 | dev_dbg(&client->dev, "got IRQ %d\n", client->irq); | |
886 | } | |
887 | ||
682d73f6 DB |
888 | if (chip->nvram56) { |
889 | err = sysfs_create_bin_file(&client->dev.kobj, &nvram); | |
890 | if (err == 0) { | |
cb49a5e9 | 891 | set_bit(HAS_NVRAM, &ds1307->flags); |
682d73f6 DB |
892 | dev_info(&client->dev, "56 bytes nvram\n"); |
893 | } | |
894 | } | |
895 | ||
1abb0dc9 DB |
896 | return 0; |
897 | ||
cb49a5e9 | 898 | exit_irq: |
72445af8 | 899 | rtc_device_unregister(ds1307->rtc); |
1abb0dc9 DB |
900 | exit_free: |
901 | kfree(ds1307); | |
1abb0dc9 DB |
902 | return err; |
903 | } | |
904 | ||
c065f35c | 905 | static int __devexit ds1307_remove(struct i2c_client *client) |
1abb0dc9 | 906 | { |
cb49a5e9 RG |
907 | struct ds1307 *ds1307 = i2c_get_clientdata(client); |
908 | ||
909 | if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) { | |
910 | free_irq(client->irq, client); | |
911 | cancel_work_sync(&ds1307->work); | |
912 | } | |
1abb0dc9 | 913 | |
cb49a5e9 | 914 | if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) |
682d73f6 DB |
915 | sysfs_remove_bin_file(&client->dev.kobj, &nvram); |
916 | ||
1abb0dc9 | 917 | rtc_device_unregister(ds1307->rtc); |
1abb0dc9 DB |
918 | kfree(ds1307); |
919 | return 0; | |
920 | } | |
921 | ||
922 | static struct i2c_driver ds1307_driver = { | |
923 | .driver = { | |
c065f35c | 924 | .name = "rtc-ds1307", |
1abb0dc9 DB |
925 | .owner = THIS_MODULE, |
926 | }, | |
c065f35c DB |
927 | .probe = ds1307_probe, |
928 | .remove = __devexit_p(ds1307_remove), | |
3760f736 | 929 | .id_table = ds1307_id, |
1abb0dc9 DB |
930 | }; |
931 | ||
932 | static int __init ds1307_init(void) | |
933 | { | |
934 | return i2c_add_driver(&ds1307_driver); | |
935 | } | |
936 | module_init(ds1307_init); | |
937 | ||
938 | static void __exit ds1307_exit(void) | |
939 | { | |
940 | i2c_del_driver(&ds1307_driver); | |
941 | } | |
942 | module_exit(ds1307_exit); | |
943 | ||
944 | MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); | |
945 | MODULE_LICENSE("GPL"); |