Commit | Line | Data |
---|---|---|
1abb0dc9 DB |
1 | /* |
2 | * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. | |
3 | * | |
4 | * Copyright (C) 2005 James Chapman (ds1337 core) | |
5 | * Copyright (C) 2006 David Brownell | |
a2166858 | 6 | * Copyright (C) 2009 Matthias Fuchs (rx8025 support) |
bc48b902 | 7 | * Copyright (C) 2012 Bertrand Achard (nvram access fixes) |
1abb0dc9 DB |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
9c19b893 | 14 | #include <linux/acpi.h> |
eac7237f NM |
15 | #include <linux/bcd.h> |
16 | #include <linux/i2c.h> | |
1abb0dc9 | 17 | #include <linux/init.h> |
eac7237f | 18 | #include <linux/module.h> |
7ef6d2c2 | 19 | #include <linux/of_device.h> |
eac7237f NM |
20 | #include <linux/rtc/ds1307.h> |
21 | #include <linux/rtc.h> | |
1abb0dc9 | 22 | #include <linux/slab.h> |
1abb0dc9 | 23 | #include <linux/string.h> |
445c0207 AM |
24 | #include <linux/hwmon.h> |
25 | #include <linux/hwmon-sysfs.h> | |
6c6ff145 | 26 | #include <linux/clk-provider.h> |
11e5890b | 27 | #include <linux/regmap.h> |
1abb0dc9 | 28 | |
40ce972d DA |
29 | /* |
30 | * We can't determine type by probing, but if we expect pre-Linux code | |
1abb0dc9 DB |
31 | * to have set the chip up as a clock (turning on the oscillator and |
32 | * setting the date and time), Linux can ignore the non-clock features. | |
33 | * That's a natural job for a factory or repair bench. | |
1abb0dc9 DB |
34 | */ |
35 | enum ds_type { | |
045e0e85 | 36 | ds_1307, |
300a7735 | 37 | ds_1308, |
045e0e85 DB |
38 | ds_1337, |
39 | ds_1338, | |
40 | ds_1339, | |
41 | ds_1340, | |
0759c886 | 42 | ds_1341, |
33df2ee1 | 43 | ds_1388, |
97f902b7 | 44 | ds_3231, |
8566f70c | 45 | m41t0, |
045e0e85 | 46 | m41t00, |
f4199f85 | 47 | mcp794xx, |
a2166858 | 48 | rx_8025, |
ee0981be | 49 | rx_8130, |
32d322bc | 50 | last_ds_type /* always last */ |
40ce972d | 51 | /* rs5c372 too? different address... */ |
1abb0dc9 DB |
52 | }; |
53 | ||
1abb0dc9 DB |
54 | /* RTC registers don't differ much, except for the century flag */ |
55 | #define DS1307_REG_SECS 0x00 /* 00-59 */ | |
56 | # define DS1307_BIT_CH 0x80 | |
be5f59f4 | 57 | # define DS1340_BIT_nEOSC 0x80 |
f4199f85 | 58 | # define MCP794XX_BIT_ST 0x80 |
1abb0dc9 | 59 | #define DS1307_REG_MIN 0x01 /* 00-59 */ |
8566f70c | 60 | # define M41T0_BIT_OF 0x80 |
1abb0dc9 | 61 | #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ |
c065f35c DB |
62 | # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ |
63 | # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ | |
1abb0dc9 DB |
64 | # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ |
65 | # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ | |
66 | #define DS1307_REG_WDAY 0x03 /* 01-07 */ | |
f4199f85 | 67 | # define MCP794XX_BIT_VBATEN 0x08 |
1abb0dc9 DB |
68 | #define DS1307_REG_MDAY 0x04 /* 01-31 */ |
69 | #define DS1307_REG_MONTH 0x05 /* 01-12 */ | |
70 | # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ | |
71 | #define DS1307_REG_YEAR 0x06 /* 00-99 */ | |
72 | ||
40ce972d DA |
73 | /* |
74 | * Other registers (control, status, alarms, trickle charge, NVRAM, etc) | |
045e0e85 DB |
75 | * start at 7, and they differ a LOT. Only control and status matter for |
76 | * basic RTC date and time functionality; be careful using them. | |
1abb0dc9 | 77 | */ |
045e0e85 | 78 | #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ |
1abb0dc9 | 79 | # define DS1307_BIT_OUT 0x80 |
be5f59f4 | 80 | # define DS1338_BIT_OSF 0x20 |
1abb0dc9 DB |
81 | # define DS1307_BIT_SQWE 0x10 |
82 | # define DS1307_BIT_RS1 0x02 | |
83 | # define DS1307_BIT_RS0 0x01 | |
84 | #define DS1337_REG_CONTROL 0x0e | |
85 | # define DS1337_BIT_nEOSC 0x80 | |
cb49a5e9 | 86 | # define DS1339_BIT_BBSQI 0x20 |
97f902b7 | 87 | # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ |
1abb0dc9 DB |
88 | # define DS1337_BIT_RS2 0x10 |
89 | # define DS1337_BIT_RS1 0x08 | |
90 | # define DS1337_BIT_INTCN 0x04 | |
91 | # define DS1337_BIT_A2IE 0x02 | |
92 | # define DS1337_BIT_A1IE 0x01 | |
045e0e85 DB |
93 | #define DS1340_REG_CONTROL 0x07 |
94 | # define DS1340_BIT_OUT 0x80 | |
95 | # define DS1340_BIT_FT 0x40 | |
96 | # define DS1340_BIT_CALIB_SIGN 0x20 | |
97 | # define DS1340_M_CALIBRATION 0x1f | |
be5f59f4 RG |
98 | #define DS1340_REG_FLAG 0x09 |
99 | # define DS1340_BIT_OSF 0x80 | |
1abb0dc9 DB |
100 | #define DS1337_REG_STATUS 0x0f |
101 | # define DS1337_BIT_OSF 0x80 | |
6c6ff145 | 102 | # define DS3231_BIT_EN32KHZ 0x08 |
1abb0dc9 DB |
103 | # define DS1337_BIT_A2I 0x02 |
104 | # define DS1337_BIT_A1I 0x01 | |
cb49a5e9 | 105 | #define DS1339_REG_ALARM1_SECS 0x07 |
eb86c306 WS |
106 | |
107 | #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 | |
1abb0dc9 | 108 | |
a2166858 MF |
109 | #define RX8025_REG_CTRL1 0x0e |
110 | # define RX8025_BIT_2412 0x20 | |
111 | #define RX8025_REG_CTRL2 0x0f | |
112 | # define RX8025_BIT_PON 0x10 | |
113 | # define RX8025_BIT_VDET 0x40 | |
114 | # define RX8025_BIT_XST 0x20 | |
1abb0dc9 | 115 | |
1abb0dc9 | 116 | struct ds1307 { |
1abb0dc9 | 117 | enum ds_type type; |
cb49a5e9 RG |
118 | unsigned long flags; |
119 | #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ | |
120 | #define HAS_ALARM 1 /* bit 1 == irq claimed */ | |
11e5890b HK |
121 | struct device *dev; |
122 | struct regmap *regmap; | |
123 | const char *name; | |
1abb0dc9 | 124 | struct rtc_device *rtc; |
6c6ff145 AM |
125 | #ifdef CONFIG_COMMON_CLK |
126 | struct clk_hw clks[2]; | |
127 | #endif | |
1abb0dc9 DB |
128 | }; |
129 | ||
045e0e85 | 130 | struct chip_desc { |
045e0e85 | 131 | unsigned alarm:1; |
9eab0a78 AB |
132 | u16 nvram_offset; |
133 | u16 nvram_size; | |
e553170a | 134 | u8 offset; /* register's offset */ |
e48585de HK |
135 | u8 century_reg; |
136 | u8 century_enable_bit; | |
137 | u8 century_bit; | |
0b6ee805 | 138 | u8 bbsqi_bit; |
45947127 | 139 | irq_handler_t irq_handler; |
1efb98ba | 140 | const struct rtc_class_ops *rtc_ops; |
eb86c306 | 141 | u16 trickle_charger_reg; |
57ec2d95 | 142 | u8 (*do_trickle_setup)(struct ds1307 *, u32, |
11e5890b | 143 | bool); |
045e0e85 DB |
144 | }; |
145 | ||
1efb98ba HK |
146 | static int ds1307_get_time(struct device *dev, struct rtc_time *t); |
147 | static int ds1307_set_time(struct device *dev, struct rtc_time *t); | |
57ec2d95 | 148 | static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode); |
45947127 | 149 | static irqreturn_t rx8130_irq(int irq, void *dev_id); |
1efb98ba HK |
150 | static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t); |
151 | static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t); | |
152 | static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled); | |
45947127 | 153 | static irqreturn_t mcp794xx_irq(int irq, void *dev_id); |
1efb98ba HK |
154 | static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t); |
155 | static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t); | |
156 | static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled); | |
33b04b7b | 157 | |
1efb98ba HK |
158 | static const struct rtc_class_ops rx8130_rtc_ops = { |
159 | .read_time = ds1307_get_time, | |
160 | .set_time = ds1307_set_time, | |
161 | .read_alarm = rx8130_read_alarm, | |
162 | .set_alarm = rx8130_set_alarm, | |
163 | .alarm_irq_enable = rx8130_alarm_irq_enable, | |
164 | }; | |
165 | ||
166 | static const struct rtc_class_ops mcp794xx_rtc_ops = { | |
167 | .read_time = ds1307_get_time, | |
168 | .set_time = ds1307_set_time, | |
169 | .read_alarm = mcp794xx_read_alarm, | |
170 | .set_alarm = mcp794xx_set_alarm, | |
171 | .alarm_irq_enable = mcp794xx_alarm_irq_enable, | |
172 | }; | |
33b04b7b | 173 | |
7624df48 | 174 | static const struct chip_desc chips[last_ds_type] = { |
32d322bc | 175 | [ds_1307] = { |
9eab0a78 AB |
176 | .nvram_offset = 8, |
177 | .nvram_size = 56, | |
32d322bc | 178 | }, |
300a7735 SN |
179 | [ds_1308] = { |
180 | .nvram_offset = 8, | |
181 | .nvram_size = 56, | |
182 | }, | |
32d322bc WS |
183 | [ds_1337] = { |
184 | .alarm = 1, | |
e48585de HK |
185 | .century_reg = DS1307_REG_MONTH, |
186 | .century_bit = DS1337_BIT_CENTURY, | |
32d322bc WS |
187 | }, |
188 | [ds_1338] = { | |
9eab0a78 AB |
189 | .nvram_offset = 8, |
190 | .nvram_size = 56, | |
32d322bc WS |
191 | }, |
192 | [ds_1339] = { | |
193 | .alarm = 1, | |
e48585de HK |
194 | .century_reg = DS1307_REG_MONTH, |
195 | .century_bit = DS1337_BIT_CENTURY, | |
0b6ee805 | 196 | .bbsqi_bit = DS1339_BIT_BBSQI, |
eb86c306 | 197 | .trickle_charger_reg = 0x10, |
33b04b7b | 198 | .do_trickle_setup = &do_trickle_setup_ds1339, |
eb86c306 WS |
199 | }, |
200 | [ds_1340] = { | |
e48585de HK |
201 | .century_reg = DS1307_REG_HOUR, |
202 | .century_enable_bit = DS1340_BIT_CENTURY_EN, | |
203 | .century_bit = DS1340_BIT_CENTURY, | |
51ed73eb | 204 | .do_trickle_setup = &do_trickle_setup_ds1339, |
eb86c306 WS |
205 | .trickle_charger_reg = 0x08, |
206 | }, | |
0759c886 NY |
207 | [ds_1341] = { |
208 | .century_reg = DS1307_REG_MONTH, | |
209 | .century_bit = DS1337_BIT_CENTURY, | |
210 | }, | |
eb86c306 | 211 | [ds_1388] = { |
e553170a | 212 | .offset = 1, |
eb86c306 | 213 | .trickle_charger_reg = 0x0a, |
32d322bc WS |
214 | }, |
215 | [ds_3231] = { | |
216 | .alarm = 1, | |
e48585de HK |
217 | .century_reg = DS1307_REG_MONTH, |
218 | .century_bit = DS1337_BIT_CENTURY, | |
0b6ee805 | 219 | .bbsqi_bit = DS3231_BIT_BBSQW, |
32d322bc | 220 | }, |
ee0981be MV |
221 | [rx_8130] = { |
222 | .alarm = 1, | |
223 | /* this is battery backed SRAM */ | |
224 | .nvram_offset = 0x20, | |
225 | .nvram_size = 4, /* 32bit (4 word x 8 bit) */ | |
e553170a | 226 | .offset = 0x10, |
45947127 | 227 | .irq_handler = rx8130_irq, |
1efb98ba | 228 | .rtc_ops = &rx8130_rtc_ops, |
ee0981be | 229 | }, |
f4199f85 | 230 | [mcp794xx] = { |
1d1945d2 | 231 | .alarm = 1, |
9eab0a78 AB |
232 | /* this is battery backed SRAM */ |
233 | .nvram_offset = 0x20, | |
234 | .nvram_size = 0x40, | |
45947127 | 235 | .irq_handler = mcp794xx_irq, |
1efb98ba | 236 | .rtc_ops = &mcp794xx_rtc_ops, |
9eab0a78 | 237 | }, |
32d322bc | 238 | }; |
045e0e85 | 239 | |
3760f736 JD |
240 | static const struct i2c_device_id ds1307_id[] = { |
241 | { "ds1307", ds_1307 }, | |
300a7735 | 242 | { "ds1308", ds_1308 }, |
3760f736 JD |
243 | { "ds1337", ds_1337 }, |
244 | { "ds1338", ds_1338 }, | |
245 | { "ds1339", ds_1339 }, | |
33df2ee1 | 246 | { "ds1388", ds_1388 }, |
3760f736 | 247 | { "ds1340", ds_1340 }, |
0759c886 | 248 | { "ds1341", ds_1341 }, |
97f902b7 | 249 | { "ds3231", ds_3231 }, |
8566f70c | 250 | { "m41t0", m41t0 }, |
3760f736 | 251 | { "m41t00", m41t00 }, |
f4199f85 TN |
252 | { "mcp7940x", mcp794xx }, |
253 | { "mcp7941x", mcp794xx }, | |
31c1771c | 254 | { "pt7c4338", ds_1307 }, |
a2166858 | 255 | { "rx8025", rx_8025 }, |
78aaa06d | 256 | { "isl12057", ds_1337 }, |
ee0981be | 257 | { "rx8130", rx_8130 }, |
3760f736 JD |
258 | { } |
259 | }; | |
260 | MODULE_DEVICE_TABLE(i2c, ds1307_id); | |
1abb0dc9 | 261 | |
7ef6d2c2 JMC |
262 | #ifdef CONFIG_OF |
263 | static const struct of_device_id ds1307_of_match[] = { | |
264 | { | |
265 | .compatible = "dallas,ds1307", | |
266 | .data = (void *)ds_1307 | |
267 | }, | |
300a7735 SN |
268 | { |
269 | .compatible = "dallas,ds1308", | |
270 | .data = (void *)ds_1308 | |
271 | }, | |
7ef6d2c2 JMC |
272 | { |
273 | .compatible = "dallas,ds1337", | |
274 | .data = (void *)ds_1337 | |
275 | }, | |
276 | { | |
277 | .compatible = "dallas,ds1338", | |
278 | .data = (void *)ds_1338 | |
279 | }, | |
280 | { | |
281 | .compatible = "dallas,ds1339", | |
282 | .data = (void *)ds_1339 | |
283 | }, | |
284 | { | |
285 | .compatible = "dallas,ds1388", | |
286 | .data = (void *)ds_1388 | |
287 | }, | |
288 | { | |
289 | .compatible = "dallas,ds1340", | |
290 | .data = (void *)ds_1340 | |
291 | }, | |
0759c886 NY |
292 | { |
293 | .compatible = "dallas,ds1341", | |
294 | .data = (void *)ds_1341 | |
295 | }, | |
7ef6d2c2 JMC |
296 | { |
297 | .compatible = "maxim,ds3231", | |
298 | .data = (void *)ds_3231 | |
299 | }, | |
db2f8141 AB |
300 | { |
301 | .compatible = "st,m41t0", | |
302 | .data = (void *)m41t00 | |
303 | }, | |
7ef6d2c2 JMC |
304 | { |
305 | .compatible = "st,m41t00", | |
306 | .data = (void *)m41t00 | |
307 | }, | |
308 | { | |
309 | .compatible = "microchip,mcp7940x", | |
310 | .data = (void *)mcp794xx | |
311 | }, | |
312 | { | |
313 | .compatible = "microchip,mcp7941x", | |
314 | .data = (void *)mcp794xx | |
315 | }, | |
316 | { | |
317 | .compatible = "pericom,pt7c4338", | |
318 | .data = (void *)ds_1307 | |
319 | }, | |
320 | { | |
321 | .compatible = "epson,rx8025", | |
322 | .data = (void *)rx_8025 | |
323 | }, | |
324 | { | |
325 | .compatible = "isil,isl12057", | |
326 | .data = (void *)ds_1337 | |
327 | }, | |
47dd4729 BS |
328 | { |
329 | .compatible = "epson,rx8130", | |
330 | .data = (void *)rx_8130 | |
331 | }, | |
7ef6d2c2 JMC |
332 | { } |
333 | }; | |
334 | MODULE_DEVICE_TABLE(of, ds1307_of_match); | |
335 | #endif | |
336 | ||
9c19b893 TH |
337 | #ifdef CONFIG_ACPI |
338 | static const struct acpi_device_id ds1307_acpi_ids[] = { | |
339 | { .id = "DS1307", .driver_data = ds_1307 }, | |
300a7735 | 340 | { .id = "DS1308", .driver_data = ds_1308 }, |
9c19b893 TH |
341 | { .id = "DS1337", .driver_data = ds_1337 }, |
342 | { .id = "DS1338", .driver_data = ds_1338 }, | |
343 | { .id = "DS1339", .driver_data = ds_1339 }, | |
344 | { .id = "DS1388", .driver_data = ds_1388 }, | |
345 | { .id = "DS1340", .driver_data = ds_1340 }, | |
0759c886 | 346 | { .id = "DS1341", .driver_data = ds_1341 }, |
9c19b893 | 347 | { .id = "DS3231", .driver_data = ds_3231 }, |
8566f70c | 348 | { .id = "M41T0", .driver_data = m41t0 }, |
9c19b893 TH |
349 | { .id = "M41T00", .driver_data = m41t00 }, |
350 | { .id = "MCP7940X", .driver_data = mcp794xx }, | |
351 | { .id = "MCP7941X", .driver_data = mcp794xx }, | |
352 | { .id = "PT7C4338", .driver_data = ds_1307 }, | |
353 | { .id = "RX8025", .driver_data = rx_8025 }, | |
354 | { .id = "ISL12057", .driver_data = ds_1337 }, | |
47dd4729 | 355 | { .id = "RX8130", .driver_data = rx_8130 }, |
9c19b893 TH |
356 | { } |
357 | }; | |
358 | MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids); | |
359 | #endif | |
360 | ||
cb49a5e9 | 361 | /* |
cb49a5e9 RG |
362 | * The ds1337 and ds1339 both have two alarms, but we only use the first |
363 | * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm | |
364 | * signal; ds1339 chips have only one alarm signal. | |
365 | */ | |
2fb07a10 | 366 | static irqreturn_t ds1307_irq(int irq, void *dev_id) |
cb49a5e9 | 367 | { |
11e5890b | 368 | struct ds1307 *ds1307 = dev_id; |
2fb07a10 | 369 | struct mutex *lock = &ds1307->rtc->ops_lock; |
078f3f64 | 370 | int stat, ret; |
cb49a5e9 | 371 | |
cb49a5e9 | 372 | mutex_lock(lock); |
11e5890b HK |
373 | ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat); |
374 | if (ret) | |
cb49a5e9 RG |
375 | goto out; |
376 | ||
377 | if (stat & DS1337_BIT_A1I) { | |
378 | stat &= ~DS1337_BIT_A1I; | |
11e5890b | 379 | regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat); |
cb49a5e9 | 380 | |
078f3f64 HK |
381 | ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, |
382 | DS1337_BIT_A1IE, 0); | |
11e5890b | 383 | if (ret) |
cb49a5e9 RG |
384 | goto out; |
385 | ||
cb49a5e9 | 386 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); |
cb49a5e9 RG |
387 | } |
388 | ||
389 | out: | |
cb49a5e9 | 390 | mutex_unlock(lock); |
cb49a5e9 | 391 | |
cb49a5e9 RG |
392 | return IRQ_HANDLED; |
393 | } | |
394 | ||
395 | /*----------------------------------------------------------------------*/ | |
396 | ||
1abb0dc9 DB |
397 | static int ds1307_get_time(struct device *dev, struct rtc_time *t) |
398 | { | |
399 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
11e5890b | 400 | int tmp, ret; |
e48585de | 401 | const struct chip_desc *chip = &chips[ds1307->type]; |
042fa8c7 | 402 | u8 regs[7]; |
1abb0dc9 | 403 | |
045e0e85 | 404 | /* read the RTC date and time registers all at once */ |
042fa8c7 AB |
405 | ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, |
406 | sizeof(regs)); | |
11e5890b HK |
407 | if (ret) { |
408 | dev_err(dev, "%s error %d\n", "read", ret); | |
409 | return ret; | |
1abb0dc9 DB |
410 | } |
411 | ||
042fa8c7 | 412 | dev_dbg(dev, "%s: %7ph\n", "read", regs); |
1abb0dc9 | 413 | |
8566f70c SA |
414 | /* if oscillator fail bit is set, no data can be trusted */ |
415 | if (ds1307->type == m41t0 && | |
042fa8c7 | 416 | regs[DS1307_REG_MIN] & M41T0_BIT_OF) { |
8566f70c SA |
417 | dev_warn_once(dev, "oscillator failed, set time!\n"); |
418 | return -EINVAL; | |
419 | } | |
420 | ||
042fa8c7 AB |
421 | t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f); |
422 | t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f); | |
423 | tmp = regs[DS1307_REG_HOUR] & 0x3f; | |
fe20ba70 | 424 | t->tm_hour = bcd2bin(tmp); |
042fa8c7 AB |
425 | t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1; |
426 | t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f); | |
427 | tmp = regs[DS1307_REG_MONTH] & 0x1f; | |
fe20ba70 | 428 | t->tm_mon = bcd2bin(tmp) - 1; |
042fa8c7 | 429 | t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100; |
1abb0dc9 | 430 | |
042fa8c7 | 431 | if (regs[chip->century_reg] & chip->century_bit && |
e48585de HK |
432 | IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY)) |
433 | t->tm_year += 100; | |
50d6c0ea | 434 | |
1abb0dc9 DB |
435 | dev_dbg(dev, "%s secs=%d, mins=%d, " |
436 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
437 | "read", t->tm_sec, t->tm_min, | |
438 | t->tm_hour, t->tm_mday, | |
439 | t->tm_mon, t->tm_year, t->tm_wday); | |
440 | ||
22652ba7 | 441 | return 0; |
1abb0dc9 DB |
442 | } |
443 | ||
444 | static int ds1307_set_time(struct device *dev, struct rtc_time *t) | |
445 | { | |
446 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
e48585de | 447 | const struct chip_desc *chip = &chips[ds1307->type]; |
1abb0dc9 DB |
448 | int result; |
449 | int tmp; | |
042fa8c7 | 450 | u8 regs[7]; |
1abb0dc9 DB |
451 | |
452 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
453 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
11966adc JG |
454 | "write", t->tm_sec, t->tm_min, |
455 | t->tm_hour, t->tm_mday, | |
456 | t->tm_mon, t->tm_year, t->tm_wday); | |
1abb0dc9 | 457 | |
50d6c0ea AB |
458 | if (t->tm_year < 100) |
459 | return -EINVAL; | |
460 | ||
e48585de HK |
461 | #ifdef CONFIG_RTC_DRV_DS1307_CENTURY |
462 | if (t->tm_year > (chip->century_bit ? 299 : 199)) | |
463 | return -EINVAL; | |
50d6c0ea | 464 | #else |
e48585de | 465 | if (t->tm_year > 199) |
50d6c0ea AB |
466 | return -EINVAL; |
467 | #endif | |
468 | ||
042fa8c7 AB |
469 | regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec); |
470 | regs[DS1307_REG_MIN] = bin2bcd(t->tm_min); | |
471 | regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); | |
472 | regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); | |
473 | regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); | |
474 | regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); | |
1abb0dc9 DB |
475 | |
476 | /* assume 20YY not 19YY */ | |
477 | tmp = t->tm_year - 100; | |
042fa8c7 | 478 | regs[DS1307_REG_YEAR] = bin2bcd(tmp); |
1abb0dc9 | 479 | |
e48585de | 480 | if (chip->century_enable_bit) |
042fa8c7 | 481 | regs[chip->century_reg] |= chip->century_enable_bit; |
e48585de | 482 | if (t->tm_year > 199 && chip->century_bit) |
042fa8c7 | 483 | regs[chip->century_reg] |= chip->century_bit; |
e48585de HK |
484 | |
485 | if (ds1307->type == mcp794xx) { | |
40ce972d DA |
486 | /* |
487 | * these bits were cleared when preparing the date/time | |
488 | * values and need to be set again before writing the | |
042fa8c7 | 489 | * regsfer out to the device. |
40ce972d | 490 | */ |
042fa8c7 AB |
491 | regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST; |
492 | regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; | |
be5f59f4 | 493 | } |
1abb0dc9 | 494 | |
042fa8c7 | 495 | dev_dbg(dev, "%s: %7ph\n", "write", regs); |
1abb0dc9 | 496 | |
042fa8c7 AB |
497 | result = regmap_bulk_write(ds1307->regmap, chip->offset, regs, |
498 | sizeof(regs)); | |
11e5890b | 499 | if (result) { |
fed40b73 BS |
500 | dev_err(dev, "%s error %d\n", "write", result); |
501 | return result; | |
1abb0dc9 DB |
502 | } |
503 | return 0; | |
504 | } | |
505 | ||
74d88eb2 | 506 | static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 | 507 | { |
11e5890b | 508 | struct ds1307 *ds1307 = dev_get_drvdata(dev); |
cb49a5e9 | 509 | int ret; |
042fa8c7 | 510 | u8 regs[9]; |
cb49a5e9 RG |
511 | |
512 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
513 | return -EINVAL; | |
514 | ||
515 | /* read all ALARM1, ALARM2, and status registers at once */ | |
11e5890b | 516 | ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, |
042fa8c7 | 517 | regs, sizeof(regs)); |
11e5890b | 518 | if (ret) { |
cb49a5e9 | 519 | dev_err(dev, "%s error %d\n", "alarm read", ret); |
11e5890b | 520 | return ret; |
cb49a5e9 RG |
521 | } |
522 | ||
ff67abd2 | 523 | dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read", |
042fa8c7 | 524 | ®s[0], ®s[4], ®s[7]); |
cb49a5e9 | 525 | |
40ce972d DA |
526 | /* |
527 | * report alarm time (ALARM1); assume 24 hour and day-of-month modes, | |
cb49a5e9 RG |
528 | * and that all four fields are checked matches |
529 | */ | |
042fa8c7 AB |
530 | t->time.tm_sec = bcd2bin(regs[0] & 0x7f); |
531 | t->time.tm_min = bcd2bin(regs[1] & 0x7f); | |
532 | t->time.tm_hour = bcd2bin(regs[2] & 0x3f); | |
533 | t->time.tm_mday = bcd2bin(regs[3] & 0x3f); | |
cb49a5e9 RG |
534 | |
535 | /* ... and status */ | |
042fa8c7 AB |
536 | t->enabled = !!(regs[7] & DS1337_BIT_A1IE); |
537 | t->pending = !!(regs[8] & DS1337_BIT_A1I); | |
cb49a5e9 RG |
538 | |
539 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
540 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
541 | "alarm read", t->time.tm_sec, t->time.tm_min, | |
542 | t->time.tm_hour, t->time.tm_mday, | |
543 | t->enabled, t->pending); | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
74d88eb2 | 548 | static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 | 549 | { |
11e5890b | 550 | struct ds1307 *ds1307 = dev_get_drvdata(dev); |
042fa8c7 | 551 | unsigned char regs[9]; |
cb49a5e9 RG |
552 | u8 control, status; |
553 | int ret; | |
554 | ||
555 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
556 | return -EINVAL; | |
557 | ||
558 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
559 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
560 | "alarm set", t->time.tm_sec, t->time.tm_min, | |
561 | t->time.tm_hour, t->time.tm_mday, | |
562 | t->enabled, t->pending); | |
563 | ||
564 | /* read current status of both alarms and the chip */ | |
042fa8c7 AB |
565 | ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, |
566 | sizeof(regs)); | |
11e5890b | 567 | if (ret) { |
cb49a5e9 | 568 | dev_err(dev, "%s error %d\n", "alarm write", ret); |
11e5890b | 569 | return ret; |
cb49a5e9 | 570 | } |
042fa8c7 AB |
571 | control = regs[7]; |
572 | status = regs[8]; | |
cb49a5e9 | 573 | |
ff67abd2 | 574 | dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)", |
042fa8c7 | 575 | ®s[0], ®s[4], control, status); |
cb49a5e9 RG |
576 | |
577 | /* set ALARM1, using 24 hour and day-of-month modes */ | |
042fa8c7 AB |
578 | regs[0] = bin2bcd(t->time.tm_sec); |
579 | regs[1] = bin2bcd(t->time.tm_min); | |
580 | regs[2] = bin2bcd(t->time.tm_hour); | |
581 | regs[3] = bin2bcd(t->time.tm_mday); | |
cb49a5e9 RG |
582 | |
583 | /* set ALARM2 to non-garbage */ | |
042fa8c7 AB |
584 | regs[4] = 0; |
585 | regs[5] = 0; | |
586 | regs[6] = 0; | |
cb49a5e9 | 587 | |
5919fb97 | 588 | /* disable alarms */ |
042fa8c7 AB |
589 | regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); |
590 | regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); | |
cb49a5e9 | 591 | |
042fa8c7 AB |
592 | ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs, |
593 | sizeof(regs)); | |
11e5890b | 594 | if (ret) { |
cb49a5e9 | 595 | dev_err(dev, "can't set alarm time\n"); |
fed40b73 | 596 | return ret; |
cb49a5e9 RG |
597 | } |
598 | ||
5919fb97 NB |
599 | /* optionally enable ALARM1 */ |
600 | if (t->enabled) { | |
601 | dev_dbg(dev, "alarm IRQ armed\n"); | |
042fa8c7 AB |
602 | regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ |
603 | regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]); | |
5919fb97 NB |
604 | } |
605 | ||
cb49a5e9 RG |
606 | return 0; |
607 | } | |
608 | ||
16380c15 | 609 | static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) |
cb49a5e9 | 610 | { |
11e5890b | 611 | struct ds1307 *ds1307 = dev_get_drvdata(dev); |
cb49a5e9 | 612 | |
16380c15 JS |
613 | if (!test_bit(HAS_ALARM, &ds1307->flags)) |
614 | return -ENOTTY; | |
cb49a5e9 | 615 | |
078f3f64 HK |
616 | return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, |
617 | DS1337_BIT_A1IE, | |
618 | enabled ? DS1337_BIT_A1IE : 0); | |
cb49a5e9 RG |
619 | } |
620 | ||
ff8371ac | 621 | static const struct rtc_class_ops ds13xx_rtc_ops = { |
1abb0dc9 DB |
622 | .read_time = ds1307_get_time, |
623 | .set_time = ds1307_set_time, | |
74d88eb2 JR |
624 | .read_alarm = ds1337_read_alarm, |
625 | .set_alarm = ds1337_set_alarm, | |
16380c15 | 626 | .alarm_irq_enable = ds1307_alarm_irq_enable, |
1abb0dc9 DB |
627 | }; |
628 | ||
682d73f6 DB |
629 | /*----------------------------------------------------------------------*/ |
630 | ||
ee0981be MV |
631 | /* |
632 | * Alarm support for rx8130 devices. | |
633 | */ | |
634 | ||
635 | #define RX8130_REG_ALARM_MIN 0x07 | |
636 | #define RX8130_REG_ALARM_HOUR 0x08 | |
637 | #define RX8130_REG_ALARM_WEEK_OR_DAY 0x09 | |
638 | #define RX8130_REG_EXTENSION 0x0c | |
eb4fd190 | 639 | #define RX8130_REG_EXTENSION_WADA BIT(3) |
ee0981be | 640 | #define RX8130_REG_FLAG 0x0d |
eb4fd190 | 641 | #define RX8130_REG_FLAG_AF BIT(3) |
ee0981be | 642 | #define RX8130_REG_CONTROL0 0x0e |
eb4fd190 | 643 | #define RX8130_REG_CONTROL0_AIE BIT(3) |
ee0981be MV |
644 | |
645 | static irqreturn_t rx8130_irq(int irq, void *dev_id) | |
646 | { | |
647 | struct ds1307 *ds1307 = dev_id; | |
648 | struct mutex *lock = &ds1307->rtc->ops_lock; | |
649 | u8 ctl[3]; | |
650 | int ret; | |
651 | ||
652 | mutex_lock(lock); | |
653 | ||
654 | /* Read control registers. */ | |
f2b48012 AB |
655 | ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, |
656 | sizeof(ctl)); | |
ee0981be MV |
657 | if (ret < 0) |
658 | goto out; | |
659 | if (!(ctl[1] & RX8130_REG_FLAG_AF)) | |
660 | goto out; | |
661 | ctl[1] &= ~RX8130_REG_FLAG_AF; | |
662 | ctl[2] &= ~RX8130_REG_CONTROL0_AIE; | |
663 | ||
f2b48012 AB |
664 | ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, |
665 | sizeof(ctl)); | |
ee0981be MV |
666 | if (ret < 0) |
667 | goto out; | |
668 | ||
669 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); | |
670 | ||
671 | out: | |
672 | mutex_unlock(lock); | |
673 | ||
674 | return IRQ_HANDLED; | |
675 | } | |
676 | ||
677 | static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
678 | { | |
679 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
680 | u8 ald[3], ctl[3]; | |
681 | int ret; | |
682 | ||
683 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
684 | return -EINVAL; | |
685 | ||
686 | /* Read alarm registers. */ | |
f2b48012 AB |
687 | ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, |
688 | sizeof(ald)); | |
ee0981be MV |
689 | if (ret < 0) |
690 | return ret; | |
691 | ||
692 | /* Read control registers. */ | |
f2b48012 AB |
693 | ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, |
694 | sizeof(ctl)); | |
ee0981be MV |
695 | if (ret < 0) |
696 | return ret; | |
697 | ||
698 | t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE); | |
699 | t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF); | |
700 | ||
701 | /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ | |
702 | t->time.tm_sec = -1; | |
703 | t->time.tm_min = bcd2bin(ald[0] & 0x7f); | |
704 | t->time.tm_hour = bcd2bin(ald[1] & 0x7f); | |
705 | t->time.tm_wday = -1; | |
706 | t->time.tm_mday = bcd2bin(ald[2] & 0x7f); | |
707 | t->time.tm_mon = -1; | |
708 | t->time.tm_year = -1; | |
709 | t->time.tm_yday = -1; | |
710 | t->time.tm_isdst = -1; | |
711 | ||
712 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n", | |
713 | __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour, | |
714 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled); | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
719 | static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |
720 | { | |
721 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
722 | u8 ald[3], ctl[3]; | |
723 | int ret; | |
724 | ||
725 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
726 | return -EINVAL; | |
727 | ||
728 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " | |
729 | "enabled=%d pending=%d\n", __func__, | |
730 | t->time.tm_sec, t->time.tm_min, t->time.tm_hour, | |
731 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, | |
732 | t->enabled, t->pending); | |
733 | ||
734 | /* Read control registers. */ | |
f2b48012 AB |
735 | ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl, |
736 | sizeof(ctl)); | |
ee0981be MV |
737 | if (ret < 0) |
738 | return ret; | |
739 | ||
740 | ctl[0] &= ~RX8130_REG_EXTENSION_WADA; | |
741 | ctl[1] |= RX8130_REG_FLAG_AF; | |
742 | ctl[2] &= ~RX8130_REG_CONTROL0_AIE; | |
743 | ||
f2b48012 AB |
744 | ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, |
745 | sizeof(ctl)); | |
ee0981be MV |
746 | if (ret < 0) |
747 | return ret; | |
748 | ||
749 | /* Hardware alarm precision is 1 minute! */ | |
750 | ald[0] = bin2bcd(t->time.tm_min); | |
751 | ald[1] = bin2bcd(t->time.tm_hour); | |
752 | ald[2] = bin2bcd(t->time.tm_mday); | |
753 | ||
f2b48012 AB |
754 | ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald, |
755 | sizeof(ald)); | |
ee0981be MV |
756 | if (ret < 0) |
757 | return ret; | |
758 | ||
759 | if (!t->enabled) | |
760 | return 0; | |
761 | ||
762 | ctl[2] |= RX8130_REG_CONTROL0_AIE; | |
763 | ||
f2b48012 AB |
764 | return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, |
765 | sizeof(ctl)); | |
ee0981be MV |
766 | } |
767 | ||
768 | static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) | |
769 | { | |
770 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
771 | int ret, reg; | |
772 | ||
773 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
774 | return -EINVAL; | |
775 | ||
776 | ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); | |
777 | if (ret < 0) | |
778 | return ret; | |
779 | ||
780 | if (enabled) | |
781 | reg |= RX8130_REG_CONTROL0_AIE; | |
782 | else | |
783 | reg &= ~RX8130_REG_CONTROL0_AIE; | |
784 | ||
785 | return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); | |
786 | } | |
787 | ||
ee0981be MV |
788 | /*----------------------------------------------------------------------*/ |
789 | ||
1d1945d2 | 790 | /* |
f4199f85 | 791 | * Alarm support for mcp794xx devices. |
1d1945d2 SG |
792 | */ |
793 | ||
f4199f85 TN |
794 | #define MCP794XX_REG_CONTROL 0x07 |
795 | # define MCP794XX_BIT_ALM0_EN 0x10 | |
796 | # define MCP794XX_BIT_ALM1_EN 0x20 | |
797 | #define MCP794XX_REG_ALARM0_BASE 0x0a | |
798 | #define MCP794XX_REG_ALARM0_CTRL 0x0d | |
799 | #define MCP794XX_REG_ALARM1_BASE 0x11 | |
800 | #define MCP794XX_REG_ALARM1_CTRL 0x14 | |
eb4fd190 AB |
801 | # define MCP794XX_BIT_ALMX_IF BIT(3) |
802 | # define MCP794XX_BIT_ALMX_C0 BIT(4) | |
803 | # define MCP794XX_BIT_ALMX_C1 BIT(5) | |
804 | # define MCP794XX_BIT_ALMX_C2 BIT(6) | |
805 | # define MCP794XX_BIT_ALMX_POL BIT(7) | |
f4199f85 TN |
806 | # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ |
807 | MCP794XX_BIT_ALMX_C1 | \ | |
808 | MCP794XX_BIT_ALMX_C2) | |
809 | ||
2fb07a10 | 810 | static irqreturn_t mcp794xx_irq(int irq, void *dev_id) |
1d1945d2 | 811 | { |
11e5890b | 812 | struct ds1307 *ds1307 = dev_id; |
2fb07a10 | 813 | struct mutex *lock = &ds1307->rtc->ops_lock; |
1d1945d2 SG |
814 | int reg, ret; |
815 | ||
2fb07a10 | 816 | mutex_lock(lock); |
1d1945d2 SG |
817 | |
818 | /* Check and clear alarm 0 interrupt flag. */ | |
11e5890b HK |
819 | ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); |
820 | if (ret) | |
1d1945d2 | 821 | goto out; |
f4199f85 | 822 | if (!(reg & MCP794XX_BIT_ALMX_IF)) |
1d1945d2 | 823 | goto out; |
f4199f85 | 824 | reg &= ~MCP794XX_BIT_ALMX_IF; |
11e5890b HK |
825 | ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); |
826 | if (ret) | |
1d1945d2 SG |
827 | goto out; |
828 | ||
829 | /* Disable alarm 0. */ | |
078f3f64 HK |
830 | ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, |
831 | MCP794XX_BIT_ALM0_EN, 0); | |
11e5890b | 832 | if (ret) |
1d1945d2 SG |
833 | goto out; |
834 | ||
835 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); | |
836 | ||
837 | out: | |
2fb07a10 FB |
838 | mutex_unlock(lock); |
839 | ||
840 | return IRQ_HANDLED; | |
1d1945d2 SG |
841 | } |
842 | ||
f4199f85 | 843 | static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
1d1945d2 | 844 | { |
11e5890b | 845 | struct ds1307 *ds1307 = dev_get_drvdata(dev); |
042fa8c7 | 846 | u8 regs[10]; |
1d1945d2 SG |
847 | int ret; |
848 | ||
849 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
850 | return -EINVAL; | |
851 | ||
852 | /* Read control and alarm 0 registers. */ | |
042fa8c7 AB |
853 | ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, |
854 | sizeof(regs)); | |
11e5890b | 855 | if (ret) |
1d1945d2 SG |
856 | return ret; |
857 | ||
f4199f85 | 858 | t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); |
1d1945d2 SG |
859 | |
860 | /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ | |
042fa8c7 AB |
861 | t->time.tm_sec = bcd2bin(regs[3] & 0x7f); |
862 | t->time.tm_min = bcd2bin(regs[4] & 0x7f); | |
863 | t->time.tm_hour = bcd2bin(regs[5] & 0x3f); | |
864 | t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1; | |
865 | t->time.tm_mday = bcd2bin(regs[7] & 0x3f); | |
866 | t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1; | |
1d1945d2 SG |
867 | t->time.tm_year = -1; |
868 | t->time.tm_yday = -1; | |
869 | t->time.tm_isdst = -1; | |
870 | ||
871 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " | |
eb4fd190 | 872 | "enabled=%d polarity=%d irq=%d match=%lu\n", __func__, |
1d1945d2 SG |
873 | t->time.tm_sec, t->time.tm_min, t->time.tm_hour, |
874 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, | |
042fa8c7 AB |
875 | !!(regs[6] & MCP794XX_BIT_ALMX_POL), |
876 | !!(regs[6] & MCP794XX_BIT_ALMX_IF), | |
877 | (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); | |
1d1945d2 SG |
878 | |
879 | return 0; | |
880 | } | |
881 | ||
584ce30c HK |
882 | /* |
883 | * We may have a random RTC weekday, therefore calculate alarm weekday based | |
884 | * on current weekday we read from the RTC timekeeping regs | |
885 | */ | |
886 | static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) | |
887 | { | |
888 | struct rtc_time tm_now; | |
889 | int days_now, days_alarm, ret; | |
890 | ||
891 | ret = ds1307_get_time(dev, &tm_now); | |
892 | if (ret) | |
893 | return ret; | |
894 | ||
895 | days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60); | |
896 | days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60); | |
897 | ||
898 | return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1; | |
899 | } | |
900 | ||
f4199f85 | 901 | static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
1d1945d2 | 902 | { |
11e5890b | 903 | struct ds1307 *ds1307 = dev_get_drvdata(dev); |
042fa8c7 | 904 | unsigned char regs[10]; |
584ce30c | 905 | int wday, ret; |
1d1945d2 SG |
906 | |
907 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
908 | return -EINVAL; | |
909 | ||
584ce30c HK |
910 | wday = mcp794xx_alm_weekday(dev, &t->time); |
911 | if (wday < 0) | |
912 | return wday; | |
913 | ||
1d1945d2 SG |
914 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " |
915 | "enabled=%d pending=%d\n", __func__, | |
916 | t->time.tm_sec, t->time.tm_min, t->time.tm_hour, | |
917 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, | |
918 | t->enabled, t->pending); | |
919 | ||
920 | /* Read control and alarm 0 registers. */ | |
042fa8c7 AB |
921 | ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs, |
922 | sizeof(regs)); | |
11e5890b | 923 | if (ret) |
1d1945d2 SG |
924 | return ret; |
925 | ||
926 | /* Set alarm 0, using 24-hour and day-of-month modes. */ | |
927 | regs[3] = bin2bcd(t->time.tm_sec); | |
928 | regs[4] = bin2bcd(t->time.tm_min); | |
929 | regs[5] = bin2bcd(t->time.tm_hour); | |
584ce30c | 930 | regs[6] = wday; |
1d1945d2 | 931 | regs[7] = bin2bcd(t->time.tm_mday); |
62c8c20a | 932 | regs[8] = bin2bcd(t->time.tm_mon + 1); |
1d1945d2 SG |
933 | |
934 | /* Clear the alarm 0 interrupt flag. */ | |
f4199f85 | 935 | regs[6] &= ~MCP794XX_BIT_ALMX_IF; |
1d1945d2 | 936 | /* Set alarm match: second, minute, hour, day, date, month. */ |
f4199f85 | 937 | regs[6] |= MCP794XX_MSK_ALMX_MATCH; |
e3edd671 NM |
938 | /* Disable interrupt. We will not enable until completely programmed */ |
939 | regs[0] &= ~MCP794XX_BIT_ALM0_EN; | |
1d1945d2 | 940 | |
042fa8c7 AB |
941 | ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs, |
942 | sizeof(regs)); | |
11e5890b | 943 | if (ret) |
1d1945d2 SG |
944 | return ret; |
945 | ||
e3edd671 NM |
946 | if (!t->enabled) |
947 | return 0; | |
948 | regs[0] |= MCP794XX_BIT_ALM0_EN; | |
11e5890b | 949 | return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]); |
1d1945d2 SG |
950 | } |
951 | ||
f4199f85 | 952 | static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) |
1d1945d2 | 953 | { |
11e5890b | 954 | struct ds1307 *ds1307 = dev_get_drvdata(dev); |
1d1945d2 SG |
955 | |
956 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
957 | return -EINVAL; | |
958 | ||
078f3f64 HK |
959 | return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL, |
960 | MCP794XX_BIT_ALM0_EN, | |
961 | enabled ? MCP794XX_BIT_ALM0_EN : 0); | |
1d1945d2 SG |
962 | } |
963 | ||
1d1945d2 SG |
964 | /*----------------------------------------------------------------------*/ |
965 | ||
abc925f7 AB |
966 | static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, |
967 | size_t bytes) | |
682d73f6 | 968 | { |
abc925f7 | 969 | struct ds1307 *ds1307 = priv; |
969fa07b | 970 | const struct chip_desc *chip = &chips[ds1307->type]; |
682d73f6 | 971 | |
969fa07b | 972 | return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset, |
abc925f7 | 973 | val, bytes); |
682d73f6 DB |
974 | } |
975 | ||
abc925f7 AB |
976 | static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, |
977 | size_t bytes) | |
682d73f6 | 978 | { |
abc925f7 | 979 | struct ds1307 *ds1307 = priv; |
969fa07b | 980 | const struct chip_desc *chip = &chips[ds1307->type]; |
682d73f6 | 981 | |
969fa07b | 982 | return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset, |
abc925f7 | 983 | val, bytes); |
682d73f6 DB |
984 | } |
985 | ||
682d73f6 DB |
986 | /*----------------------------------------------------------------------*/ |
987 | ||
11e5890b | 988 | static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, |
57ec2d95 | 989 | u32 ohms, bool diode) |
33b04b7b MV |
990 | { |
991 | u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : | |
992 | DS1307_TRICKLE_CHARGER_NO_DIODE; | |
993 | ||
994 | switch (ohms) { | |
995 | case 250: | |
996 | setup |= DS1307_TRICKLE_CHARGER_250_OHM; | |
997 | break; | |
998 | case 2000: | |
999 | setup |= DS1307_TRICKLE_CHARGER_2K_OHM; | |
1000 | break; | |
1001 | case 4000: | |
1002 | setup |= DS1307_TRICKLE_CHARGER_4K_OHM; | |
1003 | break; | |
1004 | default: | |
11e5890b | 1005 | dev_warn(ds1307->dev, |
33b04b7b MV |
1006 | "Unsupported ohm value %u in dt\n", ohms); |
1007 | return 0; | |
1008 | } | |
1009 | return setup; | |
1010 | } | |
1011 | ||
d8490fd5 | 1012 | static u8 ds1307_trickle_init(struct ds1307 *ds1307, |
7624df48 | 1013 | const struct chip_desc *chip) |
33b04b7b | 1014 | { |
57ec2d95 | 1015 | u32 ohms; |
33b04b7b MV |
1016 | bool diode = true; |
1017 | ||
1018 | if (!chip->do_trickle_setup) | |
d8490fd5 HK |
1019 | return 0; |
1020 | ||
11e5890b HK |
1021 | if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms", |
1022 | &ohms)) | |
d8490fd5 HK |
1023 | return 0; |
1024 | ||
11e5890b | 1025 | if (device_property_read_bool(ds1307->dev, "trickle-diode-disable")) |
33b04b7b | 1026 | diode = false; |
d8490fd5 HK |
1027 | |
1028 | return chip->do_trickle_setup(ds1307, ohms, diode); | |
33b04b7b MV |
1029 | } |
1030 | ||
445c0207 AM |
1031 | /*----------------------------------------------------------------------*/ |
1032 | ||
1033 | #ifdef CONFIG_RTC_DRV_DS1307_HWMON | |
1034 | ||
1035 | /* | |
1036 | * Temperature sensor support for ds3231 devices. | |
1037 | */ | |
1038 | ||
1039 | #define DS3231_REG_TEMPERATURE 0x11 | |
1040 | ||
1041 | /* | |
1042 | * A user-initiated temperature conversion is not started by this function, | |
1043 | * so the temperature is updated once every 64 seconds. | |
1044 | */ | |
9a3dce62 | 1045 | static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) |
445c0207 AM |
1046 | { |
1047 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
1048 | u8 temp_buf[2]; | |
1049 | s16 temp; | |
1050 | int ret; | |
1051 | ||
11e5890b HK |
1052 | ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE, |
1053 | temp_buf, sizeof(temp_buf)); | |
1054 | if (ret) | |
445c0207 | 1055 | return ret; |
445c0207 AM |
1056 | /* |
1057 | * Temperature is represented as a 10-bit code with a resolution of | |
1058 | * 0.25 degree celsius and encoded in two's complement format. | |
1059 | */ | |
1060 | temp = (temp_buf[0] << 8) | temp_buf[1]; | |
1061 | temp >>= 6; | |
1062 | *mC = temp * 250; | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | static ssize_t ds3231_hwmon_show_temp(struct device *dev, | |
4057a66e | 1068 | struct device_attribute *attr, char *buf) |
445c0207 AM |
1069 | { |
1070 | int ret; | |
9a3dce62 | 1071 | s32 temp; |
445c0207 AM |
1072 | |
1073 | ret = ds3231_hwmon_read_temp(dev, &temp); | |
1074 | if (ret) | |
1075 | return ret; | |
1076 | ||
1077 | return sprintf(buf, "%d\n", temp); | |
1078 | } | |
b4be271c | 1079 | static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, |
4057a66e | 1080 | NULL, 0); |
445c0207 AM |
1081 | |
1082 | static struct attribute *ds3231_hwmon_attrs[] = { | |
1083 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
1084 | NULL, | |
1085 | }; | |
1086 | ATTRIBUTE_GROUPS(ds3231_hwmon); | |
1087 | ||
1088 | static void ds1307_hwmon_register(struct ds1307 *ds1307) | |
1089 | { | |
1090 | struct device *dev; | |
1091 | ||
1092 | if (ds1307->type != ds_3231) | |
1093 | return; | |
1094 | ||
11e5890b | 1095 | dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name, |
4057a66e AB |
1096 | ds1307, |
1097 | ds3231_hwmon_groups); | |
445c0207 | 1098 | if (IS_ERR(dev)) { |
11e5890b HK |
1099 | dev_warn(ds1307->dev, "unable to register hwmon device %ld\n", |
1100 | PTR_ERR(dev)); | |
445c0207 AM |
1101 | } |
1102 | } | |
1103 | ||
1104 | #else | |
1105 | ||
1106 | static void ds1307_hwmon_register(struct ds1307 *ds1307) | |
1107 | { | |
1108 | } | |
1109 | ||
6c6ff145 AM |
1110 | #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ |
1111 | ||
1112 | /*----------------------------------------------------------------------*/ | |
1113 | ||
1114 | /* | |
1115 | * Square-wave output support for DS3231 | |
1116 | * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf | |
1117 | */ | |
1118 | #ifdef CONFIG_COMMON_CLK | |
1119 | ||
1120 | enum { | |
1121 | DS3231_CLK_SQW = 0, | |
1122 | DS3231_CLK_32KHZ, | |
1123 | }; | |
1124 | ||
1125 | #define clk_sqw_to_ds1307(clk) \ | |
1126 | container_of(clk, struct ds1307, clks[DS3231_CLK_SQW]) | |
1127 | #define clk_32khz_to_ds1307(clk) \ | |
1128 | container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ]) | |
1129 | ||
1130 | static int ds3231_clk_sqw_rates[] = { | |
1131 | 1, | |
1132 | 1024, | |
1133 | 4096, | |
1134 | 8192, | |
1135 | }; | |
1136 | ||
1137 | static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) | |
1138 | { | |
6c6ff145 | 1139 | struct mutex *lock = &ds1307->rtc->ops_lock; |
6c6ff145 AM |
1140 | int ret; |
1141 | ||
1142 | mutex_lock(lock); | |
078f3f64 HK |
1143 | ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL, |
1144 | mask, value); | |
6c6ff145 AM |
1145 | mutex_unlock(lock); |
1146 | ||
1147 | return ret; | |
1148 | } | |
1149 | ||
1150 | static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, | |
1151 | unsigned long parent_rate) | |
1152 | { | |
1153 | struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); | |
11e5890b | 1154 | int control, ret; |
6c6ff145 AM |
1155 | int rate_sel = 0; |
1156 | ||
11e5890b HK |
1157 | ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); |
1158 | if (ret) | |
1159 | return ret; | |
6c6ff145 AM |
1160 | if (control & DS1337_BIT_RS1) |
1161 | rate_sel += 1; | |
1162 | if (control & DS1337_BIT_RS2) | |
1163 | rate_sel += 2; | |
1164 | ||
1165 | return ds3231_clk_sqw_rates[rate_sel]; | |
1166 | } | |
1167 | ||
1168 | static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, | |
4057a66e | 1169 | unsigned long *prate) |
6c6ff145 AM |
1170 | { |
1171 | int i; | |
1172 | ||
1173 | for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) { | |
1174 | if (ds3231_clk_sqw_rates[i] <= rate) | |
1175 | return ds3231_clk_sqw_rates[i]; | |
1176 | } | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, | |
4057a66e | 1182 | unsigned long parent_rate) |
6c6ff145 AM |
1183 | { |
1184 | struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); | |
1185 | int control = 0; | |
1186 | int rate_sel; | |
1187 | ||
1188 | for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates); | |
1189 | rate_sel++) { | |
1190 | if (ds3231_clk_sqw_rates[rate_sel] == rate) | |
1191 | break; | |
1192 | } | |
1193 | ||
1194 | if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates)) | |
1195 | return -EINVAL; | |
1196 | ||
1197 | if (rate_sel & 1) | |
1198 | control |= DS1337_BIT_RS1; | |
1199 | if (rate_sel & 2) | |
1200 | control |= DS1337_BIT_RS2; | |
1201 | ||
1202 | return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2, | |
1203 | control); | |
1204 | } | |
1205 | ||
1206 | static int ds3231_clk_sqw_prepare(struct clk_hw *hw) | |
1207 | { | |
1208 | struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); | |
1209 | ||
1210 | return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0); | |
1211 | } | |
1212 | ||
1213 | static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) | |
1214 | { | |
1215 | struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); | |
1216 | ||
1217 | ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN); | |
1218 | } | |
1219 | ||
1220 | static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) | |
1221 | { | |
1222 | struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw); | |
11e5890b | 1223 | int control, ret; |
6c6ff145 | 1224 | |
11e5890b HK |
1225 | ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control); |
1226 | if (ret) | |
1227 | return ret; | |
6c6ff145 AM |
1228 | |
1229 | return !(control & DS1337_BIT_INTCN); | |
1230 | } | |
1231 | ||
1232 | static const struct clk_ops ds3231_clk_sqw_ops = { | |
1233 | .prepare = ds3231_clk_sqw_prepare, | |
1234 | .unprepare = ds3231_clk_sqw_unprepare, | |
1235 | .is_prepared = ds3231_clk_sqw_is_prepared, | |
1236 | .recalc_rate = ds3231_clk_sqw_recalc_rate, | |
1237 | .round_rate = ds3231_clk_sqw_round_rate, | |
1238 | .set_rate = ds3231_clk_sqw_set_rate, | |
1239 | }; | |
1240 | ||
1241 | static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, | |
4057a66e | 1242 | unsigned long parent_rate) |
6c6ff145 AM |
1243 | { |
1244 | return 32768; | |
1245 | } | |
1246 | ||
1247 | static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) | |
1248 | { | |
6c6ff145 | 1249 | struct mutex *lock = &ds1307->rtc->ops_lock; |
6c6ff145 AM |
1250 | int ret; |
1251 | ||
1252 | mutex_lock(lock); | |
078f3f64 HK |
1253 | ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS, |
1254 | DS3231_BIT_EN32KHZ, | |
1255 | enable ? DS3231_BIT_EN32KHZ : 0); | |
6c6ff145 AM |
1256 | mutex_unlock(lock); |
1257 | ||
1258 | return ret; | |
1259 | } | |
1260 | ||
1261 | static int ds3231_clk_32khz_prepare(struct clk_hw *hw) | |
1262 | { | |
1263 | struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); | |
1264 | ||
1265 | return ds3231_clk_32khz_control(ds1307, true); | |
1266 | } | |
1267 | ||
1268 | static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) | |
1269 | { | |
1270 | struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); | |
1271 | ||
1272 | ds3231_clk_32khz_control(ds1307, false); | |
1273 | } | |
1274 | ||
1275 | static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) | |
1276 | { | |
1277 | struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw); | |
11e5890b | 1278 | int status, ret; |
6c6ff145 | 1279 | |
11e5890b HK |
1280 | ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status); |
1281 | if (ret) | |
1282 | return ret; | |
6c6ff145 AM |
1283 | |
1284 | return !!(status & DS3231_BIT_EN32KHZ); | |
1285 | } | |
1286 | ||
1287 | static const struct clk_ops ds3231_clk_32khz_ops = { | |
1288 | .prepare = ds3231_clk_32khz_prepare, | |
1289 | .unprepare = ds3231_clk_32khz_unprepare, | |
1290 | .is_prepared = ds3231_clk_32khz_is_prepared, | |
1291 | .recalc_rate = ds3231_clk_32khz_recalc_rate, | |
1292 | }; | |
1293 | ||
1294 | static struct clk_init_data ds3231_clks_init[] = { | |
1295 | [DS3231_CLK_SQW] = { | |
1296 | .name = "ds3231_clk_sqw", | |
1297 | .ops = &ds3231_clk_sqw_ops, | |
6c6ff145 AM |
1298 | }, |
1299 | [DS3231_CLK_32KHZ] = { | |
1300 | .name = "ds3231_clk_32khz", | |
1301 | .ops = &ds3231_clk_32khz_ops, | |
6c6ff145 AM |
1302 | }, |
1303 | }; | |
1304 | ||
1305 | static int ds3231_clks_register(struct ds1307 *ds1307) | |
1306 | { | |
11e5890b | 1307 | struct device_node *node = ds1307->dev->of_node; |
6c6ff145 AM |
1308 | struct clk_onecell_data *onecell; |
1309 | int i; | |
1310 | ||
11e5890b | 1311 | onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL); |
6c6ff145 AM |
1312 | if (!onecell) |
1313 | return -ENOMEM; | |
1314 | ||
1315 | onecell->clk_num = ARRAY_SIZE(ds3231_clks_init); | |
11e5890b HK |
1316 | onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num, |
1317 | sizeof(onecell->clks[0]), GFP_KERNEL); | |
6c6ff145 AM |
1318 | if (!onecell->clks) |
1319 | return -ENOMEM; | |
1320 | ||
1321 | for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) { | |
1322 | struct clk_init_data init = ds3231_clks_init[i]; | |
1323 | ||
1324 | /* | |
1325 | * Interrupt signal due to alarm conditions and square-wave | |
1326 | * output share same pin, so don't initialize both. | |
1327 | */ | |
1328 | if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags)) | |
1329 | continue; | |
1330 | ||
1331 | /* optional override of the clockname */ | |
1332 | of_property_read_string_index(node, "clock-output-names", i, | |
4057a66e | 1333 | &init.name); |
6c6ff145 AM |
1334 | ds1307->clks[i].init = &init; |
1335 | ||
11e5890b HK |
1336 | onecell->clks[i] = devm_clk_register(ds1307->dev, |
1337 | &ds1307->clks[i]); | |
6c6ff145 AM |
1338 | if (IS_ERR(onecell->clks[i])) |
1339 | return PTR_ERR(onecell->clks[i]); | |
1340 | } | |
1341 | ||
1342 | if (!node) | |
1343 | return 0; | |
1344 | ||
1345 | of_clk_add_provider(node, of_clk_src_onecell_get, onecell); | |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | static void ds1307_clks_register(struct ds1307 *ds1307) | |
1351 | { | |
1352 | int ret; | |
1353 | ||
1354 | if (ds1307->type != ds_3231) | |
1355 | return; | |
1356 | ||
1357 | ret = ds3231_clks_register(ds1307); | |
1358 | if (ret) { | |
11e5890b HK |
1359 | dev_warn(ds1307->dev, "unable to register clock device %d\n", |
1360 | ret); | |
6c6ff145 AM |
1361 | } |
1362 | } | |
1363 | ||
1364 | #else | |
1365 | ||
1366 | static void ds1307_clks_register(struct ds1307 *ds1307) | |
1367 | { | |
1368 | } | |
1369 | ||
1370 | #endif /* CONFIG_COMMON_CLK */ | |
445c0207 | 1371 | |
11e5890b HK |
1372 | static const struct regmap_config regmap_config = { |
1373 | .reg_bits = 8, | |
1374 | .val_bits = 8, | |
51ed73eb | 1375 | .max_register = 0x9, |
11e5890b HK |
1376 | }; |
1377 | ||
5a167f45 GKH |
1378 | static int ds1307_probe(struct i2c_client *client, |
1379 | const struct i2c_device_id *id) | |
1abb0dc9 DB |
1380 | { |
1381 | struct ds1307 *ds1307; | |
1382 | int err = -ENODEV; | |
584ce30c | 1383 | int tmp; |
7624df48 | 1384 | const struct chip_desc *chip; |
82e2d43f | 1385 | bool want_irq; |
8bc2a407 | 1386 | bool ds1307_can_wakeup_device = false; |
042fa8c7 | 1387 | unsigned char regs[8]; |
01ce893d | 1388 | struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); |
d8490fd5 | 1389 | u8 trickle_charger_setup = 0; |
1abb0dc9 | 1390 | |
edca66d2 | 1391 | ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); |
40ce972d | 1392 | if (!ds1307) |
c065f35c | 1393 | return -ENOMEM; |
045e0e85 | 1394 | |
11e5890b HK |
1395 | dev_set_drvdata(&client->dev, ds1307); |
1396 | ds1307->dev = &client->dev; | |
1397 | ds1307->name = client->name; | |
11e5890b HK |
1398 | |
1399 | ds1307->regmap = devm_regmap_init_i2c(client, ®map_config); | |
1400 | if (IS_ERR(ds1307->regmap)) { | |
1401 | dev_err(ds1307->dev, "regmap allocation failed\n"); | |
1402 | return PTR_ERR(ds1307->regmap); | |
1403 | } | |
33df2ee1 | 1404 | |
11e5890b | 1405 | i2c_set_clientdata(client, ds1307); |
7ef6d2c2 JMC |
1406 | |
1407 | if (client->dev.of_node) { | |
1408 | ds1307->type = (enum ds_type) | |
1409 | of_device_get_match_data(&client->dev); | |
1410 | chip = &chips[ds1307->type]; | |
1411 | } else if (id) { | |
9c19b893 TH |
1412 | chip = &chips[id->driver_data]; |
1413 | ds1307->type = id->driver_data; | |
1414 | } else { | |
1415 | const struct acpi_device_id *acpi_id; | |
1416 | ||
1417 | acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids), | |
11e5890b | 1418 | ds1307->dev); |
9c19b893 TH |
1419 | if (!acpi_id) |
1420 | return -ENODEV; | |
1421 | chip = &chips[acpi_id->driver_data]; | |
1422 | ds1307->type = acpi_id->driver_data; | |
1423 | } | |
33df2ee1 | 1424 | |
82e2d43f HK |
1425 | want_irq = client->irq > 0 && chip->alarm; |
1426 | ||
9c19b893 | 1427 | if (!pdata) |
d8490fd5 | 1428 | trickle_charger_setup = ds1307_trickle_init(ds1307, chip); |
9c19b893 | 1429 | else if (pdata->trickle_charger_setup) |
d8490fd5 | 1430 | trickle_charger_setup = pdata->trickle_charger_setup; |
33b04b7b | 1431 | |
d8490fd5 HK |
1432 | if (trickle_charger_setup && chip->trickle_charger_reg) { |
1433 | trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC; | |
11e5890b HK |
1434 | dev_dbg(ds1307->dev, |
1435 | "writing trickle charger info 0x%x to 0x%x\n", | |
d8490fd5 | 1436 | trickle_charger_setup, chip->trickle_charger_reg); |
11e5890b | 1437 | regmap_write(ds1307->regmap, chip->trickle_charger_reg, |
d8490fd5 | 1438 | trickle_charger_setup); |
33b04b7b | 1439 | } |
eb86c306 | 1440 | |
8bc2a407 ML |
1441 | #ifdef CONFIG_OF |
1442 | /* | |
1443 | * For devices with no IRQ directly connected to the SoC, the RTC chip | |
1444 | * can be forced as a wakeup source by stating that explicitly in | |
1445 | * the device's .dts file using the "wakeup-source" boolean property. | |
1446 | * If the "wakeup-source" property is set, don't request an IRQ. | |
1447 | * This will guarantee the 'wakealarm' sysfs entry is available on the device, | |
1448 | * if supported by the RTC. | |
1449 | */ | |
82e2d43f HK |
1450 | if (chip->alarm && of_property_read_bool(client->dev.of_node, |
1451 | "wakeup-source")) | |
78aaa06d | 1452 | ds1307_can_wakeup_device = true; |
8bc2a407 ML |
1453 | #endif |
1454 | ||
045e0e85 DB |
1455 | switch (ds1307->type) { |
1456 | case ds_1337: | |
1457 | case ds_1339: | |
0759c886 | 1458 | case ds_1341: |
97f902b7 | 1459 | case ds_3231: |
be5f59f4 | 1460 | /* get registers that the "rtc" read below won't read... */ |
11e5890b | 1461 | err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL, |
042fa8c7 | 1462 | regs, 2); |
11e5890b HK |
1463 | if (err) { |
1464 | dev_dbg(ds1307->dev, "read error %d\n", err); | |
edca66d2 | 1465 | goto exit; |
1abb0dc9 DB |
1466 | } |
1467 | ||
be5f59f4 | 1468 | /* oscillator off? turn it on, so clock can tick. */ |
042fa8c7 AB |
1469 | if (regs[0] & DS1337_BIT_nEOSC) |
1470 | regs[0] &= ~DS1337_BIT_nEOSC; | |
cb49a5e9 | 1471 | |
40ce972d | 1472 | /* |
8bc2a407 ML |
1473 | * Using IRQ or defined as wakeup-source? |
1474 | * Disable the square wave and both alarms. | |
97f902b7 WS |
1475 | * For some variants, be sure alarms can trigger when we're |
1476 | * running on Vbackup (BBSQI/BBSQW) | |
cb49a5e9 | 1477 | */ |
82e2d43f | 1478 | if (want_irq || ds1307_can_wakeup_device) { |
042fa8c7 AB |
1479 | regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit; |
1480 | regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); | |
cb49a5e9 RG |
1481 | } |
1482 | ||
11e5890b | 1483 | regmap_write(ds1307->regmap, DS1337_REG_CONTROL, |
042fa8c7 | 1484 | regs[0]); |
be5f59f4 RG |
1485 | |
1486 | /* oscillator fault? clear flag, and warn */ | |
042fa8c7 | 1487 | if (regs[1] & DS1337_BIT_OSF) { |
11e5890b | 1488 | regmap_write(ds1307->regmap, DS1337_REG_STATUS, |
042fa8c7 | 1489 | regs[1] & ~DS1337_BIT_OSF); |
11e5890b | 1490 | dev_warn(ds1307->dev, "SET TIME!\n"); |
1abb0dc9 | 1491 | } |
045e0e85 | 1492 | break; |
a2166858 MF |
1493 | |
1494 | case rx_8025: | |
11e5890b | 1495 | err = regmap_bulk_read(ds1307->regmap, |
042fa8c7 | 1496 | RX8025_REG_CTRL1 << 4 | 0x08, regs, 2); |
11e5890b HK |
1497 | if (err) { |
1498 | dev_dbg(ds1307->dev, "read error %d\n", err); | |
edca66d2 | 1499 | goto exit; |
a2166858 MF |
1500 | } |
1501 | ||
1502 | /* oscillator off? turn it on, so clock can tick. */ | |
042fa8c7 AB |
1503 | if (!(regs[1] & RX8025_BIT_XST)) { |
1504 | regs[1] |= RX8025_BIT_XST; | |
11e5890b HK |
1505 | regmap_write(ds1307->regmap, |
1506 | RX8025_REG_CTRL2 << 4 | 0x08, | |
042fa8c7 | 1507 | regs[1]); |
11e5890b | 1508 | dev_warn(ds1307->dev, |
a2166858 MF |
1509 | "oscillator stop detected - SET TIME!\n"); |
1510 | } | |
1511 | ||
042fa8c7 AB |
1512 | if (regs[1] & RX8025_BIT_PON) { |
1513 | regs[1] &= ~RX8025_BIT_PON; | |
11e5890b HK |
1514 | regmap_write(ds1307->regmap, |
1515 | RX8025_REG_CTRL2 << 4 | 0x08, | |
042fa8c7 | 1516 | regs[1]); |
11e5890b | 1517 | dev_warn(ds1307->dev, "power-on detected\n"); |
a2166858 MF |
1518 | } |
1519 | ||
042fa8c7 AB |
1520 | if (regs[1] & RX8025_BIT_VDET) { |
1521 | regs[1] &= ~RX8025_BIT_VDET; | |
11e5890b HK |
1522 | regmap_write(ds1307->regmap, |
1523 | RX8025_REG_CTRL2 << 4 | 0x08, | |
042fa8c7 | 1524 | regs[1]); |
11e5890b | 1525 | dev_warn(ds1307->dev, "voltage drop detected\n"); |
a2166858 MF |
1526 | } |
1527 | ||
1528 | /* make sure we are running in 24hour mode */ | |
042fa8c7 | 1529 | if (!(regs[0] & RX8025_BIT_2412)) { |
a2166858 MF |
1530 | u8 hour; |
1531 | ||
1532 | /* switch to 24 hour mode */ | |
11e5890b HK |
1533 | regmap_write(ds1307->regmap, |
1534 | RX8025_REG_CTRL1 << 4 | 0x08, | |
042fa8c7 | 1535 | regs[0] | RX8025_BIT_2412); |
11e5890b HK |
1536 | |
1537 | err = regmap_bulk_read(ds1307->regmap, | |
1538 | RX8025_REG_CTRL1 << 4 | 0x08, | |
042fa8c7 | 1539 | regs, 2); |
11e5890b HK |
1540 | if (err) { |
1541 | dev_dbg(ds1307->dev, "read error %d\n", err); | |
edca66d2 | 1542 | goto exit; |
a2166858 MF |
1543 | } |
1544 | ||
1545 | /* correct hour */ | |
042fa8c7 | 1546 | hour = bcd2bin(regs[DS1307_REG_HOUR]); |
a2166858 MF |
1547 | if (hour == 12) |
1548 | hour = 0; | |
042fa8c7 | 1549 | if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) |
a2166858 MF |
1550 | hour += 12; |
1551 | ||
11e5890b HK |
1552 | regmap_write(ds1307->regmap, |
1553 | DS1307_REG_HOUR << 4 | 0x08, hour); | |
a2166858 MF |
1554 | } |
1555 | break; | |
045e0e85 DB |
1556 | default: |
1557 | break; | |
1558 | } | |
1abb0dc9 DB |
1559 | |
1560 | read_rtc: | |
1561 | /* read RTC registers */ | |
042fa8c7 AB |
1562 | err = regmap_bulk_read(ds1307->regmap, chip->offset, regs, |
1563 | sizeof(regs)); | |
11e5890b HK |
1564 | if (err) { |
1565 | dev_dbg(ds1307->dev, "read error %d\n", err); | |
edca66d2 | 1566 | goto exit; |
1abb0dc9 DB |
1567 | } |
1568 | ||
40ce972d DA |
1569 | /* |
1570 | * minimal sanity checking; some chips (like DS1340) don't | |
1abb0dc9 DB |
1571 | * specify the extra bits as must-be-zero, but there are |
1572 | * still a few values that are clearly out-of-range. | |
1573 | */ | |
042fa8c7 | 1574 | tmp = regs[DS1307_REG_SECS]; |
045e0e85 DB |
1575 | switch (ds1307->type) { |
1576 | case ds_1307: | |
8566f70c | 1577 | case m41t0: |
045e0e85 | 1578 | case m41t00: |
be5f59f4 | 1579 | /* clock halted? turn it on, so clock can tick. */ |
045e0e85 | 1580 | if (tmp & DS1307_BIT_CH) { |
11e5890b HK |
1581 | regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); |
1582 | dev_warn(ds1307->dev, "SET TIME!\n"); | |
045e0e85 | 1583 | goto read_rtc; |
1abb0dc9 | 1584 | } |
045e0e85 | 1585 | break; |
300a7735 | 1586 | case ds_1308: |
be5f59f4 RG |
1587 | case ds_1338: |
1588 | /* clock halted? turn it on, so clock can tick. */ | |
045e0e85 | 1589 | if (tmp & DS1307_BIT_CH) |
11e5890b | 1590 | regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); |
be5f59f4 RG |
1591 | |
1592 | /* oscillator fault? clear flag, and warn */ | |
042fa8c7 | 1593 | if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { |
11e5890b | 1594 | regmap_write(ds1307->regmap, DS1307_REG_CONTROL, |
4057a66e AB |
1595 | regs[DS1307_REG_CONTROL] & |
1596 | ~DS1338_BIT_OSF); | |
11e5890b | 1597 | dev_warn(ds1307->dev, "SET TIME!\n"); |
be5f59f4 RG |
1598 | goto read_rtc; |
1599 | } | |
045e0e85 | 1600 | break; |
fcd8db00 R |
1601 | case ds_1340: |
1602 | /* clock halted? turn it on, so clock can tick. */ | |
1603 | if (tmp & DS1340_BIT_nEOSC) | |
11e5890b | 1604 | regmap_write(ds1307->regmap, DS1307_REG_SECS, 0); |
fcd8db00 | 1605 | |
11e5890b HK |
1606 | err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp); |
1607 | if (err) { | |
1608 | dev_dbg(ds1307->dev, "read error %d\n", err); | |
edca66d2 | 1609 | goto exit; |
fcd8db00 R |
1610 | } |
1611 | ||
1612 | /* oscillator fault? clear flag, and warn */ | |
1613 | if (tmp & DS1340_BIT_OSF) { | |
11e5890b HK |
1614 | regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0); |
1615 | dev_warn(ds1307->dev, "SET TIME!\n"); | |
fcd8db00 | 1616 | } |
43fcb815 | 1617 | break; |
f4199f85 | 1618 | case mcp794xx: |
43fcb815 | 1619 | /* make sure that the backup battery is enabled */ |
042fa8c7 | 1620 | if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { |
11e5890b | 1621 | regmap_write(ds1307->regmap, DS1307_REG_WDAY, |
042fa8c7 | 1622 | regs[DS1307_REG_WDAY] | |
11e5890b | 1623 | MCP794XX_BIT_VBATEN); |
43fcb815 DA |
1624 | } |
1625 | ||
1626 | /* clock halted? turn it on, so clock can tick. */ | |
f4199f85 | 1627 | if (!(tmp & MCP794XX_BIT_ST)) { |
11e5890b HK |
1628 | regmap_write(ds1307->regmap, DS1307_REG_SECS, |
1629 | MCP794XX_BIT_ST); | |
1630 | dev_warn(ds1307->dev, "SET TIME!\n"); | |
43fcb815 DA |
1631 | goto read_rtc; |
1632 | } | |
1633 | ||
fcd8db00 | 1634 | break; |
32d322bc | 1635 | default: |
045e0e85 | 1636 | break; |
1abb0dc9 | 1637 | } |
045e0e85 | 1638 | |
042fa8c7 | 1639 | tmp = regs[DS1307_REG_HOUR]; |
c065f35c DB |
1640 | switch (ds1307->type) { |
1641 | case ds_1340: | |
8566f70c | 1642 | case m41t0: |
c065f35c | 1643 | case m41t00: |
40ce972d DA |
1644 | /* |
1645 | * NOTE: ignores century bits; fix before deploying | |
c065f35c DB |
1646 | * systems that will run through year 2100. |
1647 | */ | |
1648 | break; | |
a2166858 MF |
1649 | case rx_8025: |
1650 | break; | |
c065f35c DB |
1651 | default: |
1652 | if (!(tmp & DS1307_BIT_12HR)) | |
1653 | break; | |
1654 | ||
40ce972d DA |
1655 | /* |
1656 | * Be sure we're in 24 hour mode. Multi-master systems | |
c065f35c DB |
1657 | * take note... |
1658 | */ | |
fe20ba70 | 1659 | tmp = bcd2bin(tmp & 0x1f); |
c065f35c DB |
1660 | if (tmp == 12) |
1661 | tmp = 0; | |
042fa8c7 | 1662 | if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM) |
c065f35c | 1663 | tmp += 12; |
e553170a | 1664 | regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR, |
11e5890b | 1665 | bin2bcd(tmp)); |
1abb0dc9 DB |
1666 | } |
1667 | ||
82e2d43f | 1668 | if (want_irq || ds1307_can_wakeup_device) { |
11e5890b | 1669 | device_set_wakeup_capable(ds1307->dev, true); |
3abb1ada SG |
1670 | set_bit(HAS_ALARM, &ds1307->flags); |
1671 | } | |
69b119a6 AB |
1672 | |
1673 | ds1307->rtc = devm_rtc_allocate_device(ds1307->dev); | |
e69c0567 | 1674 | if (IS_ERR(ds1307->rtc)) |
4071ea25 | 1675 | return PTR_ERR(ds1307->rtc); |
1abb0dc9 | 1676 | |
82e2d43f | 1677 | if (ds1307_can_wakeup_device && !want_irq) { |
11e5890b HK |
1678 | dev_info(ds1307->dev, |
1679 | "'wakeup-source' is set, request for an IRQ is disabled!\n"); | |
8bc2a407 ML |
1680 | /* We cannot support UIE mode if we do not have an IRQ line */ |
1681 | ds1307->rtc->uie_unsupported = 1; | |
1682 | } | |
1683 | ||
cb49a5e9 | 1684 | if (want_irq) { |
45947127 HK |
1685 | err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL, |
1686 | chip->irq_handler ?: ds1307_irq, | |
c5983191 | 1687 | IRQF_SHARED | IRQF_ONESHOT, |
4b9e2a0c | 1688 | ds1307->name, ds1307); |
cb49a5e9 | 1689 | if (err) { |
4071ea25 | 1690 | client->irq = 0; |
11e5890b | 1691 | device_set_wakeup_capable(ds1307->dev, false); |
3abb1ada | 1692 | clear_bit(HAS_ALARM, &ds1307->flags); |
11e5890b | 1693 | dev_err(ds1307->dev, "unable to request IRQ!\n"); |
e69c0567 | 1694 | } else { |
11e5890b | 1695 | dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq); |
e69c0567 | 1696 | } |
cb49a5e9 RG |
1697 | } |
1698 | ||
e9fb7682 AB |
1699 | ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops; |
1700 | err = rtc_register_device(ds1307->rtc); | |
1701 | if (err) | |
1702 | return err; | |
1703 | ||
9eab0a78 | 1704 | if (chip->nvram_size) { |
409baf17 AB |
1705 | struct nvmem_config nvmem_cfg = { |
1706 | .name = "ds1307_nvram", | |
1707 | .word_size = 1, | |
1708 | .stride = 1, | |
1709 | .size = chip->nvram_size, | |
1710 | .reg_read = ds1307_nvram_read, | |
1711 | .reg_write = ds1307_nvram_write, | |
1712 | .priv = ds1307, | |
1713 | }; | |
abc925f7 | 1714 | |
abc925f7 | 1715 | ds1307->rtc->nvram_old_abi = true; |
409baf17 | 1716 | rtc_nvmem_register(ds1307->rtc, &nvmem_cfg); |
682d73f6 DB |
1717 | } |
1718 | ||
445c0207 | 1719 | ds1307_hwmon_register(ds1307); |
6c6ff145 | 1720 | ds1307_clks_register(ds1307); |
445c0207 | 1721 | |
1abb0dc9 DB |
1722 | return 0; |
1723 | ||
edca66d2 | 1724 | exit: |
1abb0dc9 DB |
1725 | return err; |
1726 | } | |
1727 | ||
1abb0dc9 DB |
1728 | static struct i2c_driver ds1307_driver = { |
1729 | .driver = { | |
c065f35c | 1730 | .name = "rtc-ds1307", |
7ef6d2c2 | 1731 | .of_match_table = of_match_ptr(ds1307_of_match), |
9c19b893 | 1732 | .acpi_match_table = ACPI_PTR(ds1307_acpi_ids), |
1abb0dc9 | 1733 | }, |
c065f35c | 1734 | .probe = ds1307_probe, |
3760f736 | 1735 | .id_table = ds1307_id, |
1abb0dc9 DB |
1736 | }; |
1737 | ||
0abc9201 | 1738 | module_i2c_driver(ds1307_driver); |
1abb0dc9 DB |
1739 | |
1740 | MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); | |
1741 | MODULE_LICENSE("GPL"); |