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rtc: isl12057: enable support for the standard "wakeup-source" property
[linux-2.6-block.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB		 1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
eac7237f
NM		 14#include <linux/bcd.h>
15#include <linux/i2c.h>
1abb0dc9 16#include <linux/init.h>
eac7237f 17#include <linux/module.h>
7abea617
NM		 18#include <linux/of_device.h>
19#include <linux/of_irq.h>
20#include <linux/pm_wakeirq.h>
eac7237f
NM		 21#include <linux/rtc/ds1307.h>
22#include <linux/rtc.h>
1abb0dc9 23#include <linux/slab.h>
1abb0dc9 24#include <linux/string.h>
1abb0dc9 25
40ce972d
DA		 26/*
27 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB		 28 * to have set the chip up as a clock (turning on the oscillator and
29 * setting the date and time), Linux can ignore the non-clock features.
30 * That's a natural job for a factory or repair bench.
1abb0dc9
DB		 31 */
32enum ds_type {
045e0e85
DB		 33 ds_1307,
34 ds_1337,
35 ds_1338,
36 ds_1339,
37 ds_1340,
33df2ee1 38 ds_1388,
97f902b7 39 ds_3231,
045e0e85 40 m41t00,
f4199f85 41 mcp794xx,
a2166858 42 rx_8025,
32d322bc 43 last_ds_type /* always last */
40ce972d 44 /* rs5c372 too? different address... */
1abb0dc9
DB		 45};
46
1abb0dc9
DB		 47
48/* RTC registers don't differ much, except for the century flag */
49#define DS1307_REG_SECS 0x00 /* 00-59 */
50# define DS1307_BIT_CH 0x80
be5f59f4 51# define DS1340_BIT_nEOSC 0x80
f4199f85 52# define MCP794XX_BIT_ST 0x80
1abb0dc9
DB		 53#define DS1307_REG_MIN 0x01 /* 00-59 */
54#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB		 55# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
56# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB		 57# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
58# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
59#define DS1307_REG_WDAY 0x03 /* 01-07 */
f4199f85 60# define MCP794XX_BIT_VBATEN 0x08
1abb0dc9
DB		 61#define DS1307_REG_MDAY 0x04 /* 01-31 */
62#define DS1307_REG_MONTH 0x05 /* 01-12 */
63# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
64#define DS1307_REG_YEAR 0x06 /* 00-99 */
65
40ce972d
DA		 66/*
67 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB		 68 * start at 7, and they differ a LOT. Only control and status matter for
69 * basic RTC date and time functionality; be careful using them.
1abb0dc9 70 */
045e0e85 71#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 72# define DS1307_BIT_OUT 0x80
be5f59f4 73# define DS1338_BIT_OSF 0x20
1abb0dc9
DB		 74# define DS1307_BIT_SQWE 0x10
75# define DS1307_BIT_RS1 0x02
76# define DS1307_BIT_RS0 0x01
77#define DS1337_REG_CONTROL 0x0e
78# define DS1337_BIT_nEOSC 0x80
cb49a5e9 79# define DS1339_BIT_BBSQI 0x20
97f902b7 80# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB		 81# define DS1337_BIT_RS2 0x10
82# define DS1337_BIT_RS1 0x08
83# define DS1337_BIT_INTCN 0x04
84# define DS1337_BIT_A2IE 0x02
85# define DS1337_BIT_A1IE 0x01
045e0e85
DB		 86#define DS1340_REG_CONTROL 0x07
87# define DS1340_BIT_OUT 0x80
88# define DS1340_BIT_FT 0x40
89# define DS1340_BIT_CALIB_SIGN 0x20
90# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG		 91#define DS1340_REG_FLAG 0x09
92# define DS1340_BIT_OSF 0x80
1abb0dc9
DB		 93#define DS1337_REG_STATUS 0x0f
94# define DS1337_BIT_OSF 0x80
95# define DS1337_BIT_A2I 0x02
96# define DS1337_BIT_A1I 0x01
cb49a5e9 97#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS		 98
99#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 100
a2166858
MF		 101#define RX8025_REG_CTRL1 0x0e
102# define RX8025_BIT_2412 0x20
103#define RX8025_REG_CTRL2 0x0f
104# define RX8025_BIT_PON 0x10
105# define RX8025_BIT_VDET 0x40
106# define RX8025_BIT_XST 0x20
1abb0dc9
DB		 107
108
109struct ds1307 {
33df2ee1 110 u8 offset; /* register's offset */
cb49a5e9 111 u8 regs[11];
9eab0a78
AB		 112 u16 nvram_offset;
113 struct bin_attribute *nvram;
1abb0dc9 114 enum ds_type type;
cb49a5e9
RG		 115 unsigned long flags;
116#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
117#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 118 struct i2c_client *client;
1abb0dc9 119 struct rtc_device *rtc;
7abea617 120 int wakeirq;
0cc43a18 121 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
30e7b039 122 u8 length, u8 *values);
0cc43a18 123 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
30e7b039 124 u8 length, const u8 *values);
1abb0dc9
DB		 125};
126
045e0e85 127struct chip_desc {
045e0e85 128 unsigned alarm:1;
9eab0a78
AB		 129 u16 nvram_offset;
130 u16 nvram_size;
eb86c306 131 u16 trickle_charger_reg;
33b04b7b
MV		 132 u8 trickle_charger_setup;
133 u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool);
045e0e85
DB		 134};
135
33b04b7b
MV		 136static u8 do_trickle_setup_ds1339(struct i2c_client *,
137 uint32_t ohms, bool diode);
138
139static struct chip_desc chips[last_ds_type] = {
32d322bc 140 [ds_1307] = {
9eab0a78
AB		 141 .nvram_offset = 8,
142 .nvram_size = 56,
32d322bc
WS		 143 },
144 [ds_1337] = {
145 .alarm = 1,
146 },
147 [ds_1338] = {
9eab0a78
AB		 148 .nvram_offset = 8,
149 .nvram_size = 56,
32d322bc
WS		 150 },
151 [ds_1339] = {
152 .alarm = 1,
eb86c306 153 .trickle_charger_reg = 0x10,
33b04b7b 154 .do_trickle_setup = &do_trickle_setup_ds1339,
eb86c306
WS		 155 },
156 [ds_1340] = {
157 .trickle_charger_reg = 0x08,
158 },
159 [ds_1388] = {
160 .trickle_charger_reg = 0x0a,
32d322bc
WS		 161 },
162 [ds_3231] = {
163 .alarm = 1,
164 },
f4199f85 165 [mcp794xx] = {
1d1945d2 166 .alarm = 1,
9eab0a78
AB		 167 /* this is battery backed SRAM */
168 .nvram_offset = 0x20,
169 .nvram_size = 0x40,
170 },
32d322bc 171};
045e0e85 172
3760f736
JD		 173static const struct i2c_device_id ds1307_id[] = {
174 { "ds1307", ds_1307 },
175 { "ds1337", ds_1337 },
176 { "ds1338", ds_1338 },
177 { "ds1339", ds_1339 },
33df2ee1 178 { "ds1388", ds_1388 },
3760f736 179 { "ds1340", ds_1340 },
97f902b7 180 { "ds3231", ds_3231 },
3760f736 181 { "m41t00", m41t00 },
f4199f85
TN		 182 { "mcp7940x", mcp794xx },
183 { "mcp7941x", mcp794xx },
31c1771c 184 { "pt7c4338", ds_1307 },
a2166858 185 { "rx8025", rx_8025 },
3760f736
JD		 186 { }
187};
188MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 189
cb49a5e9
RG		 190/*----------------------------------------------------------------------*/
191
30e7b039
ES		 192#define BLOCK_DATA_MAX_TRIES 10
193
0cc43a18
JD		 194static s32 ds1307_read_block_data_once(const struct i2c_client *client,
195 u8 command, u8 length, u8 *values)
30e7b039
ES		 196{
197 s32 i, data;
198
199 for (i = 0; i < length; i++) {
200 data = i2c_smbus_read_byte_data(client, command + i);
201 if (data < 0)
202 return data;
203 values[i] = data;
204 }
205 return i;
206}
207
0cc43a18 208static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES		 209 u8 length, u8 *values)
210{
bc48b902 211 u8 oldvalues[255];
30e7b039
ES		 212 s32 ret;
213 int tries = 0;
214
215 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
216 ret = ds1307_read_block_data_once(client, command, length, values);
217 if (ret < 0)
218 return ret;
219 do {
220 if (++tries > BLOCK_DATA_MAX_TRIES) {
221 dev_err(&client->dev,
222 "ds1307_read_block_data failed\n");
223 return -EIO;
224 }
225 memcpy(oldvalues, values, length);
226 ret = ds1307_read_block_data_once(client, command, length,
227 values);
228 if (ret < 0)
229 return ret;
230 } while (memcmp(oldvalues, values, length));
231 return length;
232}
233
0cc43a18 234static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES		 235 u8 length, const u8 *values)
236{
bc48b902 237 u8 currvalues[255];
30e7b039
ES		 238 int tries = 0;
239
240 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
241 do {
242 s32 i, ret;
243
244 if (++tries > BLOCK_DATA_MAX_TRIES) {
245 dev_err(&client->dev,
246 "ds1307_write_block_data failed\n");
247 return -EIO;
248 }
249 for (i = 0; i < length; i++) {
250 ret = i2c_smbus_write_byte_data(client, command + i,
251 values[i]);
252 if (ret < 0)
253 return ret;
254 }
255 ret = ds1307_read_block_data_once(client, command, length,
256 currvalues);
257 if (ret < 0)
258 return ret;
259 } while (memcmp(currvalues, values, length));
260 return length;
261}
262
263/*----------------------------------------------------------------------*/
264
bc48b902
BA		 265/* These RTC devices are not designed to be connected to a SMbus adapter.
266 SMbus limits block operations length to 32 bytes, whereas it's not
267 limited on I2C buses. As a result, accesses may exceed 32 bytes;
268 in that case, split them into smaller blocks */
269
270static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
271 u8 command, u8 length, const u8 *values)
272{
273 u8 suboffset = 0;
274
275 if (length <= I2C_SMBUS_BLOCK_MAX)
276 return i2c_smbus_write_i2c_block_data(client,
277 command, length, values);
278
279 while (suboffset < length) {
280 s32 retval = i2c_smbus_write_i2c_block_data(client,
281 command + suboffset,
282 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
283 values + suboffset);
284 if (retval < 0)
285 return retval;
286
287 suboffset += I2C_SMBUS_BLOCK_MAX;
288 }
289 return length;
290}
291
292static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
293 u8 command, u8 length, u8 *values)
294{
295 u8 suboffset = 0;
296
297 if (length <= I2C_SMBUS_BLOCK_MAX)
298 return i2c_smbus_read_i2c_block_data(client,
299 command, length, values);
300
301 while (suboffset < length) {
302 s32 retval = i2c_smbus_read_i2c_block_data(client,
303 command + suboffset,
304 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
305 values + suboffset);
306 if (retval < 0)
307 return retval;
308
309 suboffset += I2C_SMBUS_BLOCK_MAX;
310 }
311 return length;
312}
313
314/*----------------------------------------------------------------------*/
315
cb49a5e9 316/*
cb49a5e9
RG		 317 * The ds1337 and ds1339 both have two alarms, but we only use the first
318 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
319 * signal; ds1339 chips have only one alarm signal.
320 */
2fb07a10 321static irqreturn_t ds1307_irq(int irq, void *dev_id)
cb49a5e9 322{
2fb07a10
FB		 323 struct i2c_client *client = dev_id;
324 struct ds1307 *ds1307 = i2c_get_clientdata(client);
325 struct mutex *lock = &ds1307->rtc->ops_lock;
cb49a5e9
RG		 326 int stat, control;
327
cb49a5e9
RG		 328 mutex_lock(lock);
329 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
330 if (stat < 0)
331 goto out;
332
333 if (stat & DS1337_BIT_A1I) {
334 stat &= ~DS1337_BIT_A1I;
335 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
336
337 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
338 if (control < 0)
339 goto out;
340
341 control &= ~DS1337_BIT_A1IE;
342 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
343
cb49a5e9 344 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG		 345 }
346
347out:
cb49a5e9 348 mutex_unlock(lock);
cb49a5e9 349
cb49a5e9
RG		 350 return IRQ_HANDLED;
351}
352
353/*----------------------------------------------------------------------*/
354
1abb0dc9
DB		 355static int ds1307_get_time(struct device *dev, struct rtc_time *t)
356{
357 struct ds1307 *ds1307 = dev_get_drvdata(dev);
358 int tmp;
359
045e0e85 360 /* read the RTC date and time registers all at once */
30e7b039 361 tmp = ds1307->read_block_data(ds1307->client,
33df2ee1 362 ds1307->offset, 7, ds1307->regs);
fed40b73 363 if (tmp != 7) {
1abb0dc9
DB		 364 dev_err(dev, "%s error %d\n", "read", tmp);
365 return -EIO;
366 }
367
01a4ca16 368 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
1abb0dc9 369
fe20ba70
AB		 370 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
371 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 372 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB		 373 t->tm_hour = bcd2bin(tmp);
374 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
375 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 376 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 377 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB		 378
379 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 380 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB		 381
382 dev_dbg(dev, "%s secs=%d, mins=%d, "
383 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
384 "read", t->tm_sec, t->tm_min,
385 t->tm_hour, t->tm_mday,
386 t->tm_mon, t->tm_year, t->tm_wday);
387
045e0e85
DB		 388 /* initial clock setting can be undefined */
389 return rtc_valid_tm(t);
1abb0dc9
DB		 390}
391
392static int ds1307_set_time(struct device *dev, struct rtc_time *t)
393{
394 struct ds1307 *ds1307 = dev_get_drvdata(dev);
395 int result;
396 int tmp;
397 u8 *buf = ds1307->regs;
398
399 dev_dbg(dev, "%s secs=%d, mins=%d, "
400 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG		 401 "write", t->tm_sec, t->tm_min,
402 t->tm_hour, t->tm_mday,
403 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 404
fe20ba70
AB		 405 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
406 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
407 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
408 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
409 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
410 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB		 411
412 /* assume 20YY not 19YY */
413 tmp = t->tm_year - 100;
fe20ba70 414 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 415
be5f59f4
RG		 416 switch (ds1307->type) {
417 case ds_1337:
418 case ds_1339:
97f902b7 419 case ds_3231:
1abb0dc9 420 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG		 421 break;
422 case ds_1340:
1abb0dc9
DB		 423 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
424 | DS1340_BIT_CENTURY;
be5f59f4 425 break;
f4199f85 426 case mcp794xx:
40ce972d
DA		 427 /*
428 * these bits were cleared when preparing the date/time
429 * values and need to be set again before writing the
430 * buffer out to the device.
431 */
f4199f85
TN		 432 buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
433 buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
43fcb815 434 break;
be5f59f4
RG		 435 default:
436 break;
437 }
1abb0dc9 438
01a4ca16 439 dev_dbg(dev, "%s: %7ph\n", "write", buf);
1abb0dc9 440
33df2ee1
JT		 441 result = ds1307->write_block_data(ds1307->client,
442 ds1307->offset, 7, buf);
fed40b73
BS		 443 if (result < 0) {
444 dev_err(dev, "%s error %d\n", "write", result);
445 return result;
1abb0dc9
DB		 446 }
447 return 0;
448}
449
74d88eb2 450static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG		 451{
452 struct i2c_client *client = to_i2c_client(dev);
453 struct ds1307 *ds1307 = i2c_get_clientdata(client);
454 int ret;
455
456 if (!test_bit(HAS_ALARM, &ds1307->flags))
457 return -EINVAL;
458
459 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 460 ret = ds1307->read_block_data(client,
fed40b73
BS		 461 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
462 if (ret != 9) {
cb49a5e9
RG		 463 dev_err(dev, "%s error %d\n", "alarm read", ret);
464 return -EIO;
465 }
466
467 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
468 "alarm read",
469 ds1307->regs[0], ds1307->regs[1],
470 ds1307->regs[2], ds1307->regs[3],
471 ds1307->regs[4], ds1307->regs[5],
472 ds1307->regs[6], ds1307->regs[7],
473 ds1307->regs[8]);
474
40ce972d
DA		 475 /*
476 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG		 477 * and that all four fields are checked matches
478 */
479 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
480 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
481 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
482 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
483 t->time.tm_mon = -1;
484 t->time.tm_year = -1;
485 t->time.tm_wday = -1;
486 t->time.tm_yday = -1;
487 t->time.tm_isdst = -1;
488
489 /* ... and status */
490 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
491 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
492
493 dev_dbg(dev, "%s secs=%d, mins=%d, "
494 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
495 "alarm read", t->time.tm_sec, t->time.tm_min,
496 t->time.tm_hour, t->time.tm_mday,
497 t->enabled, t->pending);
498
499 return 0;
500}
501
74d88eb2 502static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 503{
40ce972d 504 struct i2c_client *client = to_i2c_client(dev);
cb49a5e9
RG		 505 struct ds1307 *ds1307 = i2c_get_clientdata(client);
506 unsigned char *buf = ds1307->regs;
507 u8 control, status;
508 int ret;
509
510 if (!test_bit(HAS_ALARM, &ds1307->flags))
511 return -EINVAL;
512
513 dev_dbg(dev, "%s secs=%d, mins=%d, "
514 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
515 "alarm set", t->time.tm_sec, t->time.tm_min,
516 t->time.tm_hour, t->time.tm_mday,
517 t->enabled, t->pending);
518
519 /* read current status of both alarms and the chip */
30e7b039 520 ret = ds1307->read_block_data(client,
fed40b73
BS		 521 DS1339_REG_ALARM1_SECS, 9, buf);
522 if (ret != 9) {
cb49a5e9
RG		 523 dev_err(dev, "%s error %d\n", "alarm write", ret);
524 return -EIO;
525 }
526 control = ds1307->regs[7];
527 status = ds1307->regs[8];
528
529 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
530 "alarm set (old status)",
531 ds1307->regs[0], ds1307->regs[1],
532 ds1307->regs[2], ds1307->regs[3],
533 ds1307->regs[4], ds1307->regs[5],
534 ds1307->regs[6], control, status);
535
536 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG		 537 buf[0] = bin2bcd(t->time.tm_sec);
538 buf[1] = bin2bcd(t->time.tm_min);
539 buf[2] = bin2bcd(t->time.tm_hour);
540 buf[3] = bin2bcd(t->time.tm_mday);
541
542 /* set ALARM2 to non-garbage */
543 buf[4] = 0;
544 buf[5] = 0;
545 buf[6] = 0;
546
547 /* optionally enable ALARM1 */
548 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
549 if (t->enabled) {
550 dev_dbg(dev, "alarm IRQ armed\n");
551 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
552 }
553 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
554
30e7b039 555 ret = ds1307->write_block_data(client,
fed40b73
BS		 556 DS1339_REG_ALARM1_SECS, 9, buf);
557 if (ret < 0) {
cb49a5e9 558 dev_err(dev, "can't set alarm time\n");
fed40b73 559 return ret;
cb49a5e9
RG		 560 }
561
562 return 0;
563}
564
16380c15 565static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9
RG		 566{
567 struct i2c_client *client = to_i2c_client(dev);
568 struct ds1307 *ds1307 = i2c_get_clientdata(client);
569 int ret;
570
16380c15
JS		 571 if (!test_bit(HAS_ALARM, &ds1307->flags))
572 return -ENOTTY;
cb49a5e9 573
16380c15
JS		 574 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
575 if (ret < 0)
576 return ret;
cb49a5e9 577
16380c15 578 if (enabled)
cb49a5e9 579 ret |= DS1337_BIT_A1IE;
16380c15
JS		 580 else
581 ret &= ~DS1337_BIT_A1IE;
cb49a5e9 582
16380c15
JS		 583 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
584 if (ret < 0)
585 return ret;
cb49a5e9
RG		 586
587 return 0;
588}
589
ff8371ac 590static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB		 591 .read_time = ds1307_get_time,
592 .set_time = ds1307_set_time,
74d88eb2
JR		 593 .read_alarm = ds1337_read_alarm,
594 .set_alarm = ds1337_set_alarm,
16380c15 595 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB		 596};
597
682d73f6
DB		 598/*----------------------------------------------------------------------*/
599
1d1945d2 600/*
f4199f85 601 * Alarm support for mcp794xx devices.
1d1945d2
SG		 602 */
603
f4199f85
TN		 604#define MCP794XX_REG_CONTROL 0x07
605# define MCP794XX_BIT_ALM0_EN 0x10
606# define MCP794XX_BIT_ALM1_EN 0x20
607#define MCP794XX_REG_ALARM0_BASE 0x0a
608#define MCP794XX_REG_ALARM0_CTRL 0x0d
609#define MCP794XX_REG_ALARM1_BASE 0x11
610#define MCP794XX_REG_ALARM1_CTRL 0x14
611# define MCP794XX_BIT_ALMX_IF (1 << 3)
612# define MCP794XX_BIT_ALMX_C0 (1 << 4)
613# define MCP794XX_BIT_ALMX_C1 (1 << 5)
614# define MCP794XX_BIT_ALMX_C2 (1 << 6)
615# define MCP794XX_BIT_ALMX_POL (1 << 7)
616# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
617 MCP794XX_BIT_ALMX_C1 | \
618 MCP794XX_BIT_ALMX_C2)
619
2fb07a10 620static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
1d1945d2 621{
2fb07a10
FB		 622 struct i2c_client *client = dev_id;
623 struct ds1307 *ds1307 = i2c_get_clientdata(client);
624 struct mutex *lock = &ds1307->rtc->ops_lock;
1d1945d2
SG		 625 int reg, ret;
626
2fb07a10 627 mutex_lock(lock);
1d1945d2
SG		 628
629 /* Check and clear alarm 0 interrupt flag. */
f4199f85 630 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_ALARM0_CTRL);
1d1945d2
SG		 631 if (reg < 0)
632 goto out;
f4199f85 633 if (!(reg & MCP794XX_BIT_ALMX_IF))
1d1945d2 634 goto out;
f4199f85
TN		 635 reg &= ~MCP794XX_BIT_ALMX_IF;
636 ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_ALARM0_CTRL, reg);
1d1945d2
SG		 637 if (ret < 0)
638 goto out;
639
640 /* Disable alarm 0. */
f4199f85 641 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
1d1945d2
SG		 642 if (reg < 0)
643 goto out;
f4199f85
TN		 644 reg &= ~MCP794XX_BIT_ALM0_EN;
645 ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
1d1945d2
SG		 646 if (ret < 0)
647 goto out;
648
649 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
650
651out:
2fb07a10
FB		 652 mutex_unlock(lock);
653
654 return IRQ_HANDLED;
1d1945d2
SG		 655}
656
f4199f85 657static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2
SG		 658{
659 struct i2c_client *client = to_i2c_client(dev);
660 struct ds1307 *ds1307 = i2c_get_clientdata(client);
661 u8 *regs = ds1307->regs;
662 int ret;
663
664 if (!test_bit(HAS_ALARM, &ds1307->flags))
665 return -EINVAL;
666
667 /* Read control and alarm 0 registers. */
f4199f85 668 ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
1d1945d2
SG		 669 if (ret < 0)
670 return ret;
671
f4199f85 672 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
1d1945d2
SG		 673
674 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
675 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
676 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
677 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
678 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
679 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
680 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
681 t->time.tm_year = -1;
682 t->time.tm_yday = -1;
683 t->time.tm_isdst = -1;
684
685 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
686 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
687 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
688 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
f4199f85
TN		 689 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
690 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
691 (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
1d1945d2
SG		 692
693 return 0;
694}
695
f4199f85 696static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2
SG		 697{
698 struct i2c_client *client = to_i2c_client(dev);
699 struct ds1307 *ds1307 = i2c_get_clientdata(client);
700 unsigned char *regs = ds1307->regs;
701 int ret;
702
703 if (!test_bit(HAS_ALARM, &ds1307->flags))
704 return -EINVAL;
705
706 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
707 "enabled=%d pending=%d\n", __func__,
708 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
709 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
710 t->enabled, t->pending);
711
712 /* Read control and alarm 0 registers. */
f4199f85 713 ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
1d1945d2
SG		 714 if (ret < 0)
715 return ret;
716
717 /* Set alarm 0, using 24-hour and day-of-month modes. */
718 regs[3] = bin2bcd(t->time.tm_sec);
719 regs[4] = bin2bcd(t->time.tm_min);
720 regs[5] = bin2bcd(t->time.tm_hour);
721 regs[6] = bin2bcd(t->time.tm_wday) + 1;
722 regs[7] = bin2bcd(t->time.tm_mday);
723 regs[8] = bin2bcd(t->time.tm_mon) + 1;
724
725 /* Clear the alarm 0 interrupt flag. */
f4199f85 726 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
1d1945d2 727 /* Set alarm match: second, minute, hour, day, date, month. */
f4199f85 728 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
e3edd671
NM		 729 /* Disable interrupt. We will not enable until completely programmed */
730 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
1d1945d2 731
f4199f85 732 ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
1d1945d2
SG		 733 if (ret < 0)
734 return ret;
735
e3edd671
NM		 736 if (!t->enabled)
737 return 0;
738 regs[0] |= MCP794XX_BIT_ALM0_EN;
739 return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, regs[0]);
1d1945d2
SG		 740}
741
f4199f85 742static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
1d1945d2
SG		 743{
744 struct i2c_client *client = to_i2c_client(dev);
745 struct ds1307 *ds1307 = i2c_get_clientdata(client);
746 int reg;
747
748 if (!test_bit(HAS_ALARM, &ds1307->flags))
749 return -EINVAL;
750
f4199f85 751 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
1d1945d2
SG		 752 if (reg < 0)
753 return reg;
754
755 if (enabled)
f4199f85 756 reg |= MCP794XX_BIT_ALM0_EN;
1d1945d2 757 else
f4199f85 758 reg &= ~MCP794XX_BIT_ALM0_EN;
1d1945d2 759
f4199f85 760 return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
1d1945d2
SG		 761}
762
f4199f85 763static const struct rtc_class_ops mcp794xx_rtc_ops = {
1d1945d2
SG		 764 .read_time = ds1307_get_time,
765 .set_time = ds1307_set_time,
f4199f85
TN		 766 .read_alarm = mcp794xx_read_alarm,
767 .set_alarm = mcp794xx_set_alarm,
768 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
1d1945d2
SG		 769};
770
771/*----------------------------------------------------------------------*/
772
682d73f6 773static ssize_t
2c3c8bea
CW		 774ds1307_nvram_read(struct file *filp, struct kobject *kobj,
775 struct bin_attribute *attr,
682d73f6
DB		 776 char *buf, loff_t off, size_t count)
777{
778 struct i2c_client *client;
779 struct ds1307 *ds1307;
682d73f6
DB		 780 int result;
781
fcd8db00 782 client = kobj_to_i2c_client(kobj);
682d73f6
DB		 783 ds1307 = i2c_get_clientdata(client);
784
9eab0a78
AB		 785 result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
786 count, buf);
fed40b73 787 if (result < 0)
682d73f6 788 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 789 return result;
682d73f6
DB		 790}
791
792static ssize_t
2c3c8bea
CW		 793ds1307_nvram_write(struct file *filp, struct kobject *kobj,
794 struct bin_attribute *attr,
682d73f6
DB		 795 char *buf, loff_t off, size_t count)
796{
797 struct i2c_client *client;
30e7b039 798 struct ds1307 *ds1307;
fed40b73 799 int result;
682d73f6 800
fcd8db00 801 client = kobj_to_i2c_client(kobj);
30e7b039 802 ds1307 = i2c_get_clientdata(client);
682d73f6 803
9eab0a78
AB		 804 result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
805 count, buf);
fed40b73
BS		 806 if (result < 0) {
807 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
808 return result;
809 }
810 return count;
682d73f6
DB		 811}
812
33b04b7b 813
682d73f6
DB		 814/*----------------------------------------------------------------------*/
815
33b04b7b
MV		 816static u8 do_trickle_setup_ds1339(struct i2c_client *client,
817 uint32_t ohms, bool diode)
818{
819 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
820 DS1307_TRICKLE_CHARGER_NO_DIODE;
821
822 switch (ohms) {
823 case 250:
824 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
825 break;
826 case 2000:
827 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
828 break;
829 case 4000:
830 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
831 break;
832 default:
833 dev_warn(&client->dev,
834 "Unsupported ohm value %u in dt\n", ohms);
835 return 0;
836 }
837 return setup;
838}
839
840static void ds1307_trickle_of_init(struct i2c_client *client,
841 struct chip_desc *chip)
842{
843 uint32_t ohms = 0;
844 bool diode = true;
845
846 if (!chip->do_trickle_setup)
847 goto out;
848 if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms))
849 goto out;
850 if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable"))
851 diode = false;
852 chip->trickle_charger_setup = chip->do_trickle_setup(client,
853 ohms, diode);
854out:
855 return;
856}
857
5a167f45
GKH		 858static int ds1307_probe(struct i2c_client *client,
859 const struct i2c_device_id *id)
1abb0dc9
DB		 860{
861 struct ds1307 *ds1307;
862 int err = -ENODEV;
1abb0dc9 863 int tmp;
33b04b7b 864 struct chip_desc *chip = &chips[id->driver_data];
c065f35c 865 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
c8b18da7 866 bool want_irq = false;
fed40b73 867 unsigned char *buf;
01ce893d 868 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
2fb07a10
FB		 869 irq_handler_t irq_handler = ds1307_irq;
870
97f902b7
WS		 871 static const int bbsqi_bitpos[] = {
872 [ds_1337] = 0,
873 [ds_1339] = DS1339_BIT_BBSQI,
874 [ds_3231] = DS3231_BIT_BBSQW,
875 };
1d1945d2 876 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1abb0dc9 877
30e7b039
ES		 878 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
879 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB		 880 return -EIO;
881
edca66d2 882 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 883 if (!ds1307)
c065f35c 884 return -ENOMEM;
045e0e85 885
1abb0dc9 886 i2c_set_clientdata(client, ds1307);
33df2ee1
JT		 887
888 ds1307->client = client;
889 ds1307->type = id->driver_data;
33df2ee1 890
33b04b7b
MV		 891 if (!pdata && client->dev.of_node)
892 ds1307_trickle_of_init(client, chip);
893 else if (pdata && pdata->trickle_charger_setup)
894 chip->trickle_charger_setup = pdata->trickle_charger_setup;
895
896 if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
897 dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n",
898 DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
899 chip->trickle_charger_reg);
eb86c306 900 i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
33b04b7b
MV		 901 DS13XX_TRICKLE_CHARGER_MAGIC |
902 chip->trickle_charger_setup);
903 }
eb86c306 904
fed40b73 905 buf = ds1307->regs;
30e7b039 906 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
bc48b902
BA		 907 ds1307->read_block_data = ds1307_native_smbus_read_block_data;
908 ds1307->write_block_data = ds1307_native_smbus_write_block_data;
30e7b039
ES		 909 } else {
910 ds1307->read_block_data = ds1307_read_block_data;
911 ds1307->write_block_data = ds1307_write_block_data;
912 }
045e0e85
DB		 913
914 switch (ds1307->type) {
915 case ds_1337:
916 case ds_1339:
97f902b7 917 case ds_3231:
be5f59f4 918 /* get registers that the "rtc" read below won't read... */
30e7b039 919 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 920 DS1337_REG_CONTROL, 2, buf);
1abb0dc9 921 if (tmp != 2) {
6df80e21 922 dev_dbg(&client->dev, "read error %d\n", tmp);
1abb0dc9 923 err = -EIO;
edca66d2 924 goto exit;
1abb0dc9
DB		 925 }
926
be5f59f4
RG		 927 /* oscillator off? turn it on, so clock can tick. */
928 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG		 929 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
930
40ce972d
DA		 931 /*
932 * Using IRQ? Disable the square wave and both alarms.
97f902b7
WS		 933 * For some variants, be sure alarms can trigger when we're
934 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 935 */
b24a7267 936 if (ds1307->client->irq > 0 && chip->alarm) {
97f902b7
WS		 937 ds1307->regs[0] |= DS1337_BIT_INTCN
938 | bbsqi_bitpos[ds1307->type];
cb49a5e9 939 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
b24a7267
WS		 940
941 want_irq = true;
cb49a5e9
RG		 942 }
943
944 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
945 ds1307->regs[0]);
be5f59f4
RG		 946
947 /* oscillator fault? clear flag, and warn */
948 if (ds1307->regs[1] & DS1337_BIT_OSF) {
949 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
950 ds1307->regs[1] & ~DS1337_BIT_OSF);
951 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 952 }
045e0e85 953 break;
a2166858
MF		 954
955 case rx_8025:
956 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
957 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
958 if (tmp != 2) {
6df80e21 959 dev_dbg(&client->dev, "read error %d\n", tmp);
a2166858 960 err = -EIO;
edca66d2 961 goto exit;
a2166858
MF		 962 }
963
964 /* oscillator off? turn it on, so clock can tick. */
965 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
966 ds1307->regs[1] |= RX8025_BIT_XST;
967 i2c_smbus_write_byte_data(client,
968 RX8025_REG_CTRL2 << 4 | 0x08,
969 ds1307->regs[1]);
970 dev_warn(&client->dev,
971 "oscillator stop detected - SET TIME!\n");
972 }
973
974 if (ds1307->regs[1] & RX8025_BIT_PON) {
975 ds1307->regs[1] &= ~RX8025_BIT_PON;
976 i2c_smbus_write_byte_data(client,
977 RX8025_REG_CTRL2 << 4 | 0x08,
978 ds1307->regs[1]);
979 dev_warn(&client->dev, "power-on detected\n");
980 }
981
982 if (ds1307->regs[1] & RX8025_BIT_VDET) {
983 ds1307->regs[1] &= ~RX8025_BIT_VDET;
984 i2c_smbus_write_byte_data(client,
985 RX8025_REG_CTRL2 << 4 | 0x08,
986 ds1307->regs[1]);
987 dev_warn(&client->dev, "voltage drop detected\n");
988 }
989
990 /* make sure we are running in 24hour mode */
991 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
992 u8 hour;
993
994 /* switch to 24 hour mode */
995 i2c_smbus_write_byte_data(client,
996 RX8025_REG_CTRL1 << 4 | 0x08,
997 ds1307->regs[0] |
998 RX8025_BIT_2412);
999
1000 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
1001 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
1002 if (tmp != 2) {
6df80e21 1003 dev_dbg(&client->dev, "read error %d\n", tmp);
a2166858 1004 err = -EIO;
edca66d2 1005 goto exit;
a2166858
MF		 1006 }
1007
1008 /* correct hour */
1009 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
1010 if (hour == 12)
1011 hour = 0;
1012 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1013 hour += 12;
1014
1015 i2c_smbus_write_byte_data(client,
1016 DS1307_REG_HOUR << 4 | 0x08,
1017 hour);
1018 }
1019 break;
33df2ee1
JT		 1020 case ds_1388:
1021 ds1307->offset = 1; /* Seconds starts at 1 */
1022 break;
f4199f85
TN		 1023 case mcp794xx:
1024 rtc_ops = &mcp794xx_rtc_ops;
1d1945d2 1025 if (ds1307->client->irq > 0 && chip->alarm) {
2fb07a10 1026 irq_handler = mcp794xx_irq;
1d1945d2
SG		 1027 want_irq = true;
1028 }
1029 break;
045e0e85
DB		 1030 default:
1031 break;
1032 }
1abb0dc9
DB		 1033
1034read_rtc:
1035 /* read RTC registers */
96fc3a45 1036 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
fed40b73 1037 if (tmp != 8) {
6df80e21 1038 dev_dbg(&client->dev, "read error %d\n", tmp);
1abb0dc9 1039 err = -EIO;
edca66d2 1040 goto exit;
1abb0dc9
DB		 1041 }
1042
40ce972d
DA		 1043 /*
1044 * minimal sanity checking; some chips (like DS1340) don't
1abb0dc9
DB		 1045 * specify the extra bits as must-be-zero, but there are
1046 * still a few values that are clearly out-of-range.
1047 */
1048 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB		 1049 switch (ds1307->type) {
1050 case ds_1307:
045e0e85 1051 case m41t00:
be5f59f4 1052 /* clock halted? turn it on, so clock can tick. */
045e0e85 1053 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG		 1054 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1055 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 1056 goto read_rtc;
1abb0dc9 1057 }
045e0e85 1058 break;
be5f59f4
RG		 1059 case ds_1338:
1060 /* clock halted? turn it on, so clock can tick. */
045e0e85 1061 if (tmp & DS1307_BIT_CH)
be5f59f4
RG		 1062 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1063
1064 /* oscillator fault? clear flag, and warn */
1065 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1066 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 1067 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG		 1068 & ~DS1338_BIT_OSF);
1069 dev_warn(&client->dev, "SET TIME!\n");
1070 goto read_rtc;
1071 }
045e0e85 1072 break;
fcd8db00
R		 1073 case ds_1340:
1074 /* clock halted? turn it on, so clock can tick. */
1075 if (tmp & DS1340_BIT_nEOSC)
1076 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1077
1078 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
1079 if (tmp < 0) {
6df80e21 1080 dev_dbg(&client->dev, "read error %d\n", tmp);
fcd8db00 1081 err = -EIO;
edca66d2 1082 goto exit;
fcd8db00
R		 1083 }
1084
1085 /* oscillator fault? clear flag, and warn */
1086 if (tmp & DS1340_BIT_OSF) {
1087 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
1088 dev_warn(&client->dev, "SET TIME!\n");
1089 }
43fcb815 1090 break;
f4199f85 1091 case mcp794xx:
43fcb815 1092 /* make sure that the backup battery is enabled */
f4199f85 1093 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
43fcb815
DA		 1094 i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
1095 ds1307->regs[DS1307_REG_WDAY]
f4199f85 1096 | MCP794XX_BIT_VBATEN);
43fcb815
DA		 1097 }
1098
1099 /* clock halted? turn it on, so clock can tick. */
f4199f85 1100 if (!(tmp & MCP794XX_BIT_ST)) {
43fcb815 1101 i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
f4199f85 1102 MCP794XX_BIT_ST);
43fcb815
DA		 1103 dev_warn(&client->dev, "SET TIME!\n");
1104 goto read_rtc;
1105 }
1106
fcd8db00 1107 break;
32d322bc 1108 default:
045e0e85 1109 break;
1abb0dc9 1110 }
045e0e85 1111
1abb0dc9 1112 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB		 1113 switch (ds1307->type) {
1114 case ds_1340:
1115 case m41t00:
40ce972d
DA		 1116 /*
1117 * NOTE: ignores century bits; fix before deploying
c065f35c
DB		 1118 * systems that will run through year 2100.
1119 */
1120 break;
a2166858
MF		 1121 case rx_8025:
1122 break;
c065f35c
DB		 1123 default:
1124 if (!(tmp & DS1307_BIT_12HR))
1125 break;
1126
40ce972d
DA		 1127 /*
1128 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB		 1129 * take note...
1130 */
fe20ba70 1131 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB		 1132 if (tmp == 12)
1133 tmp = 0;
1134 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1135 tmp += 12;
1abb0dc9 1136 i2c_smbus_write_byte_data(client,
96fc3a45 1137 ds1307->offset + DS1307_REG_HOUR,
fe20ba70 1138 bin2bcd(tmp));
1abb0dc9
DB		 1139 }
1140
5ea73514 1141 device_set_wakeup_capable(&client->dev, want_irq);
edca66d2 1142 ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
1d1945d2 1143 rtc_ops, THIS_MODULE);
1abb0dc9 1144 if (IS_ERR(ds1307->rtc)) {
4071ea25 1145 return PTR_ERR(ds1307->rtc);
1abb0dc9
DB		 1146 }
1147
cb49a5e9 1148 if (want_irq) {
7abea617
NM		 1149 struct device_node *node = client->dev.of_node;
1150
c5983191
NM		 1151 err = devm_request_threaded_irq(&client->dev,
1152 client->irq, NULL, irq_handler,
1153 IRQF_SHARED | IRQF_ONESHOT,
1154 ds1307->rtc->name, client);
cb49a5e9 1155 if (err) {
4071ea25
AZ		 1156 client->irq = 0;
1157 dev_err(&client->dev, "unable to request IRQ!\n");
7abea617
NM		 1158 goto no_irq;
1159 }
26b3c01f 1160
7abea617
NM		 1161 set_bit(HAS_ALARM, &ds1307->flags);
1162 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
1163
1164 /* Currently supported by OF code only! */
1165 if (!node)
1166 goto no_irq;
1167
1168 err = of_irq_get(node, 1);
1169 if (err <= 0) {
1170 if (err == -EPROBE_DEFER)
1171 goto exit;
1172 goto no_irq;
1173 }
1174 ds1307->wakeirq = err;
1175
1176 err = dev_pm_set_dedicated_wake_irq(&client->dev,
1177 ds1307->wakeirq);
1178 if (err) {
1179 dev_err(&client->dev, "unable to setup wakeIRQ %d!\n",
1180 err);
1181 goto exit;
4071ea25 1182 }
cb49a5e9
RG		 1183 }
1184
7abea617 1185no_irq:
9eab0a78 1186 if (chip->nvram_size) {
4071ea25 1187
edca66d2
JH		 1188 ds1307->nvram = devm_kzalloc(&client->dev,
1189 sizeof(struct bin_attribute),
1190 GFP_KERNEL);
9eab0a78 1191 if (!ds1307->nvram) {
4071ea25
AZ		 1192 dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
1193 } else {
1194
1195 ds1307->nvram->attr.name = "nvram";
1196 ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
1197
1198 sysfs_bin_attr_init(ds1307->nvram);
1199
1200 ds1307->nvram->read = ds1307_nvram_read;
1201 ds1307->nvram->write = ds1307_nvram_write;
1202 ds1307->nvram->size = chip->nvram_size;
1203 ds1307->nvram_offset = chip->nvram_offset;
1204
1205 err = sysfs_create_bin_file(&client->dev.kobj,
1206 ds1307->nvram);
1207 if (err) {
1208 dev_err(&client->dev,
1209 "unable to create sysfs file: %s\n",
1210 ds1307->nvram->attr.name);
1211 } else {
1212 set_bit(HAS_NVRAM, &ds1307->flags);
1213 dev_info(&client->dev, "%zu bytes nvram\n",
1214 ds1307->nvram->size);
1215 }
9eab0a78 1216 }
682d73f6
DB		 1217 }
1218
1abb0dc9
DB		 1219 return 0;
1220
edca66d2 1221exit:
1abb0dc9
DB		 1222 return err;
1223}
1224
5a167f45 1225static int ds1307_remove(struct i2c_client *client)
1abb0dc9 1226{
40ce972d 1227 struct ds1307 *ds1307 = i2c_get_clientdata(client);
cb49a5e9 1228
7abea617
NM		 1229 if (ds1307->wakeirq)
1230 dev_pm_clear_wake_irq(&client->dev);
1231
edca66d2 1232 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
9eab0a78 1233 sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
682d73f6 1234
1abb0dc9
DB		 1235 return 0;
1236}
1237
1238static struct i2c_driver ds1307_driver = {
1239 .driver = {
c065f35c 1240 .name = "rtc-ds1307",
1abb0dc9 1241 },
c065f35c 1242 .probe = ds1307_probe,
5a167f45 1243 .remove = ds1307_remove,
3760f736 1244 .id_table = ds1307_id,
1abb0dc9
DB		 1245};
1246
0abc9201 1247module_i2c_driver(ds1307_driver);
1abb0dc9
DB		 1248
1249MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1250MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)