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Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv...
[linux-2.6-block.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1abb0dc9
DB		 2/*
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
4 *
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
a2166858 7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB		 9 */
10
9c19b893 11#include <linux/acpi.h>
eac7237f
NM		 12#include <linux/bcd.h>
13#include <linux/i2c.h>
1abb0dc9 14#include <linux/init.h>
eac7237f 15#include <linux/module.h>
7ef6d2c2 16#include <linux/of_device.h>
eac7237f
NM		 17#include <linux/rtc/ds1307.h>
18#include <linux/rtc.h>
1abb0dc9 19#include <linux/slab.h>
1abb0dc9 20#include <linux/string.h>
445c0207
AM		 21#include <linux/hwmon.h>
22#include <linux/hwmon-sysfs.h>
6c6ff145 23#include <linux/clk-provider.h>
11e5890b 24#include <linux/regmap.h>
1abb0dc9 25
40ce972d
DA		 26/*
27 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB		 28 * to have set the chip up as a clock (turning on the oscillator and
29 * setting the date and time), Linux can ignore the non-clock features.
30 * That's a natural job for a factory or repair bench.
1abb0dc9
DB		 31 */
32enum ds_type {
045e0e85 33 ds_1307,
300a7735 34 ds_1308,
045e0e85
DB		 35 ds_1337,
36 ds_1338,
37 ds_1339,
38 ds_1340,
0759c886 39 ds_1341,
33df2ee1 40 ds_1388,
97f902b7 41 ds_3231,
8566f70c 42 m41t0,
045e0e85 43 m41t00,
7e580769 44 m41t11,
f4199f85 45 mcp794xx,
a2166858 46 rx_8025,
ee0981be 47 rx_8130,
32d322bc 48 last_ds_type /* always last */
40ce972d 49 /* rs5c372 too? different address... */
1abb0dc9
DB		 50};
51
1abb0dc9
DB		 52/* RTC registers don't differ much, except for the century flag */
53#define DS1307_REG_SECS 0x00 /* 00-59 */
54# define DS1307_BIT_CH 0x80
be5f59f4 55# define DS1340_BIT_nEOSC 0x80
f4199f85 56# define MCP794XX_BIT_ST 0x80
1abb0dc9 57#define DS1307_REG_MIN 0x01 /* 00-59 */
8566f70c 58# define M41T0_BIT_OF 0x80
1abb0dc9 59#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB		 60# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
61# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB		 62# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
63# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
64#define DS1307_REG_WDAY 0x03 /* 01-07 */
f4199f85 65# define MCP794XX_BIT_VBATEN 0x08
1abb0dc9
DB		 66#define DS1307_REG_MDAY 0x04 /* 01-31 */
67#define DS1307_REG_MONTH 0x05 /* 01-12 */
68# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
69#define DS1307_REG_YEAR 0x06 /* 00-99 */
70
40ce972d
DA		 71/*
72 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB		 73 * start at 7, and they differ a LOT. Only control and status matter for
74 * basic RTC date and time functionality; be careful using them.
1abb0dc9 75 */
045e0e85 76#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 77# define DS1307_BIT_OUT 0x80
be5f59f4 78# define DS1338_BIT_OSF 0x20
1abb0dc9
DB		 79# define DS1307_BIT_SQWE 0x10
80# define DS1307_BIT_RS1 0x02
81# define DS1307_BIT_RS0 0x01
82#define DS1337_REG_CONTROL 0x0e
83# define DS1337_BIT_nEOSC 0x80
cb49a5e9 84# define DS1339_BIT_BBSQI 0x20
97f902b7 85# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB		 86# define DS1337_BIT_RS2 0x10
87# define DS1337_BIT_RS1 0x08
88# define DS1337_BIT_INTCN 0x04
89# define DS1337_BIT_A2IE 0x02
90# define DS1337_BIT_A1IE 0x01
045e0e85
DB		 91#define DS1340_REG_CONTROL 0x07
92# define DS1340_BIT_OUT 0x80
93# define DS1340_BIT_FT 0x40
94# define DS1340_BIT_CALIB_SIGN 0x20
95# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG		 96#define DS1340_REG_FLAG 0x09
97# define DS1340_BIT_OSF 0x80
1abb0dc9
DB		 98#define DS1337_REG_STATUS 0x0f
99# define DS1337_BIT_OSF 0x80
6c6ff145 100# define DS3231_BIT_EN32KHZ 0x08
1abb0dc9
DB		 101# define DS1337_BIT_A2I 0x02
102# define DS1337_BIT_A1I 0x01
cb49a5e9 103#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS		 104
105#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 106
a2166858
MF		 107#define RX8025_REG_CTRL1 0x0e
108# define RX8025_BIT_2412 0x20
109#define RX8025_REG_CTRL2 0x0f
110# define RX8025_BIT_PON 0x10
111# define RX8025_BIT_VDET 0x40
112# define RX8025_BIT_XST 0x20
1abb0dc9 113
3ffd4a2f
UKK		 114#define RX8130_REG_ALARM_MIN 0x17
115#define RX8130_REG_ALARM_HOUR 0x18
116#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
117#define RX8130_REG_EXTENSION 0x1c
92cbf12f 118#define RX8130_REG_EXTENSION_WADA BIT(3)
3ffd4a2f
UKK		 119#define RX8130_REG_FLAG 0x1d
120#define RX8130_REG_FLAG_VLF BIT(1)
92cbf12f 121#define RX8130_REG_FLAG_AF BIT(3)
3ffd4a2f 122#define RX8130_REG_CONTROL0 0x1e
92cbf12f
UKK		 123#define RX8130_REG_CONTROL0_AIE BIT(3)
124
125#define MCP794XX_REG_CONTROL 0x07
126# define MCP794XX_BIT_ALM0_EN 0x10
127# define MCP794XX_BIT_ALM1_EN 0x20
128#define MCP794XX_REG_ALARM0_BASE 0x0a
129#define MCP794XX_REG_ALARM0_CTRL 0x0d
130#define MCP794XX_REG_ALARM1_BASE 0x11
131#define MCP794XX_REG_ALARM1_CTRL 0x14
132# define MCP794XX_BIT_ALMX_IF BIT(3)
133# define MCP794XX_BIT_ALMX_C0 BIT(4)
134# define MCP794XX_BIT_ALMX_C1 BIT(5)
135# define MCP794XX_BIT_ALMX_C2 BIT(6)
136# define MCP794XX_BIT_ALMX_POL BIT(7)
137# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
138 MCP794XX_BIT_ALMX_C1 | \
139 MCP794XX_BIT_ALMX_C2)
140
79230ff6
GB		 141#define M41TXX_REG_CONTROL 0x07
142# define M41TXX_BIT_OUT BIT(7)
143# define M41TXX_BIT_FT BIT(6)
144# define M41TXX_BIT_CALIB_SIGN BIT(5)
145# define M41TXX_M_CALIBRATION GENMASK(4, 0)
146
147/* negative offset step is -2.034ppm */
148#define M41TXX_NEG_OFFSET_STEP_PPB 2034
149/* positive offset step is +4.068ppm */
150#define M41TXX_POS_OFFSET_STEP_PPB 4068
151/* Min and max values supported with 'offset' interface by M41TXX */
152#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
153#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
154
1abb0dc9 155struct ds1307 {
1abb0dc9 156 enum ds_type type;
cb49a5e9
RG		 157 unsigned long flags;
158#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
159#define HAS_ALARM 1 /* bit 1 == irq claimed */
11e5890b
HK		 160 struct device *dev;
161 struct regmap *regmap;
162 const char *name;
1abb0dc9 163 struct rtc_device *rtc;
6c6ff145
AM		 164#ifdef CONFIG_COMMON_CLK
165 struct clk_hw clks[2];
166#endif
1abb0dc9
DB		 167};
168
045e0e85 169struct chip_desc {
045e0e85 170 unsigned alarm:1;
9eab0a78
AB		 171 u16 nvram_offset;
172 u16 nvram_size;
e553170a 173 u8 offset; /* register's offset */
e48585de
HK		 174 u8 century_reg;
175 u8 century_enable_bit;
176 u8 century_bit;
0b6ee805 177 u8 bbsqi_bit;
45947127 178 irq_handler_t irq_handler;
1efb98ba 179 const struct rtc_class_ops *rtc_ops;
eb86c306 180 u16 trickle_charger_reg;
57ec2d95 181 u8 (*do_trickle_setup)(struct ds1307 *, u32,
11e5890b 182 bool);
045e0e85
DB		 183};
184
d0e3f61b 185static const struct chip_desc chips[last_ds_type];
cb49a5e9 186
1abb0dc9
DB		 187static int ds1307_get_time(struct device *dev, struct rtc_time *t)
188{
189 struct ds1307 *ds1307 = dev_get_drvdata(dev);
11e5890b 190 int tmp, ret;
e48585de 191 const struct chip_desc *chip = &chips[ds1307->type];
042fa8c7 192 u8 regs[7];
1abb0dc9 193
501f9826
UKK		 194 if (ds1307->type == rx_8130) {
195 unsigned int regflag;
196 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
197 if (ret) {
198 dev_err(dev, "%s error %d\n", "read", ret);
199 return ret;
200 }
201
202 if (regflag & RX8130_REG_FLAG_VLF) {
203 dev_warn_once(dev, "oscillator failed, set time!\n");
204 return -EINVAL;
205 }
206 }
207
045e0e85 208 /* read the RTC date and time registers all at once */
042fa8c7
AB		 209 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
210 sizeof(regs));
11e5890b
HK		 211 if (ret) {
212 dev_err(dev, "%s error %d\n", "read", ret);
213 return ret;
1abb0dc9
DB		 214 }
215
042fa8c7 216 dev_dbg(dev, "%s: %7ph\n", "read", regs);
1abb0dc9 217
8566f70c
SA		 218 /* if oscillator fail bit is set, no data can be trusted */
219 if (ds1307->type == m41t0 &&
042fa8c7 220 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
8566f70c
SA		 221 dev_warn_once(dev, "oscillator failed, set time!\n");
222 return -EINVAL;
223 }
224
b3a50169
AB		 225 tmp = regs[DS1307_REG_SECS];
226 switch (ds1307->type) {
227 case ds_1307:
228 case m41t0:
229 case m41t00:
230 case m41t11:
231 if (tmp & DS1307_BIT_CH)
232 return -EINVAL;
233 break;
234 case ds_1308:
235 case ds_1338:
236 if (tmp & DS1307_BIT_CH)
237 return -EINVAL;
238
239 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
240 if (ret)
241 return ret;
242 if (tmp & DS1338_BIT_OSF)
243 return -EINVAL;
244 break;
245 case ds_1340:
246 if (tmp & DS1340_BIT_nEOSC)
247 return -EINVAL;
248
249 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
250 if (ret)
251 return ret;
252 if (tmp & DS1340_BIT_OSF)
253 return -EINVAL;
254 break;
255 case mcp794xx:
256 if (!(tmp & MCP794XX_BIT_ST))
257 return -EINVAL;
258
259 break;
260 default:
261 break;
262 }
263
042fa8c7
AB		 264 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
265 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
266 tmp = regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70 267 t->tm_hour = bcd2bin(tmp);
042fa8c7
AB		 268 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
269 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
270 tmp = regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 271 t->tm_mon = bcd2bin(tmp) - 1;
042fa8c7 272 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
1abb0dc9 273
042fa8c7 274 if (regs[chip->century_reg] & chip->century_bit &&
e48585de
HK		 275 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
276 t->tm_year += 100;
50d6c0ea 277
1abb0dc9
DB		 278 dev_dbg(dev, "%s secs=%d, mins=%d, "
279 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
280 "read", t->tm_sec, t->tm_min,
281 t->tm_hour, t->tm_mday,
282 t->tm_mon, t->tm_year, t->tm_wday);
283
22652ba7 284 return 0;
1abb0dc9
DB		 285}
286
287static int ds1307_set_time(struct device *dev, struct rtc_time *t)
288{
289 struct ds1307 *ds1307 = dev_get_drvdata(dev);
e48585de 290 const struct chip_desc *chip = &chips[ds1307->type];
1abb0dc9
DB		 291 int result;
292 int tmp;
042fa8c7 293 u8 regs[7];
1abb0dc9
DB		 294
295 dev_dbg(dev, "%s secs=%d, mins=%d, "
296 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG		 297 "write", t->tm_sec, t->tm_min,
298 t->tm_hour, t->tm_mday,
299 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 300
50d6c0ea
AB		 301 if (t->tm_year < 100)
302 return -EINVAL;
303
e48585de
HK		 304#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
305 if (t->tm_year > (chip->century_bit ? 299 : 199))
306 return -EINVAL;
50d6c0ea 307#else
e48585de 308 if (t->tm_year > 199)
50d6c0ea
AB		 309 return -EINVAL;
310#endif
311
042fa8c7
AB		 312 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
313 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
314 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
315 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
316 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
317 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB		 318
319 /* assume 20YY not 19YY */
320 tmp = t->tm_year - 100;
042fa8c7 321 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 322
e48585de 323 if (chip->century_enable_bit)
042fa8c7 324 regs[chip->century_reg] |= chip->century_enable_bit;
e48585de 325 if (t->tm_year > 199 && chip->century_bit)
042fa8c7 326 regs[chip->century_reg] |= chip->century_bit;
e48585de 327
b3a50169
AB		 328 switch (ds1307->type) {
329 case ds_1308:
330 case ds_1338:
331 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
332 DS1338_BIT_OSF, 0);
333 break;
334 case ds_1340:
335 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
336 DS1340_BIT_OSF, 0);
337 break;
338 case mcp794xx:
40ce972d
DA		 339 /*
340 * these bits were cleared when preparing the date/time
341 * values and need to be set again before writing the
042fa8c7 342 * regsfer out to the device.
40ce972d 343 */
042fa8c7
AB		 344 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
345 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
b3a50169
AB		 346 break;
347 default:
348 break;
be5f59f4 349 }
1abb0dc9 350
042fa8c7 351 dev_dbg(dev, "%s: %7ph\n", "write", regs);
1abb0dc9 352
042fa8c7
AB		 353 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
354 sizeof(regs));
11e5890b 355 if (result) {
fed40b73
BS		 356 dev_err(dev, "%s error %d\n", "write", result);
357 return result;
1abb0dc9 358 }
501f9826
UKK		 359
360 if (ds1307->type == rx_8130) {
361 /* clear Voltage Loss Flag as data is available now */
362 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
363 ~(u8)RX8130_REG_FLAG_VLF);
364 if (result) {
365 dev_err(dev, "%s error %d\n", "write", result);
366 return result;
367 }
368 }
369
1abb0dc9
DB		 370 return 0;
371}
372
74d88eb2 373static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 374{
11e5890b 375 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9 376 int ret;
042fa8c7 377 u8 regs[9];
cb49a5e9
RG		 378
379 if (!test_bit(HAS_ALARM, &ds1307->flags))
380 return -EINVAL;
381
382 /* read all ALARM1, ALARM2, and status registers at once */
11e5890b 383 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
042fa8c7 384 regs, sizeof(regs));
11e5890b 385 if (ret) {
cb49a5e9 386 dev_err(dev, "%s error %d\n", "alarm read", ret);
11e5890b 387 return ret;
cb49a5e9
RG		 388 }
389
ff67abd2 390 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
042fa8c7 391 &regs[0], &regs[4], &regs[7]);
cb49a5e9 392
40ce972d
DA		 393 /*
394 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG		 395 * and that all four fields are checked matches
396 */
042fa8c7
AB		 397 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
398 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
399 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
400 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
cb49a5e9
RG		 401
402 /* ... and status */
042fa8c7
AB		 403 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
404 t->pending = !!(regs[8] & DS1337_BIT_A1I);
cb49a5e9
RG		 405
406 dev_dbg(dev, "%s secs=%d, mins=%d, "
407 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
408 "alarm read", t->time.tm_sec, t->time.tm_min,
409 t->time.tm_hour, t->time.tm_mday,
410 t->enabled, t->pending);
411
412 return 0;
413}
414
74d88eb2 415static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 416{
11e5890b 417 struct ds1307 *ds1307 = dev_get_drvdata(dev);
042fa8c7 418 unsigned char regs[9];
cb49a5e9
RG		 419 u8 control, status;
420 int ret;
421
422 if (!test_bit(HAS_ALARM, &ds1307->flags))
423 return -EINVAL;
424
425 dev_dbg(dev, "%s secs=%d, mins=%d, "
426 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
427 "alarm set", t->time.tm_sec, t->time.tm_min,
428 t->time.tm_hour, t->time.tm_mday,
429 t->enabled, t->pending);
430
431 /* read current status of both alarms and the chip */
042fa8c7
AB		 432 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
433 sizeof(regs));
11e5890b 434 if (ret) {
cb49a5e9 435 dev_err(dev, "%s error %d\n", "alarm write", ret);
11e5890b 436 return ret;
cb49a5e9 437 }
042fa8c7
AB		 438 control = regs[7];
439 status = regs[8];
cb49a5e9 440
ff67abd2 441 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
042fa8c7 442 &regs[0], &regs[4], control, status);
cb49a5e9
RG		 443
444 /* set ALARM1, using 24 hour and day-of-month modes */
042fa8c7
AB		 445 regs[0] = bin2bcd(t->time.tm_sec);
446 regs[1] = bin2bcd(t->time.tm_min);
447 regs[2] = bin2bcd(t->time.tm_hour);
448 regs[3] = bin2bcd(t->time.tm_mday);
cb49a5e9
RG		 449
450 /* set ALARM2 to non-garbage */
042fa8c7
AB		 451 regs[4] = 0;
452 regs[5] = 0;
453 regs[6] = 0;
cb49a5e9 454
5919fb97 455 /* disable alarms */
042fa8c7
AB		 456 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
457 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
cb49a5e9 458
042fa8c7
AB		 459 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
460 sizeof(regs));
11e5890b 461 if (ret) {
cb49a5e9 462 dev_err(dev, "can't set alarm time\n");
fed40b73 463 return ret;
cb49a5e9
RG		 464 }
465
5919fb97
NB		 466 /* optionally enable ALARM1 */
467 if (t->enabled) {
468 dev_dbg(dev, "alarm IRQ armed\n");
042fa8c7
AB		 469 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
470 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
5919fb97
NB		 471 }
472
cb49a5e9
RG		 473 return 0;
474}
475
16380c15 476static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9 477{
11e5890b 478 struct ds1307 *ds1307 = dev_get_drvdata(dev);
cb49a5e9 479
16380c15
JS		 480 if (!test_bit(HAS_ALARM, &ds1307->flags))
481 return -ENOTTY;
cb49a5e9 482
078f3f64
HK		 483 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
484 DS1337_BIT_A1IE,
485 enabled ? DS1337_BIT_A1IE : 0);
cb49a5e9
RG		 486}
487
d0e3f61b
UKK		 488static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
489{
490 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
491 DS1307_TRICKLE_CHARGER_NO_DIODE;
682d73f6 492
d0e3f61b
UKK		 493 switch (ohms) {
494 case 250:
495 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
496 break;
497 case 2000:
498 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
499 break;
500 case 4000:
501 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
502 break;
503 default:
504 dev_warn(ds1307->dev,
505 "Unsupported ohm value %u in dt\n", ohms);
506 return 0;
507 }
508 return setup;
509}
ee0981be 510
ee0981be
MV		 511static irqreturn_t rx8130_irq(int irq, void *dev_id)
512{
513 struct ds1307 *ds1307 = dev_id;
514 struct mutex *lock = &ds1307->rtc->ops_lock;
515 u8 ctl[3];
516 int ret;
517
518 mutex_lock(lock);
519
520 /* Read control registers. */
f2b48012
AB		 521 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
522 sizeof(ctl));
ee0981be
MV		 523 if (ret < 0)
524 goto out;
525 if (!(ctl[1] & RX8130_REG_FLAG_AF))
526 goto out;
527 ctl[1] &= ~RX8130_REG_FLAG_AF;
528 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
529
f2b48012
AB		 530 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
531 sizeof(ctl));
ee0981be
MV		 532 if (ret < 0)
533 goto out;
534
535 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
536
537out:
538 mutex_unlock(lock);
539
540 return IRQ_HANDLED;
541}
542
543static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
544{
545 struct ds1307 *ds1307 = dev_get_drvdata(dev);
546 u8 ald[3], ctl[3];
547 int ret;
548
549 if (!test_bit(HAS_ALARM, &ds1307->flags))
550 return -EINVAL;
551
552 /* Read alarm registers. */
f2b48012
AB		 553 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
554 sizeof(ald));
ee0981be
MV		 555 if (ret < 0)
556 return ret;
557
558 /* Read control registers. */
f2b48012
AB		 559 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
560 sizeof(ctl));
ee0981be
MV		 561 if (ret < 0)
562 return ret;
563
564 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
565 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
566
567 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
568 t->time.tm_sec = -1;
569 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
570 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
571 t->time.tm_wday = -1;
572 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
573 t->time.tm_mon = -1;
574 t->time.tm_year = -1;
575 t->time.tm_yday = -1;
576 t->time.tm_isdst = -1;
577
578 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
579 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
580 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
581
582 return 0;
583}
584
585static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
586{
587 struct ds1307 *ds1307 = dev_get_drvdata(dev);
588 u8 ald[3], ctl[3];
589 int ret;
590
591 if (!test_bit(HAS_ALARM, &ds1307->flags))
592 return -EINVAL;
593
594 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
595 "enabled=%d pending=%d\n", __func__,
596 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
597 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
598 t->enabled, t->pending);
599
600 /* Read control registers. */
f2b48012
AB		 601 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
602 sizeof(ctl));
ee0981be
MV		 603 if (ret < 0)
604 return ret;
605
3f929cad
UKK		 606 ctl[0] &= RX8130_REG_EXTENSION_WADA;
607 ctl[1] &= ~RX8130_REG_FLAG_AF;
ee0981be
MV		 608 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
609
f2b48012
AB		 610 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
611 sizeof(ctl));
ee0981be
MV		 612 if (ret < 0)
613 return ret;
614
615 /* Hardware alarm precision is 1 minute! */
616 ald[0] = bin2bcd(t->time.tm_min);
617 ald[1] = bin2bcd(t->time.tm_hour);
618 ald[2] = bin2bcd(t->time.tm_mday);
619
f2b48012
AB		 620 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
621 sizeof(ald));
ee0981be
MV		 622 if (ret < 0)
623 return ret;
624
625 if (!t->enabled)
626 return 0;
627
628 ctl[2] |= RX8130_REG_CONTROL0_AIE;
629
3f929cad 630 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
ee0981be
MV		 631}
632
d0e3f61b
UKK		 633static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
634{
635 struct ds1307 *ds1307 = dev_get_drvdata(dev);
636 int ret, reg;
637
638 if (!test_bit(HAS_ALARM, &ds1307->flags))
639 return -EINVAL;
640
641 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
642 if (ret < 0)
643 return ret;
644
645 if (enabled)
646 reg |= RX8130_REG_CONTROL0_AIE;
647 else
648 reg &= ~RX8130_REG_CONTROL0_AIE;
649
650 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
651}
652
653static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
654{
655 struct ds1307 *ds1307 = dev_id;
656 struct mutex *lock = &ds1307->rtc->ops_lock;
657 int reg, ret;
658
659 mutex_lock(lock);
660
661 /* Check and clear alarm 0 interrupt flag. */
662 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
663 if (ret)
664 goto out;
665 if (!(reg & MCP794XX_BIT_ALMX_IF))
666 goto out;
667 reg &= ~MCP794XX_BIT_ALMX_IF;
668 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
669 if (ret)
670 goto out;
671
672 /* Disable alarm 0. */
673 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
674 MCP794XX_BIT_ALM0_EN, 0);
675 if (ret)
676 goto out;
677
678 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
679
680out:
681 mutex_unlock(lock);
682
683 return IRQ_HANDLED;
684}
685
686static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
687{
688 struct ds1307 *ds1307 = dev_get_drvdata(dev);
689 u8 regs[10];
690 int ret;
691
692 if (!test_bit(HAS_ALARM, &ds1307->flags))
693 return -EINVAL;
694
695 /* Read control and alarm 0 registers. */
696 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
697 sizeof(regs));
698 if (ret)
699 return ret;
700
701 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
702
703 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
704 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
705 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
706 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
707 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
708 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
709 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
710 t->time.tm_year = -1;
711 t->time.tm_yday = -1;
712 t->time.tm_isdst = -1;
713
714 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
715 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
716 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
717 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
718 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
719 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
720 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
721
722 return 0;
723}
724
725/*
726 * We may have a random RTC weekday, therefore calculate alarm weekday based
727 * on current weekday we read from the RTC timekeeping regs
728 */
729static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
730{
731 struct rtc_time tm_now;
732 int days_now, days_alarm, ret;
733
734 ret = ds1307_get_time(dev, &tm_now);
735 if (ret)
736 return ret;
737
738 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
739 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
740
741 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
742}
743
744static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
745{
746 struct ds1307 *ds1307 = dev_get_drvdata(dev);
747 unsigned char regs[10];
748 int wday, ret;
749
750 if (!test_bit(HAS_ALARM, &ds1307->flags))
751 return -EINVAL;
752
753 wday = mcp794xx_alm_weekday(dev, &t->time);
754 if (wday < 0)
755 return wday;
756
757 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
758 "enabled=%d pending=%d\n", __func__,
759 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
760 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
761 t->enabled, t->pending);
762
763 /* Read control and alarm 0 registers. */
764 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
765 sizeof(regs));
766 if (ret)
767 return ret;
768
769 /* Set alarm 0, using 24-hour and day-of-month modes. */
770 regs[3] = bin2bcd(t->time.tm_sec);
771 regs[4] = bin2bcd(t->time.tm_min);
772 regs[5] = bin2bcd(t->time.tm_hour);
773 regs[6] = wday;
774 regs[7] = bin2bcd(t->time.tm_mday);
775 regs[8] = bin2bcd(t->time.tm_mon + 1);
776
777 /* Clear the alarm 0 interrupt flag. */
778 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
779 /* Set alarm match: second, minute, hour, day, date, month. */
780 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
781 /* Disable interrupt. We will not enable until completely programmed */
782 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
783
784 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
785 sizeof(regs));
786 if (ret)
787 return ret;
788
789 if (!t->enabled)
790 return 0;
791 regs[0] |= MCP794XX_BIT_ALM0_EN;
792 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
793}
794
795static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
ee0981be
MV		 796{
797 struct ds1307 *ds1307 = dev_get_drvdata(dev);
ee0981be
MV		 798
799 if (!test_bit(HAS_ALARM, &ds1307->flags))
800 return -EINVAL;
801
d0e3f61b
UKK		 802 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
803 MCP794XX_BIT_ALM0_EN,
804 enabled ? MCP794XX_BIT_ALM0_EN : 0);
805}
ee0981be 806
d0e3f61b
UKK		 807static int m41txx_rtc_read_offset(struct device *dev, long *offset)
808{
809 struct ds1307 *ds1307 = dev_get_drvdata(dev);
810 unsigned int ctrl_reg;
811 u8 val;
812
813 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
814
815 val = ctrl_reg & M41TXX_M_CALIBRATION;
816
817 /* check if positive */
818 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
819 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
ee0981be 820 else
d0e3f61b 821 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
ee0981be 822
d0e3f61b
UKK		 823 return 0;
824}
825
826static int m41txx_rtc_set_offset(struct device *dev, long offset)
827{
828 struct ds1307 *ds1307 = dev_get_drvdata(dev);
829 unsigned int ctrl_reg;
830
831 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
832 return -ERANGE;
833
834 if (offset >= 0) {
835 ctrl_reg = DIV_ROUND_CLOSEST(offset,
836 M41TXX_POS_OFFSET_STEP_PPB);
837 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
838 } else {
839 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
840 M41TXX_NEG_OFFSET_STEP_PPB);
841 }
842
843 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
844 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
845 ctrl_reg);
ee0981be
MV		 846}
847
d0e3f61b
UKK		 848static const struct rtc_class_ops rx8130_rtc_ops = {
849 .read_time = ds1307_get_time,
850 .set_time = ds1307_set_time,
851 .read_alarm = rx8130_read_alarm,
852 .set_alarm = rx8130_set_alarm,
853 .alarm_irq_enable = rx8130_alarm_irq_enable,
854};
855
856static const struct rtc_class_ops mcp794xx_rtc_ops = {
857 .read_time = ds1307_get_time,
858 .set_time = ds1307_set_time,
859 .read_alarm = mcp794xx_read_alarm,
860 .set_alarm = mcp794xx_set_alarm,
861 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
862};
863
864static const struct rtc_class_ops m41txx_rtc_ops = {
865 .read_time = ds1307_get_time,
866 .set_time = ds1307_set_time,
867 .read_alarm = ds1337_read_alarm,
868 .set_alarm = ds1337_set_alarm,
869 .alarm_irq_enable = ds1307_alarm_irq_enable,
870 .read_offset = m41txx_rtc_read_offset,
871 .set_offset = m41txx_rtc_set_offset,
872};
873
874static const struct chip_desc chips[last_ds_type] = {
875 [ds_1307] = {
876 .nvram_offset = 8,
877 .nvram_size = 56,
878 },
879 [ds_1308] = {
880 .nvram_offset = 8,
881 .nvram_size = 56,
882 },
883 [ds_1337] = {
884 .alarm = 1,
885 .century_reg = DS1307_REG_MONTH,
886 .century_bit = DS1337_BIT_CENTURY,
887 },
888 [ds_1338] = {
889 .nvram_offset = 8,
890 .nvram_size = 56,
891 },
892 [ds_1339] = {
893 .alarm = 1,
894 .century_reg = DS1307_REG_MONTH,
895 .century_bit = DS1337_BIT_CENTURY,
896 .bbsqi_bit = DS1339_BIT_BBSQI,
897 .trickle_charger_reg = 0x10,
898 .do_trickle_setup = &do_trickle_setup_ds1339,
899 },
900 [ds_1340] = {
901 .century_reg = DS1307_REG_HOUR,
902 .century_enable_bit = DS1340_BIT_CENTURY_EN,
903 .century_bit = DS1340_BIT_CENTURY,
904 .do_trickle_setup = &do_trickle_setup_ds1339,
905 .trickle_charger_reg = 0x08,
906 },
907 [ds_1341] = {
908 .century_reg = DS1307_REG_MONTH,
909 .century_bit = DS1337_BIT_CENTURY,
910 },
911 [ds_1388] = {
912 .offset = 1,
913 .trickle_charger_reg = 0x0a,
914 },
915 [ds_3231] = {
916 .alarm = 1,
917 .century_reg = DS1307_REG_MONTH,
918 .century_bit = DS1337_BIT_CENTURY,
919 .bbsqi_bit = DS3231_BIT_BBSQW,
920 },
921 [rx_8130] = {
922 .alarm = 1,
923 /* this is battery backed SRAM */
924 .nvram_offset = 0x20,
925 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
926 .offset = 0x10,
927 .irq_handler = rx8130_irq,
928 .rtc_ops = &rx8130_rtc_ops,
929 },
930 [m41t0] = {
931 .rtc_ops = &m41txx_rtc_ops,
932 },
933 [m41t00] = {
934 .rtc_ops = &m41txx_rtc_ops,
935 },
936 [m41t11] = {
937 /* this is battery backed SRAM */
938 .nvram_offset = 8,
939 .nvram_size = 56,
940 .rtc_ops = &m41txx_rtc_ops,
941 },
942 [mcp794xx] = {
943 .alarm = 1,
944 /* this is battery backed SRAM */
945 .nvram_offset = 0x20,
946 .nvram_size = 0x40,
947 .irq_handler = mcp794xx_irq,
948 .rtc_ops = &mcp794xx_rtc_ops,
949 },
950};
951
952static const struct i2c_device_id ds1307_id[] = {
953 { "ds1307", ds_1307 },
954 { "ds1308", ds_1308 },
955 { "ds1337", ds_1337 },
956 { "ds1338", ds_1338 },
957 { "ds1339", ds_1339 },
958 { "ds1388", ds_1388 },
959 { "ds1340", ds_1340 },
960 { "ds1341", ds_1341 },
961 { "ds3231", ds_3231 },
962 { "m41t0", m41t0 },
963 { "m41t00", m41t00 },
964 { "m41t11", m41t11 },
965 { "mcp7940x", mcp794xx },
966 { "mcp7941x", mcp794xx },
967 { "pt7c4338", ds_1307 },
968 { "rx8025", rx_8025 },
969 { "isl12057", ds_1337 },
970 { "rx8130", rx_8130 },
971 { }
972};
973MODULE_DEVICE_TABLE(i2c, ds1307_id);
974
975#ifdef CONFIG_OF
976static const struct of_device_id ds1307_of_match[] = {
977 {
978 .compatible = "dallas,ds1307",
979 .data = (void *)ds_1307
980 },
981 {
982 .compatible = "dallas,ds1308",
983 .data = (void *)ds_1308
984 },
985 {
986 .compatible = "dallas,ds1337",
987 .data = (void *)ds_1337
988 },
989 {
990 .compatible = "dallas,ds1338",
991 .data = (void *)ds_1338
992 },
993 {
994 .compatible = "dallas,ds1339",
995 .data = (void *)ds_1339
996 },
997 {
998 .compatible = "dallas,ds1388",
999 .data = (void *)ds_1388
1000 },
1001 {
1002 .compatible = "dallas,ds1340",
1003 .data = (void *)ds_1340
1004 },
1005 {
1006 .compatible = "dallas,ds1341",
1007 .data = (void *)ds_1341
1008 },
1009 {
1010 .compatible = "maxim,ds3231",
1011 .data = (void *)ds_3231
1012 },
1013 {
1014 .compatible = "st,m41t0",
1015 .data = (void *)m41t0
1016 },
1017 {
1018 .compatible = "st,m41t00",
1019 .data = (void *)m41t00
1020 },
1021 {
1022 .compatible = "st,m41t11",
1023 .data = (void *)m41t11
1024 },
1025 {
1026 .compatible = "microchip,mcp7940x",
1027 .data = (void *)mcp794xx
1028 },
1029 {
1030 .compatible = "microchip,mcp7941x",
1031 .data = (void *)mcp794xx
1032 },
1033 {
1034 .compatible = "pericom,pt7c4338",
1035 .data = (void *)ds_1307
1036 },
1037 {
1038 .compatible = "epson,rx8025",
1039 .data = (void *)rx_8025
1040 },
1041 {
1042 .compatible = "isil,isl12057",
1043 .data = (void *)ds_1337
1044 },
1045 {
1046 .compatible = "epson,rx8130",
1047 .data = (void *)rx_8130
1048 },
1049 { }
1050};
1051MODULE_DEVICE_TABLE(of, ds1307_of_match);
1052#endif
1053
1054#ifdef CONFIG_ACPI
1055static const struct acpi_device_id ds1307_acpi_ids[] = {
1056 { .id = "DS1307", .driver_data = ds_1307 },
1057 { .id = "DS1308", .driver_data = ds_1308 },
1058 { .id = "DS1337", .driver_data = ds_1337 },
1059 { .id = "DS1338", .driver_data = ds_1338 },
1060 { .id = "DS1339", .driver_data = ds_1339 },
1061 { .id = "DS1388", .driver_data = ds_1388 },
1062 { .id = "DS1340", .driver_data = ds_1340 },
1063 { .id = "DS1341", .driver_data = ds_1341 },
1064 { .id = "DS3231", .driver_data = ds_3231 },
1065 { .id = "M41T0", .driver_data = m41t0 },
1066 { .id = "M41T00", .driver_data = m41t00 },
1067 { .id = "M41T11", .driver_data = m41t11 },
1068 { .id = "MCP7940X", .driver_data = mcp794xx },
1069 { .id = "MCP7941X", .driver_data = mcp794xx },
1070 { .id = "PT7C4338", .driver_data = ds_1307 },
1071 { .id = "RX8025", .driver_data = rx_8025 },
1072 { .id = "ISL12057", .driver_data = ds_1337 },
1073 { .id = "RX8130", .driver_data = rx_8130 },
1074 { }
1075};
1076MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1077#endif
ee0981be 1078
1d1945d2 1079/*
d0e3f61b
UKK		 1080 * The ds1337 and ds1339 both have two alarms, but we only use the first
1081 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1082 * signal; ds1339 chips have only one alarm signal.
1d1945d2 1083 */
d0e3f61b 1084static irqreturn_t ds1307_irq(int irq, void *dev_id)
1d1945d2 1085{
d0e3f61b
UKK		 1086 struct ds1307 *ds1307 = dev_id;
1087 struct mutex *lock = &ds1307->rtc->ops_lock;
1088 int stat, ret;
1d1945d2 1089
2fb07a10 1090 mutex_lock(lock);
d0e3f61b 1091 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
11e5890b 1092 if (ret)
1d1945d2
SG		 1093 goto out;
1094
d0e3f61b
UKK		 1095 if (stat & DS1337_BIT_A1I) {
1096 stat &= ~DS1337_BIT_A1I;
1097 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1d1945d2 1098
d0e3f61b
UKK		 1099 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1100 DS1337_BIT_A1IE, 0);
1101 if (ret)
1102 goto out;
1103
1104 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1105 }
1d1945d2
SG		 1106
1107out:
2fb07a10
FB		 1108 mutex_unlock(lock);
1109
1110 return IRQ_HANDLED;
1d1945d2
SG		 1111}
1112
d0e3f61b 1113/*----------------------------------------------------------------------*/
79230ff6 1114
d0e3f61b
UKK		 1115static const struct rtc_class_ops ds13xx_rtc_ops = {
1116 .read_time = ds1307_get_time,
1117 .set_time = ds1307_set_time,
1118 .read_alarm = ds1337_read_alarm,
1119 .set_alarm = ds1337_set_alarm,
1120 .alarm_irq_enable = ds1307_alarm_irq_enable,
1121};
79230ff6 1122
6a5f2a1f
AB		 1123static ssize_t frequency_test_store(struct device *dev,
1124 struct device_attribute *attr,
1125 const char *buf, size_t count)
b41c23e1 1126{
6a5f2a1f 1127 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
b41c23e1
GB		 1128 bool freq_test_en;
1129 int ret;
1130
1131 ret = kstrtobool(buf, &freq_test_en);
1132 if (ret) {
1133 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1134 return ret;
1135 }
1136
1137 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1138 freq_test_en ? M41TXX_BIT_FT : 0);
1139
1140 return count;
1141}
1142
6a5f2a1f
AB		 1143static ssize_t frequency_test_show(struct device *dev,
1144 struct device_attribute *attr,
1145 char *buf)
b41c23e1 1146{
6a5f2a1f 1147 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
b41c23e1
GB		 1148 unsigned int ctrl_reg;
1149
1150 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1151
1152 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1153 "off\n");
1154}
1155
6a5f2a1f 1156static DEVICE_ATTR_RW(frequency_test);
b41c23e1
GB		 1157
1158static struct attribute *rtc_freq_test_attrs[] = {
6a5f2a1f 1159 &dev_attr_frequency_test.attr,
b41c23e1
GB		 1160 NULL,
1161};
1162
1163static const struct attribute_group rtc_freq_test_attr_group = {
1164 .attrs = rtc_freq_test_attrs,
1165};
1166
b41c23e1
GB		 1167static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1168{
1169 int err;
1170
1171 switch (ds1307->type) {
1172 case m41t0:
1173 case m41t00:
1174 case m41t11:
6a5f2a1f
AB		 1175 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1176 if (err)
b41c23e1 1177 return err;
b41c23e1
GB		 1178 break;
1179 default:
1180 break;
1181 }
1182
1183 return 0;
1184}
1185
1d1945d2
SG		 1186/*----------------------------------------------------------------------*/
1187
abc925f7
AB		 1188static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1189 size_t bytes)
682d73f6 1190{
abc925f7 1191 struct ds1307 *ds1307 = priv;
969fa07b 1192 const struct chip_desc *chip = &chips[ds1307->type];
682d73f6 1193
969fa07b 1194 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
abc925f7 1195 val, bytes);
682d73f6
DB		 1196}
1197
abc925f7
AB		 1198static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1199 size_t bytes)
682d73f6 1200{
abc925f7 1201 struct ds1307 *ds1307 = priv;
969fa07b 1202 const struct chip_desc *chip = &chips[ds1307->type];
682d73f6 1203
969fa07b 1204 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
abc925f7 1205 val, bytes);
682d73f6
DB		 1206}
1207
682d73f6
DB		 1208/*----------------------------------------------------------------------*/
1209
d8490fd5 1210static u8 ds1307_trickle_init(struct ds1307 *ds1307,
7624df48 1211 const struct chip_desc *chip)
33b04b7b 1212{
57ec2d95 1213 u32 ohms;
33b04b7b
MV		 1214 bool diode = true;
1215
1216 if (!chip->do_trickle_setup)
d8490fd5
HK		 1217 return 0;
1218
11e5890b
HK		 1219 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1220 &ohms))
d8490fd5
HK		 1221 return 0;
1222
11e5890b 1223 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
33b04b7b 1224 diode = false;
d8490fd5
HK		 1225
1226 return chip->do_trickle_setup(ds1307, ohms, diode);
33b04b7b
MV		 1227}
1228
445c0207
AM		 1229/*----------------------------------------------------------------------*/
1230
6b583a64 1231#if IS_REACHABLE(CONFIG_HWMON)
445c0207
AM		 1232
1233/*
1234 * Temperature sensor support for ds3231 devices.
1235 */
1236
1237#define DS3231_REG_TEMPERATURE 0x11
1238
1239/*
1240 * A user-initiated temperature conversion is not started by this function,
1241 * so the temperature is updated once every 64 seconds.
1242 */
9a3dce62 1243static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
445c0207
AM		 1244{
1245 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1246 u8 temp_buf[2];
1247 s16 temp;
1248 int ret;
1249
11e5890b
HK		 1250 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1251 temp_buf, sizeof(temp_buf));
1252 if (ret)
445c0207 1253 return ret;
445c0207
AM		 1254 /*
1255 * Temperature is represented as a 10-bit code with a resolution of
1256 * 0.25 degree celsius and encoded in two's complement format.
1257 */
1258 temp = (temp_buf[0] << 8) | temp_buf[1];
1259 temp >>= 6;
1260 *mC = temp * 250;
1261
1262 return 0;
1263}
1264
1265static ssize_t ds3231_hwmon_show_temp(struct device *dev,
4057a66e 1266 struct device_attribute *attr, char *buf)
445c0207
AM		 1267{
1268 int ret;
9a3dce62 1269 s32 temp;
445c0207
AM		 1270
1271 ret = ds3231_hwmon_read_temp(dev, &temp);
1272 if (ret)
1273 return ret;
1274
1275 return sprintf(buf, "%d\n", temp);
1276}
b4be271c 1277static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
4057a66e 1278 NULL, 0);
445c0207
AM		 1279
1280static struct attribute *ds3231_hwmon_attrs[] = {
1281 &sensor_dev_attr_temp1_input.dev_attr.attr,
1282 NULL,
1283};
1284ATTRIBUTE_GROUPS(ds3231_hwmon);
1285
1286static void ds1307_hwmon_register(struct ds1307 *ds1307)
1287{
1288 struct device *dev;
1289
1290 if (ds1307->type != ds_3231)
1291 return;
1292
11e5890b 1293 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
4057a66e
AB		 1294 ds1307,
1295 ds3231_hwmon_groups);
445c0207 1296 if (IS_ERR(dev)) {
11e5890b
HK		 1297 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1298 PTR_ERR(dev));
445c0207
AM		 1299 }
1300}
1301
1302#else
1303
1304static void ds1307_hwmon_register(struct ds1307 *ds1307)
1305{
1306}
1307
6c6ff145
AM		 1308#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1309
1310/*----------------------------------------------------------------------*/
1311
1312/*
1313 * Square-wave output support for DS3231
1314 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1315 */
1316#ifdef CONFIG_COMMON_CLK
1317
1318enum {
1319 DS3231_CLK_SQW = 0,
1320 DS3231_CLK_32KHZ,
1321};
1322
1323#define clk_sqw_to_ds1307(clk) \
1324 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1325#define clk_32khz_to_ds1307(clk) \
1326 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1327
1328static int ds3231_clk_sqw_rates[] = {
1329 1,
1330 1024,
1331 4096,
1332 8192,
1333};
1334
1335static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1336{
6c6ff145 1337 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1338 int ret;
1339
1340 mutex_lock(lock);
078f3f64
HK		 1341 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1342 mask, value);
6c6ff145
AM		 1343 mutex_unlock(lock);
1344
1345 return ret;
1346}
1347
1348static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1349 unsigned long parent_rate)
1350{
1351 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1352 int control, ret;
6c6ff145
AM		 1353 int rate_sel = 0;
1354
11e5890b
HK		 1355 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1356 if (ret)
1357 return ret;
6c6ff145
AM		 1358 if (control & DS1337_BIT_RS1)
1359 rate_sel += 1;
1360 if (control & DS1337_BIT_RS2)
1361 rate_sel += 2;
1362
1363 return ds3231_clk_sqw_rates[rate_sel];
1364}
1365
1366static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
4057a66e 1367 unsigned long *prate)
6c6ff145
AM		 1368{
1369 int i;
1370
1371 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1372 if (ds3231_clk_sqw_rates[i] <= rate)
1373 return ds3231_clk_sqw_rates[i];
1374 }
1375
1376 return 0;
1377}
1378
1379static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
4057a66e 1380 unsigned long parent_rate)
6c6ff145
AM		 1381{
1382 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1383 int control = 0;
1384 int rate_sel;
1385
1386 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1387 rate_sel++) {
1388 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1389 break;
1390 }
1391
1392 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1393 return -EINVAL;
1394
1395 if (rate_sel & 1)
1396 control |= DS1337_BIT_RS1;
1397 if (rate_sel & 2)
1398 control |= DS1337_BIT_RS2;
1399
1400 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1401 control);
1402}
1403
1404static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1405{
1406 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1407
1408 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1409}
1410
1411static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1412{
1413 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1414
1415 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1416}
1417
1418static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1419{
1420 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
11e5890b 1421 int control, ret;
6c6ff145 1422
11e5890b
HK		 1423 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1424 if (ret)
1425 return ret;
6c6ff145
AM		 1426
1427 return !(control & DS1337_BIT_INTCN);
1428}
1429
1430static const struct clk_ops ds3231_clk_sqw_ops = {
1431 .prepare = ds3231_clk_sqw_prepare,
1432 .unprepare = ds3231_clk_sqw_unprepare,
1433 .is_prepared = ds3231_clk_sqw_is_prepared,
1434 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1435 .round_rate = ds3231_clk_sqw_round_rate,
1436 .set_rate = ds3231_clk_sqw_set_rate,
1437};
1438
1439static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
4057a66e 1440 unsigned long parent_rate)
6c6ff145
AM		 1441{
1442 return 32768;
1443}
1444
1445static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1446{
6c6ff145 1447 struct mutex *lock = &ds1307->rtc->ops_lock;
6c6ff145
AM		 1448 int ret;
1449
1450 mutex_lock(lock);
078f3f64
HK		 1451 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1452 DS3231_BIT_EN32KHZ,
1453 enable ? DS3231_BIT_EN32KHZ : 0);
6c6ff145
AM		 1454 mutex_unlock(lock);
1455
1456 return ret;
1457}
1458
1459static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1460{
1461 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1462
1463 return ds3231_clk_32khz_control(ds1307, true);
1464}
1465
1466static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1467{
1468 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1469
1470 ds3231_clk_32khz_control(ds1307, false);
1471}
1472
1473static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1474{
1475 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
11e5890b 1476 int status, ret;
6c6ff145 1477
11e5890b
HK		 1478 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1479 if (ret)
1480 return ret;
6c6ff145
AM		 1481
1482 return !!(status & DS3231_BIT_EN32KHZ);
1483}
1484
1485static const struct clk_ops ds3231_clk_32khz_ops = {
1486 .prepare = ds3231_clk_32khz_prepare,
1487 .unprepare = ds3231_clk_32khz_unprepare,
1488 .is_prepared = ds3231_clk_32khz_is_prepared,
1489 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1490};
1491
1492static struct clk_init_data ds3231_clks_init[] = {
1493 [DS3231_CLK_SQW] = {
1494 .name = "ds3231_clk_sqw",
1495 .ops = &ds3231_clk_sqw_ops,
6c6ff145
AM		 1496 },
1497 [DS3231_CLK_32KHZ] = {
1498 .name = "ds3231_clk_32khz",
1499 .ops = &ds3231_clk_32khz_ops,
6c6ff145
AM		 1500 },
1501};
1502
1503static int ds3231_clks_register(struct ds1307 *ds1307)
1504{
11e5890b 1505 struct device_node *node = ds1307->dev->of_node;
6c6ff145
AM		 1506 struct clk_onecell_data *onecell;
1507 int i;
1508
11e5890b 1509 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
6c6ff145
AM		 1510 if (!onecell)
1511 return -ENOMEM;
1512
1513 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
11e5890b
HK		 1514 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1515 sizeof(onecell->clks[0]), GFP_KERNEL);
6c6ff145
AM		 1516 if (!onecell->clks)
1517 return -ENOMEM;
1518
1519 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1520 struct clk_init_data init = ds3231_clks_init[i];
1521
1522 /*
1523 * Interrupt signal due to alarm conditions and square-wave
1524 * output share same pin, so don't initialize both.
1525 */
1526 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1527 continue;
1528
1529 /* optional override of the clockname */
1530 of_property_read_string_index(node, "clock-output-names", i,
4057a66e 1531 &init.name);
6c6ff145
AM		 1532 ds1307->clks[i].init = &init;
1533
11e5890b
HK		 1534 onecell->clks[i] = devm_clk_register(ds1307->dev,
1535 &ds1307->clks[i]);
6c6ff145
AM		 1536 if (IS_ERR(onecell->clks[i]))
1537 return PTR_ERR(onecell->clks[i]);
1538 }
1539
1540 if (!node)
1541 return 0;
1542
1543 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1544
1545 return 0;
1546}
1547
1548static void ds1307_clks_register(struct ds1307 *ds1307)
1549{
1550 int ret;
1551
1552 if (ds1307->type != ds_3231)
1553 return;
1554
1555 ret = ds3231_clks_register(ds1307);
1556 if (ret) {
11e5890b
HK		 1557 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1558 ret);
6c6ff145
AM		 1559 }
1560}
1561
1562#else
1563
1564static void ds1307_clks_register(struct ds1307 *ds1307)
1565{
1566}
1567
1568#endif /* CONFIG_COMMON_CLK */
445c0207 1569
11e5890b
HK		 1570static const struct regmap_config regmap_config = {
1571 .reg_bits = 8,
1572 .val_bits = 8,
11e5890b
HK		 1573};
1574
5a167f45
GKH		 1575static int ds1307_probe(struct i2c_client *client,
1576 const struct i2c_device_id *id)
1abb0dc9
DB		 1577{
1578 struct ds1307 *ds1307;
1579 int err = -ENODEV;
584ce30c 1580 int tmp;
7624df48 1581 const struct chip_desc *chip;
82e2d43f 1582 bool want_irq;
8bc2a407 1583 bool ds1307_can_wakeup_device = false;
042fa8c7 1584 unsigned char regs[8];
01ce893d 1585 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
d8490fd5 1586 u8 trickle_charger_setup = 0;
1abb0dc9 1587
edca66d2 1588 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 1589 if (!ds1307)
c065f35c 1590 return -ENOMEM;
045e0e85 1591
11e5890b
HK		 1592 dev_set_drvdata(&client->dev, ds1307);
1593 ds1307->dev = &client->dev;
1594 ds1307->name = client->name;
11e5890b
HK		 1595
1596 ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1597 if (IS_ERR(ds1307->regmap)) {
1598 dev_err(ds1307->dev, "regmap allocation failed\n");
1599 return PTR_ERR(ds1307->regmap);
1600 }
33df2ee1 1601
11e5890b 1602 i2c_set_clientdata(client, ds1307);
7ef6d2c2
JMC		 1603
1604 if (client->dev.of_node) {
1605 ds1307->type = (enum ds_type)
1606 of_device_get_match_data(&client->dev);
1607 chip = &chips[ds1307->type];
1608 } else if (id) {
9c19b893
TH		 1609 chip = &chips[id->driver_data];
1610 ds1307->type = id->driver_data;
1611 } else {
1612 const struct acpi_device_id *acpi_id;
1613
1614 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
11e5890b 1615 ds1307->dev);
9c19b893
TH		 1616 if (!acpi_id)
1617 return -ENODEV;
1618 chip = &chips[acpi_id->driver_data];
1619 ds1307->type = acpi_id->driver_data;
1620 }
33df2ee1 1621
82e2d43f
HK		 1622 want_irq = client->irq > 0 && chip->alarm;
1623
9c19b893 1624 if (!pdata)
d8490fd5 1625 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
9c19b893 1626 else if (pdata->trickle_charger_setup)
d8490fd5 1627 trickle_charger_setup = pdata->trickle_charger_setup;
33b04b7b 1628
d8490fd5
HK		 1629 if (trickle_charger_setup && chip->trickle_charger_reg) {
1630 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
11e5890b
HK		 1631 dev_dbg(ds1307->dev,
1632 "writing trickle charger info 0x%x to 0x%x\n",
d8490fd5 1633 trickle_charger_setup, chip->trickle_charger_reg);
11e5890b 1634 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
d8490fd5 1635 trickle_charger_setup);
33b04b7b 1636 }
eb86c306 1637
8bc2a407
ML		 1638#ifdef CONFIG_OF
1639/*
1640 * For devices with no IRQ directly connected to the SoC, the RTC chip
1641 * can be forced as a wakeup source by stating that explicitly in
1642 * the device's .dts file using the "wakeup-source" boolean property.
1643 * If the "wakeup-source" property is set, don't request an IRQ.
1644 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1645 * if supported by the RTC.
1646 */
82e2d43f
HK		 1647 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1648 "wakeup-source"))
78aaa06d 1649 ds1307_can_wakeup_device = true;
8bc2a407
ML		 1650#endif
1651
045e0e85
DB		 1652 switch (ds1307->type) {
1653 case ds_1337:
1654 case ds_1339:
0759c886 1655 case ds_1341:
97f902b7 1656 case ds_3231:
be5f59f4 1657 /* get registers that the "rtc" read below won't read... */
11e5890b 1658 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
042fa8c7 1659 regs, 2);
11e5890b
HK		 1660 if (err) {
1661 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1662 goto exit;
1abb0dc9
DB		 1663 }
1664
be5f59f4 1665 /* oscillator off? turn it on, so clock can tick. */
042fa8c7
AB		 1666 if (regs[0] & DS1337_BIT_nEOSC)
1667 regs[0] &= ~DS1337_BIT_nEOSC;
cb49a5e9 1668
40ce972d 1669 /*
8bc2a407
ML		 1670 * Using IRQ or defined as wakeup-source?
1671 * Disable the square wave and both alarms.
97f902b7
WS		 1672 * For some variants, be sure alarms can trigger when we're
1673 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 1674 */
82e2d43f 1675 if (want_irq || ds1307_can_wakeup_device) {
042fa8c7
AB		 1676 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1677 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
cb49a5e9
RG		 1678 }
1679
11e5890b 1680 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
042fa8c7 1681 regs[0]);
be5f59f4
RG		 1682
1683 /* oscillator fault? clear flag, and warn */
042fa8c7 1684 if (regs[1] & DS1337_BIT_OSF) {
11e5890b 1685 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
042fa8c7 1686 regs[1] & ~DS1337_BIT_OSF);
11e5890b 1687 dev_warn(ds1307->dev, "SET TIME!\n");
1abb0dc9 1688 }
045e0e85 1689 break;
a2166858
MF		 1690
1691 case rx_8025:
11e5890b 1692 err = regmap_bulk_read(ds1307->regmap,
042fa8c7 1693 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
11e5890b
HK		 1694 if (err) {
1695 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1696 goto exit;
a2166858
MF		 1697 }
1698
1699 /* oscillator off? turn it on, so clock can tick. */
042fa8c7
AB		 1700 if (!(regs[1] & RX8025_BIT_XST)) {
1701 regs[1] |= RX8025_BIT_XST;
11e5890b
HK		 1702 regmap_write(ds1307->regmap,
1703 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1704 regs[1]);
11e5890b 1705 dev_warn(ds1307->dev,
a2166858
MF		 1706 "oscillator stop detected - SET TIME!\n");
1707 }
1708
042fa8c7
AB		 1709 if (regs[1] & RX8025_BIT_PON) {
1710 regs[1] &= ~RX8025_BIT_PON;
11e5890b
HK		 1711 regmap_write(ds1307->regmap,
1712 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1713 regs[1]);
11e5890b 1714 dev_warn(ds1307->dev, "power-on detected\n");
a2166858
MF		 1715 }
1716
042fa8c7
AB		 1717 if (regs[1] & RX8025_BIT_VDET) {
1718 regs[1] &= ~RX8025_BIT_VDET;
11e5890b
HK		 1719 regmap_write(ds1307->regmap,
1720 RX8025_REG_CTRL2 << 4 | 0x08,
042fa8c7 1721 regs[1]);
11e5890b 1722 dev_warn(ds1307->dev, "voltage drop detected\n");
a2166858
MF		 1723 }
1724
1725 /* make sure we are running in 24hour mode */
042fa8c7 1726 if (!(regs[0] & RX8025_BIT_2412)) {
a2166858
MF		 1727 u8 hour;
1728
1729 /* switch to 24 hour mode */
11e5890b
HK		 1730 regmap_write(ds1307->regmap,
1731 RX8025_REG_CTRL1 << 4 | 0x08,
042fa8c7 1732 regs[0] | RX8025_BIT_2412);
11e5890b
HK		 1733
1734 err = regmap_bulk_read(ds1307->regmap,
1735 RX8025_REG_CTRL1 << 4 | 0x08,
042fa8c7 1736 regs, 2);
11e5890b
HK		 1737 if (err) {
1738 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1739 goto exit;
a2166858
MF		 1740 }
1741
1742 /* correct hour */
042fa8c7 1743 hour = bcd2bin(regs[DS1307_REG_HOUR]);
a2166858
MF		 1744 if (hour == 12)
1745 hour = 0;
042fa8c7 1746 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
a2166858
MF		 1747 hour += 12;
1748
11e5890b
HK		 1749 regmap_write(ds1307->regmap,
1750 DS1307_REG_HOUR << 4 | 0x08, hour);
a2166858
MF		 1751 }
1752 break;
045e0e85
DB		 1753 default:
1754 break;
1755 }
1abb0dc9 1756
1abb0dc9 1757 /* read RTC registers */
042fa8c7
AB		 1758 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1759 sizeof(regs));
11e5890b
HK		 1760 if (err) {
1761 dev_dbg(ds1307->dev, "read error %d\n", err);
edca66d2 1762 goto exit;
1abb0dc9
DB		 1763 }
1764
b3a50169
AB		 1765 if (ds1307->type == mcp794xx &&
1766 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1767 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1768 regs[DS1307_REG_WDAY] |
1769 MCP794XX_BIT_VBATEN);
1abb0dc9 1770 }
045e0e85 1771
042fa8c7 1772 tmp = regs[DS1307_REG_HOUR];
c065f35c
DB		 1773 switch (ds1307->type) {
1774 case ds_1340:
8566f70c 1775 case m41t0:
c065f35c 1776 case m41t00:
7e580769 1777 case m41t11:
40ce972d
DA		 1778 /*
1779 * NOTE: ignores century bits; fix before deploying
c065f35c
DB		 1780 * systems that will run through year 2100.
1781 */
1782 break;
a2166858
MF		 1783 case rx_8025:
1784 break;
c065f35c
DB		 1785 default:
1786 if (!(tmp & DS1307_BIT_12HR))
1787 break;
1788
40ce972d
DA		 1789 /*
1790 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB		 1791 * take note...
1792 */
fe20ba70 1793 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB		 1794 if (tmp == 12)
1795 tmp = 0;
042fa8c7 1796 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
c065f35c 1797 tmp += 12;
e553170a 1798 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
11e5890b 1799 bin2bcd(tmp));
1abb0dc9
DB		 1800 }
1801
82e2d43f 1802 if (want_irq || ds1307_can_wakeup_device) {
11e5890b 1803 device_set_wakeup_capable(ds1307->dev, true);
3abb1ada
SG		 1804 set_bit(HAS_ALARM, &ds1307->flags);
1805 }
69b119a6
AB		 1806
1807 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
e69c0567 1808 if (IS_ERR(ds1307->rtc))
4071ea25 1809 return PTR_ERR(ds1307->rtc);
1abb0dc9 1810
82e2d43f 1811 if (ds1307_can_wakeup_device && !want_irq) {
11e5890b
HK		 1812 dev_info(ds1307->dev,
1813 "'wakeup-source' is set, request for an IRQ is disabled!\n");
8bc2a407
ML		 1814 /* We cannot support UIE mode if we do not have an IRQ line */
1815 ds1307->rtc->uie_unsupported = 1;
1816 }
1817
cb49a5e9 1818 if (want_irq) {
45947127
HK		 1819 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1820 chip->irq_handler ?: ds1307_irq,
c5983191 1821 IRQF_SHARED | IRQF_ONESHOT,
4b9e2a0c 1822 ds1307->name, ds1307);
cb49a5e9 1823 if (err) {
4071ea25 1824 client->irq = 0;
11e5890b 1825 device_set_wakeup_capable(ds1307->dev, false);
3abb1ada 1826 clear_bit(HAS_ALARM, &ds1307->flags);
11e5890b 1827 dev_err(ds1307->dev, "unable to request IRQ!\n");
e69c0567 1828 } else {
11e5890b 1829 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
e69c0567 1830 }
cb49a5e9
RG		 1831 }
1832
e9fb7682 1833 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
6a5f2a1f 1834 err = ds1307_add_frequency_test(ds1307);
e9fb7682
AB		 1835 if (err)
1836 return err;
1837
6a5f2a1f 1838 err = rtc_register_device(ds1307->rtc);
b41c23e1
GB		 1839 if (err)
1840 return err;
1841
9eab0a78 1842 if (chip->nvram_size) {
409baf17
AB		 1843 struct nvmem_config nvmem_cfg = {
1844 .name = "ds1307_nvram",
1845 .word_size = 1,
1846 .stride = 1,
1847 .size = chip->nvram_size,
1848 .reg_read = ds1307_nvram_read,
1849 .reg_write = ds1307_nvram_write,
1850 .priv = ds1307,
1851 };
abc925f7 1852
abc925f7 1853 ds1307->rtc->nvram_old_abi = true;
409baf17 1854 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
682d73f6
DB		 1855 }
1856
445c0207 1857 ds1307_hwmon_register(ds1307);
6c6ff145 1858 ds1307_clks_register(ds1307);
445c0207 1859
1abb0dc9
DB		 1860 return 0;
1861
edca66d2 1862exit:
1abb0dc9
DB		 1863 return err;
1864}
1865
1abb0dc9
DB		 1866static struct i2c_driver ds1307_driver = {
1867 .driver = {
c065f35c 1868 .name = "rtc-ds1307",
7ef6d2c2 1869 .of_match_table = of_match_ptr(ds1307_of_match),
9c19b893 1870 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1abb0dc9 1871 },
c065f35c 1872 .probe = ds1307_probe,
3760f736 1873 .id_table = ds1307_id,
1abb0dc9
DB		 1874};
1875
0abc9201 1876module_i2c_driver(ds1307_driver);
1abb0dc9
DB		 1877
1878MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1879MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)