Commit | Line | Data |
---|---|---|
7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
a737e835 JP |
31 | |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
33 | ||
7be2c7c9 DB |
34 | #include <linux/kernel.h> |
35 | #include <linux/module.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/platform_device.h> | |
5d2a5037 | 40 | #include <linux/log2.h> |
2fb08e6c | 41 | #include <linux/pm.h> |
3bcbaf6e SAS |
42 | #include <linux/of.h> |
43 | #include <linux/of_platform.h> | |
7be2c7c9 DB |
44 | |
45 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ | |
5ab788d7 | 46 | #include <linux/mc146818rtc.h> |
7be2c7c9 | 47 | |
7be2c7c9 DB |
48 | struct cmos_rtc { |
49 | struct rtc_device *rtc; | |
50 | struct device *dev; | |
51 | int irq; | |
52 | struct resource *iomem; | |
88b8d33b | 53 | time64_t alarm_expires; |
7be2c7c9 | 54 | |
87ac84f4 DB |
55 | void (*wake_on)(struct device *); |
56 | void (*wake_off)(struct device *); | |
57 | ||
58 | u8 enabled_wake; | |
7be2c7c9 DB |
59 | u8 suspend_ctrl; |
60 | ||
61 | /* newer hardware extends the original register set */ | |
62 | u8 day_alrm; | |
63 | u8 mon_alrm; | |
64 | u8 century; | |
68669d55 GM |
65 | |
66 | struct rtc_wkalrm saved_wkalrm; | |
7be2c7c9 DB |
67 | }; |
68 | ||
69 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
2fac6674 | 70 | #define is_valid_irq(n) ((n) > 0) |
7be2c7c9 DB |
71 | |
72 | static const char driver_name[] = "rtc_cmos"; | |
73 | ||
bcd9b89c DB |
74 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
75 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
76 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
77 | */ | |
78 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
79 | ||
80 | static inline int is_intr(u8 rtc_intr) | |
81 | { | |
82 | if (!(rtc_intr & RTC_IRQF)) | |
83 | return 0; | |
84 | return rtc_intr & RTC_IRQMASK; | |
85 | } | |
86 | ||
7be2c7c9 DB |
87 | /*----------------------------------------------------------------*/ |
88 | ||
35d3fdd5 DB |
89 | /* Much modern x86 hardware has HPETs (10+ MHz timers) which, because |
90 | * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly | |
91 | * used in a broken "legacy replacement" mode. The breakage includes | |
92 | * HPET #1 hijacking the IRQ for this RTC, and being unavailable for | |
93 | * other (better) use. | |
94 | * | |
95 | * When that broken mode is in use, platform glue provides a partial | |
96 | * emulation of hardware RTC IRQ facilities using HPET #1. We don't | |
97 | * want to use HPET for anything except those IRQs though... | |
98 | */ | |
99 | #ifdef CONFIG_HPET_EMULATE_RTC | |
100 | #include <asm/hpet.h> | |
101 | #else | |
102 | ||
103 | static inline int is_hpet_enabled(void) | |
104 | { | |
105 | return 0; | |
106 | } | |
107 | ||
108 | static inline int hpet_mask_rtc_irq_bit(unsigned long mask) | |
109 | { | |
110 | return 0; | |
111 | } | |
112 | ||
113 | static inline int hpet_set_rtc_irq_bit(unsigned long mask) | |
114 | { | |
115 | return 0; | |
116 | } | |
117 | ||
118 | static inline int | |
119 | hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | |
120 | { | |
121 | return 0; | |
122 | } | |
123 | ||
124 | static inline int hpet_set_periodic_freq(unsigned long freq) | |
125 | { | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static inline int hpet_rtc_dropped_irq(void) | |
130 | { | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static inline int hpet_rtc_timer_init(void) | |
135 | { | |
136 | return 0; | |
137 | } | |
138 | ||
139 | extern irq_handler_t hpet_rtc_interrupt; | |
140 | ||
141 | static inline int hpet_register_irq_handler(irq_handler_t handler) | |
142 | { | |
143 | return 0; | |
144 | } | |
145 | ||
146 | static inline int hpet_unregister_irq_handler(irq_handler_t handler) | |
147 | { | |
148 | return 0; | |
149 | } | |
150 | ||
151 | #endif | |
152 | ||
153 | /*----------------------------------------------------------------*/ | |
154 | ||
c8fc40cd DB |
155 | #ifdef RTC_PORT |
156 | ||
157 | /* Most newer x86 systems have two register banks, the first used | |
158 | * for RTC and NVRAM and the second only for NVRAM. Caller must | |
159 | * own rtc_lock ... and we won't worry about access during NMI. | |
160 | */ | |
161 | #define can_bank2 true | |
162 | ||
163 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
164 | { | |
165 | outb(addr, RTC_PORT(2)); | |
166 | return inb(RTC_PORT(3)); | |
167 | } | |
168 | ||
169 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
170 | { | |
171 | outb(addr, RTC_PORT(2)); | |
b43c1ea4 | 172 | outb(val, RTC_PORT(3)); |
c8fc40cd DB |
173 | } |
174 | ||
175 | #else | |
176 | ||
177 | #define can_bank2 false | |
178 | ||
179 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
180 | { | |
181 | return 0; | |
182 | } | |
183 | ||
184 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
185 | { | |
186 | } | |
187 | ||
188 | #endif | |
189 | ||
190 | /*----------------------------------------------------------------*/ | |
191 | ||
7be2c7c9 DB |
192 | static int cmos_read_time(struct device *dev, struct rtc_time *t) |
193 | { | |
194 | /* REVISIT: if the clock has a "century" register, use | |
5ab788d7 | 195 | * that instead of the heuristic in mc146818_get_time(). |
7be2c7c9 DB |
196 | * That'll make Y3K compatility (year > 2070) easy! |
197 | */ | |
5ab788d7 | 198 | mc146818_get_time(t); |
7be2c7c9 DB |
199 | return 0; |
200 | } | |
201 | ||
202 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
203 | { | |
204 | /* REVISIT: set the "century" register if available | |
205 | * | |
206 | * NOTE: this ignores the issue whereby updating the seconds | |
207 | * takes effect exactly 500ms after we write the register. | |
208 | * (Also queueing and other delays before we get this far.) | |
209 | */ | |
5ab788d7 | 210 | return mc146818_set_time(t); |
7be2c7c9 DB |
211 | } |
212 | ||
213 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
214 | { | |
215 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
216 | unsigned char rtc_control; | |
217 | ||
218 | if (!is_valid_irq(cmos->irq)) | |
219 | return -EIO; | |
220 | ||
221 | /* Basic alarms only support hour, minute, and seconds fields. | |
222 | * Some also support day and month, for alarms up to a year in | |
223 | * the future. | |
224 | */ | |
7be2c7c9 DB |
225 | |
226 | spin_lock_irq(&rtc_lock); | |
227 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
228 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
229 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
230 | ||
231 | if (cmos->day_alrm) { | |
615bb29c ML |
232 | /* ignore upper bits on readback per ACPI spec */ |
233 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
234 | if (!t->time.tm_mday) |
235 | t->time.tm_mday = -1; | |
236 | ||
237 | if (cmos->mon_alrm) { | |
238 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
239 | if (!t->time.tm_mon) | |
240 | t->time.tm_mon = -1; | |
241 | } | |
242 | } | |
243 | ||
244 | rtc_control = CMOS_READ(RTC_CONTROL); | |
245 | spin_unlock_irq(&rtc_lock); | |
246 | ||
3804a89b AP |
247 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { |
248 | if (((unsigned)t->time.tm_sec) < 0x60) | |
249 | t->time.tm_sec = bcd2bin(t->time.tm_sec); | |
7be2c7c9 | 250 | else |
3804a89b AP |
251 | t->time.tm_sec = -1; |
252 | if (((unsigned)t->time.tm_min) < 0x60) | |
253 | t->time.tm_min = bcd2bin(t->time.tm_min); | |
254 | else | |
255 | t->time.tm_min = -1; | |
256 | if (((unsigned)t->time.tm_hour) < 0x24) | |
257 | t->time.tm_hour = bcd2bin(t->time.tm_hour); | |
258 | else | |
259 | t->time.tm_hour = -1; | |
260 | ||
261 | if (cmos->day_alrm) { | |
262 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
263 | t->time.tm_mday = bcd2bin(t->time.tm_mday); | |
7be2c7c9 | 264 | else |
3804a89b AP |
265 | t->time.tm_mday = -1; |
266 | ||
267 | if (cmos->mon_alrm) { | |
268 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
269 | t->time.tm_mon = bcd2bin(t->time.tm_mon)-1; | |
270 | else | |
271 | t->time.tm_mon = -1; | |
272 | } | |
7be2c7c9 DB |
273 | } |
274 | } | |
7be2c7c9 DB |
275 | |
276 | t->enabled = !!(rtc_control & RTC_AIE); | |
277 | t->pending = 0; | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
7e2a31da DB |
282 | static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control) |
283 | { | |
284 | unsigned char rtc_intr; | |
285 | ||
286 | /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
287 | * allegedly some older rtcs need that to handle irqs properly | |
288 | */ | |
289 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
290 | ||
291 | if (is_hpet_enabled()) | |
292 | return; | |
293 | ||
294 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
295 | if (is_intr(rtc_intr)) | |
296 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
297 | } | |
298 | ||
299 | static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) | |
300 | { | |
301 | unsigned char rtc_control; | |
302 | ||
303 | /* flush any pending IRQ status, notably for update irqs, | |
304 | * before we enable new IRQs | |
305 | */ | |
306 | rtc_control = CMOS_READ(RTC_CONTROL); | |
307 | cmos_checkintr(cmos, rtc_control); | |
308 | ||
309 | rtc_control |= mask; | |
310 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
311 | hpet_set_rtc_irq_bit(mask); | |
312 | ||
313 | cmos_checkintr(cmos, rtc_control); | |
314 | } | |
315 | ||
316 | static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) | |
317 | { | |
318 | unsigned char rtc_control; | |
319 | ||
320 | rtc_control = CMOS_READ(RTC_CONTROL); | |
321 | rtc_control &= ~mask; | |
322 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
323 | hpet_mask_rtc_irq_bit(mask); | |
324 | ||
325 | cmos_checkintr(cmos, rtc_control); | |
326 | } | |
327 | ||
7be2c7c9 DB |
328 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
329 | { | |
330 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
5e8599d2 | 331 | unsigned char mon, mday, hrs, min, sec, rtc_control; |
7be2c7c9 DB |
332 | |
333 | if (!is_valid_irq(cmos->irq)) | |
334 | return -EIO; | |
335 | ||
2b653e06 | 336 | mon = t->time.tm_mon + 1; |
7be2c7c9 | 337 | mday = t->time.tm_mday; |
7be2c7c9 | 338 | hrs = t->time.tm_hour; |
7be2c7c9 | 339 | min = t->time.tm_min; |
7be2c7c9 | 340 | sec = t->time.tm_sec; |
3804a89b AP |
341 | |
342 | rtc_control = CMOS_READ(RTC_CONTROL); | |
343 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { | |
344 | /* Writing 0xff means "don't care" or "match all". */ | |
345 | mon = (mon <= 12) ? bin2bcd(mon) : 0xff; | |
346 | mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; | |
347 | hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff; | |
348 | min = (min < 60) ? bin2bcd(min) : 0xff; | |
349 | sec = (sec < 60) ? bin2bcd(sec) : 0xff; | |
350 | } | |
7be2c7c9 DB |
351 | |
352 | spin_lock_irq(&rtc_lock); | |
353 | ||
354 | /* next rtc irq must not be from previous alarm setting */ | |
7e2a31da | 355 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
356 | |
357 | /* update alarm */ | |
358 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
359 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
360 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
361 | ||
362 | /* the system may support an "enhanced" alarm */ | |
363 | if (cmos->day_alrm) { | |
364 | CMOS_WRITE(mday, cmos->day_alrm); | |
365 | if (cmos->mon_alrm) | |
366 | CMOS_WRITE(mon, cmos->mon_alrm); | |
367 | } | |
368 | ||
35d3fdd5 DB |
369 | /* FIXME the HPET alarm glue currently ignores day_alrm |
370 | * and mon_alrm ... | |
371 | */ | |
372 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); | |
373 | ||
7e2a31da DB |
374 | if (t->enabled) |
375 | cmos_irq_enable(cmos, RTC_AIE); | |
7be2c7c9 DB |
376 | |
377 | spin_unlock_irq(&rtc_lock); | |
378 | ||
88b8d33b AH |
379 | cmos->alarm_expires = rtc_tm_to_time64(&t->time); |
380 | ||
7be2c7c9 DB |
381 | return 0; |
382 | } | |
383 | ||
a8462ef6 | 384 | static int cmos_alarm_irq_enable(struct device *dev, unsigned int enabled) |
7be2c7c9 DB |
385 | { |
386 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
7be2c7c9 DB |
387 | unsigned long flags; |
388 | ||
a8462ef6 HRK |
389 | if (!is_valid_irq(cmos->irq)) |
390 | return -EINVAL; | |
7be2c7c9 DB |
391 | |
392 | spin_lock_irqsave(&rtc_lock, flags); | |
a8462ef6 HRK |
393 | |
394 | if (enabled) | |
7e2a31da | 395 | cmos_irq_enable(cmos, RTC_AIE); |
a8462ef6 HRK |
396 | else |
397 | cmos_irq_disable(cmos, RTC_AIE); | |
398 | ||
7be2c7c9 DB |
399 | spin_unlock_irqrestore(&rtc_lock, flags); |
400 | return 0; | |
401 | } | |
402 | ||
6fca3fc5 | 403 | #if IS_ENABLED(CONFIG_RTC_INTF_PROC) |
7be2c7c9 DB |
404 | |
405 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
406 | { | |
407 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
408 | unsigned char rtc_control, valid; | |
409 | ||
410 | spin_lock_irq(&rtc_lock); | |
411 | rtc_control = CMOS_READ(RTC_CONTROL); | |
412 | valid = CMOS_READ(RTC_VALID); | |
413 | spin_unlock_irq(&rtc_lock); | |
414 | ||
415 | /* NOTE: at least ICH6 reports battery status using a different | |
416 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
417 | */ | |
4395eb1f JP |
418 | seq_printf(seq, |
419 | "periodic_IRQ\t: %s\n" | |
420 | "update_IRQ\t: %s\n" | |
421 | "HPET_emulated\t: %s\n" | |
422 | // "square_wave\t: %s\n" | |
423 | "BCD\t\t: %s\n" | |
424 | "DST_enable\t: %s\n" | |
425 | "periodic_freq\t: %d\n" | |
426 | "batt_status\t: %s\n", | |
427 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
428 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
429 | is_hpet_enabled() ? "yes" : "no", | |
430 | // (rtc_control & RTC_SQWE) ? "yes" : "no", | |
431 | (rtc_control & RTC_DM_BINARY) ? "no" : "yes", | |
432 | (rtc_control & RTC_DST_EN) ? "yes" : "no", | |
433 | cmos->rtc->irq_freq, | |
434 | (valid & RTC_VRT) ? "okay" : "dead"); | |
435 | ||
436 | return 0; | |
7be2c7c9 DB |
437 | } |
438 | ||
439 | #else | |
440 | #define cmos_procfs NULL | |
441 | #endif | |
442 | ||
443 | static const struct rtc_class_ops cmos_rtc_ops = { | |
a8462ef6 HRK |
444 | .read_time = cmos_read_time, |
445 | .set_time = cmos_set_time, | |
446 | .read_alarm = cmos_read_alarm, | |
447 | .set_alarm = cmos_set_alarm, | |
448 | .proc = cmos_procfs, | |
a8462ef6 | 449 | .alarm_irq_enable = cmos_alarm_irq_enable, |
7be2c7c9 DB |
450 | }; |
451 | ||
452 | /*----------------------------------------------------------------*/ | |
453 | ||
e07e232c DB |
454 | /* |
455 | * All these chips have at least 64 bytes of address space, shared by | |
456 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
457 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
458 | */ | |
459 | ||
460 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
461 | ||
462 | static ssize_t | |
2c3c8bea CW |
463 | cmos_nvram_read(struct file *filp, struct kobject *kobj, |
464 | struct bin_attribute *attr, | |
e07e232c DB |
465 | char *buf, loff_t off, size_t count) |
466 | { | |
467 | int retval; | |
468 | ||
c8fc40cd | 469 | off += NVRAM_OFFSET; |
e07e232c | 470 | spin_lock_irq(&rtc_lock); |
c8fc40cd DB |
471 | for (retval = 0; count; count--, off++, retval++) { |
472 | if (off < 128) | |
473 | *buf++ = CMOS_READ(off); | |
474 | else if (can_bank2) | |
475 | *buf++ = cmos_read_bank2(off); | |
476 | else | |
477 | break; | |
478 | } | |
e07e232c DB |
479 | spin_unlock_irq(&rtc_lock); |
480 | ||
481 | return retval; | |
482 | } | |
483 | ||
484 | static ssize_t | |
2c3c8bea CW |
485 | cmos_nvram_write(struct file *filp, struct kobject *kobj, |
486 | struct bin_attribute *attr, | |
e07e232c DB |
487 | char *buf, loff_t off, size_t count) |
488 | { | |
489 | struct cmos_rtc *cmos; | |
490 | int retval; | |
491 | ||
492 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
e07e232c DB |
493 | |
494 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
495 | * checksum on part of the NVRAM data. That's currently ignored | |
496 | * here. If userspace is smart enough to know what fields of | |
497 | * NVRAM to update, updating checksums is also part of its job. | |
498 | */ | |
c8fc40cd | 499 | off += NVRAM_OFFSET; |
e07e232c | 500 | spin_lock_irq(&rtc_lock); |
c8fc40cd | 501 | for (retval = 0; count; count--, off++, retval++) { |
e07e232c DB |
502 | /* don't trash RTC registers */ |
503 | if (off == cmos->day_alrm | |
504 | || off == cmos->mon_alrm | |
505 | || off == cmos->century) | |
506 | buf++; | |
c8fc40cd | 507 | else if (off < 128) |
e07e232c | 508 | CMOS_WRITE(*buf++, off); |
c8fc40cd DB |
509 | else if (can_bank2) |
510 | cmos_write_bank2(*buf++, off); | |
511 | else | |
512 | break; | |
e07e232c DB |
513 | } |
514 | spin_unlock_irq(&rtc_lock); | |
515 | ||
516 | return retval; | |
517 | } | |
518 | ||
519 | static struct bin_attribute nvram = { | |
520 | .attr = { | |
521 | .name = "nvram", | |
522 | .mode = S_IRUGO | S_IWUSR, | |
e07e232c DB |
523 | }, |
524 | ||
525 | .read = cmos_nvram_read, | |
526 | .write = cmos_nvram_write, | |
527 | /* size gets set up later */ | |
528 | }; | |
529 | ||
530 | /*----------------------------------------------------------------*/ | |
531 | ||
7be2c7c9 DB |
532 | static struct cmos_rtc cmos_rtc; |
533 | ||
534 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
535 | { | |
536 | u8 irqstat; | |
8a0bdfd7 | 537 | u8 rtc_control; |
7be2c7c9 DB |
538 | |
539 | spin_lock(&rtc_lock); | |
35d3fdd5 DB |
540 | |
541 | /* When the HPET interrupt handler calls us, the interrupt | |
542 | * status is passed as arg1 instead of the irq number. But | |
543 | * always clear irq status, even when HPET is in the way. | |
544 | * | |
545 | * Note that HPET and RTC are almost certainly out of phase, | |
546 | * giving different IRQ status ... | |
9d8af78b | 547 | */ |
35d3fdd5 DB |
548 | irqstat = CMOS_READ(RTC_INTR_FLAGS); |
549 | rtc_control = CMOS_READ(RTC_CONTROL); | |
9d8af78b BW |
550 | if (is_hpet_enabled()) |
551 | irqstat = (unsigned long)irq & 0xF0; | |
998a0605 DB |
552 | |
553 | /* If we were suspended, RTC_CONTROL may not be accurate since the | |
554 | * bios may have cleared it. | |
555 | */ | |
556 | if (!cmos_rtc.suspend_ctrl) | |
557 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
558 | else | |
559 | irqstat &= (cmos_rtc.suspend_ctrl & RTC_IRQMASK) | RTC_IRQF; | |
8a0bdfd7 DB |
560 | |
561 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
562 | * Similar code may be needed in system wakeup paths, in case the | |
563 | * alarm woke the system. | |
564 | */ | |
565 | if (irqstat & RTC_AIE) { | |
998a0605 | 566 | cmos_rtc.suspend_ctrl &= ~RTC_AIE; |
8a0bdfd7 DB |
567 | rtc_control &= ~RTC_AIE; |
568 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
35d3fdd5 | 569 | hpet_mask_rtc_irq_bit(RTC_AIE); |
8a0bdfd7 DB |
570 | CMOS_READ(RTC_INTR_FLAGS); |
571 | } | |
7be2c7c9 DB |
572 | spin_unlock(&rtc_lock); |
573 | ||
bcd9b89c | 574 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
575 | rtc_update_irq(p, 1, irqstat); |
576 | return IRQ_HANDLED; | |
577 | } else | |
578 | return IRQ_NONE; | |
579 | } | |
580 | ||
41ac8df9 | 581 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
582 | #define INITSECTION |
583 | ||
584 | #else | |
7be2c7c9 DB |
585 | #define INITSECTION __init |
586 | #endif | |
587 | ||
588 | static int INITSECTION | |
589 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
590 | { | |
97a92e77 | 591 | struct cmos_rtc_board_info *info = dev_get_platdata(dev); |
7be2c7c9 DB |
592 | int retval = 0; |
593 | unsigned char rtc_control; | |
e07e232c | 594 | unsigned address_space; |
31632dbd | 595 | u32 flags = 0; |
7be2c7c9 DB |
596 | |
597 | /* there can be only one ... */ | |
598 | if (cmos_rtc.dev) | |
599 | return -EBUSY; | |
600 | ||
601 | if (!ports) | |
602 | return -ENODEV; | |
603 | ||
05440dfc DB |
604 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
605 | * | |
606 | * REVISIT non-x86 systems may instead use memory space resources | |
607 | * (needing ioremap etc), not i/o space resources like this ... | |
608 | */ | |
31632dbd MR |
609 | if (RTC_IOMAPPED) |
610 | ports = request_region(ports->start, resource_size(ports), | |
611 | driver_name); | |
612 | else | |
613 | ports = request_mem_region(ports->start, resource_size(ports), | |
614 | driver_name); | |
05440dfc DB |
615 | if (!ports) { |
616 | dev_dbg(dev, "i/o registers already in use\n"); | |
617 | return -EBUSY; | |
618 | } | |
619 | ||
7be2c7c9 DB |
620 | cmos_rtc.irq = rtc_irq; |
621 | cmos_rtc.iomem = ports; | |
622 | ||
e07e232c DB |
623 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
624 | * driver did, but don't reject unknown configs. Old hardware | |
c8fc40cd DB |
625 | * won't address 128 bytes. Newer chips have multiple banks, |
626 | * though they may not be listed in one I/O resource. | |
e07e232c DB |
627 | */ |
628 | #if defined(CONFIG_ATARI) | |
629 | address_space = 64; | |
95abd0df | 630 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ |
8cb7c71b | 631 | || defined(__sparc__) || defined(__mips__) \ |
5ee98ab3 | 632 | || defined(__powerpc__) || defined(CONFIG_MN10300) |
e07e232c DB |
633 | address_space = 128; |
634 | #else | |
635 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
636 | address_space = 128; | |
637 | #endif | |
c8fc40cd DB |
638 | if (can_bank2 && ports->end > (ports->start + 1)) |
639 | address_space = 256; | |
e07e232c | 640 | |
87ac84f4 DB |
641 | /* For ACPI systems extension info comes from the FADT. On others, |
642 | * board specific setup provides it as appropriate. Systems where | |
643 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
644 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
645 | * |
646 | * Note that ACPI doesn't preclude putting these registers into | |
647 | * "extended" areas of the chip, including some that we won't yet | |
648 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
649 | */ |
650 | if (info) { | |
31632dbd MR |
651 | if (info->flags) |
652 | flags = info->flags; | |
653 | if (info->address_space) | |
654 | address_space = info->address_space; | |
655 | ||
e07e232c DB |
656 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
657 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
658 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
659 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
660 | if (info->rtc_century && info->rtc_century < 128) | |
661 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
662 | |
663 | if (info->wake_on && info->wake_off) { | |
664 | cmos_rtc.wake_on = info->wake_on; | |
665 | cmos_rtc.wake_off = info->wake_off; | |
666 | } | |
7be2c7c9 DB |
667 | } |
668 | ||
6ba8bcd4 DC |
669 | cmos_rtc.dev = dev; |
670 | dev_set_drvdata(dev, &cmos_rtc); | |
671 | ||
7be2c7c9 DB |
672 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, |
673 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
674 | if (IS_ERR(cmos_rtc.rtc)) { |
675 | retval = PTR_ERR(cmos_rtc.rtc); | |
676 | goto cleanup0; | |
677 | } | |
7be2c7c9 | 678 | |
d4afc76c | 679 | rename_region(ports, dev_name(&cmos_rtc.rtc->dev)); |
7be2c7c9 DB |
680 | |
681 | spin_lock_irq(&rtc_lock); | |
682 | ||
31632dbd MR |
683 | if (!(flags & CMOS_RTC_FLAGS_NOFREQ)) { |
684 | /* force periodic irq to CMOS reset default of 1024Hz; | |
685 | * | |
686 | * REVISIT it's been reported that at least one x86_64 ALI | |
687 | * mobo doesn't use 32KHz here ... for portability we might | |
688 | * need to do something about other clock frequencies. | |
689 | */ | |
690 | cmos_rtc.rtc->irq_freq = 1024; | |
691 | hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq); | |
692 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
693 | } | |
7be2c7c9 | 694 | |
7e2a31da | 695 | /* disable irqs */ |
31632dbd MR |
696 | if (is_valid_irq(rtc_irq)) |
697 | cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE); | |
35d3fdd5 | 698 | |
7e2a31da | 699 | rtc_control = CMOS_READ(RTC_CONTROL); |
7be2c7c9 DB |
700 | |
701 | spin_unlock_irq(&rtc_lock); | |
702 | ||
3804a89b | 703 | /* FIXME: |
7be2c7c9 DB |
704 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. |
705 | */ | |
5e8599d2 | 706 | if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { |
3804a89b | 707 | dev_warn(dev, "only 24-hr supported\n"); |
7be2c7c9 DB |
708 | retval = -ENXIO; |
709 | goto cleanup1; | |
710 | } | |
711 | ||
970fc7f4 PA |
712 | hpet_rtc_timer_init(); |
713 | ||
9d8af78b BW |
714 | if (is_valid_irq(rtc_irq)) { |
715 | irq_handler_t rtc_cmos_int_handler; | |
716 | ||
717 | if (is_hpet_enabled()) { | |
9d8af78b | 718 | rtc_cmos_int_handler = hpet_rtc_interrupt; |
24b34472 AM |
719 | retval = hpet_register_irq_handler(cmos_interrupt); |
720 | if (retval) { | |
970fc7f4 | 721 | hpet_mask_rtc_irq_bit(RTC_IRQMASK); |
ee443357 | 722 | dev_warn(dev, "hpet_register_irq_handler " |
9d8af78b BW |
723 | " failed in rtc_init()."); |
724 | goto cleanup1; | |
725 | } | |
726 | } else | |
727 | rtc_cmos_int_handler = cmos_interrupt; | |
728 | ||
729 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
079062b2 | 730 | IRQF_SHARED, dev_name(&cmos_rtc.rtc->dev), |
ab6a2d70 | 731 | cmos_rtc.rtc); |
9d8af78b BW |
732 | if (retval < 0) { |
733 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
734 | goto cleanup1; | |
735 | } | |
7be2c7c9 DB |
736 | } |
737 | ||
e07e232c DB |
738 | /* export at least the first block of NVRAM */ |
739 | nvram.size = address_space - NVRAM_OFFSET; | |
740 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
741 | if (retval < 0) { | |
742 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
743 | goto cleanup2; | |
744 | } | |
7be2c7c9 | 745 | |
ee443357 | 746 | dev_info(dev, "%s%s, %zd bytes nvram%s\n", |
6d029b64 KH |
747 | !is_valid_irq(rtc_irq) ? "no alarms" : |
748 | cmos_rtc.mon_alrm ? "alarms up to one year" : | |
749 | cmos_rtc.day_alrm ? "alarms up to one month" : | |
750 | "alarms up to one day", | |
751 | cmos_rtc.century ? ", y3k" : "", | |
752 | nvram.size, | |
753 | is_hpet_enabled() ? ", hpet irqs" : ""); | |
7be2c7c9 DB |
754 | |
755 | return 0; | |
756 | ||
e07e232c DB |
757 | cleanup2: |
758 | if (is_valid_irq(rtc_irq)) | |
759 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 760 | cleanup1: |
05440dfc | 761 | cmos_rtc.dev = NULL; |
7be2c7c9 | 762 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc | 763 | cleanup0: |
31632dbd MR |
764 | if (RTC_IOMAPPED) |
765 | release_region(ports->start, resource_size(ports)); | |
766 | else | |
767 | release_mem_region(ports->start, resource_size(ports)); | |
7be2c7c9 DB |
768 | return retval; |
769 | } | |
770 | ||
31632dbd | 771 | static void cmos_do_shutdown(int rtc_irq) |
7be2c7c9 | 772 | { |
7be2c7c9 | 773 | spin_lock_irq(&rtc_lock); |
31632dbd MR |
774 | if (is_valid_irq(rtc_irq)) |
775 | cmos_irq_disable(&cmos_rtc, RTC_IRQMASK); | |
7be2c7c9 DB |
776 | spin_unlock_irq(&rtc_lock); |
777 | } | |
778 | ||
779 | static void __exit cmos_do_remove(struct device *dev) | |
780 | { | |
781 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 782 | struct resource *ports; |
7be2c7c9 | 783 | |
31632dbd | 784 | cmos_do_shutdown(cmos->irq); |
7be2c7c9 | 785 | |
e07e232c DB |
786 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
787 | ||
9d8af78b | 788 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 789 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
790 | hpet_unregister_irq_handler(cmos_interrupt); |
791 | } | |
7be2c7c9 | 792 | |
05440dfc DB |
793 | rtc_device_unregister(cmos->rtc); |
794 | cmos->rtc = NULL; | |
7be2c7c9 | 795 | |
05440dfc | 796 | ports = cmos->iomem; |
31632dbd MR |
797 | if (RTC_IOMAPPED) |
798 | release_region(ports->start, resource_size(ports)); | |
799 | else | |
800 | release_mem_region(ports->start, resource_size(ports)); | |
05440dfc DB |
801 | cmos->iomem = NULL; |
802 | ||
803 | cmos->dev = NULL; | |
7be2c7c9 DB |
804 | } |
805 | ||
88b8d33b AH |
806 | static int cmos_aie_poweroff(struct device *dev) |
807 | { | |
808 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
809 | struct rtc_time now; | |
810 | time64_t t_now; | |
811 | int retval = 0; | |
812 | unsigned char rtc_control; | |
813 | ||
814 | if (!cmos->alarm_expires) | |
815 | return -EINVAL; | |
816 | ||
817 | spin_lock_irq(&rtc_lock); | |
818 | rtc_control = CMOS_READ(RTC_CONTROL); | |
819 | spin_unlock_irq(&rtc_lock); | |
820 | ||
821 | /* We only care about the situation where AIE is disabled. */ | |
822 | if (rtc_control & RTC_AIE) | |
823 | return -EBUSY; | |
824 | ||
825 | cmos_read_time(dev, &now); | |
826 | t_now = rtc_tm_to_time64(&now); | |
827 | ||
828 | /* | |
829 | * When enabling "RTC wake-up" in BIOS setup, the machine reboots | |
830 | * automatically right after shutdown on some buggy boxes. | |
831 | * This automatic rebooting issue won't happen when the alarm | |
832 | * time is larger than now+1 seconds. | |
833 | * | |
834 | * If the alarm time is equal to now+1 seconds, the issue can be | |
835 | * prevented by cancelling the alarm. | |
836 | */ | |
837 | if (cmos->alarm_expires == t_now + 1) { | |
838 | struct rtc_wkalrm alarm; | |
839 | ||
840 | /* Cancel the AIE timer by configuring the past time. */ | |
841 | rtc_time64_to_tm(t_now - 1, &alarm.time); | |
842 | alarm.enabled = 0; | |
843 | retval = cmos_set_alarm(dev, &alarm); | |
844 | } else if (cmos->alarm_expires > t_now + 1) { | |
845 | retval = -EBUSY; | |
846 | } | |
847 | ||
848 | return retval; | |
849 | } | |
850 | ||
2fb08e6c | 851 | static int cmos_suspend(struct device *dev) |
7be2c7c9 DB |
852 | { |
853 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
bcd9b89c | 854 | unsigned char tmp; |
7be2c7c9 DB |
855 | |
856 | /* only the alarm might be a wakeup event source */ | |
857 | spin_lock_irq(&rtc_lock); | |
858 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
859 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
35d3fdd5 | 860 | unsigned char mask; |
bcd9b89c | 861 | |
74c4633d | 862 | if (device_may_wakeup(dev)) |
35d3fdd5 | 863 | mask = RTC_IRQMASK & ~RTC_AIE; |
7be2c7c9 | 864 | else |
35d3fdd5 DB |
865 | mask = RTC_IRQMASK; |
866 | tmp &= ~mask; | |
7be2c7c9 | 867 | CMOS_WRITE(tmp, RTC_CONTROL); |
e005715e | 868 | hpet_mask_rtc_irq_bit(mask); |
35d3fdd5 | 869 | |
7e2a31da | 870 | cmos_checkintr(cmos, tmp); |
bcd9b89c | 871 | } |
7be2c7c9 DB |
872 | spin_unlock_irq(&rtc_lock); |
873 | ||
87ac84f4 DB |
874 | if (tmp & RTC_AIE) { |
875 | cmos->enabled_wake = 1; | |
876 | if (cmos->wake_on) | |
877 | cmos->wake_on(dev); | |
878 | else | |
879 | enable_irq_wake(cmos->irq); | |
880 | } | |
7be2c7c9 | 881 | |
68669d55 GM |
882 | cmos_read_alarm(dev, &cmos->saved_wkalrm); |
883 | ||
ee443357 | 884 | dev_dbg(dev, "suspend%s, ctrl %02x\n", |
7be2c7c9 DB |
885 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
886 | tmp); | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
74c4633d RW |
891 | /* We want RTC alarms to wake us from e.g. ACPI G2/S5 "soft off", even |
892 | * after a detour through G3 "mechanical off", although the ACPI spec | |
893 | * says wakeup should only work from G1/S4 "hibernate". To most users, | |
894 | * distinctions between S4 and S5 are pointless. So when the hardware | |
895 | * allows, don't draw that distinction. | |
896 | */ | |
897 | static inline int cmos_poweroff(struct device *dev) | |
898 | { | |
00f7f90c AB |
899 | if (!IS_ENABLED(CONFIG_PM)) |
900 | return -ENOSYS; | |
901 | ||
2fb08e6c | 902 | return cmos_suspend(dev); |
74c4633d RW |
903 | } |
904 | ||
68669d55 GM |
905 | static void cmos_check_wkalrm(struct device *dev) |
906 | { | |
907 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
908 | struct rtc_wkalrm current_alarm; | |
909 | time64_t t_current_expires; | |
910 | time64_t t_saved_expires; | |
911 | ||
912 | cmos_read_alarm(dev, ¤t_alarm); | |
913 | t_current_expires = rtc_tm_to_time64(¤t_alarm.time); | |
914 | t_saved_expires = rtc_tm_to_time64(&cmos->saved_wkalrm.time); | |
915 | if (t_current_expires != t_saved_expires || | |
916 | cmos->saved_wkalrm.enabled != current_alarm.enabled) { | |
917 | cmos_set_alarm(dev, &cmos->saved_wkalrm); | |
918 | } | |
919 | } | |
920 | ||
983bf125 GM |
921 | static void cmos_check_acpi_rtc_status(struct device *dev, |
922 | unsigned char *rtc_control); | |
923 | ||
00f7f90c | 924 | static int __maybe_unused cmos_resume(struct device *dev) |
7be2c7c9 DB |
925 | { |
926 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
998a0605 DB |
927 | unsigned char tmp; |
928 | ||
929 | if (cmos->enabled_wake) { | |
930 | if (cmos->wake_off) | |
931 | cmos->wake_off(dev); | |
932 | else | |
933 | disable_irq_wake(cmos->irq); | |
934 | cmos->enabled_wake = 0; | |
935 | } | |
7be2c7c9 | 936 | |
68669d55 GM |
937 | /* The BIOS might have changed the alarm, restore it */ |
938 | cmos_check_wkalrm(dev); | |
939 | ||
998a0605 DB |
940 | spin_lock_irq(&rtc_lock); |
941 | tmp = cmos->suspend_ctrl; | |
942 | cmos->suspend_ctrl = 0; | |
7be2c7c9 | 943 | /* re-enable any irqs previously active */ |
35d3fdd5 DB |
944 | if (tmp & RTC_IRQMASK) { |
945 | unsigned char mask; | |
7be2c7c9 | 946 | |
ebf8d6c8 DB |
947 | if (device_may_wakeup(dev)) |
948 | hpet_rtc_timer_init(); | |
949 | ||
35d3fdd5 DB |
950 | do { |
951 | CMOS_WRITE(tmp, RTC_CONTROL); | |
952 | hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK); | |
953 | ||
954 | mask = CMOS_READ(RTC_INTR_FLAGS); | |
955 | mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; | |
7e2a31da | 956 | if (!is_hpet_enabled() || !is_intr(mask)) |
35d3fdd5 DB |
957 | break; |
958 | ||
959 | /* force one-shot behavior if HPET blocked | |
960 | * the wake alarm's irq | |
961 | */ | |
962 | rtc_update_irq(cmos->rtc, 1, mask); | |
963 | tmp &= ~RTC_AIE; | |
964 | hpet_mask_rtc_irq_bit(RTC_AIE); | |
965 | } while (mask & RTC_AIE); | |
983bf125 GM |
966 | |
967 | if (tmp & RTC_AIE) | |
968 | cmos_check_acpi_rtc_status(dev, &tmp); | |
7be2c7c9 | 969 | } |
998a0605 | 970 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 | 971 | |
ee443357 | 972 | dev_dbg(dev, "resume, ctrl %02x\n", tmp); |
7be2c7c9 DB |
973 | |
974 | return 0; | |
975 | } | |
976 | ||
b5ada460 MW |
977 | static SIMPLE_DEV_PM_OPS(cmos_pm_ops, cmos_suspend, cmos_resume); |
978 | ||
7be2c7c9 DB |
979 | /*----------------------------------------------------------------*/ |
980 | ||
e07e232c DB |
981 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
982 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
983 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
984 | * | |
985 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
986 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
987 | */ |
988 | ||
a474aaed BH |
989 | #ifdef CONFIG_ACPI |
990 | ||
991 | #include <linux/acpi.h> | |
992 | ||
a474aaed BH |
993 | static u32 rtc_handler(void *context) |
994 | { | |
b2201e54 | 995 | struct device *dev = context; |
983bf125 GM |
996 | struct cmos_rtc *cmos = dev_get_drvdata(dev); |
997 | unsigned char rtc_control = 0; | |
998 | unsigned char rtc_intr; | |
999 | ||
1000 | spin_lock_irq(&rtc_lock); | |
1001 | if (cmos_rtc.suspend_ctrl) | |
1002 | rtc_control = CMOS_READ(RTC_CONTROL); | |
1003 | if (rtc_control & RTC_AIE) { | |
1004 | cmos_rtc.suspend_ctrl &= ~RTC_AIE; | |
1005 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
1006 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
1007 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
1008 | } | |
1009 | spin_unlock_irq(&rtc_lock); | |
b2201e54 DD |
1010 | |
1011 | pm_wakeup_event(dev, 0); | |
a474aaed BH |
1012 | acpi_clear_event(ACPI_EVENT_RTC); |
1013 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
1014 | return ACPI_INTERRUPT_HANDLED; | |
1015 | } | |
1016 | ||
b2201e54 | 1017 | static inline void rtc_wake_setup(struct device *dev) |
a474aaed | 1018 | { |
b2201e54 | 1019 | acpi_install_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler, dev); |
a474aaed BH |
1020 | /* |
1021 | * After the RTC handler is installed, the Fixed_RTC event should | |
1022 | * be disabled. Only when the RTC alarm is set will it be enabled. | |
1023 | */ | |
1024 | acpi_clear_event(ACPI_EVENT_RTC); | |
1025 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
1026 | } | |
1027 | ||
1028 | static void rtc_wake_on(struct device *dev) | |
1029 | { | |
1030 | acpi_clear_event(ACPI_EVENT_RTC); | |
1031 | acpi_enable_event(ACPI_EVENT_RTC, 0); | |
1032 | } | |
1033 | ||
1034 | static void rtc_wake_off(struct device *dev) | |
1035 | { | |
1036 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
1037 | } | |
a474aaed BH |
1038 | |
1039 | /* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find | |
1040 | * its device node and pass extra config data. This helps its driver use | |
1041 | * capabilities that the now-obsolete mc146818 didn't have, and informs it | |
1042 | * that this board's RTC is wakeup-capable (per ACPI spec). | |
1043 | */ | |
1044 | static struct cmos_rtc_board_info acpi_rtc_info; | |
1045 | ||
5a167f45 | 1046 | static void cmos_wake_setup(struct device *dev) |
a474aaed BH |
1047 | { |
1048 | if (acpi_disabled) | |
1049 | return; | |
1050 | ||
b2201e54 | 1051 | rtc_wake_setup(dev); |
a474aaed BH |
1052 | acpi_rtc_info.wake_on = rtc_wake_on; |
1053 | acpi_rtc_info.wake_off = rtc_wake_off; | |
1054 | ||
1055 | /* workaround bug in some ACPI tables */ | |
1056 | if (acpi_gbl_FADT.month_alarm && !acpi_gbl_FADT.day_alarm) { | |
1057 | dev_dbg(dev, "bogus FADT month_alarm (%d)\n", | |
1058 | acpi_gbl_FADT.month_alarm); | |
1059 | acpi_gbl_FADT.month_alarm = 0; | |
1060 | } | |
1061 | ||
1062 | acpi_rtc_info.rtc_day_alarm = acpi_gbl_FADT.day_alarm; | |
1063 | acpi_rtc_info.rtc_mon_alarm = acpi_gbl_FADT.month_alarm; | |
1064 | acpi_rtc_info.rtc_century = acpi_gbl_FADT.century; | |
1065 | ||
1066 | /* NOTE: S4_RTC_WAKE is NOT currently useful to Linux */ | |
1067 | if (acpi_gbl_FADT.flags & ACPI_FADT_S4_RTC_WAKE) | |
1068 | dev_info(dev, "RTC can wake from S4\n"); | |
1069 | ||
1070 | dev->platform_data = &acpi_rtc_info; | |
1071 | ||
1072 | /* RTC always wakes from S1/S2/S3, and often S4/STD */ | |
1073 | device_init_wakeup(dev, 1); | |
1074 | } | |
1075 | ||
983bf125 GM |
1076 | static void cmos_check_acpi_rtc_status(struct device *dev, |
1077 | unsigned char *rtc_control) | |
1078 | { | |
1079 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
1080 | acpi_event_status rtc_status; | |
1081 | acpi_status status; | |
1082 | ||
1083 | if (acpi_gbl_FADT.flags & ACPI_FADT_FIXED_RTC) | |
1084 | return; | |
1085 | ||
1086 | status = acpi_get_event_status(ACPI_EVENT_RTC, &rtc_status); | |
1087 | if (ACPI_FAILURE(status)) { | |
1088 | dev_err(dev, "Could not get RTC status\n"); | |
1089 | } else if (rtc_status & ACPI_EVENT_FLAG_SET) { | |
1090 | unsigned char mask; | |
1091 | *rtc_control &= ~RTC_AIE; | |
1092 | CMOS_WRITE(*rtc_control, RTC_CONTROL); | |
1093 | mask = CMOS_READ(RTC_INTR_FLAGS); | |
1094 | rtc_update_irq(cmos->rtc, 1, mask); | |
1095 | } | |
1096 | } | |
1097 | ||
a474aaed BH |
1098 | #else |
1099 | ||
5a167f45 | 1100 | static void cmos_wake_setup(struct device *dev) |
a474aaed BH |
1101 | { |
1102 | } | |
1103 | ||
983bf125 GM |
1104 | static void cmos_check_acpi_rtc_status(struct device *dev, |
1105 | unsigned char *rtc_control) | |
1106 | { | |
1107 | } | |
1108 | ||
a474aaed BH |
1109 | #endif |
1110 | ||
41ac8df9 | 1111 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
1112 | |
1113 | #include <linux/pnp.h> | |
1114 | ||
5a167f45 | 1115 | static int cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) |
7be2c7c9 | 1116 | { |
a474aaed BH |
1117 | cmos_wake_setup(&pnp->dev); |
1118 | ||
5e8599d2 | 1119 | if (pnp_port_start(pnp, 0) == 0x70 && !pnp_irq_valid(pnp, 0)) |
6cd8fa87 MG |
1120 | /* Some machines contain a PNP entry for the RTC, but |
1121 | * don't define the IRQ. It should always be safe to | |
1122 | * hardcode it in these cases | |
1123 | */ | |
8766ad0c BH |
1124 | return cmos_do_probe(&pnp->dev, |
1125 | pnp_get_resource(pnp, IORESOURCE_IO, 0), 8); | |
6cd8fa87 MG |
1126 | else |
1127 | return cmos_do_probe(&pnp->dev, | |
8766ad0c BH |
1128 | pnp_get_resource(pnp, IORESOURCE_IO, 0), |
1129 | pnp_irq(pnp, 0)); | |
7be2c7c9 DB |
1130 | } |
1131 | ||
1132 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
1133 | { | |
1134 | cmos_do_remove(&pnp->dev); | |
1135 | } | |
1136 | ||
004731b2 | 1137 | static void cmos_pnp_shutdown(struct pnp_dev *pnp) |
74c4633d | 1138 | { |
31632dbd MR |
1139 | struct device *dev = &pnp->dev; |
1140 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
1141 | ||
88b8d33b AH |
1142 | if (system_state == SYSTEM_POWER_OFF) { |
1143 | int retval = cmos_poweroff(dev); | |
1144 | ||
1145 | if (cmos_aie_poweroff(dev) < 0 && !retval) | |
1146 | return; | |
1147 | } | |
74c4633d | 1148 | |
31632dbd | 1149 | cmos_do_shutdown(cmos->irq); |
74c4633d | 1150 | } |
7be2c7c9 DB |
1151 | |
1152 | static const struct pnp_device_id rtc_ids[] = { | |
1153 | { .id = "PNP0b00", }, | |
1154 | { .id = "PNP0b01", }, | |
1155 | { .id = "PNP0b02", }, | |
1156 | { }, | |
1157 | }; | |
1158 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
1159 | ||
1160 | static struct pnp_driver cmos_pnp_driver = { | |
1161 | .name = (char *) driver_name, | |
1162 | .id_table = rtc_ids, | |
1163 | .probe = cmos_pnp_probe, | |
1164 | .remove = __exit_p(cmos_pnp_remove), | |
004731b2 | 1165 | .shutdown = cmos_pnp_shutdown, |
7be2c7c9 DB |
1166 | |
1167 | /* flag ensures resume() gets called, and stops syslog spam */ | |
1168 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
a8a3808b SK |
1169 | .driver = { |
1170 | .pm = &cmos_pm_ops, | |
1171 | }, | |
7be2c7c9 DB |
1172 | }; |
1173 | ||
1da2e3d6 | 1174 | #endif /* CONFIG_PNP */ |
7be2c7c9 | 1175 | |
3bcbaf6e SAS |
1176 | #ifdef CONFIG_OF |
1177 | static const struct of_device_id of_cmos_match[] = { | |
1178 | { | |
1179 | .compatible = "motorola,mc146818", | |
1180 | }, | |
1181 | { }, | |
1182 | }; | |
1183 | MODULE_DEVICE_TABLE(of, of_cmos_match); | |
1184 | ||
1185 | static __init void cmos_of_init(struct platform_device *pdev) | |
1186 | { | |
1187 | struct device_node *node = pdev->dev.of_node; | |
1188 | struct rtc_time time; | |
1189 | int ret; | |
1190 | const __be32 *val; | |
1191 | ||
1192 | if (!node) | |
1193 | return; | |
1194 | ||
1195 | val = of_get_property(node, "ctrl-reg", NULL); | |
1196 | if (val) | |
1197 | CMOS_WRITE(be32_to_cpup(val), RTC_CONTROL); | |
1198 | ||
1199 | val = of_get_property(node, "freq-reg", NULL); | |
1200 | if (val) | |
1201 | CMOS_WRITE(be32_to_cpup(val), RTC_FREQ_SELECT); | |
1202 | ||
5ab788d7 | 1203 | cmos_read_time(&pdev->dev, &time); |
3bcbaf6e SAS |
1204 | ret = rtc_valid_tm(&time); |
1205 | if (ret) { | |
1206 | struct rtc_time def_time = { | |
1207 | .tm_year = 1, | |
1208 | .tm_mday = 1, | |
1209 | }; | |
5ab788d7 | 1210 | cmos_set_time(&pdev->dev, &def_time); |
3bcbaf6e SAS |
1211 | } |
1212 | } | |
1213 | #else | |
1214 | static inline void cmos_of_init(struct platform_device *pdev) {} | |
3bcbaf6e | 1215 | #endif |
7be2c7c9 DB |
1216 | /*----------------------------------------------------------------*/ |
1217 | ||
41ac8df9 | 1218 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 1219 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
1220 | */ |
1221 | ||
1222 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
1223 | { | |
31632dbd MR |
1224 | struct resource *resource; |
1225 | int irq; | |
1226 | ||
3bcbaf6e | 1227 | cmos_of_init(pdev); |
a474aaed | 1228 | cmos_wake_setup(&pdev->dev); |
31632dbd MR |
1229 | |
1230 | if (RTC_IOMAPPED) | |
1231 | resource = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
1232 | else | |
1233 | resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1234 | irq = platform_get_irq(pdev, 0); | |
1235 | if (irq < 0) | |
1236 | irq = -1; | |
1237 | ||
1238 | return cmos_do_probe(&pdev->dev, resource, irq); | |
7be2c7c9 DB |
1239 | } |
1240 | ||
1241 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
1242 | { | |
1243 | cmos_do_remove(&pdev->dev); | |
1244 | return 0; | |
1245 | } | |
1246 | ||
1247 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
1248 | { | |
31632dbd MR |
1249 | struct device *dev = &pdev->dev; |
1250 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
1251 | ||
88b8d33b AH |
1252 | if (system_state == SYSTEM_POWER_OFF) { |
1253 | int retval = cmos_poweroff(dev); | |
1254 | ||
1255 | if (cmos_aie_poweroff(dev) < 0 && !retval) | |
1256 | return; | |
1257 | } | |
74c4633d | 1258 | |
31632dbd | 1259 | cmos_do_shutdown(cmos->irq); |
7be2c7c9 DB |
1260 | } |
1261 | ||
ad28a07b KS |
1262 | /* work with hotplug and coldplug */ |
1263 | MODULE_ALIAS("platform:rtc_cmos"); | |
1264 | ||
7be2c7c9 DB |
1265 | static struct platform_driver cmos_platform_driver = { |
1266 | .remove = __exit_p(cmos_platform_remove), | |
1267 | .shutdown = cmos_platform_shutdown, | |
1268 | .driver = { | |
c823a202 | 1269 | .name = driver_name, |
2fb08e6c | 1270 | .pm = &cmos_pm_ops, |
c8a6046e | 1271 | .of_match_table = of_match_ptr(of_cmos_match), |
7be2c7c9 DB |
1272 | } |
1273 | }; | |
1274 | ||
65909814 TLSC |
1275 | #ifdef CONFIG_PNP |
1276 | static bool pnp_driver_registered; | |
1277 | #endif | |
1278 | static bool platform_driver_registered; | |
1279 | ||
7be2c7c9 DB |
1280 | static int __init cmos_init(void) |
1281 | { | |
72f22b1e BH |
1282 | int retval = 0; |
1283 | ||
1da2e3d6 | 1284 | #ifdef CONFIG_PNP |
65909814 TLSC |
1285 | retval = pnp_register_driver(&cmos_pnp_driver); |
1286 | if (retval == 0) | |
1287 | pnp_driver_registered = true; | |
72f22b1e BH |
1288 | #endif |
1289 | ||
65909814 | 1290 | if (!cmos_rtc.dev) { |
72f22b1e BH |
1291 | retval = platform_driver_probe(&cmos_platform_driver, |
1292 | cmos_platform_probe); | |
65909814 TLSC |
1293 | if (retval == 0) |
1294 | platform_driver_registered = true; | |
1295 | } | |
72f22b1e BH |
1296 | |
1297 | if (retval == 0) | |
1298 | return 0; | |
1299 | ||
1300 | #ifdef CONFIG_PNP | |
65909814 TLSC |
1301 | if (pnp_driver_registered) |
1302 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e BH |
1303 | #endif |
1304 | return retval; | |
7be2c7c9 DB |
1305 | } |
1306 | module_init(cmos_init); | |
1307 | ||
1308 | static void __exit cmos_exit(void) | |
1309 | { | |
1da2e3d6 | 1310 | #ifdef CONFIG_PNP |
65909814 TLSC |
1311 | if (pnp_driver_registered) |
1312 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e | 1313 | #endif |
65909814 TLSC |
1314 | if (platform_driver_registered) |
1315 | platform_driver_unregister(&cmos_platform_driver); | |
7be2c7c9 DB |
1316 | } |
1317 | module_exit(cmos_exit); | |
1318 | ||
1319 | ||
7be2c7c9 DB |
1320 | MODULE_AUTHOR("David Brownell"); |
1321 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
1322 | MODULE_LICENSE("GPL"); |