Commit | Line | Data |
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7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/mod_devicetable.h> | |
38 | ||
39 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ | |
40 | #include <asm-generic/rtc.h> | |
41 | ||
7be2c7c9 DB |
42 | struct cmos_rtc { |
43 | struct rtc_device *rtc; | |
44 | struct device *dev; | |
45 | int irq; | |
46 | struct resource *iomem; | |
47 | ||
87ac84f4 DB |
48 | void (*wake_on)(struct device *); |
49 | void (*wake_off)(struct device *); | |
50 | ||
51 | u8 enabled_wake; | |
7be2c7c9 DB |
52 | u8 suspend_ctrl; |
53 | ||
54 | /* newer hardware extends the original register set */ | |
55 | u8 day_alrm; | |
56 | u8 mon_alrm; | |
57 | u8 century; | |
58 | }; | |
59 | ||
60 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
61 | #define is_valid_irq(n) ((n) >= 0) | |
62 | ||
63 | static const char driver_name[] = "rtc_cmos"; | |
64 | ||
bcd9b89c DB |
65 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
66 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
67 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
68 | */ | |
69 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
70 | ||
71 | static inline int is_intr(u8 rtc_intr) | |
72 | { | |
73 | if (!(rtc_intr & RTC_IRQF)) | |
74 | return 0; | |
75 | return rtc_intr & RTC_IRQMASK; | |
76 | } | |
77 | ||
7be2c7c9 DB |
78 | /*----------------------------------------------------------------*/ |
79 | ||
35d3fdd5 DB |
80 | /* Much modern x86 hardware has HPETs (10+ MHz timers) which, because |
81 | * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly | |
82 | * used in a broken "legacy replacement" mode. The breakage includes | |
83 | * HPET #1 hijacking the IRQ for this RTC, and being unavailable for | |
84 | * other (better) use. | |
85 | * | |
86 | * When that broken mode is in use, platform glue provides a partial | |
87 | * emulation of hardware RTC IRQ facilities using HPET #1. We don't | |
88 | * want to use HPET for anything except those IRQs though... | |
89 | */ | |
90 | #ifdef CONFIG_HPET_EMULATE_RTC | |
91 | #include <asm/hpet.h> | |
92 | #else | |
93 | ||
94 | static inline int is_hpet_enabled(void) | |
95 | { | |
96 | return 0; | |
97 | } | |
98 | ||
99 | static inline int hpet_mask_rtc_irq_bit(unsigned long mask) | |
100 | { | |
101 | return 0; | |
102 | } | |
103 | ||
104 | static inline int hpet_set_rtc_irq_bit(unsigned long mask) | |
105 | { | |
106 | return 0; | |
107 | } | |
108 | ||
109 | static inline int | |
110 | hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | |
111 | { | |
112 | return 0; | |
113 | } | |
114 | ||
115 | static inline int hpet_set_periodic_freq(unsigned long freq) | |
116 | { | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static inline int hpet_rtc_dropped_irq(void) | |
121 | { | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static inline int hpet_rtc_timer_init(void) | |
126 | { | |
127 | return 0; | |
128 | } | |
129 | ||
130 | extern irq_handler_t hpet_rtc_interrupt; | |
131 | ||
132 | static inline int hpet_register_irq_handler(irq_handler_t handler) | |
133 | { | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static inline int hpet_unregister_irq_handler(irq_handler_t handler) | |
138 | { | |
139 | return 0; | |
140 | } | |
141 | ||
142 | #endif | |
143 | ||
144 | /*----------------------------------------------------------------*/ | |
145 | ||
7be2c7c9 DB |
146 | static int cmos_read_time(struct device *dev, struct rtc_time *t) |
147 | { | |
148 | /* REVISIT: if the clock has a "century" register, use | |
149 | * that instead of the heuristic in get_rtc_time(). | |
150 | * That'll make Y3K compatility (year > 2070) easy! | |
151 | */ | |
152 | get_rtc_time(t); | |
153 | return 0; | |
154 | } | |
155 | ||
156 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
157 | { | |
158 | /* REVISIT: set the "century" register if available | |
159 | * | |
160 | * NOTE: this ignores the issue whereby updating the seconds | |
161 | * takes effect exactly 500ms after we write the register. | |
162 | * (Also queueing and other delays before we get this far.) | |
163 | */ | |
164 | return set_rtc_time(t); | |
165 | } | |
166 | ||
167 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
168 | { | |
169 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
170 | unsigned char rtc_control; | |
171 | ||
172 | if (!is_valid_irq(cmos->irq)) | |
173 | return -EIO; | |
174 | ||
175 | /* Basic alarms only support hour, minute, and seconds fields. | |
176 | * Some also support day and month, for alarms up to a year in | |
177 | * the future. | |
178 | */ | |
179 | t->time.tm_mday = -1; | |
180 | t->time.tm_mon = -1; | |
181 | ||
182 | spin_lock_irq(&rtc_lock); | |
183 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
184 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
185 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
186 | ||
187 | if (cmos->day_alrm) { | |
615bb29c ML |
188 | /* ignore upper bits on readback per ACPI spec */ |
189 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
190 | if (!t->time.tm_mday) |
191 | t->time.tm_mday = -1; | |
192 | ||
193 | if (cmos->mon_alrm) { | |
194 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
195 | if (!t->time.tm_mon) | |
196 | t->time.tm_mon = -1; | |
197 | } | |
198 | } | |
199 | ||
200 | rtc_control = CMOS_READ(RTC_CONTROL); | |
201 | spin_unlock_irq(&rtc_lock); | |
202 | ||
203 | /* REVISIT this assumes PC style usage: always BCD */ | |
204 | ||
205 | if (((unsigned)t->time.tm_sec) < 0x60) | |
206 | t->time.tm_sec = BCD2BIN(t->time.tm_sec); | |
207 | else | |
208 | t->time.tm_sec = -1; | |
209 | if (((unsigned)t->time.tm_min) < 0x60) | |
210 | t->time.tm_min = BCD2BIN(t->time.tm_min); | |
211 | else | |
212 | t->time.tm_min = -1; | |
213 | if (((unsigned)t->time.tm_hour) < 0x24) | |
214 | t->time.tm_hour = BCD2BIN(t->time.tm_hour); | |
215 | else | |
216 | t->time.tm_hour = -1; | |
217 | ||
218 | if (cmos->day_alrm) { | |
219 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
220 | t->time.tm_mday = BCD2BIN(t->time.tm_mday); | |
221 | else | |
222 | t->time.tm_mday = -1; | |
223 | if (cmos->mon_alrm) { | |
224 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
225 | t->time.tm_mon = BCD2BIN(t->time.tm_mon) - 1; | |
226 | else | |
227 | t->time.tm_mon = -1; | |
228 | } | |
229 | } | |
230 | t->time.tm_year = -1; | |
231 | ||
232 | t->enabled = !!(rtc_control & RTC_AIE); | |
233 | t->pending = 0; | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
7e2a31da DB |
238 | static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control) |
239 | { | |
240 | unsigned char rtc_intr; | |
241 | ||
242 | /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
243 | * allegedly some older rtcs need that to handle irqs properly | |
244 | */ | |
245 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
246 | ||
247 | if (is_hpet_enabled()) | |
248 | return; | |
249 | ||
250 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
251 | if (is_intr(rtc_intr)) | |
252 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
253 | } | |
254 | ||
255 | static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) | |
256 | { | |
257 | unsigned char rtc_control; | |
258 | ||
259 | /* flush any pending IRQ status, notably for update irqs, | |
260 | * before we enable new IRQs | |
261 | */ | |
262 | rtc_control = CMOS_READ(RTC_CONTROL); | |
263 | cmos_checkintr(cmos, rtc_control); | |
264 | ||
265 | rtc_control |= mask; | |
266 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
267 | hpet_set_rtc_irq_bit(mask); | |
268 | ||
269 | cmos_checkintr(cmos, rtc_control); | |
270 | } | |
271 | ||
272 | static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) | |
273 | { | |
274 | unsigned char rtc_control; | |
275 | ||
276 | rtc_control = CMOS_READ(RTC_CONTROL); | |
277 | rtc_control &= ~mask; | |
278 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
279 | hpet_mask_rtc_irq_bit(mask); | |
280 | ||
281 | cmos_checkintr(cmos, rtc_control); | |
282 | } | |
283 | ||
7be2c7c9 DB |
284 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
285 | { | |
286 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
287 | unsigned char mon, mday, hrs, min, sec; | |
7be2c7c9 DB |
288 | |
289 | if (!is_valid_irq(cmos->irq)) | |
290 | return -EIO; | |
291 | ||
292 | /* REVISIT this assumes PC style usage: always BCD */ | |
293 | ||
294 | /* Writing 0xff means "don't care" or "match all". */ | |
295 | ||
2b653e06 ZY |
296 | mon = t->time.tm_mon + 1; |
297 | mon = (mon <= 12) ? BIN2BCD(mon) : 0xff; | |
7be2c7c9 DB |
298 | |
299 | mday = t->time.tm_mday; | |
300 | mday = (mday >= 1 && mday <= 31) ? BIN2BCD(mday) : 0xff; | |
301 | ||
302 | hrs = t->time.tm_hour; | |
303 | hrs = (hrs < 24) ? BIN2BCD(hrs) : 0xff; | |
304 | ||
305 | min = t->time.tm_min; | |
306 | min = (min < 60) ? BIN2BCD(min) : 0xff; | |
307 | ||
308 | sec = t->time.tm_sec; | |
309 | sec = (sec < 60) ? BIN2BCD(sec) : 0xff; | |
310 | ||
311 | spin_lock_irq(&rtc_lock); | |
312 | ||
313 | /* next rtc irq must not be from previous alarm setting */ | |
7e2a31da | 314 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
315 | |
316 | /* update alarm */ | |
317 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
318 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
319 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
320 | ||
321 | /* the system may support an "enhanced" alarm */ | |
322 | if (cmos->day_alrm) { | |
323 | CMOS_WRITE(mday, cmos->day_alrm); | |
324 | if (cmos->mon_alrm) | |
325 | CMOS_WRITE(mon, cmos->mon_alrm); | |
326 | } | |
327 | ||
35d3fdd5 DB |
328 | /* FIXME the HPET alarm glue currently ignores day_alrm |
329 | * and mon_alrm ... | |
330 | */ | |
331 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); | |
332 | ||
7e2a31da DB |
333 | if (t->enabled) |
334 | cmos_irq_enable(cmos, RTC_AIE); | |
7be2c7c9 DB |
335 | |
336 | spin_unlock_irq(&rtc_lock); | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
57deb526 | 341 | static int cmos_irq_set_freq(struct device *dev, int freq) |
7be2c7c9 DB |
342 | { |
343 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
344 | int f; | |
345 | unsigned long flags; | |
346 | ||
347 | if (!is_valid_irq(cmos->irq)) | |
348 | return -ENXIO; | |
349 | ||
350 | /* 0 = no irqs; 1 = 2^15 Hz ... 15 = 2^0 Hz */ | |
351 | f = ffs(freq); | |
97144c67 DB |
352 | if (f-- > 16) |
353 | return -EINVAL; | |
354 | f = 16 - f; | |
7be2c7c9 DB |
355 | |
356 | spin_lock_irqsave(&rtc_lock, flags); | |
35d3fdd5 DB |
357 | hpet_set_periodic_freq(freq); |
358 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
359 | spin_unlock_irqrestore(&rtc_lock, flags); |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
57deb526 AZ |
364 | static int cmos_irq_set_state(struct device *dev, int enabled) |
365 | { | |
366 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
57deb526 AZ |
367 | unsigned long flags; |
368 | ||
369 | if (!is_valid_irq(cmos->irq)) | |
370 | return -ENXIO; | |
371 | ||
372 | spin_lock_irqsave(&rtc_lock, flags); | |
57deb526 | 373 | |
7e2a31da DB |
374 | if (enabled) |
375 | cmos_irq_enable(cmos, RTC_PIE); | |
376 | else | |
377 | cmos_irq_disable(cmos, RTC_PIE); | |
57deb526 AZ |
378 | |
379 | spin_unlock_irqrestore(&rtc_lock, flags); | |
380 | return 0; | |
381 | } | |
382 | ||
7be2c7c9 DB |
383 | #if defined(CONFIG_RTC_INTF_DEV) || defined(CONFIG_RTC_INTF_DEV_MODULE) |
384 | ||
385 | static int | |
386 | cmos_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
387 | { | |
388 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
7be2c7c9 DB |
389 | unsigned long flags; |
390 | ||
391 | switch (cmd) { | |
392 | case RTC_AIE_OFF: | |
393 | case RTC_AIE_ON: | |
394 | case RTC_UIE_OFF: | |
395 | case RTC_UIE_ON: | |
7be2c7c9 DB |
396 | if (!is_valid_irq(cmos->irq)) |
397 | return -EINVAL; | |
398 | break; | |
35d3fdd5 | 399 | /* PIE ON/OFF is handled by cmos_irq_set_state() */ |
7be2c7c9 DB |
400 | default: |
401 | return -ENOIOCTLCMD; | |
402 | } | |
403 | ||
404 | spin_lock_irqsave(&rtc_lock, flags); | |
7be2c7c9 DB |
405 | switch (cmd) { |
406 | case RTC_AIE_OFF: /* alarm off */ | |
7e2a31da | 407 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
408 | break; |
409 | case RTC_AIE_ON: /* alarm on */ | |
7e2a31da | 410 | cmos_irq_enable(cmos, RTC_AIE); |
7be2c7c9 DB |
411 | break; |
412 | case RTC_UIE_OFF: /* update off */ | |
7e2a31da | 413 | cmos_irq_disable(cmos, RTC_UIE); |
7be2c7c9 DB |
414 | break; |
415 | case RTC_UIE_ON: /* update on */ | |
7e2a31da | 416 | cmos_irq_enable(cmos, RTC_UIE); |
7be2c7c9 | 417 | break; |
7be2c7c9 | 418 | } |
7be2c7c9 DB |
419 | spin_unlock_irqrestore(&rtc_lock, flags); |
420 | return 0; | |
421 | } | |
422 | ||
423 | #else | |
424 | #define cmos_rtc_ioctl NULL | |
425 | #endif | |
426 | ||
427 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) | |
428 | ||
429 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
430 | { | |
431 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
432 | unsigned char rtc_control, valid; | |
433 | ||
434 | spin_lock_irq(&rtc_lock); | |
435 | rtc_control = CMOS_READ(RTC_CONTROL); | |
436 | valid = CMOS_READ(RTC_VALID); | |
437 | spin_unlock_irq(&rtc_lock); | |
438 | ||
439 | /* NOTE: at least ICH6 reports battery status using a different | |
440 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
441 | */ | |
442 | return seq_printf(seq, | |
443 | "periodic_IRQ\t: %s\n" | |
444 | "update_IRQ\t: %s\n" | |
c8626a1d | 445 | "HPET_emulated\t: %s\n" |
7be2c7c9 DB |
446 | // "square_wave\t: %s\n" |
447 | // "BCD\t\t: %s\n" | |
448 | "DST_enable\t: %s\n" | |
449 | "periodic_freq\t: %d\n" | |
450 | "batt_status\t: %s\n", | |
451 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
452 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
c8626a1d | 453 | is_hpet_enabled() ? "yes" : "no", |
7be2c7c9 DB |
454 | // (rtc_control & RTC_SQWE) ? "yes" : "no", |
455 | // (rtc_control & RTC_DM_BINARY) ? "no" : "yes", | |
456 | (rtc_control & RTC_DST_EN) ? "yes" : "no", | |
457 | cmos->rtc->irq_freq, | |
458 | (valid & RTC_VRT) ? "okay" : "dead"); | |
459 | } | |
460 | ||
461 | #else | |
462 | #define cmos_procfs NULL | |
463 | #endif | |
464 | ||
465 | static const struct rtc_class_ops cmos_rtc_ops = { | |
466 | .ioctl = cmos_rtc_ioctl, | |
467 | .read_time = cmos_read_time, | |
468 | .set_time = cmos_set_time, | |
469 | .read_alarm = cmos_read_alarm, | |
470 | .set_alarm = cmos_set_alarm, | |
471 | .proc = cmos_procfs, | |
57deb526 AZ |
472 | .irq_set_freq = cmos_irq_set_freq, |
473 | .irq_set_state = cmos_irq_set_state, | |
7be2c7c9 DB |
474 | }; |
475 | ||
476 | /*----------------------------------------------------------------*/ | |
477 | ||
e07e232c DB |
478 | /* |
479 | * All these chips have at least 64 bytes of address space, shared by | |
480 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
481 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
482 | */ | |
483 | ||
484 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
485 | ||
486 | static ssize_t | |
487 | cmos_nvram_read(struct kobject *kobj, struct bin_attribute *attr, | |
488 | char *buf, loff_t off, size_t count) | |
489 | { | |
490 | int retval; | |
491 | ||
492 | if (unlikely(off >= attr->size)) | |
493 | return 0; | |
494 | if ((off + count) > attr->size) | |
495 | count = attr->size - off; | |
496 | ||
497 | spin_lock_irq(&rtc_lock); | |
498 | for (retval = 0, off += NVRAM_OFFSET; count--; retval++, off++) | |
499 | *buf++ = CMOS_READ(off); | |
500 | spin_unlock_irq(&rtc_lock); | |
501 | ||
502 | return retval; | |
503 | } | |
504 | ||
505 | static ssize_t | |
506 | cmos_nvram_write(struct kobject *kobj, struct bin_attribute *attr, | |
507 | char *buf, loff_t off, size_t count) | |
508 | { | |
509 | struct cmos_rtc *cmos; | |
510 | int retval; | |
511 | ||
512 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
513 | if (unlikely(off >= attr->size)) | |
514 | return -EFBIG; | |
515 | if ((off + count) > attr->size) | |
516 | count = attr->size - off; | |
517 | ||
518 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
519 | * checksum on part of the NVRAM data. That's currently ignored | |
520 | * here. If userspace is smart enough to know what fields of | |
521 | * NVRAM to update, updating checksums is also part of its job. | |
522 | */ | |
523 | spin_lock_irq(&rtc_lock); | |
524 | for (retval = 0, off += NVRAM_OFFSET; count--; retval++, off++) { | |
525 | /* don't trash RTC registers */ | |
526 | if (off == cmos->day_alrm | |
527 | || off == cmos->mon_alrm | |
528 | || off == cmos->century) | |
529 | buf++; | |
530 | else | |
531 | CMOS_WRITE(*buf++, off); | |
532 | } | |
533 | spin_unlock_irq(&rtc_lock); | |
534 | ||
535 | return retval; | |
536 | } | |
537 | ||
538 | static struct bin_attribute nvram = { | |
539 | .attr = { | |
540 | .name = "nvram", | |
541 | .mode = S_IRUGO | S_IWUSR, | |
542 | .owner = THIS_MODULE, | |
543 | }, | |
544 | ||
545 | .read = cmos_nvram_read, | |
546 | .write = cmos_nvram_write, | |
547 | /* size gets set up later */ | |
548 | }; | |
549 | ||
550 | /*----------------------------------------------------------------*/ | |
551 | ||
7be2c7c9 DB |
552 | static struct cmos_rtc cmos_rtc; |
553 | ||
554 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
555 | { | |
556 | u8 irqstat; | |
8a0bdfd7 | 557 | u8 rtc_control; |
7be2c7c9 DB |
558 | |
559 | spin_lock(&rtc_lock); | |
35d3fdd5 DB |
560 | |
561 | /* When the HPET interrupt handler calls us, the interrupt | |
562 | * status is passed as arg1 instead of the irq number. But | |
563 | * always clear irq status, even when HPET is in the way. | |
564 | * | |
565 | * Note that HPET and RTC are almost certainly out of phase, | |
566 | * giving different IRQ status ... | |
9d8af78b | 567 | */ |
35d3fdd5 DB |
568 | irqstat = CMOS_READ(RTC_INTR_FLAGS); |
569 | rtc_control = CMOS_READ(RTC_CONTROL); | |
9d8af78b BW |
570 | if (is_hpet_enabled()) |
571 | irqstat = (unsigned long)irq & 0xF0; | |
35d3fdd5 | 572 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
8a0bdfd7 DB |
573 | |
574 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
575 | * Similar code may be needed in system wakeup paths, in case the | |
576 | * alarm woke the system. | |
577 | */ | |
578 | if (irqstat & RTC_AIE) { | |
579 | rtc_control &= ~RTC_AIE; | |
580 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
35d3fdd5 DB |
581 | hpet_mask_rtc_irq_bit(RTC_AIE); |
582 | ||
8a0bdfd7 DB |
583 | CMOS_READ(RTC_INTR_FLAGS); |
584 | } | |
7be2c7c9 DB |
585 | spin_unlock(&rtc_lock); |
586 | ||
bcd9b89c | 587 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
588 | rtc_update_irq(p, 1, irqstat); |
589 | return IRQ_HANDLED; | |
590 | } else | |
591 | return IRQ_NONE; | |
592 | } | |
593 | ||
41ac8df9 | 594 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
595 | #define INITSECTION |
596 | ||
597 | #else | |
7be2c7c9 DB |
598 | #define INITSECTION __init |
599 | #endif | |
600 | ||
601 | static int INITSECTION | |
602 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
603 | { | |
604 | struct cmos_rtc_board_info *info = dev->platform_data; | |
605 | int retval = 0; | |
606 | unsigned char rtc_control; | |
e07e232c | 607 | unsigned address_space; |
7be2c7c9 DB |
608 | |
609 | /* there can be only one ... */ | |
610 | if (cmos_rtc.dev) | |
611 | return -EBUSY; | |
612 | ||
613 | if (!ports) | |
614 | return -ENODEV; | |
615 | ||
05440dfc DB |
616 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
617 | * | |
618 | * REVISIT non-x86 systems may instead use memory space resources | |
619 | * (needing ioremap etc), not i/o space resources like this ... | |
620 | */ | |
621 | ports = request_region(ports->start, | |
622 | ports->end + 1 - ports->start, | |
623 | driver_name); | |
624 | if (!ports) { | |
625 | dev_dbg(dev, "i/o registers already in use\n"); | |
626 | return -EBUSY; | |
627 | } | |
628 | ||
7be2c7c9 DB |
629 | cmos_rtc.irq = rtc_irq; |
630 | cmos_rtc.iomem = ports; | |
631 | ||
e07e232c DB |
632 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
633 | * driver did, but don't reject unknown configs. Old hardware | |
634 | * won't address 128 bytes, and for now we ignore the way newer | |
635 | * chips can address 256 bytes (using two more i/o ports). | |
636 | */ | |
637 | #if defined(CONFIG_ATARI) | |
638 | address_space = 64; | |
639 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) | |
640 | address_space = 128; | |
641 | #else | |
642 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
643 | address_space = 128; | |
644 | #endif | |
645 | ||
87ac84f4 DB |
646 | /* For ACPI systems extension info comes from the FADT. On others, |
647 | * board specific setup provides it as appropriate. Systems where | |
648 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
649 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
650 | * |
651 | * Note that ACPI doesn't preclude putting these registers into | |
652 | * "extended" areas of the chip, including some that we won't yet | |
653 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
654 | */ |
655 | if (info) { | |
e07e232c DB |
656 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
657 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
658 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
659 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
660 | if (info->rtc_century && info->rtc_century < 128) | |
661 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
662 | |
663 | if (info->wake_on && info->wake_off) { | |
664 | cmos_rtc.wake_on = info->wake_on; | |
665 | cmos_rtc.wake_off = info->wake_off; | |
666 | } | |
7be2c7c9 DB |
667 | } |
668 | ||
669 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, | |
670 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
671 | if (IS_ERR(cmos_rtc.rtc)) { |
672 | retval = PTR_ERR(cmos_rtc.rtc); | |
673 | goto cleanup0; | |
674 | } | |
7be2c7c9 DB |
675 | |
676 | cmos_rtc.dev = dev; | |
677 | dev_set_drvdata(dev, &cmos_rtc); | |
cd966209 | 678 | rename_region(ports, cmos_rtc.rtc->dev.bus_id); |
7be2c7c9 DB |
679 | |
680 | spin_lock_irq(&rtc_lock); | |
681 | ||
682 | /* force periodic irq to CMOS reset default of 1024Hz; | |
683 | * | |
684 | * REVISIT it's been reported that at least one x86_64 ALI mobo | |
685 | * doesn't use 32KHz here ... for portability we might need to | |
686 | * do something about other clock frequencies. | |
687 | */ | |
7be2c7c9 | 688 | cmos_rtc.rtc->irq_freq = 1024; |
35d3fdd5 DB |
689 | hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq); |
690 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
7be2c7c9 | 691 | |
7e2a31da DB |
692 | /* disable irqs */ |
693 | cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE); | |
35d3fdd5 | 694 | |
7e2a31da | 695 | rtc_control = CMOS_READ(RTC_CONTROL); |
7be2c7c9 DB |
696 | |
697 | spin_unlock_irq(&rtc_lock); | |
698 | ||
699 | /* FIXME teach the alarm code how to handle binary mode; | |
700 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. | |
701 | */ | |
702 | if (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY))) { | |
703 | dev_dbg(dev, "only 24-hr BCD mode supported\n"); | |
704 | retval = -ENXIO; | |
705 | goto cleanup1; | |
706 | } | |
707 | ||
9d8af78b BW |
708 | if (is_valid_irq(rtc_irq)) { |
709 | irq_handler_t rtc_cmos_int_handler; | |
710 | ||
711 | if (is_hpet_enabled()) { | |
712 | int err; | |
713 | ||
714 | rtc_cmos_int_handler = hpet_rtc_interrupt; | |
715 | err = hpet_register_irq_handler(cmos_interrupt); | |
716 | if (err != 0) { | |
717 | printk(KERN_WARNING "hpet_register_irq_handler " | |
718 | " failed in rtc_init()."); | |
719 | goto cleanup1; | |
720 | } | |
721 | } else | |
722 | rtc_cmos_int_handler = cmos_interrupt; | |
723 | ||
724 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
725 | IRQF_DISABLED, cmos_rtc.rtc->dev.bus_id, | |
ab6a2d70 | 726 | cmos_rtc.rtc); |
9d8af78b BW |
727 | if (retval < 0) { |
728 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
729 | goto cleanup1; | |
730 | } | |
7be2c7c9 | 731 | } |
9d8af78b | 732 | hpet_rtc_timer_init(); |
7be2c7c9 | 733 | |
e07e232c DB |
734 | /* export at least the first block of NVRAM */ |
735 | nvram.size = address_space - NVRAM_OFFSET; | |
736 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
737 | if (retval < 0) { | |
738 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
739 | goto cleanup2; | |
740 | } | |
7be2c7c9 | 741 | |
35d3fdd5 | 742 | pr_info("%s: alarms up to one %s%s%s\n", |
cd966209 | 743 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
744 | is_valid_irq(rtc_irq) |
745 | ? (cmos_rtc.mon_alrm | |
746 | ? "year" | |
747 | : (cmos_rtc.day_alrm | |
748 | ? "month" : "day")) | |
749 | : "no", | |
35d3fdd5 DB |
750 | cmos_rtc.century ? ", y3k" : "", |
751 | is_hpet_enabled() ? ", hpet irqs" : ""); | |
7be2c7c9 DB |
752 | |
753 | return 0; | |
754 | ||
e07e232c DB |
755 | cleanup2: |
756 | if (is_valid_irq(rtc_irq)) | |
757 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 758 | cleanup1: |
05440dfc | 759 | cmos_rtc.dev = NULL; |
7be2c7c9 | 760 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc DB |
761 | cleanup0: |
762 | release_region(ports->start, ports->end + 1 - ports->start); | |
7be2c7c9 DB |
763 | return retval; |
764 | } | |
765 | ||
766 | static void cmos_do_shutdown(void) | |
767 | { | |
7be2c7c9 | 768 | spin_lock_irq(&rtc_lock); |
7e2a31da | 769 | cmos_irq_disable(&cmos_rtc, RTC_IRQMASK); |
7be2c7c9 DB |
770 | spin_unlock_irq(&rtc_lock); |
771 | } | |
772 | ||
773 | static void __exit cmos_do_remove(struct device *dev) | |
774 | { | |
775 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 776 | struct resource *ports; |
7be2c7c9 DB |
777 | |
778 | cmos_do_shutdown(); | |
779 | ||
e07e232c DB |
780 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
781 | ||
9d8af78b | 782 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 783 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
784 | hpet_unregister_irq_handler(cmos_interrupt); |
785 | } | |
7be2c7c9 | 786 | |
05440dfc DB |
787 | rtc_device_unregister(cmos->rtc); |
788 | cmos->rtc = NULL; | |
7be2c7c9 | 789 | |
05440dfc DB |
790 | ports = cmos->iomem; |
791 | release_region(ports->start, ports->end + 1 - ports->start); | |
792 | cmos->iomem = NULL; | |
793 | ||
794 | cmos->dev = NULL; | |
7be2c7c9 DB |
795 | dev_set_drvdata(dev, NULL); |
796 | } | |
797 | ||
798 | #ifdef CONFIG_PM | |
799 | ||
800 | static int cmos_suspend(struct device *dev, pm_message_t mesg) | |
801 | { | |
802 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
803 | int do_wake = device_may_wakeup(dev); | |
bcd9b89c | 804 | unsigned char tmp; |
7be2c7c9 DB |
805 | |
806 | /* only the alarm might be a wakeup event source */ | |
807 | spin_lock_irq(&rtc_lock); | |
808 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
809 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
35d3fdd5 | 810 | unsigned char mask; |
bcd9b89c | 811 | |
7be2c7c9 | 812 | if (do_wake) |
35d3fdd5 | 813 | mask = RTC_IRQMASK & ~RTC_AIE; |
7be2c7c9 | 814 | else |
35d3fdd5 DB |
815 | mask = RTC_IRQMASK; |
816 | tmp &= ~mask; | |
7be2c7c9 | 817 | CMOS_WRITE(tmp, RTC_CONTROL); |
35d3fdd5 DB |
818 | hpet_mask_rtc_irq_bit(mask); |
819 | ||
7e2a31da | 820 | cmos_checkintr(cmos, tmp); |
bcd9b89c | 821 | } |
7be2c7c9 DB |
822 | spin_unlock_irq(&rtc_lock); |
823 | ||
87ac84f4 DB |
824 | if (tmp & RTC_AIE) { |
825 | cmos->enabled_wake = 1; | |
826 | if (cmos->wake_on) | |
827 | cmos->wake_on(dev); | |
828 | else | |
829 | enable_irq_wake(cmos->irq); | |
830 | } | |
7be2c7c9 DB |
831 | |
832 | pr_debug("%s: suspend%s, ctrl %02x\n", | |
cd966209 | 833 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
834 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
835 | tmp); | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
840 | static int cmos_resume(struct device *dev) | |
841 | { | |
842 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
843 | unsigned char tmp = cmos->suspend_ctrl; | |
844 | ||
7be2c7c9 | 845 | /* re-enable any irqs previously active */ |
35d3fdd5 DB |
846 | if (tmp & RTC_IRQMASK) { |
847 | unsigned char mask; | |
7be2c7c9 | 848 | |
87ac84f4 DB |
849 | if (cmos->enabled_wake) { |
850 | if (cmos->wake_off) | |
851 | cmos->wake_off(dev); | |
852 | else | |
853 | disable_irq_wake(cmos->irq); | |
854 | cmos->enabled_wake = 0; | |
855 | } | |
7be2c7c9 DB |
856 | |
857 | spin_lock_irq(&rtc_lock); | |
35d3fdd5 DB |
858 | do { |
859 | CMOS_WRITE(tmp, RTC_CONTROL); | |
860 | hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK); | |
861 | ||
862 | mask = CMOS_READ(RTC_INTR_FLAGS); | |
863 | mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; | |
7e2a31da | 864 | if (!is_hpet_enabled() || !is_intr(mask)) |
35d3fdd5 DB |
865 | break; |
866 | ||
867 | /* force one-shot behavior if HPET blocked | |
868 | * the wake alarm's irq | |
869 | */ | |
870 | rtc_update_irq(cmos->rtc, 1, mask); | |
871 | tmp &= ~RTC_AIE; | |
872 | hpet_mask_rtc_irq_bit(RTC_AIE); | |
873 | } while (mask & RTC_AIE); | |
bcd9b89c | 874 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 DB |
875 | } |
876 | ||
877 | pr_debug("%s: resume, ctrl %02x\n", | |
cd966209 | 878 | cmos_rtc.rtc->dev.bus_id, |
35d3fdd5 | 879 | tmp); |
7be2c7c9 DB |
880 | |
881 | return 0; | |
882 | } | |
883 | ||
884 | #else | |
885 | #define cmos_suspend NULL | |
886 | #define cmos_resume NULL | |
887 | #endif | |
888 | ||
889 | /*----------------------------------------------------------------*/ | |
890 | ||
e07e232c DB |
891 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
892 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
893 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
894 | * | |
895 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
896 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
897 | */ |
898 | ||
41ac8df9 | 899 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
900 | |
901 | #include <linux/pnp.h> | |
902 | ||
903 | static int __devinit | |
904 | cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) | |
905 | { | |
906 | /* REVISIT paranoia argues for a shutdown notifier, since PNP | |
907 | * drivers can't provide shutdown() methods to disable IRQs. | |
908 | * Or better yet, fix PNP to allow those methods... | |
909 | */ | |
6cd8fa87 MG |
910 | if (pnp_port_start(pnp,0) == 0x70 && !pnp_irq_valid(pnp,0)) |
911 | /* Some machines contain a PNP entry for the RTC, but | |
912 | * don't define the IRQ. It should always be safe to | |
913 | * hardcode it in these cases | |
914 | */ | |
8766ad0c BH |
915 | return cmos_do_probe(&pnp->dev, |
916 | pnp_get_resource(pnp, IORESOURCE_IO, 0), 8); | |
6cd8fa87 MG |
917 | else |
918 | return cmos_do_probe(&pnp->dev, | |
8766ad0c BH |
919 | pnp_get_resource(pnp, IORESOURCE_IO, 0), |
920 | pnp_irq(pnp, 0)); | |
7be2c7c9 DB |
921 | } |
922 | ||
923 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
924 | { | |
925 | cmos_do_remove(&pnp->dev); | |
926 | } | |
927 | ||
928 | #ifdef CONFIG_PM | |
929 | ||
930 | static int cmos_pnp_suspend(struct pnp_dev *pnp, pm_message_t mesg) | |
931 | { | |
932 | return cmos_suspend(&pnp->dev, mesg); | |
933 | } | |
934 | ||
935 | static int cmos_pnp_resume(struct pnp_dev *pnp) | |
936 | { | |
937 | return cmos_resume(&pnp->dev); | |
938 | } | |
939 | ||
940 | #else | |
941 | #define cmos_pnp_suspend NULL | |
942 | #define cmos_pnp_resume NULL | |
943 | #endif | |
944 | ||
945 | ||
946 | static const struct pnp_device_id rtc_ids[] = { | |
947 | { .id = "PNP0b00", }, | |
948 | { .id = "PNP0b01", }, | |
949 | { .id = "PNP0b02", }, | |
950 | { }, | |
951 | }; | |
952 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
953 | ||
954 | static struct pnp_driver cmos_pnp_driver = { | |
955 | .name = (char *) driver_name, | |
956 | .id_table = rtc_ids, | |
957 | .probe = cmos_pnp_probe, | |
958 | .remove = __exit_p(cmos_pnp_remove), | |
959 | ||
960 | /* flag ensures resume() gets called, and stops syslog spam */ | |
961 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
962 | .suspend = cmos_pnp_suspend, | |
963 | .resume = cmos_pnp_resume, | |
964 | }; | |
965 | ||
1da2e3d6 | 966 | #endif /* CONFIG_PNP */ |
7be2c7c9 DB |
967 | |
968 | /*----------------------------------------------------------------*/ | |
969 | ||
41ac8df9 | 970 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 971 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
972 | */ |
973 | ||
974 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
975 | { | |
976 | return cmos_do_probe(&pdev->dev, | |
977 | platform_get_resource(pdev, IORESOURCE_IO, 0), | |
978 | platform_get_irq(pdev, 0)); | |
979 | } | |
980 | ||
981 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
982 | { | |
983 | cmos_do_remove(&pdev->dev); | |
984 | return 0; | |
985 | } | |
986 | ||
987 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
988 | { | |
989 | cmos_do_shutdown(); | |
990 | } | |
991 | ||
ad28a07b KS |
992 | /* work with hotplug and coldplug */ |
993 | MODULE_ALIAS("platform:rtc_cmos"); | |
994 | ||
7be2c7c9 DB |
995 | static struct platform_driver cmos_platform_driver = { |
996 | .remove = __exit_p(cmos_platform_remove), | |
997 | .shutdown = cmos_platform_shutdown, | |
998 | .driver = { | |
999 | .name = (char *) driver_name, | |
1000 | .suspend = cmos_suspend, | |
1001 | .resume = cmos_resume, | |
1002 | } | |
1003 | }; | |
1004 | ||
1005 | static int __init cmos_init(void) | |
1006 | { | |
1da2e3d6 SS |
1007 | #ifdef CONFIG_PNP |
1008 | if (pnp_platform_devices) | |
1009 | return pnp_register_driver(&cmos_pnp_driver); | |
1010 | else | |
1011 | return platform_driver_probe(&cmos_platform_driver, | |
1012 | cmos_platform_probe); | |
1013 | #else | |
7be2c7c9 DB |
1014 | return platform_driver_probe(&cmos_platform_driver, |
1015 | cmos_platform_probe); | |
1da2e3d6 | 1016 | #endif /* CONFIG_PNP */ |
7be2c7c9 DB |
1017 | } |
1018 | module_init(cmos_init); | |
1019 | ||
1020 | static void __exit cmos_exit(void) | |
1021 | { | |
1da2e3d6 SS |
1022 | #ifdef CONFIG_PNP |
1023 | if (pnp_platform_devices) | |
1024 | pnp_unregister_driver(&cmos_pnp_driver); | |
1025 | else | |
1026 | platform_driver_unregister(&cmos_platform_driver); | |
1027 | #else | |
7be2c7c9 | 1028 | platform_driver_unregister(&cmos_platform_driver); |
1da2e3d6 | 1029 | #endif /* CONFIG_PNP */ |
7be2c7c9 DB |
1030 | } |
1031 | module_exit(cmos_exit); | |
1032 | ||
1033 | ||
7be2c7c9 DB |
1034 | MODULE_AUTHOR("David Brownell"); |
1035 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
1036 | MODULE_LICENSE("GPL"); |