Commit | Line | Data |
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7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/mod_devicetable.h> | |
5d2a5037 | 38 | #include <linux/log2.h> |
7be2c7c9 DB |
39 | |
40 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ | |
41 | #include <asm-generic/rtc.h> | |
42 | ||
7be2c7c9 DB |
43 | struct cmos_rtc { |
44 | struct rtc_device *rtc; | |
45 | struct device *dev; | |
46 | int irq; | |
47 | struct resource *iomem; | |
48 | ||
87ac84f4 DB |
49 | void (*wake_on)(struct device *); |
50 | void (*wake_off)(struct device *); | |
51 | ||
52 | u8 enabled_wake; | |
7be2c7c9 DB |
53 | u8 suspend_ctrl; |
54 | ||
55 | /* newer hardware extends the original register set */ | |
56 | u8 day_alrm; | |
57 | u8 mon_alrm; | |
58 | u8 century; | |
59 | }; | |
60 | ||
61 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
2fac6674 | 62 | #define is_valid_irq(n) ((n) > 0) |
7be2c7c9 DB |
63 | |
64 | static const char driver_name[] = "rtc_cmos"; | |
65 | ||
bcd9b89c DB |
66 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
67 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
68 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
69 | */ | |
70 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
71 | ||
72 | static inline int is_intr(u8 rtc_intr) | |
73 | { | |
74 | if (!(rtc_intr & RTC_IRQF)) | |
75 | return 0; | |
76 | return rtc_intr & RTC_IRQMASK; | |
77 | } | |
78 | ||
7be2c7c9 DB |
79 | /*----------------------------------------------------------------*/ |
80 | ||
35d3fdd5 DB |
81 | /* Much modern x86 hardware has HPETs (10+ MHz timers) which, because |
82 | * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly | |
83 | * used in a broken "legacy replacement" mode. The breakage includes | |
84 | * HPET #1 hijacking the IRQ for this RTC, and being unavailable for | |
85 | * other (better) use. | |
86 | * | |
87 | * When that broken mode is in use, platform glue provides a partial | |
88 | * emulation of hardware RTC IRQ facilities using HPET #1. We don't | |
89 | * want to use HPET for anything except those IRQs though... | |
90 | */ | |
91 | #ifdef CONFIG_HPET_EMULATE_RTC | |
92 | #include <asm/hpet.h> | |
93 | #else | |
94 | ||
95 | static inline int is_hpet_enabled(void) | |
96 | { | |
97 | return 0; | |
98 | } | |
99 | ||
100 | static inline int hpet_mask_rtc_irq_bit(unsigned long mask) | |
101 | { | |
102 | return 0; | |
103 | } | |
104 | ||
105 | static inline int hpet_set_rtc_irq_bit(unsigned long mask) | |
106 | { | |
107 | return 0; | |
108 | } | |
109 | ||
110 | static inline int | |
111 | hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | |
112 | { | |
113 | return 0; | |
114 | } | |
115 | ||
116 | static inline int hpet_set_periodic_freq(unsigned long freq) | |
117 | { | |
118 | return 0; | |
119 | } | |
120 | ||
121 | static inline int hpet_rtc_dropped_irq(void) | |
122 | { | |
123 | return 0; | |
124 | } | |
125 | ||
126 | static inline int hpet_rtc_timer_init(void) | |
127 | { | |
128 | return 0; | |
129 | } | |
130 | ||
131 | extern irq_handler_t hpet_rtc_interrupt; | |
132 | ||
133 | static inline int hpet_register_irq_handler(irq_handler_t handler) | |
134 | { | |
135 | return 0; | |
136 | } | |
137 | ||
138 | static inline int hpet_unregister_irq_handler(irq_handler_t handler) | |
139 | { | |
140 | return 0; | |
141 | } | |
142 | ||
143 | #endif | |
144 | ||
145 | /*----------------------------------------------------------------*/ | |
146 | ||
c8fc40cd DB |
147 | #ifdef RTC_PORT |
148 | ||
149 | /* Most newer x86 systems have two register banks, the first used | |
150 | * for RTC and NVRAM and the second only for NVRAM. Caller must | |
151 | * own rtc_lock ... and we won't worry about access during NMI. | |
152 | */ | |
153 | #define can_bank2 true | |
154 | ||
155 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
156 | { | |
157 | outb(addr, RTC_PORT(2)); | |
158 | return inb(RTC_PORT(3)); | |
159 | } | |
160 | ||
161 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
162 | { | |
163 | outb(addr, RTC_PORT(2)); | |
164 | outb(val, RTC_PORT(2)); | |
165 | } | |
166 | ||
167 | #else | |
168 | ||
169 | #define can_bank2 false | |
170 | ||
171 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
172 | { | |
173 | return 0; | |
174 | } | |
175 | ||
176 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
177 | { | |
178 | } | |
179 | ||
180 | #endif | |
181 | ||
182 | /*----------------------------------------------------------------*/ | |
183 | ||
7be2c7c9 DB |
184 | static int cmos_read_time(struct device *dev, struct rtc_time *t) |
185 | { | |
186 | /* REVISIT: if the clock has a "century" register, use | |
187 | * that instead of the heuristic in get_rtc_time(). | |
188 | * That'll make Y3K compatility (year > 2070) easy! | |
189 | */ | |
190 | get_rtc_time(t); | |
191 | return 0; | |
192 | } | |
193 | ||
194 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
195 | { | |
196 | /* REVISIT: set the "century" register if available | |
197 | * | |
198 | * NOTE: this ignores the issue whereby updating the seconds | |
199 | * takes effect exactly 500ms after we write the register. | |
200 | * (Also queueing and other delays before we get this far.) | |
201 | */ | |
202 | return set_rtc_time(t); | |
203 | } | |
204 | ||
205 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
206 | { | |
207 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
208 | unsigned char rtc_control; | |
209 | ||
210 | if (!is_valid_irq(cmos->irq)) | |
211 | return -EIO; | |
212 | ||
213 | /* Basic alarms only support hour, minute, and seconds fields. | |
214 | * Some also support day and month, for alarms up to a year in | |
215 | * the future. | |
216 | */ | |
217 | t->time.tm_mday = -1; | |
218 | t->time.tm_mon = -1; | |
219 | ||
220 | spin_lock_irq(&rtc_lock); | |
221 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
222 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
223 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
224 | ||
225 | if (cmos->day_alrm) { | |
615bb29c ML |
226 | /* ignore upper bits on readback per ACPI spec */ |
227 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
228 | if (!t->time.tm_mday) |
229 | t->time.tm_mday = -1; | |
230 | ||
231 | if (cmos->mon_alrm) { | |
232 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
233 | if (!t->time.tm_mon) | |
234 | t->time.tm_mon = -1; | |
235 | } | |
236 | } | |
237 | ||
238 | rtc_control = CMOS_READ(RTC_CONTROL); | |
239 | spin_unlock_irq(&rtc_lock); | |
240 | ||
3804a89b AP |
241 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { |
242 | if (((unsigned)t->time.tm_sec) < 0x60) | |
243 | t->time.tm_sec = bcd2bin(t->time.tm_sec); | |
7be2c7c9 | 244 | else |
3804a89b AP |
245 | t->time.tm_sec = -1; |
246 | if (((unsigned)t->time.tm_min) < 0x60) | |
247 | t->time.tm_min = bcd2bin(t->time.tm_min); | |
248 | else | |
249 | t->time.tm_min = -1; | |
250 | if (((unsigned)t->time.tm_hour) < 0x24) | |
251 | t->time.tm_hour = bcd2bin(t->time.tm_hour); | |
252 | else | |
253 | t->time.tm_hour = -1; | |
254 | ||
255 | if (cmos->day_alrm) { | |
256 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
257 | t->time.tm_mday = bcd2bin(t->time.tm_mday); | |
7be2c7c9 | 258 | else |
3804a89b AP |
259 | t->time.tm_mday = -1; |
260 | ||
261 | if (cmos->mon_alrm) { | |
262 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
263 | t->time.tm_mon = bcd2bin(t->time.tm_mon)-1; | |
264 | else | |
265 | t->time.tm_mon = -1; | |
266 | } | |
7be2c7c9 DB |
267 | } |
268 | } | |
269 | t->time.tm_year = -1; | |
270 | ||
271 | t->enabled = !!(rtc_control & RTC_AIE); | |
272 | t->pending = 0; | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
7e2a31da DB |
277 | static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control) |
278 | { | |
279 | unsigned char rtc_intr; | |
280 | ||
281 | /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
282 | * allegedly some older rtcs need that to handle irqs properly | |
283 | */ | |
284 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
285 | ||
286 | if (is_hpet_enabled()) | |
287 | return; | |
288 | ||
289 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
290 | if (is_intr(rtc_intr)) | |
291 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
292 | } | |
293 | ||
294 | static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) | |
295 | { | |
296 | unsigned char rtc_control; | |
297 | ||
298 | /* flush any pending IRQ status, notably for update irqs, | |
299 | * before we enable new IRQs | |
300 | */ | |
301 | rtc_control = CMOS_READ(RTC_CONTROL); | |
302 | cmos_checkintr(cmos, rtc_control); | |
303 | ||
304 | rtc_control |= mask; | |
305 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
306 | hpet_set_rtc_irq_bit(mask); | |
307 | ||
308 | cmos_checkintr(cmos, rtc_control); | |
309 | } | |
310 | ||
311 | static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) | |
312 | { | |
313 | unsigned char rtc_control; | |
314 | ||
315 | rtc_control = CMOS_READ(RTC_CONTROL); | |
316 | rtc_control &= ~mask; | |
317 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
318 | hpet_mask_rtc_irq_bit(mask); | |
319 | ||
320 | cmos_checkintr(cmos, rtc_control); | |
321 | } | |
322 | ||
7be2c7c9 DB |
323 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
324 | { | |
325 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
3804a89b | 326 | unsigned char mon, mday, hrs, min, sec, rtc_control; |
7be2c7c9 DB |
327 | |
328 | if (!is_valid_irq(cmos->irq)) | |
329 | return -EIO; | |
330 | ||
2b653e06 | 331 | mon = t->time.tm_mon + 1; |
7be2c7c9 | 332 | mday = t->time.tm_mday; |
7be2c7c9 | 333 | hrs = t->time.tm_hour; |
7be2c7c9 | 334 | min = t->time.tm_min; |
7be2c7c9 | 335 | sec = t->time.tm_sec; |
3804a89b AP |
336 | |
337 | rtc_control = CMOS_READ(RTC_CONTROL); | |
338 | if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { | |
339 | /* Writing 0xff means "don't care" or "match all". */ | |
340 | mon = (mon <= 12) ? bin2bcd(mon) : 0xff; | |
341 | mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; | |
342 | hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff; | |
343 | min = (min < 60) ? bin2bcd(min) : 0xff; | |
344 | sec = (sec < 60) ? bin2bcd(sec) : 0xff; | |
345 | } | |
7be2c7c9 DB |
346 | |
347 | spin_lock_irq(&rtc_lock); | |
348 | ||
349 | /* next rtc irq must not be from previous alarm setting */ | |
7e2a31da | 350 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
351 | |
352 | /* update alarm */ | |
353 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
354 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
355 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
356 | ||
357 | /* the system may support an "enhanced" alarm */ | |
358 | if (cmos->day_alrm) { | |
359 | CMOS_WRITE(mday, cmos->day_alrm); | |
360 | if (cmos->mon_alrm) | |
361 | CMOS_WRITE(mon, cmos->mon_alrm); | |
362 | } | |
363 | ||
35d3fdd5 DB |
364 | /* FIXME the HPET alarm glue currently ignores day_alrm |
365 | * and mon_alrm ... | |
366 | */ | |
367 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); | |
368 | ||
7e2a31da DB |
369 | if (t->enabled) |
370 | cmos_irq_enable(cmos, RTC_AIE); | |
7be2c7c9 DB |
371 | |
372 | spin_unlock_irq(&rtc_lock); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
57deb526 | 377 | static int cmos_irq_set_freq(struct device *dev, int freq) |
7be2c7c9 DB |
378 | { |
379 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
380 | int f; | |
381 | unsigned long flags; | |
382 | ||
383 | if (!is_valid_irq(cmos->irq)) | |
384 | return -ENXIO; | |
385 | ||
5d2a5037 JC |
386 | if (!is_power_of_2(freq)) |
387 | return -EINVAL; | |
7be2c7c9 DB |
388 | /* 0 = no irqs; 1 = 2^15 Hz ... 15 = 2^0 Hz */ |
389 | f = ffs(freq); | |
97144c67 DB |
390 | if (f-- > 16) |
391 | return -EINVAL; | |
392 | f = 16 - f; | |
7be2c7c9 DB |
393 | |
394 | spin_lock_irqsave(&rtc_lock, flags); | |
35d3fdd5 DB |
395 | hpet_set_periodic_freq(freq); |
396 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
397 | spin_unlock_irqrestore(&rtc_lock, flags); |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
57deb526 AZ |
402 | static int cmos_irq_set_state(struct device *dev, int enabled) |
403 | { | |
404 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
57deb526 AZ |
405 | unsigned long flags; |
406 | ||
407 | if (!is_valid_irq(cmos->irq)) | |
408 | return -ENXIO; | |
409 | ||
410 | spin_lock_irqsave(&rtc_lock, flags); | |
57deb526 | 411 | |
7e2a31da DB |
412 | if (enabled) |
413 | cmos_irq_enable(cmos, RTC_PIE); | |
414 | else | |
415 | cmos_irq_disable(cmos, RTC_PIE); | |
57deb526 AZ |
416 | |
417 | spin_unlock_irqrestore(&rtc_lock, flags); | |
418 | return 0; | |
419 | } | |
420 | ||
a8462ef6 | 421 | static int cmos_alarm_irq_enable(struct device *dev, unsigned int enabled) |
7be2c7c9 DB |
422 | { |
423 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
7be2c7c9 DB |
424 | unsigned long flags; |
425 | ||
a8462ef6 HRK |
426 | if (!is_valid_irq(cmos->irq)) |
427 | return -EINVAL; | |
7be2c7c9 DB |
428 | |
429 | spin_lock_irqsave(&rtc_lock, flags); | |
a8462ef6 HRK |
430 | |
431 | if (enabled) | |
7e2a31da | 432 | cmos_irq_enable(cmos, RTC_AIE); |
a8462ef6 HRK |
433 | else |
434 | cmos_irq_disable(cmos, RTC_AIE); | |
435 | ||
7be2c7c9 DB |
436 | spin_unlock_irqrestore(&rtc_lock, flags); |
437 | return 0; | |
438 | } | |
439 | ||
a8462ef6 HRK |
440 | static int cmos_update_irq_enable(struct device *dev, unsigned int enabled) |
441 | { | |
442 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
443 | unsigned long flags; | |
444 | ||
445 | if (!is_valid_irq(cmos->irq)) | |
446 | return -EINVAL; | |
447 | ||
448 | spin_lock_irqsave(&rtc_lock, flags); | |
449 | ||
450 | if (enabled) | |
451 | cmos_irq_enable(cmos, RTC_UIE); | |
452 | else | |
453 | cmos_irq_disable(cmos, RTC_UIE); | |
454 | ||
455 | spin_unlock_irqrestore(&rtc_lock, flags); | |
456 | return 0; | |
457 | } | |
7be2c7c9 DB |
458 | |
459 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) | |
460 | ||
461 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
462 | { | |
463 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
464 | unsigned char rtc_control, valid; | |
465 | ||
466 | spin_lock_irq(&rtc_lock); | |
467 | rtc_control = CMOS_READ(RTC_CONTROL); | |
468 | valid = CMOS_READ(RTC_VALID); | |
469 | spin_unlock_irq(&rtc_lock); | |
470 | ||
471 | /* NOTE: at least ICH6 reports battery status using a different | |
472 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
473 | */ | |
474 | return seq_printf(seq, | |
475 | "periodic_IRQ\t: %s\n" | |
476 | "update_IRQ\t: %s\n" | |
c8626a1d | 477 | "HPET_emulated\t: %s\n" |
7be2c7c9 | 478 | // "square_wave\t: %s\n" |
3804a89b | 479 | "BCD\t\t: %s\n" |
7be2c7c9 DB |
480 | "DST_enable\t: %s\n" |
481 | "periodic_freq\t: %d\n" | |
482 | "batt_status\t: %s\n", | |
483 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
484 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
c8626a1d | 485 | is_hpet_enabled() ? "yes" : "no", |
7be2c7c9 | 486 | // (rtc_control & RTC_SQWE) ? "yes" : "no", |
3804a89b | 487 | (rtc_control & RTC_DM_BINARY) ? "no" : "yes", |
7be2c7c9 DB |
488 | (rtc_control & RTC_DST_EN) ? "yes" : "no", |
489 | cmos->rtc->irq_freq, | |
490 | (valid & RTC_VRT) ? "okay" : "dead"); | |
491 | } | |
492 | ||
493 | #else | |
494 | #define cmos_procfs NULL | |
495 | #endif | |
496 | ||
497 | static const struct rtc_class_ops cmos_rtc_ops = { | |
a8462ef6 HRK |
498 | .read_time = cmos_read_time, |
499 | .set_time = cmos_set_time, | |
500 | .read_alarm = cmos_read_alarm, | |
501 | .set_alarm = cmos_set_alarm, | |
502 | .proc = cmos_procfs, | |
503 | .irq_set_freq = cmos_irq_set_freq, | |
504 | .irq_set_state = cmos_irq_set_state, | |
505 | .alarm_irq_enable = cmos_alarm_irq_enable, | |
506 | .update_irq_enable = cmos_update_irq_enable, | |
7be2c7c9 DB |
507 | }; |
508 | ||
509 | /*----------------------------------------------------------------*/ | |
510 | ||
e07e232c DB |
511 | /* |
512 | * All these chips have at least 64 bytes of address space, shared by | |
513 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
514 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
515 | */ | |
516 | ||
517 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
518 | ||
519 | static ssize_t | |
2c3c8bea CW |
520 | cmos_nvram_read(struct file *filp, struct kobject *kobj, |
521 | struct bin_attribute *attr, | |
e07e232c DB |
522 | char *buf, loff_t off, size_t count) |
523 | { | |
524 | int retval; | |
525 | ||
526 | if (unlikely(off >= attr->size)) | |
527 | return 0; | |
c8fc40cd DB |
528 | if (unlikely(off < 0)) |
529 | return -EINVAL; | |
e07e232c DB |
530 | if ((off + count) > attr->size) |
531 | count = attr->size - off; | |
532 | ||
c8fc40cd | 533 | off += NVRAM_OFFSET; |
e07e232c | 534 | spin_lock_irq(&rtc_lock); |
c8fc40cd DB |
535 | for (retval = 0; count; count--, off++, retval++) { |
536 | if (off < 128) | |
537 | *buf++ = CMOS_READ(off); | |
538 | else if (can_bank2) | |
539 | *buf++ = cmos_read_bank2(off); | |
540 | else | |
541 | break; | |
542 | } | |
e07e232c DB |
543 | spin_unlock_irq(&rtc_lock); |
544 | ||
545 | return retval; | |
546 | } | |
547 | ||
548 | static ssize_t | |
2c3c8bea CW |
549 | cmos_nvram_write(struct file *filp, struct kobject *kobj, |
550 | struct bin_attribute *attr, | |
e07e232c DB |
551 | char *buf, loff_t off, size_t count) |
552 | { | |
553 | struct cmos_rtc *cmos; | |
554 | int retval; | |
555 | ||
556 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
557 | if (unlikely(off >= attr->size)) | |
558 | return -EFBIG; | |
c8fc40cd DB |
559 | if (unlikely(off < 0)) |
560 | return -EINVAL; | |
e07e232c DB |
561 | if ((off + count) > attr->size) |
562 | count = attr->size - off; | |
563 | ||
564 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
565 | * checksum on part of the NVRAM data. That's currently ignored | |
566 | * here. If userspace is smart enough to know what fields of | |
567 | * NVRAM to update, updating checksums is also part of its job. | |
568 | */ | |
c8fc40cd | 569 | off += NVRAM_OFFSET; |
e07e232c | 570 | spin_lock_irq(&rtc_lock); |
c8fc40cd | 571 | for (retval = 0; count; count--, off++, retval++) { |
e07e232c DB |
572 | /* don't trash RTC registers */ |
573 | if (off == cmos->day_alrm | |
574 | || off == cmos->mon_alrm | |
575 | || off == cmos->century) | |
576 | buf++; | |
c8fc40cd | 577 | else if (off < 128) |
e07e232c | 578 | CMOS_WRITE(*buf++, off); |
c8fc40cd DB |
579 | else if (can_bank2) |
580 | cmos_write_bank2(*buf++, off); | |
581 | else | |
582 | break; | |
e07e232c DB |
583 | } |
584 | spin_unlock_irq(&rtc_lock); | |
585 | ||
586 | return retval; | |
587 | } | |
588 | ||
589 | static struct bin_attribute nvram = { | |
590 | .attr = { | |
591 | .name = "nvram", | |
592 | .mode = S_IRUGO | S_IWUSR, | |
e07e232c DB |
593 | }, |
594 | ||
595 | .read = cmos_nvram_read, | |
596 | .write = cmos_nvram_write, | |
597 | /* size gets set up later */ | |
598 | }; | |
599 | ||
600 | /*----------------------------------------------------------------*/ | |
601 | ||
7be2c7c9 DB |
602 | static struct cmos_rtc cmos_rtc; |
603 | ||
604 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
605 | { | |
606 | u8 irqstat; | |
8a0bdfd7 | 607 | u8 rtc_control; |
7be2c7c9 DB |
608 | |
609 | spin_lock(&rtc_lock); | |
35d3fdd5 DB |
610 | |
611 | /* When the HPET interrupt handler calls us, the interrupt | |
612 | * status is passed as arg1 instead of the irq number. But | |
613 | * always clear irq status, even when HPET is in the way. | |
614 | * | |
615 | * Note that HPET and RTC are almost certainly out of phase, | |
616 | * giving different IRQ status ... | |
9d8af78b | 617 | */ |
35d3fdd5 DB |
618 | irqstat = CMOS_READ(RTC_INTR_FLAGS); |
619 | rtc_control = CMOS_READ(RTC_CONTROL); | |
9d8af78b BW |
620 | if (is_hpet_enabled()) |
621 | irqstat = (unsigned long)irq & 0xF0; | |
35d3fdd5 | 622 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
8a0bdfd7 DB |
623 | |
624 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
625 | * Similar code may be needed in system wakeup paths, in case the | |
626 | * alarm woke the system. | |
627 | */ | |
628 | if (irqstat & RTC_AIE) { | |
629 | rtc_control &= ~RTC_AIE; | |
630 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
35d3fdd5 DB |
631 | hpet_mask_rtc_irq_bit(RTC_AIE); |
632 | ||
8a0bdfd7 DB |
633 | CMOS_READ(RTC_INTR_FLAGS); |
634 | } | |
7be2c7c9 DB |
635 | spin_unlock(&rtc_lock); |
636 | ||
bcd9b89c | 637 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
638 | rtc_update_irq(p, 1, irqstat); |
639 | return IRQ_HANDLED; | |
640 | } else | |
641 | return IRQ_NONE; | |
642 | } | |
643 | ||
41ac8df9 | 644 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
645 | #define INITSECTION |
646 | ||
647 | #else | |
7be2c7c9 DB |
648 | #define INITSECTION __init |
649 | #endif | |
650 | ||
651 | static int INITSECTION | |
652 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
653 | { | |
654 | struct cmos_rtc_board_info *info = dev->platform_data; | |
655 | int retval = 0; | |
656 | unsigned char rtc_control; | |
e07e232c | 657 | unsigned address_space; |
7be2c7c9 DB |
658 | |
659 | /* there can be only one ... */ | |
660 | if (cmos_rtc.dev) | |
661 | return -EBUSY; | |
662 | ||
663 | if (!ports) | |
664 | return -ENODEV; | |
665 | ||
05440dfc DB |
666 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
667 | * | |
668 | * REVISIT non-x86 systems may instead use memory space resources | |
669 | * (needing ioremap etc), not i/o space resources like this ... | |
670 | */ | |
671 | ports = request_region(ports->start, | |
672 | ports->end + 1 - ports->start, | |
673 | driver_name); | |
674 | if (!ports) { | |
675 | dev_dbg(dev, "i/o registers already in use\n"); | |
676 | return -EBUSY; | |
677 | } | |
678 | ||
7be2c7c9 DB |
679 | cmos_rtc.irq = rtc_irq; |
680 | cmos_rtc.iomem = ports; | |
681 | ||
e07e232c DB |
682 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
683 | * driver did, but don't reject unknown configs. Old hardware | |
c8fc40cd DB |
684 | * won't address 128 bytes. Newer chips have multiple banks, |
685 | * though they may not be listed in one I/O resource. | |
e07e232c DB |
686 | */ |
687 | #if defined(CONFIG_ATARI) | |
688 | address_space = 64; | |
95abd0df WZ |
689 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ |
690 | || defined(__sparc__) || defined(__mips__) | |
e07e232c DB |
691 | address_space = 128; |
692 | #else | |
693 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
694 | address_space = 128; | |
695 | #endif | |
c8fc40cd DB |
696 | if (can_bank2 && ports->end > (ports->start + 1)) |
697 | address_space = 256; | |
e07e232c | 698 | |
87ac84f4 DB |
699 | /* For ACPI systems extension info comes from the FADT. On others, |
700 | * board specific setup provides it as appropriate. Systems where | |
701 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
702 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
703 | * |
704 | * Note that ACPI doesn't preclude putting these registers into | |
705 | * "extended" areas of the chip, including some that we won't yet | |
706 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
707 | */ |
708 | if (info) { | |
e07e232c DB |
709 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
710 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
711 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
712 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
713 | if (info->rtc_century && info->rtc_century < 128) | |
714 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
715 | |
716 | if (info->wake_on && info->wake_off) { | |
717 | cmos_rtc.wake_on = info->wake_on; | |
718 | cmos_rtc.wake_off = info->wake_off; | |
719 | } | |
7be2c7c9 DB |
720 | } |
721 | ||
6ba8bcd4 DC |
722 | cmos_rtc.dev = dev; |
723 | dev_set_drvdata(dev, &cmos_rtc); | |
724 | ||
7be2c7c9 DB |
725 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, |
726 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
727 | if (IS_ERR(cmos_rtc.rtc)) { |
728 | retval = PTR_ERR(cmos_rtc.rtc); | |
729 | goto cleanup0; | |
730 | } | |
7be2c7c9 | 731 | |
d4afc76c | 732 | rename_region(ports, dev_name(&cmos_rtc.rtc->dev)); |
7be2c7c9 DB |
733 | |
734 | spin_lock_irq(&rtc_lock); | |
735 | ||
736 | /* force periodic irq to CMOS reset default of 1024Hz; | |
737 | * | |
738 | * REVISIT it's been reported that at least one x86_64 ALI mobo | |
739 | * doesn't use 32KHz here ... for portability we might need to | |
740 | * do something about other clock frequencies. | |
741 | */ | |
7be2c7c9 | 742 | cmos_rtc.rtc->irq_freq = 1024; |
35d3fdd5 DB |
743 | hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq); |
744 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
7be2c7c9 | 745 | |
7e2a31da DB |
746 | /* disable irqs */ |
747 | cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE); | |
35d3fdd5 | 748 | |
7e2a31da | 749 | rtc_control = CMOS_READ(RTC_CONTROL); |
7be2c7c9 DB |
750 | |
751 | spin_unlock_irq(&rtc_lock); | |
752 | ||
3804a89b | 753 | /* FIXME: |
7be2c7c9 DB |
754 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. |
755 | */ | |
3804a89b AP |
756 | if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { |
757 | dev_warn(dev, "only 24-hr supported\n"); | |
7be2c7c9 DB |
758 | retval = -ENXIO; |
759 | goto cleanup1; | |
760 | } | |
761 | ||
9d8af78b BW |
762 | if (is_valid_irq(rtc_irq)) { |
763 | irq_handler_t rtc_cmos_int_handler; | |
764 | ||
765 | if (is_hpet_enabled()) { | |
766 | int err; | |
767 | ||
768 | rtc_cmos_int_handler = hpet_rtc_interrupt; | |
769 | err = hpet_register_irq_handler(cmos_interrupt); | |
770 | if (err != 0) { | |
771 | printk(KERN_WARNING "hpet_register_irq_handler " | |
772 | " failed in rtc_init()."); | |
773 | goto cleanup1; | |
774 | } | |
775 | } else | |
776 | rtc_cmos_int_handler = cmos_interrupt; | |
777 | ||
778 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
d4afc76c | 779 | IRQF_DISABLED, dev_name(&cmos_rtc.rtc->dev), |
ab6a2d70 | 780 | cmos_rtc.rtc); |
9d8af78b BW |
781 | if (retval < 0) { |
782 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
783 | goto cleanup1; | |
784 | } | |
7be2c7c9 | 785 | } |
9d8af78b | 786 | hpet_rtc_timer_init(); |
7be2c7c9 | 787 | |
e07e232c DB |
788 | /* export at least the first block of NVRAM */ |
789 | nvram.size = address_space - NVRAM_OFFSET; | |
790 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
791 | if (retval < 0) { | |
792 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
793 | goto cleanup2; | |
794 | } | |
7be2c7c9 | 795 | |
6d029b64 KH |
796 | pr_info("%s: %s%s, %zd bytes nvram%s\n", |
797 | dev_name(&cmos_rtc.rtc->dev), | |
798 | !is_valid_irq(rtc_irq) ? "no alarms" : | |
799 | cmos_rtc.mon_alrm ? "alarms up to one year" : | |
800 | cmos_rtc.day_alrm ? "alarms up to one month" : | |
801 | "alarms up to one day", | |
802 | cmos_rtc.century ? ", y3k" : "", | |
803 | nvram.size, | |
804 | is_hpet_enabled() ? ", hpet irqs" : ""); | |
7be2c7c9 DB |
805 | |
806 | return 0; | |
807 | ||
e07e232c DB |
808 | cleanup2: |
809 | if (is_valid_irq(rtc_irq)) | |
810 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 811 | cleanup1: |
05440dfc | 812 | cmos_rtc.dev = NULL; |
7be2c7c9 | 813 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc DB |
814 | cleanup0: |
815 | release_region(ports->start, ports->end + 1 - ports->start); | |
7be2c7c9 DB |
816 | return retval; |
817 | } | |
818 | ||
819 | static void cmos_do_shutdown(void) | |
820 | { | |
7be2c7c9 | 821 | spin_lock_irq(&rtc_lock); |
7e2a31da | 822 | cmos_irq_disable(&cmos_rtc, RTC_IRQMASK); |
7be2c7c9 DB |
823 | spin_unlock_irq(&rtc_lock); |
824 | } | |
825 | ||
826 | static void __exit cmos_do_remove(struct device *dev) | |
827 | { | |
828 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 829 | struct resource *ports; |
7be2c7c9 DB |
830 | |
831 | cmos_do_shutdown(); | |
832 | ||
e07e232c DB |
833 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
834 | ||
9d8af78b | 835 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 836 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
837 | hpet_unregister_irq_handler(cmos_interrupt); |
838 | } | |
7be2c7c9 | 839 | |
05440dfc DB |
840 | rtc_device_unregister(cmos->rtc); |
841 | cmos->rtc = NULL; | |
7be2c7c9 | 842 | |
05440dfc DB |
843 | ports = cmos->iomem; |
844 | release_region(ports->start, ports->end + 1 - ports->start); | |
845 | cmos->iomem = NULL; | |
846 | ||
847 | cmos->dev = NULL; | |
7be2c7c9 DB |
848 | dev_set_drvdata(dev, NULL); |
849 | } | |
850 | ||
851 | #ifdef CONFIG_PM | |
852 | ||
853 | static int cmos_suspend(struct device *dev, pm_message_t mesg) | |
854 | { | |
855 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
bcd9b89c | 856 | unsigned char tmp; |
7be2c7c9 DB |
857 | |
858 | /* only the alarm might be a wakeup event source */ | |
859 | spin_lock_irq(&rtc_lock); | |
860 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
861 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
35d3fdd5 | 862 | unsigned char mask; |
bcd9b89c | 863 | |
74c4633d | 864 | if (device_may_wakeup(dev)) |
35d3fdd5 | 865 | mask = RTC_IRQMASK & ~RTC_AIE; |
7be2c7c9 | 866 | else |
35d3fdd5 DB |
867 | mask = RTC_IRQMASK; |
868 | tmp &= ~mask; | |
7be2c7c9 | 869 | CMOS_WRITE(tmp, RTC_CONTROL); |
35d3fdd5 | 870 | |
d1b2efa8 ML |
871 | /* shut down hpet emulation - we don't need it for alarm */ |
872 | hpet_mask_rtc_irq_bit(RTC_PIE|RTC_AIE|RTC_UIE); | |
7e2a31da | 873 | cmos_checkintr(cmos, tmp); |
bcd9b89c | 874 | } |
7be2c7c9 DB |
875 | spin_unlock_irq(&rtc_lock); |
876 | ||
87ac84f4 DB |
877 | if (tmp & RTC_AIE) { |
878 | cmos->enabled_wake = 1; | |
879 | if (cmos->wake_on) | |
880 | cmos->wake_on(dev); | |
881 | else | |
882 | enable_irq_wake(cmos->irq); | |
883 | } | |
7be2c7c9 DB |
884 | |
885 | pr_debug("%s: suspend%s, ctrl %02x\n", | |
d4afc76c | 886 | dev_name(&cmos_rtc.rtc->dev), |
7be2c7c9 DB |
887 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
888 | tmp); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
74c4633d RW |
893 | /* We want RTC alarms to wake us from e.g. ACPI G2/S5 "soft off", even |
894 | * after a detour through G3 "mechanical off", although the ACPI spec | |
895 | * says wakeup should only work from G1/S4 "hibernate". To most users, | |
896 | * distinctions between S4 and S5 are pointless. So when the hardware | |
897 | * allows, don't draw that distinction. | |
898 | */ | |
899 | static inline int cmos_poweroff(struct device *dev) | |
900 | { | |
901 | return cmos_suspend(dev, PMSG_HIBERNATE); | |
902 | } | |
903 | ||
7be2c7c9 DB |
904 | static int cmos_resume(struct device *dev) |
905 | { | |
906 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
907 | unsigned char tmp = cmos->suspend_ctrl; | |
908 | ||
7be2c7c9 | 909 | /* re-enable any irqs previously active */ |
35d3fdd5 DB |
910 | if (tmp & RTC_IRQMASK) { |
911 | unsigned char mask; | |
7be2c7c9 | 912 | |
87ac84f4 DB |
913 | if (cmos->enabled_wake) { |
914 | if (cmos->wake_off) | |
915 | cmos->wake_off(dev); | |
916 | else | |
917 | disable_irq_wake(cmos->irq); | |
918 | cmos->enabled_wake = 0; | |
919 | } | |
7be2c7c9 DB |
920 | |
921 | spin_lock_irq(&rtc_lock); | |
35d3fdd5 DB |
922 | do { |
923 | CMOS_WRITE(tmp, RTC_CONTROL); | |
924 | hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK); | |
925 | ||
926 | mask = CMOS_READ(RTC_INTR_FLAGS); | |
927 | mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; | |
7e2a31da | 928 | if (!is_hpet_enabled() || !is_intr(mask)) |
35d3fdd5 DB |
929 | break; |
930 | ||
931 | /* force one-shot behavior if HPET blocked | |
932 | * the wake alarm's irq | |
933 | */ | |
934 | rtc_update_irq(cmos->rtc, 1, mask); | |
935 | tmp &= ~RTC_AIE; | |
936 | hpet_mask_rtc_irq_bit(RTC_AIE); | |
937 | } while (mask & RTC_AIE); | |
bcd9b89c | 938 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 DB |
939 | } |
940 | ||
941 | pr_debug("%s: resume, ctrl %02x\n", | |
d4afc76c | 942 | dev_name(&cmos_rtc.rtc->dev), |
35d3fdd5 | 943 | tmp); |
7be2c7c9 DB |
944 | |
945 | return 0; | |
946 | } | |
947 | ||
948 | #else | |
949 | #define cmos_suspend NULL | |
950 | #define cmos_resume NULL | |
74c4633d RW |
951 | |
952 | static inline int cmos_poweroff(struct device *dev) | |
953 | { | |
954 | return -ENOSYS; | |
955 | } | |
956 | ||
7be2c7c9 DB |
957 | #endif |
958 | ||
959 | /*----------------------------------------------------------------*/ | |
960 | ||
e07e232c DB |
961 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
962 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
963 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
964 | * | |
965 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
966 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
967 | */ |
968 | ||
a474aaed BH |
969 | #ifdef CONFIG_ACPI |
970 | ||
971 | #include <linux/acpi.h> | |
972 | ||
a474aaed BH |
973 | static u32 rtc_handler(void *context) |
974 | { | |
975 | acpi_clear_event(ACPI_EVENT_RTC); | |
976 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
977 | return ACPI_INTERRUPT_HANDLED; | |
978 | } | |
979 | ||
980 | static inline void rtc_wake_setup(void) | |
981 | { | |
982 | acpi_install_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler, NULL); | |
983 | /* | |
984 | * After the RTC handler is installed, the Fixed_RTC event should | |
985 | * be disabled. Only when the RTC alarm is set will it be enabled. | |
986 | */ | |
987 | acpi_clear_event(ACPI_EVENT_RTC); | |
988 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
989 | } | |
990 | ||
991 | static void rtc_wake_on(struct device *dev) | |
992 | { | |
993 | acpi_clear_event(ACPI_EVENT_RTC); | |
994 | acpi_enable_event(ACPI_EVENT_RTC, 0); | |
995 | } | |
996 | ||
997 | static void rtc_wake_off(struct device *dev) | |
998 | { | |
999 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
1000 | } | |
a474aaed BH |
1001 | |
1002 | /* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find | |
1003 | * its device node and pass extra config data. This helps its driver use | |
1004 | * capabilities that the now-obsolete mc146818 didn't have, and informs it | |
1005 | * that this board's RTC is wakeup-capable (per ACPI spec). | |
1006 | */ | |
1007 | static struct cmos_rtc_board_info acpi_rtc_info; | |
1008 | ||
1009 | static void __devinit | |
1010 | cmos_wake_setup(struct device *dev) | |
1011 | { | |
1012 | if (acpi_disabled) | |
1013 | return; | |
1014 | ||
1015 | rtc_wake_setup(); | |
1016 | acpi_rtc_info.wake_on = rtc_wake_on; | |
1017 | acpi_rtc_info.wake_off = rtc_wake_off; | |
1018 | ||
1019 | /* workaround bug in some ACPI tables */ | |
1020 | if (acpi_gbl_FADT.month_alarm && !acpi_gbl_FADT.day_alarm) { | |
1021 | dev_dbg(dev, "bogus FADT month_alarm (%d)\n", | |
1022 | acpi_gbl_FADT.month_alarm); | |
1023 | acpi_gbl_FADT.month_alarm = 0; | |
1024 | } | |
1025 | ||
1026 | acpi_rtc_info.rtc_day_alarm = acpi_gbl_FADT.day_alarm; | |
1027 | acpi_rtc_info.rtc_mon_alarm = acpi_gbl_FADT.month_alarm; | |
1028 | acpi_rtc_info.rtc_century = acpi_gbl_FADT.century; | |
1029 | ||
1030 | /* NOTE: S4_RTC_WAKE is NOT currently useful to Linux */ | |
1031 | if (acpi_gbl_FADT.flags & ACPI_FADT_S4_RTC_WAKE) | |
1032 | dev_info(dev, "RTC can wake from S4\n"); | |
1033 | ||
1034 | dev->platform_data = &acpi_rtc_info; | |
1035 | ||
1036 | /* RTC always wakes from S1/S2/S3, and often S4/STD */ | |
1037 | device_init_wakeup(dev, 1); | |
1038 | } | |
1039 | ||
1040 | #else | |
1041 | ||
1042 | static void __devinit | |
1043 | cmos_wake_setup(struct device *dev) | |
1044 | { | |
1045 | } | |
1046 | ||
1047 | #endif | |
1048 | ||
41ac8df9 | 1049 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
1050 | |
1051 | #include <linux/pnp.h> | |
1052 | ||
1053 | static int __devinit | |
1054 | cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) | |
1055 | { | |
a474aaed BH |
1056 | cmos_wake_setup(&pnp->dev); |
1057 | ||
6cd8fa87 MG |
1058 | if (pnp_port_start(pnp,0) == 0x70 && !pnp_irq_valid(pnp,0)) |
1059 | /* Some machines contain a PNP entry for the RTC, but | |
1060 | * don't define the IRQ. It should always be safe to | |
1061 | * hardcode it in these cases | |
1062 | */ | |
8766ad0c BH |
1063 | return cmos_do_probe(&pnp->dev, |
1064 | pnp_get_resource(pnp, IORESOURCE_IO, 0), 8); | |
6cd8fa87 MG |
1065 | else |
1066 | return cmos_do_probe(&pnp->dev, | |
8766ad0c BH |
1067 | pnp_get_resource(pnp, IORESOURCE_IO, 0), |
1068 | pnp_irq(pnp, 0)); | |
7be2c7c9 DB |
1069 | } |
1070 | ||
1071 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
1072 | { | |
1073 | cmos_do_remove(&pnp->dev); | |
1074 | } | |
1075 | ||
1076 | #ifdef CONFIG_PM | |
1077 | ||
1078 | static int cmos_pnp_suspend(struct pnp_dev *pnp, pm_message_t mesg) | |
1079 | { | |
1080 | return cmos_suspend(&pnp->dev, mesg); | |
1081 | } | |
1082 | ||
1083 | static int cmos_pnp_resume(struct pnp_dev *pnp) | |
1084 | { | |
1085 | return cmos_resume(&pnp->dev); | |
1086 | } | |
1087 | ||
1088 | #else | |
1089 | #define cmos_pnp_suspend NULL | |
1090 | #define cmos_pnp_resume NULL | |
1091 | #endif | |
1092 | ||
004731b2 | 1093 | static void cmos_pnp_shutdown(struct pnp_dev *pnp) |
74c4633d | 1094 | { |
004731b2 | 1095 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(&pnp->dev)) |
74c4633d RW |
1096 | return; |
1097 | ||
1098 | cmos_do_shutdown(); | |
1099 | } | |
7be2c7c9 DB |
1100 | |
1101 | static const struct pnp_device_id rtc_ids[] = { | |
1102 | { .id = "PNP0b00", }, | |
1103 | { .id = "PNP0b01", }, | |
1104 | { .id = "PNP0b02", }, | |
1105 | { }, | |
1106 | }; | |
1107 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
1108 | ||
1109 | static struct pnp_driver cmos_pnp_driver = { | |
1110 | .name = (char *) driver_name, | |
1111 | .id_table = rtc_ids, | |
1112 | .probe = cmos_pnp_probe, | |
1113 | .remove = __exit_p(cmos_pnp_remove), | |
004731b2 | 1114 | .shutdown = cmos_pnp_shutdown, |
7be2c7c9 DB |
1115 | |
1116 | /* flag ensures resume() gets called, and stops syslog spam */ | |
1117 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1118 | .suspend = cmos_pnp_suspend, | |
1119 | .resume = cmos_pnp_resume, | |
1120 | }; | |
1121 | ||
1da2e3d6 | 1122 | #endif /* CONFIG_PNP */ |
7be2c7c9 DB |
1123 | |
1124 | /*----------------------------------------------------------------*/ | |
1125 | ||
41ac8df9 | 1126 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 1127 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
1128 | */ |
1129 | ||
1130 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
1131 | { | |
a474aaed | 1132 | cmos_wake_setup(&pdev->dev); |
7be2c7c9 DB |
1133 | return cmos_do_probe(&pdev->dev, |
1134 | platform_get_resource(pdev, IORESOURCE_IO, 0), | |
1135 | platform_get_irq(pdev, 0)); | |
1136 | } | |
1137 | ||
1138 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
1139 | { | |
1140 | cmos_do_remove(&pdev->dev); | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
1145 | { | |
74c4633d RW |
1146 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(&pdev->dev)) |
1147 | return; | |
1148 | ||
7be2c7c9 DB |
1149 | cmos_do_shutdown(); |
1150 | } | |
1151 | ||
ad28a07b KS |
1152 | /* work with hotplug and coldplug */ |
1153 | MODULE_ALIAS("platform:rtc_cmos"); | |
1154 | ||
7be2c7c9 DB |
1155 | static struct platform_driver cmos_platform_driver = { |
1156 | .remove = __exit_p(cmos_platform_remove), | |
1157 | .shutdown = cmos_platform_shutdown, | |
1158 | .driver = { | |
1159 | .name = (char *) driver_name, | |
1160 | .suspend = cmos_suspend, | |
1161 | .resume = cmos_resume, | |
1162 | } | |
1163 | }; | |
1164 | ||
65909814 TLSC |
1165 | #ifdef CONFIG_PNP |
1166 | static bool pnp_driver_registered; | |
1167 | #endif | |
1168 | static bool platform_driver_registered; | |
1169 | ||
7be2c7c9 DB |
1170 | static int __init cmos_init(void) |
1171 | { | |
72f22b1e BH |
1172 | int retval = 0; |
1173 | ||
1da2e3d6 | 1174 | #ifdef CONFIG_PNP |
65909814 TLSC |
1175 | retval = pnp_register_driver(&cmos_pnp_driver); |
1176 | if (retval == 0) | |
1177 | pnp_driver_registered = true; | |
72f22b1e BH |
1178 | #endif |
1179 | ||
65909814 | 1180 | if (!cmos_rtc.dev) { |
72f22b1e BH |
1181 | retval = platform_driver_probe(&cmos_platform_driver, |
1182 | cmos_platform_probe); | |
65909814 TLSC |
1183 | if (retval == 0) |
1184 | platform_driver_registered = true; | |
1185 | } | |
72f22b1e BH |
1186 | |
1187 | if (retval == 0) | |
1188 | return 0; | |
1189 | ||
1190 | #ifdef CONFIG_PNP | |
65909814 TLSC |
1191 | if (pnp_driver_registered) |
1192 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e BH |
1193 | #endif |
1194 | return retval; | |
7be2c7c9 DB |
1195 | } |
1196 | module_init(cmos_init); | |
1197 | ||
1198 | static void __exit cmos_exit(void) | |
1199 | { | |
1da2e3d6 | 1200 | #ifdef CONFIG_PNP |
65909814 TLSC |
1201 | if (pnp_driver_registered) |
1202 | pnp_unregister_driver(&cmos_pnp_driver); | |
72f22b1e | 1203 | #endif |
65909814 TLSC |
1204 | if (platform_driver_registered) |
1205 | platform_driver_unregister(&cmos_platform_driver); | |
7be2c7c9 DB |
1206 | } |
1207 | module_exit(cmos_exit); | |
1208 | ||
1209 | ||
7be2c7c9 DB |
1210 | MODULE_AUTHOR("David Brownell"); |
1211 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
1212 | MODULE_LICENSE("GPL"); |