rtc: add devm_ prefix to rtc_nvmem_register()
[linux-2.6-block.git] / drivers / rtc / rtc-cmos.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
7be2c7c9
DB
2/*
3 * RTC class driver for "CMOS RTC": PCs, ACPI, etc
4 *
5 * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c)
6 * Copyright (C) 2006 David Brownell (convert to new framework)
7be2c7c9
DB
7 */
8
9/*
10 * The original "cmos clock" chip was an MC146818 chip, now obsolete.
11 * That defined the register interface now provided by all PCs, some
12 * non-PC systems, and incorporated into ACPI. Modern PC chipsets
13 * integrate an MC146818 clone in their southbridge, and boards use
14 * that instead of discrete clones like the DS12887 or M48T86. There
15 * are also clones that connect using the LPC bus.
16 *
17 * That register API is also used directly by various other drivers
18 * (notably for integrated NVRAM), infrastructure (x86 has code to
19 * bypass the RTC framework, directly reading the RTC during boot
20 * and updating minutes/seconds for systems using NTP synch) and
21 * utilities (like userspace 'hwclock', if no /dev node exists).
22 *
23 * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with
24 * interrupts disabled, holding the global rtc_lock, to exclude those
25 * other drivers and utilities on correctly configured systems.
26 */
a737e835
JP
27
28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
7be2c7c9
DB
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/interrupt.h>
34#include <linux/spinlock.h>
35#include <linux/platform_device.h>
5d2a5037 36#include <linux/log2.h>
2fb08e6c 37#include <linux/pm.h>
3bcbaf6e
SAS
38#include <linux/of.h>
39#include <linux/of_platform.h>
a1e23a42
HG
40#ifdef CONFIG_X86
41#include <asm/i8259.h>
36d91a4d
ZR
42#include <asm/processor.h>
43#include <linux/dmi.h>
a1e23a42 44#endif
7be2c7c9
DB
45
46/* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */
5ab788d7 47#include <linux/mc146818rtc.h>
7be2c7c9 48
bc51098c 49#ifdef CONFIG_ACPI
311ee9c1
ZR
50/*
51 * Use ACPI SCI to replace HPET interrupt for RTC Alarm event
52 *
53 * If cleared, ACPI SCI is only used to wake up the system from suspend
54 *
55 * If set, ACPI SCI is used to handle UIE/AIE and system wakeup
56 */
57
58static bool use_acpi_alarm;
59module_param(use_acpi_alarm, bool, 0444);
60
bc51098c
MR
61static inline int cmos_use_acpi_alarm(void)
62{
63 return use_acpi_alarm;
64}
65#else /* !CONFIG_ACPI */
66
67static inline int cmos_use_acpi_alarm(void)
68{
69 return 0;
70}
71#endif
72
7be2c7c9
DB
73struct cmos_rtc {
74 struct rtc_device *rtc;
75 struct device *dev;
76 int irq;
77 struct resource *iomem;
88b8d33b 78 time64_t alarm_expires;
7be2c7c9 79
87ac84f4
DB
80 void (*wake_on)(struct device *);
81 void (*wake_off)(struct device *);
82
83 u8 enabled_wake;
7be2c7c9
DB
84 u8 suspend_ctrl;
85
86 /* newer hardware extends the original register set */
87 u8 day_alrm;
88 u8 mon_alrm;
89 u8 century;
68669d55
GM
90
91 struct rtc_wkalrm saved_wkalrm;
7be2c7c9
DB
92};
93
94/* both platform and pnp busses use negative numbers for invalid irqs */
2fac6674 95#define is_valid_irq(n) ((n) > 0)
7be2c7c9
DB
96
97static const char driver_name[] = "rtc_cmos";
98
bcd9b89c
DB
99/* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear;
100 * always mask it against the irq enable bits in RTC_CONTROL. Bit values
101 * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both.
102 */
103#define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF)
104
105static inline int is_intr(u8 rtc_intr)
106{
107 if (!(rtc_intr & RTC_IRQF))
108 return 0;
109 return rtc_intr & RTC_IRQMASK;
110}
111
7be2c7c9
DB
112/*----------------------------------------------------------------*/
113
35d3fdd5
DB
114/* Much modern x86 hardware has HPETs (10+ MHz timers) which, because
115 * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly
116 * used in a broken "legacy replacement" mode. The breakage includes
117 * HPET #1 hijacking the IRQ for this RTC, and being unavailable for
118 * other (better) use.
119 *
120 * When that broken mode is in use, platform glue provides a partial
121 * emulation of hardware RTC IRQ facilities using HPET #1. We don't
122 * want to use HPET for anything except those IRQs though...
123 */
124#ifdef CONFIG_HPET_EMULATE_RTC
125#include <asm/hpet.h>
126#else
127
128static inline int is_hpet_enabled(void)
129{
130 return 0;
131}
132
133static inline int hpet_mask_rtc_irq_bit(unsigned long mask)
134{
135 return 0;
136}
137
138static inline int hpet_set_rtc_irq_bit(unsigned long mask)
139{
140 return 0;
141}
142
143static inline int
144hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
145{
146 return 0;
147}
148
149static inline int hpet_set_periodic_freq(unsigned long freq)
150{
151 return 0;
152}
153
154static inline int hpet_rtc_dropped_irq(void)
155{
156 return 0;
157}
158
159static inline int hpet_rtc_timer_init(void)
160{
161 return 0;
162}
163
164extern irq_handler_t hpet_rtc_interrupt;
165
166static inline int hpet_register_irq_handler(irq_handler_t handler)
167{
168 return 0;
169}
170
171static inline int hpet_unregister_irq_handler(irq_handler_t handler)
172{
173 return 0;
174}
175
176#endif
177
311ee9c1 178/* Don't use HPET for RTC Alarm event if ACPI Fixed event is used */
d197a253 179static inline int use_hpet_alarm(void)
311ee9c1 180{
bc51098c 181 return is_hpet_enabled() && !cmos_use_acpi_alarm();
311ee9c1
ZR
182}
183
35d3fdd5
DB
184/*----------------------------------------------------------------*/
185
c8fc40cd
DB
186#ifdef RTC_PORT
187
188/* Most newer x86 systems have two register banks, the first used
189 * for RTC and NVRAM and the second only for NVRAM. Caller must
190 * own rtc_lock ... and we won't worry about access during NMI.
191 */
192#define can_bank2 true
193
194static inline unsigned char cmos_read_bank2(unsigned char addr)
195{
196 outb(addr, RTC_PORT(2));
197 return inb(RTC_PORT(3));
198}
199
200static inline void cmos_write_bank2(unsigned char val, unsigned char addr)
201{
202 outb(addr, RTC_PORT(2));
b43c1ea4 203 outb(val, RTC_PORT(3));
c8fc40cd
DB
204}
205
206#else
207
208#define can_bank2 false
209
210static inline unsigned char cmos_read_bank2(unsigned char addr)
211{
212 return 0;
213}
214
215static inline void cmos_write_bank2(unsigned char val, unsigned char addr)
216{
217}
218
219#endif
220
221/*----------------------------------------------------------------*/
222
7be2c7c9
DB
223static int cmos_read_time(struct device *dev, struct rtc_time *t)
224{
ba58d102
CY
225 /*
226 * If pm_trace abused the RTC for storage, set the timespec to 0,
227 * which tells the caller that this RTC value is unusable.
228 */
229 if (!pm_trace_rtc_valid())
230 return -EIO;
231
7be2c7c9 232 /* REVISIT: if the clock has a "century" register, use
5ab788d7 233 * that instead of the heuristic in mc146818_get_time().
7be2c7c9
DB
234 * That'll make Y3K compatility (year > 2070) easy!
235 */
5ab788d7 236 mc146818_get_time(t);
7be2c7c9
DB
237 return 0;
238}
239
240static int cmos_set_time(struct device *dev, struct rtc_time *t)
241{
242 /* REVISIT: set the "century" register if available
243 *
244 * NOTE: this ignores the issue whereby updating the seconds
245 * takes effect exactly 500ms after we write the register.
246 * (Also queueing and other delays before we get this far.)
247 */
5ab788d7 248 return mc146818_set_time(t);
7be2c7c9
DB
249}
250
251static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t)
252{
253 struct cmos_rtc *cmos = dev_get_drvdata(dev);
254 unsigned char rtc_control;
255
fbb974ba 256 /* This not only a rtc_op, but also called directly */
7be2c7c9
DB
257 if (!is_valid_irq(cmos->irq))
258 return -EIO;
259
260 /* Basic alarms only support hour, minute, and seconds fields.
261 * Some also support day and month, for alarms up to a year in
262 * the future.
263 */
7be2c7c9
DB
264
265 spin_lock_irq(&rtc_lock);
266 t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM);
267 t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM);
268 t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM);
269
270 if (cmos->day_alrm) {
615bb29c
ML
271 /* ignore upper bits on readback per ACPI spec */
272 t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f;
7be2c7c9
DB
273 if (!t->time.tm_mday)
274 t->time.tm_mday = -1;
275
276 if (cmos->mon_alrm) {
277 t->time.tm_mon = CMOS_READ(cmos->mon_alrm);
278 if (!t->time.tm_mon)
279 t->time.tm_mon = -1;
280 }
281 }
282
283 rtc_control = CMOS_READ(RTC_CONTROL);
284 spin_unlock_irq(&rtc_lock);
285
3804a89b
AP
286 if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
287 if (((unsigned)t->time.tm_sec) < 0x60)
288 t->time.tm_sec = bcd2bin(t->time.tm_sec);
7be2c7c9 289 else
3804a89b
AP
290 t->time.tm_sec = -1;
291 if (((unsigned)t->time.tm_min) < 0x60)
292 t->time.tm_min = bcd2bin(t->time.tm_min);
293 else
294 t->time.tm_min = -1;
295 if (((unsigned)t->time.tm_hour) < 0x24)
296 t->time.tm_hour = bcd2bin(t->time.tm_hour);
297 else
298 t->time.tm_hour = -1;
299
300 if (cmos->day_alrm) {
301 if (((unsigned)t->time.tm_mday) <= 0x31)
302 t->time.tm_mday = bcd2bin(t->time.tm_mday);
7be2c7c9 303 else
3804a89b
AP
304 t->time.tm_mday = -1;
305
306 if (cmos->mon_alrm) {
307 if (((unsigned)t->time.tm_mon) <= 0x12)
308 t->time.tm_mon = bcd2bin(t->time.tm_mon)-1;
309 else
310 t->time.tm_mon = -1;
311 }
7be2c7c9
DB
312 }
313 }
7be2c7c9
DB
314
315 t->enabled = !!(rtc_control & RTC_AIE);
316 t->pending = 0;
317
318 return 0;
319}
320
7e2a31da
DB
321static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control)
322{
323 unsigned char rtc_intr;
324
325 /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS;
326 * allegedly some older rtcs need that to handle irqs properly
327 */
328 rtc_intr = CMOS_READ(RTC_INTR_FLAGS);
329
311ee9c1 330 if (use_hpet_alarm())
7e2a31da
DB
331 return;
332
333 rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF;
334 if (is_intr(rtc_intr))
335 rtc_update_irq(cmos->rtc, 1, rtc_intr);
336}
337
338static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask)
339{
340 unsigned char rtc_control;
341
342 /* flush any pending IRQ status, notably for update irqs,
343 * before we enable new IRQs
344 */
345 rtc_control = CMOS_READ(RTC_CONTROL);
346 cmos_checkintr(cmos, rtc_control);
347
348 rtc_control |= mask;
349 CMOS_WRITE(rtc_control, RTC_CONTROL);
311ee9c1
ZR
350 if (use_hpet_alarm())
351 hpet_set_rtc_irq_bit(mask);
352
bc51098c 353 if ((mask & RTC_AIE) && cmos_use_acpi_alarm()) {
311ee9c1
ZR
354 if (cmos->wake_on)
355 cmos->wake_on(cmos->dev);
356 }
7e2a31da
DB
357
358 cmos_checkintr(cmos, rtc_control);
359}
360
361static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask)
362{
363 unsigned char rtc_control;
364
365 rtc_control = CMOS_READ(RTC_CONTROL);
366 rtc_control &= ~mask;
367 CMOS_WRITE(rtc_control, RTC_CONTROL);
311ee9c1
ZR
368 if (use_hpet_alarm())
369 hpet_mask_rtc_irq_bit(mask);
370
bc51098c 371 if ((mask & RTC_AIE) && cmos_use_acpi_alarm()) {
311ee9c1
ZR
372 if (cmos->wake_off)
373 cmos->wake_off(cmos->dev);
374 }
7e2a31da
DB
375
376 cmos_checkintr(cmos, rtc_control);
377}
378
6a6af3d0
GM
379static int cmos_validate_alarm(struct device *dev, struct rtc_wkalrm *t)
380{
381 struct cmos_rtc *cmos = dev_get_drvdata(dev);
382 struct rtc_time now;
383
384 cmos_read_time(dev, &now);
385
386 if (!cmos->day_alrm) {
387 time64_t t_max_date;
388 time64_t t_alrm;
389
390 t_max_date = rtc_tm_to_time64(&now);
391 t_max_date += 24 * 60 * 60 - 1;
392 t_alrm = rtc_tm_to_time64(&t->time);
393 if (t_alrm > t_max_date) {
394 dev_err(dev,
395 "Alarms can be up to one day in the future\n");
396 return -EINVAL;
397 }
398 } else if (!cmos->mon_alrm) {
399 struct rtc_time max_date = now;
400 time64_t t_max_date;
401 time64_t t_alrm;
402 int max_mday;
403
404 if (max_date.tm_mon == 11) {
405 max_date.tm_mon = 0;
406 max_date.tm_year += 1;
407 } else {
408 max_date.tm_mon += 1;
409 }
410 max_mday = rtc_month_days(max_date.tm_mon, max_date.tm_year);
411 if (max_date.tm_mday > max_mday)
412 max_date.tm_mday = max_mday;
413
414 t_max_date = rtc_tm_to_time64(&max_date);
415 t_max_date -= 1;
416 t_alrm = rtc_tm_to_time64(&t->time);
417 if (t_alrm > t_max_date) {
418 dev_err(dev,
419 "Alarms can be up to one month in the future\n");
420 return -EINVAL;
421 }
422 } else {
423 struct rtc_time max_date = now;
424 time64_t t_max_date;
425 time64_t t_alrm;
426 int max_mday;
427
428 max_date.tm_year += 1;
429 max_mday = rtc_month_days(max_date.tm_mon, max_date.tm_year);
430 if (max_date.tm_mday > max_mday)
431 max_date.tm_mday = max_mday;
432
433 t_max_date = rtc_tm_to_time64(&max_date);
434 t_max_date -= 1;
435 t_alrm = rtc_tm_to_time64(&t->time);
436 if (t_alrm > t_max_date) {
437 dev_err(dev,
438 "Alarms can be up to one year in the future\n");
439 return -EINVAL;
440 }
441 }
442
443 return 0;
444}
445
7be2c7c9
DB
446static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t)
447{
448 struct cmos_rtc *cmos = dev_get_drvdata(dev);
5e8599d2 449 unsigned char mon, mday, hrs, min, sec, rtc_control;
6a6af3d0 450 int ret;
7be2c7c9 451
fbb974ba 452 /* This not only a rtc_op, but also called directly */
7be2c7c9
DB
453 if (!is_valid_irq(cmos->irq))
454 return -EIO;
455
6a6af3d0
GM
456 ret = cmos_validate_alarm(dev, t);
457 if (ret < 0)
458 return ret;
459
2b653e06 460 mon = t->time.tm_mon + 1;
7be2c7c9 461 mday = t->time.tm_mday;
7be2c7c9 462 hrs = t->time.tm_hour;
7be2c7c9 463 min = t->time.tm_min;
7be2c7c9 464 sec = t->time.tm_sec;
3804a89b
AP
465
466 rtc_control = CMOS_READ(RTC_CONTROL);
467 if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
468 /* Writing 0xff means "don't care" or "match all". */
469 mon = (mon <= 12) ? bin2bcd(mon) : 0xff;
470 mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
471 hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff;
472 min = (min < 60) ? bin2bcd(min) : 0xff;
473 sec = (sec < 60) ? bin2bcd(sec) : 0xff;
474 }
7be2c7c9
DB
475
476 spin_lock_irq(&rtc_lock);
477
478 /* next rtc irq must not be from previous alarm setting */
7e2a31da 479 cmos_irq_disable(cmos, RTC_AIE);
7be2c7c9
DB
480
481 /* update alarm */
482 CMOS_WRITE(hrs, RTC_HOURS_ALARM);
483 CMOS_WRITE(min, RTC_MINUTES_ALARM);
484 CMOS_WRITE(sec, RTC_SECONDS_ALARM);
485
486 /* the system may support an "enhanced" alarm */
487 if (cmos->day_alrm) {
488 CMOS_WRITE(mday, cmos->day_alrm);
489 if (cmos->mon_alrm)
490 CMOS_WRITE(mon, cmos->mon_alrm);
491 }
492
311ee9c1
ZR
493 if (use_hpet_alarm()) {
494 /*
495 * FIXME the HPET alarm glue currently ignores day_alrm
496 * and mon_alrm ...
497 */
498 hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min,
499 t->time.tm_sec);
500 }
35d3fdd5 501
7e2a31da
DB
502 if (t->enabled)
503 cmos_irq_enable(cmos, RTC_AIE);
7be2c7c9
DB
504
505 spin_unlock_irq(&rtc_lock);
506
88b8d33b
AH
507 cmos->alarm_expires = rtc_tm_to_time64(&t->time);
508
7be2c7c9
DB
509 return 0;
510}
511
a8462ef6 512static int cmos_alarm_irq_enable(struct device *dev, unsigned int enabled)
7be2c7c9
DB
513{
514 struct cmos_rtc *cmos = dev_get_drvdata(dev);
7be2c7c9
DB
515 unsigned long flags;
516
7be2c7c9 517 spin_lock_irqsave(&rtc_lock, flags);
a8462ef6
HRK
518
519 if (enabled)
7e2a31da 520 cmos_irq_enable(cmos, RTC_AIE);
a8462ef6
HRK
521 else
522 cmos_irq_disable(cmos, RTC_AIE);
523
7be2c7c9
DB
524 spin_unlock_irqrestore(&rtc_lock, flags);
525 return 0;
526}
527
6fca3fc5 528#if IS_ENABLED(CONFIG_RTC_INTF_PROC)
7be2c7c9
DB
529
530static int cmos_procfs(struct device *dev, struct seq_file *seq)
531{
532 struct cmos_rtc *cmos = dev_get_drvdata(dev);
533 unsigned char rtc_control, valid;
534
535 spin_lock_irq(&rtc_lock);
536 rtc_control = CMOS_READ(RTC_CONTROL);
537 valid = CMOS_READ(RTC_VALID);
538 spin_unlock_irq(&rtc_lock);
539
540 /* NOTE: at least ICH6 reports battery status using a different
541 * (non-RTC) bit; and SQWE is ignored on many current systems.
542 */
4395eb1f
JP
543 seq_printf(seq,
544 "periodic_IRQ\t: %s\n"
545 "update_IRQ\t: %s\n"
546 "HPET_emulated\t: %s\n"
547 // "square_wave\t: %s\n"
548 "BCD\t\t: %s\n"
549 "DST_enable\t: %s\n"
550 "periodic_freq\t: %d\n"
551 "batt_status\t: %s\n",
552 (rtc_control & RTC_PIE) ? "yes" : "no",
553 (rtc_control & RTC_UIE) ? "yes" : "no",
311ee9c1 554 use_hpet_alarm() ? "yes" : "no",
4395eb1f
JP
555 // (rtc_control & RTC_SQWE) ? "yes" : "no",
556 (rtc_control & RTC_DM_BINARY) ? "no" : "yes",
557 (rtc_control & RTC_DST_EN) ? "yes" : "no",
558 cmos->rtc->irq_freq,
559 (valid & RTC_VRT) ? "okay" : "dead");
560
561 return 0;
7be2c7c9
DB
562}
563
564#else
565#define cmos_procfs NULL
566#endif
567
568static const struct rtc_class_ops cmos_rtc_ops = {
a8462ef6
HRK
569 .read_time = cmos_read_time,
570 .set_time = cmos_set_time,
571 .read_alarm = cmos_read_alarm,
572 .set_alarm = cmos_set_alarm,
573 .proc = cmos_procfs,
a8462ef6 574 .alarm_irq_enable = cmos_alarm_irq_enable,
7be2c7c9
DB
575};
576
fbb974ba
HG
577static const struct rtc_class_ops cmos_rtc_ops_no_alarm = {
578 .read_time = cmos_read_time,
579 .set_time = cmos_set_time,
580 .proc = cmos_procfs,
581};
582
7be2c7c9
DB
583/*----------------------------------------------------------------*/
584
e07e232c
DB
585/*
586 * All these chips have at least 64 bytes of address space, shared by
587 * RTC registers and NVRAM. Most of those bytes of NVRAM are used
588 * by boot firmware. Modern chips have 128 or 256 bytes.
589 */
590
591#define NVRAM_OFFSET (RTC_REG_D + 1)
592
8b5b7958
AB
593static int cmos_nvram_read(void *priv, unsigned int off, void *val,
594 size_t count)
e07e232c 595{
8b5b7958 596 unsigned char *buf = val;
e07e232c
DB
597 int retval;
598
c8fc40cd 599 off += NVRAM_OFFSET;
e07e232c 600 spin_lock_irq(&rtc_lock);
c8fc40cd
DB
601 for (retval = 0; count; count--, off++, retval++) {
602 if (off < 128)
603 *buf++ = CMOS_READ(off);
604 else if (can_bank2)
605 *buf++ = cmos_read_bank2(off);
606 else
607 break;
608 }
e07e232c
DB
609 spin_unlock_irq(&rtc_lock);
610
611 return retval;
612}
613
8b5b7958
AB
614static int cmos_nvram_write(void *priv, unsigned int off, void *val,
615 size_t count)
e07e232c 616{
8b5b7958
AB
617 struct cmos_rtc *cmos = priv;
618 unsigned char *buf = val;
e07e232c
DB
619 int retval;
620
e07e232c
DB
621 /* NOTE: on at least PCs and Ataris, the boot firmware uses a
622 * checksum on part of the NVRAM data. That's currently ignored
623 * here. If userspace is smart enough to know what fields of
624 * NVRAM to update, updating checksums is also part of its job.
625 */
c8fc40cd 626 off += NVRAM_OFFSET;
e07e232c 627 spin_lock_irq(&rtc_lock);
c8fc40cd 628 for (retval = 0; count; count--, off++, retval++) {
e07e232c
DB
629 /* don't trash RTC registers */
630 if (off == cmos->day_alrm
631 || off == cmos->mon_alrm
632 || off == cmos->century)
633 buf++;
c8fc40cd 634 else if (off < 128)
e07e232c 635 CMOS_WRITE(*buf++, off);
c8fc40cd
DB
636 else if (can_bank2)
637 cmos_write_bank2(*buf++, off);
638 else
639 break;
e07e232c
DB
640 }
641 spin_unlock_irq(&rtc_lock);
642
643 return retval;
644}
645
e07e232c
DB
646/*----------------------------------------------------------------*/
647
7be2c7c9
DB
648static struct cmos_rtc cmos_rtc;
649
650static irqreturn_t cmos_interrupt(int irq, void *p)
651{
66e4f4a9 652 unsigned long flags;
7be2c7c9 653 u8 irqstat;
8a0bdfd7 654 u8 rtc_control;
7be2c7c9 655
66e4f4a9 656 spin_lock_irqsave(&rtc_lock, flags);
35d3fdd5
DB
657
658 /* When the HPET interrupt handler calls us, the interrupt
659 * status is passed as arg1 instead of the irq number. But
660 * always clear irq status, even when HPET is in the way.
661 *
662 * Note that HPET and RTC are almost certainly out of phase,
663 * giving different IRQ status ...
9d8af78b 664 */
35d3fdd5
DB
665 irqstat = CMOS_READ(RTC_INTR_FLAGS);
666 rtc_control = CMOS_READ(RTC_CONTROL);
311ee9c1 667 if (use_hpet_alarm())
9d8af78b 668 irqstat = (unsigned long)irq & 0xF0;
998a0605
DB
669
670 /* If we were suspended, RTC_CONTROL may not be accurate since the
671 * bios may have cleared it.
672 */
673 if (!cmos_rtc.suspend_ctrl)
674 irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF;
675 else
676 irqstat &= (cmos_rtc.suspend_ctrl & RTC_IRQMASK) | RTC_IRQF;
8a0bdfd7
DB
677
678 /* All Linux RTC alarms should be treated as if they were oneshot.
679 * Similar code may be needed in system wakeup paths, in case the
680 * alarm woke the system.
681 */
682 if (irqstat & RTC_AIE) {
998a0605 683 cmos_rtc.suspend_ctrl &= ~RTC_AIE;
8a0bdfd7
DB
684 rtc_control &= ~RTC_AIE;
685 CMOS_WRITE(rtc_control, RTC_CONTROL);
311ee9c1
ZR
686 if (use_hpet_alarm())
687 hpet_mask_rtc_irq_bit(RTC_AIE);
8a0bdfd7
DB
688 CMOS_READ(RTC_INTR_FLAGS);
689 }
66e4f4a9 690 spin_unlock_irqrestore(&rtc_lock, flags);
7be2c7c9 691
bcd9b89c 692 if (is_intr(irqstat)) {
7be2c7c9
DB
693 rtc_update_irq(p, 1, irqstat);
694 return IRQ_HANDLED;
695 } else
696 return IRQ_NONE;
697}
698
41ac8df9 699#ifdef CONFIG_PNP
7be2c7c9
DB
700#define INITSECTION
701
702#else
7be2c7c9
DB
703#define INITSECTION __init
704#endif
705
706static int INITSECTION
707cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
708{
97a92e77 709 struct cmos_rtc_board_info *info = dev_get_platdata(dev);
7be2c7c9
DB
710 int retval = 0;
711 unsigned char rtc_control;
e07e232c 712 unsigned address_space;
31632dbd 713 u32 flags = 0;
8b5b7958
AB
714 struct nvmem_config nvmem_cfg = {
715 .name = "cmos_nvram",
716 .word_size = 1,
717 .stride = 1,
718 .reg_read = cmos_nvram_read,
719 .reg_write = cmos_nvram_write,
720 .priv = &cmos_rtc,
721 };
7be2c7c9
DB
722
723 /* there can be only one ... */
724 if (cmos_rtc.dev)
725 return -EBUSY;
726
727 if (!ports)
728 return -ENODEV;
729
05440dfc
DB
730 /* Claim I/O ports ASAP, minimizing conflict with legacy driver.
731 *
732 * REVISIT non-x86 systems may instead use memory space resources
733 * (needing ioremap etc), not i/o space resources like this ...
734 */
31632dbd
MR
735 if (RTC_IOMAPPED)
736 ports = request_region(ports->start, resource_size(ports),
737 driver_name);
738 else
739 ports = request_mem_region(ports->start, resource_size(ports),
740 driver_name);
05440dfc
DB
741 if (!ports) {
742 dev_dbg(dev, "i/o registers already in use\n");
743 return -EBUSY;
744 }
745
7be2c7c9
DB
746 cmos_rtc.irq = rtc_irq;
747 cmos_rtc.iomem = ports;
748
e07e232c
DB
749 /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM
750 * driver did, but don't reject unknown configs. Old hardware
c8fc40cd
DB
751 * won't address 128 bytes. Newer chips have multiple banks,
752 * though they may not be listed in one I/O resource.
e07e232c
DB
753 */
754#if defined(CONFIG_ATARI)
755 address_space = 64;
95abd0df 756#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \
8cb7c71b 757 || defined(__sparc__) || defined(__mips__) \
739d875d 758 || defined(__powerpc__)
e07e232c
DB
759 address_space = 128;
760#else
761#warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes.
762 address_space = 128;
763#endif
c8fc40cd
DB
764 if (can_bank2 && ports->end > (ports->start + 1))
765 address_space = 256;
e07e232c 766
87ac84f4
DB
767 /* For ACPI systems extension info comes from the FADT. On others,
768 * board specific setup provides it as appropriate. Systems where
769 * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and
770 * some almost-clones) can provide hooks to make that behave.
e07e232c
DB
771 *
772 * Note that ACPI doesn't preclude putting these registers into
773 * "extended" areas of the chip, including some that we won't yet
774 * expect CMOS_READ and friends to handle.
7be2c7c9
DB
775 */
776 if (info) {
31632dbd
MR
777 if (info->flags)
778 flags = info->flags;
779 if (info->address_space)
780 address_space = info->address_space;
781
e07e232c
DB
782 if (info->rtc_day_alarm && info->rtc_day_alarm < 128)
783 cmos_rtc.day_alrm = info->rtc_day_alarm;
784 if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128)
785 cmos_rtc.mon_alrm = info->rtc_mon_alarm;
786 if (info->rtc_century && info->rtc_century < 128)
787 cmos_rtc.century = info->rtc_century;
87ac84f4
DB
788
789 if (info->wake_on && info->wake_off) {
790 cmos_rtc.wake_on = info->wake_on;
791 cmos_rtc.wake_off = info->wake_off;
792 }
7be2c7c9
DB
793 }
794
6ba8bcd4
DC
795 cmos_rtc.dev = dev;
796 dev_set_drvdata(dev, &cmos_rtc);
797
53d29e0a 798 cmos_rtc.rtc = devm_rtc_allocate_device(dev);
05440dfc
DB
799 if (IS_ERR(cmos_rtc.rtc)) {
800 retval = PTR_ERR(cmos_rtc.rtc);
801 goto cleanup0;
802 }
7be2c7c9 803
d4afc76c 804 rename_region(ports, dev_name(&cmos_rtc.rtc->dev));
7be2c7c9
DB
805
806 spin_lock_irq(&rtc_lock);
807
31632dbd
MR
808 if (!(flags & CMOS_RTC_FLAGS_NOFREQ)) {
809 /* force periodic irq to CMOS reset default of 1024Hz;
810 *
811 * REVISIT it's been reported that at least one x86_64 ALI
812 * mobo doesn't use 32KHz here ... for portability we might
813 * need to do something about other clock frequencies.
814 */
815 cmos_rtc.rtc->irq_freq = 1024;
311ee9c1
ZR
816 if (use_hpet_alarm())
817 hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq);
31632dbd
MR
818 CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT);
819 }
7be2c7c9 820
7e2a31da 821 /* disable irqs */
31632dbd
MR
822 if (is_valid_irq(rtc_irq))
823 cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE);
35d3fdd5 824
7e2a31da 825 rtc_control = CMOS_READ(RTC_CONTROL);
7be2c7c9
DB
826
827 spin_unlock_irq(&rtc_lock);
828
5e8599d2 829 if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) {
3804a89b 830 dev_warn(dev, "only 24-hr supported\n");
7be2c7c9
DB
831 retval = -ENXIO;
832 goto cleanup1;
833 }
834
311ee9c1
ZR
835 if (use_hpet_alarm())
836 hpet_rtc_timer_init();
970fc7f4 837
9d8af78b
BW
838 if (is_valid_irq(rtc_irq)) {
839 irq_handler_t rtc_cmos_int_handler;
840
311ee9c1 841 if (use_hpet_alarm()) {
9d8af78b 842 rtc_cmos_int_handler = hpet_rtc_interrupt;
24b34472
AM
843 retval = hpet_register_irq_handler(cmos_interrupt);
844 if (retval) {
970fc7f4 845 hpet_mask_rtc_irq_bit(RTC_IRQMASK);
ee443357 846 dev_warn(dev, "hpet_register_irq_handler "
9d8af78b
BW
847 " failed in rtc_init().");
848 goto cleanup1;
849 }
850 } else
851 rtc_cmos_int_handler = cmos_interrupt;
852
853 retval = request_irq(rtc_irq, rtc_cmos_int_handler,
b6da197a 854 0, dev_name(&cmos_rtc.rtc->dev),
ab6a2d70 855 cmos_rtc.rtc);
9d8af78b
BW
856 if (retval < 0) {
857 dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq);
858 goto cleanup1;
859 }
fbb974ba
HG
860
861 cmos_rtc.rtc->ops = &cmos_rtc_ops;
862 } else {
863 cmos_rtc.rtc->ops = &cmos_rtc_ops_no_alarm;
7be2c7c9
DB
864 }
865
53d29e0a
AB
866 retval = rtc_register_device(cmos_rtc.rtc);
867 if (retval)
e07e232c 868 goto cleanup2;
7be2c7c9 869
8b5b7958
AB
870 /* export at least the first block of NVRAM */
871 nvmem_cfg.size = address_space - NVRAM_OFFSET;
3a905c2d 872 if (devm_rtc_nvmem_register(cmos_rtc.rtc, &nvmem_cfg))
8b5b7958
AB
873 dev_err(dev, "nvmem registration failed\n");
874
875 dev_info(dev, "%s%s, %d bytes nvram%s\n",
876 !is_valid_irq(rtc_irq) ? "no alarms" :
877 cmos_rtc.mon_alrm ? "alarms up to one year" :
878 cmos_rtc.day_alrm ? "alarms up to one month" :
879 "alarms up to one day",
880 cmos_rtc.century ? ", y3k" : "",
881 nvmem_cfg.size,
311ee9c1 882 use_hpet_alarm() ? ", hpet irqs" : "");
7be2c7c9
DB
883
884 return 0;
885
e07e232c
DB
886cleanup2:
887 if (is_valid_irq(rtc_irq))
888 free_irq(rtc_irq, cmos_rtc.rtc);
7be2c7c9 889cleanup1:
05440dfc 890 cmos_rtc.dev = NULL;
05440dfc 891cleanup0:
31632dbd
MR
892 if (RTC_IOMAPPED)
893 release_region(ports->start, resource_size(ports));
894 else
895 release_mem_region(ports->start, resource_size(ports));
7be2c7c9
DB
896 return retval;
897}
898
31632dbd 899static void cmos_do_shutdown(int rtc_irq)
7be2c7c9 900{
7be2c7c9 901 spin_lock_irq(&rtc_lock);
31632dbd
MR
902 if (is_valid_irq(rtc_irq))
903 cmos_irq_disable(&cmos_rtc, RTC_IRQMASK);
7be2c7c9
DB
904 spin_unlock_irq(&rtc_lock);
905}
906
a3a0673b 907static void cmos_do_remove(struct device *dev)
7be2c7c9
DB
908{
909 struct cmos_rtc *cmos = dev_get_drvdata(dev);
05440dfc 910 struct resource *ports;
7be2c7c9 911
31632dbd 912 cmos_do_shutdown(cmos->irq);
7be2c7c9 913
9d8af78b 914 if (is_valid_irq(cmos->irq)) {
05440dfc 915 free_irq(cmos->irq, cmos->rtc);
311ee9c1
ZR
916 if (use_hpet_alarm())
917 hpet_unregister_irq_handler(cmos_interrupt);
9d8af78b 918 }
7be2c7c9 919
05440dfc 920 cmos->rtc = NULL;
7be2c7c9 921
05440dfc 922 ports = cmos->iomem;
31632dbd
MR
923 if (RTC_IOMAPPED)
924 release_region(ports->start, resource_size(ports));
925 else
926 release_mem_region(ports->start, resource_size(ports));
05440dfc
DB
927 cmos->iomem = NULL;
928
929 cmos->dev = NULL;
7be2c7c9
DB
930}
931
88b8d33b
AH
932static int cmos_aie_poweroff(struct device *dev)
933{
934 struct cmos_rtc *cmos = dev_get_drvdata(dev);
935 struct rtc_time now;
936 time64_t t_now;
937 int retval = 0;
938 unsigned char rtc_control;
939
940 if (!cmos->alarm_expires)
941 return -EINVAL;
942
943 spin_lock_irq(&rtc_lock);
944 rtc_control = CMOS_READ(RTC_CONTROL);
945 spin_unlock_irq(&rtc_lock);
946
947 /* We only care about the situation where AIE is disabled. */
948 if (rtc_control & RTC_AIE)
949 return -EBUSY;
950
951 cmos_read_time(dev, &now);
952 t_now = rtc_tm_to_time64(&now);
953
954 /*
955 * When enabling "RTC wake-up" in BIOS setup, the machine reboots
956 * automatically right after shutdown on some buggy boxes.
957 * This automatic rebooting issue won't happen when the alarm
958 * time is larger than now+1 seconds.
959 *
960 * If the alarm time is equal to now+1 seconds, the issue can be
961 * prevented by cancelling the alarm.
962 */
963 if (cmos->alarm_expires == t_now + 1) {
964 struct rtc_wkalrm alarm;
965
966 /* Cancel the AIE timer by configuring the past time. */
967 rtc_time64_to_tm(t_now - 1, &alarm.time);
968 alarm.enabled = 0;
969 retval = cmos_set_alarm(dev, &alarm);
970 } else if (cmos->alarm_expires > t_now + 1) {
971 retval = -EBUSY;
972 }
973
974 return retval;
975}
976
2fb08e6c 977static int cmos_suspend(struct device *dev)
7be2c7c9
DB
978{
979 struct cmos_rtc *cmos = dev_get_drvdata(dev);
bcd9b89c 980 unsigned char tmp;
7be2c7c9
DB
981
982 /* only the alarm might be a wakeup event source */
983 spin_lock_irq(&rtc_lock);
984 cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL);
985 if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) {
35d3fdd5 986 unsigned char mask;
bcd9b89c 987
74c4633d 988 if (device_may_wakeup(dev))
35d3fdd5 989 mask = RTC_IRQMASK & ~RTC_AIE;
7be2c7c9 990 else
35d3fdd5
DB
991 mask = RTC_IRQMASK;
992 tmp &= ~mask;
7be2c7c9 993 CMOS_WRITE(tmp, RTC_CONTROL);
311ee9c1
ZR
994 if (use_hpet_alarm())
995 hpet_mask_rtc_irq_bit(mask);
7e2a31da 996 cmos_checkintr(cmos, tmp);
bcd9b89c 997 }
7be2c7c9
DB
998 spin_unlock_irq(&rtc_lock);
999
bc51098c 1000 if ((tmp & RTC_AIE) && !cmos_use_acpi_alarm()) {
87ac84f4
DB
1001 cmos->enabled_wake = 1;
1002 if (cmos->wake_on)
1003 cmos->wake_on(dev);
1004 else
1005 enable_irq_wake(cmos->irq);
1006 }
7be2c7c9 1007
c254bcd7 1008 memset(&cmos->saved_wkalrm, 0, sizeof(struct rtc_wkalrm));
68669d55
GM
1009 cmos_read_alarm(dev, &cmos->saved_wkalrm);
1010
ee443357 1011 dev_dbg(dev, "suspend%s, ctrl %02x\n",
7be2c7c9
DB
1012 (tmp & RTC_AIE) ? ", alarm may wake" : "",
1013 tmp);
1014
1015 return 0;
1016}
1017
74c4633d
RW
1018/* We want RTC alarms to wake us from e.g. ACPI G2/S5 "soft off", even
1019 * after a detour through G3 "mechanical off", although the ACPI spec
1020 * says wakeup should only work from G1/S4 "hibernate". To most users,
1021 * distinctions between S4 and S5 are pointless. So when the hardware
1022 * allows, don't draw that distinction.
1023 */
1024static inline int cmos_poweroff(struct device *dev)
1025{
00f7f90c
AB
1026 if (!IS_ENABLED(CONFIG_PM))
1027 return -ENOSYS;
1028
2fb08e6c 1029 return cmos_suspend(dev);
74c4633d
RW
1030}
1031
68669d55
GM
1032static void cmos_check_wkalrm(struct device *dev)
1033{
1034 struct cmos_rtc *cmos = dev_get_drvdata(dev);
1035 struct rtc_wkalrm current_alarm;
c6d3a278 1036 time64_t t_now;
68669d55
GM
1037 time64_t t_current_expires;
1038 time64_t t_saved_expires;
c6d3a278
ZR
1039 struct rtc_time now;
1040
1041 /* Check if we have RTC Alarm armed */
1042 if (!(cmos->suspend_ctrl & RTC_AIE))
1043 return;
1044
1045 cmos_read_time(dev, &now);
1046 t_now = rtc_tm_to_time64(&now);
1047
1048 /*
1049 * ACPI RTC wake event is cleared after resume from STR,
1050 * ACK the rtc irq here
1051 */
bc51098c 1052 if (t_now >= cmos->alarm_expires && cmos_use_acpi_alarm()) {
c6d3a278
ZR
1053 cmos_interrupt(0, (void *)cmos->rtc);
1054 return;
1055 }
68669d55 1056
c254bcd7 1057 memset(&current_alarm, 0, sizeof(struct rtc_wkalrm));
68669d55
GM
1058 cmos_read_alarm(dev, &current_alarm);
1059 t_current_expires = rtc_tm_to_time64(&current_alarm.time);
1060 t_saved_expires = rtc_tm_to_time64(&cmos->saved_wkalrm.time);
1061 if (t_current_expires != t_saved_expires ||
1062 cmos->saved_wkalrm.enabled != current_alarm.enabled) {
1063 cmos_set_alarm(dev, &cmos->saved_wkalrm);
1064 }
1065}
1066
983bf125
GM
1067static void cmos_check_acpi_rtc_status(struct device *dev,
1068 unsigned char *rtc_control);
1069
00f7f90c 1070static int __maybe_unused cmos_resume(struct device *dev)
7be2c7c9
DB
1071{
1072 struct cmos_rtc *cmos = dev_get_drvdata(dev);
998a0605
DB
1073 unsigned char tmp;
1074
bc51098c 1075 if (cmos->enabled_wake && !cmos_use_acpi_alarm()) {
998a0605
DB
1076 if (cmos->wake_off)
1077 cmos->wake_off(dev);
1078 else
1079 disable_irq_wake(cmos->irq);
1080 cmos->enabled_wake = 0;
1081 }
7be2c7c9 1082
68669d55
GM
1083 /* The BIOS might have changed the alarm, restore it */
1084 cmos_check_wkalrm(dev);
1085
998a0605
DB
1086 spin_lock_irq(&rtc_lock);
1087 tmp = cmos->suspend_ctrl;
1088 cmos->suspend_ctrl = 0;
7be2c7c9 1089 /* re-enable any irqs previously active */
35d3fdd5
DB
1090 if (tmp & RTC_IRQMASK) {
1091 unsigned char mask;
7be2c7c9 1092
311ee9c1 1093 if (device_may_wakeup(dev) && use_hpet_alarm())
ebf8d6c8
DB
1094 hpet_rtc_timer_init();
1095
35d3fdd5
DB
1096 do {
1097 CMOS_WRITE(tmp, RTC_CONTROL);
311ee9c1
ZR
1098 if (use_hpet_alarm())
1099 hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK);
35d3fdd5
DB
1100
1101 mask = CMOS_READ(RTC_INTR_FLAGS);
1102 mask &= (tmp & RTC_IRQMASK) | RTC_IRQF;
311ee9c1 1103 if (!use_hpet_alarm() || !is_intr(mask))
35d3fdd5
DB
1104 break;
1105
1106 /* force one-shot behavior if HPET blocked
1107 * the wake alarm's irq
1108 */
1109 rtc_update_irq(cmos->rtc, 1, mask);
1110 tmp &= ~RTC_AIE;
1111 hpet_mask_rtc_irq_bit(RTC_AIE);
1112 } while (mask & RTC_AIE);
983bf125
GM
1113
1114 if (tmp & RTC_AIE)
1115 cmos_check_acpi_rtc_status(dev, &tmp);
7be2c7c9 1116 }
998a0605 1117 spin_unlock_irq(&rtc_lock);
7be2c7c9 1118
ee443357 1119 dev_dbg(dev, "resume, ctrl %02x\n", tmp);
7be2c7c9
DB
1120
1121 return 0;
1122}
1123
b5ada460
MW
1124static SIMPLE_DEV_PM_OPS(cmos_pm_ops, cmos_suspend, cmos_resume);
1125
7be2c7c9
DB
1126/*----------------------------------------------------------------*/
1127
e07e232c
DB
1128/* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus.
1129 * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs
1130 * probably list them in similar PNPBIOS tables; so PNP is more common.
1131 *
1132 * We don't use legacy "poke at the hardware" probing. Ancient PCs that
1133 * predate even PNPBIOS should set up platform_bus devices.
7be2c7c9
DB
1134 */
1135
a474aaed
BH
1136#ifdef CONFIG_ACPI
1137
1138#include <linux/acpi.h>
1139
a474aaed
BH
1140static u32 rtc_handler(void *context)
1141{
b2201e54 1142 struct device *dev = context;
983bf125
GM
1143 struct cmos_rtc *cmos = dev_get_drvdata(dev);
1144 unsigned char rtc_control = 0;
1145 unsigned char rtc_intr;
368e21ae 1146 unsigned long flags;
983bf125 1147
311ee9c1
ZR
1148
1149 /*
1150 * Always update rtc irq when ACPI is used as RTC Alarm.
1151 * Or else, ACPI SCI is enabled during suspend/resume only,
1152 * update rtc irq in that case.
1153 */
bc51098c 1154 if (cmos_use_acpi_alarm())
311ee9c1
ZR
1155 cmos_interrupt(0, (void *)cmos->rtc);
1156 else {
1157 /* Fix me: can we use cmos_interrupt() here as well? */
1158 spin_lock_irqsave(&rtc_lock, flags);
1159 if (cmos_rtc.suspend_ctrl)
1160 rtc_control = CMOS_READ(RTC_CONTROL);
1161 if (rtc_control & RTC_AIE) {
1162 cmos_rtc.suspend_ctrl &= ~RTC_AIE;
1163 CMOS_WRITE(rtc_control, RTC_CONTROL);
1164 rtc_intr = CMOS_READ(RTC_INTR_FLAGS);
1165 rtc_update_irq(cmos->rtc, 1, rtc_intr);
1166 }
1167 spin_unlock_irqrestore(&rtc_lock, flags);
983bf125 1168 }
b2201e54 1169
967b08c2 1170 pm_wakeup_hard_event(dev);
a474aaed
BH
1171 acpi_clear_event(ACPI_EVENT_RTC);
1172 acpi_disable_event(ACPI_EVENT_RTC, 0);
1173 return ACPI_INTERRUPT_HANDLED;
1174}
1175
b2201e54 1176static inline void rtc_wake_setup(struct device *dev)
a474aaed 1177{
b2201e54 1178 acpi_install_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler, dev);
a474aaed
BH
1179 /*
1180 * After the RTC handler is installed, the Fixed_RTC event should
1181 * be disabled. Only when the RTC alarm is set will it be enabled.
1182 */
1183 acpi_clear_event(ACPI_EVENT_RTC);
1184 acpi_disable_event(ACPI_EVENT_RTC, 0);
1185}
1186
1187static void rtc_wake_on(struct device *dev)
1188{
1189 acpi_clear_event(ACPI_EVENT_RTC);
1190 acpi_enable_event(ACPI_EVENT_RTC, 0);
1191}
1192
1193static void rtc_wake_off(struct device *dev)
1194{
1195 acpi_disable_event(ACPI_EVENT_RTC, 0);
1196}
a474aaed 1197
36d91a4d
ZR
1198#ifdef CONFIG_X86
1199/* Enable use_acpi_alarm mode for Intel platforms no earlier than 2015 */
1200static void use_acpi_alarm_quirks(void)
1201{
36d91a4d
ZR
1202 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1203 return;
1204
1205 if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0))
1206 return;
1207
1208 if (!is_hpet_enabled())
1209 return;
1210
604c5212
AS
1211 if (dmi_get_bios_year() < 2015)
1212 return;
1213
1214 use_acpi_alarm = true;
36d91a4d
ZR
1215}
1216#else
1217static inline void use_acpi_alarm_quirks(void) { }
1218#endif
1219
a474aaed
BH
1220/* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find
1221 * its device node and pass extra config data. This helps its driver use
1222 * capabilities that the now-obsolete mc146818 didn't have, and informs it
1223 * that this board's RTC is wakeup-capable (per ACPI spec).
1224 */
1225static struct cmos_rtc_board_info acpi_rtc_info;
1226
5a167f45 1227static void cmos_wake_setup(struct device *dev)
a474aaed
BH
1228{
1229 if (acpi_disabled)
1230 return;
1231
36d91a4d
ZR
1232 use_acpi_alarm_quirks();
1233
b2201e54 1234 rtc_wake_setup(dev);
a474aaed
BH
1235 acpi_rtc_info.wake_on = rtc_wake_on;
1236 acpi_rtc_info.wake_off = rtc_wake_off;
1237
1238 /* workaround bug in some ACPI tables */
1239 if (acpi_gbl_FADT.month_alarm && !acpi_gbl_FADT.day_alarm) {
1240 dev_dbg(dev, "bogus FADT month_alarm (%d)\n",
1241 acpi_gbl_FADT.month_alarm);
1242 acpi_gbl_FADT.month_alarm = 0;
1243 }
1244
1245 acpi_rtc_info.rtc_day_alarm = acpi_gbl_FADT.day_alarm;
1246 acpi_rtc_info.rtc_mon_alarm = acpi_gbl_FADT.month_alarm;
1247 acpi_rtc_info.rtc_century = acpi_gbl_FADT.century;
1248
1249 /* NOTE: S4_RTC_WAKE is NOT currently useful to Linux */
1250 if (acpi_gbl_FADT.flags & ACPI_FADT_S4_RTC_WAKE)
1251 dev_info(dev, "RTC can wake from S4\n");
1252
1253 dev->platform_data = &acpi_rtc_info;
1254
1255 /* RTC always wakes from S1/S2/S3, and often S4/STD */
1256 device_init_wakeup(dev, 1);
1257}
1258
983bf125
GM
1259static void cmos_check_acpi_rtc_status(struct device *dev,
1260 unsigned char *rtc_control)
1261{
1262 struct cmos_rtc *cmos = dev_get_drvdata(dev);
1263 acpi_event_status rtc_status;
1264 acpi_status status;
1265
1266 if (acpi_gbl_FADT.flags & ACPI_FADT_FIXED_RTC)
1267 return;
1268
1269 status = acpi_get_event_status(ACPI_EVENT_RTC, &rtc_status);
1270 if (ACPI_FAILURE(status)) {
1271 dev_err(dev, "Could not get RTC status\n");
1272 } else if (rtc_status & ACPI_EVENT_FLAG_SET) {
1273 unsigned char mask;
1274 *rtc_control &= ~RTC_AIE;
1275 CMOS_WRITE(*rtc_control, RTC_CONTROL);
1276 mask = CMOS_READ(RTC_INTR_FLAGS);
1277 rtc_update_irq(cmos->rtc, 1, mask);
1278 }
1279}
1280
a474aaed
BH
1281#else
1282
5a167f45 1283static void cmos_wake_setup(struct device *dev)
a474aaed
BH
1284{
1285}
1286
983bf125
GM
1287static void cmos_check_acpi_rtc_status(struct device *dev,
1288 unsigned char *rtc_control)
1289{
1290}
1291
a474aaed
BH
1292#endif
1293
41ac8df9 1294#ifdef CONFIG_PNP
7be2c7c9
DB
1295
1296#include <linux/pnp.h>
1297
5a167f45 1298static int cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id)
7be2c7c9 1299{
a474aaed
BH
1300 cmos_wake_setup(&pnp->dev);
1301
a1e23a42
HG
1302 if (pnp_port_start(pnp, 0) == 0x70 && !pnp_irq_valid(pnp, 0)) {
1303 unsigned int irq = 0;
1304#ifdef CONFIG_X86
6cd8fa87
MG
1305 /* Some machines contain a PNP entry for the RTC, but
1306 * don't define the IRQ. It should always be safe to
a1e23a42 1307 * hardcode it on systems with a legacy PIC.
6cd8fa87 1308 */
a1e23a42 1309 if (nr_legacy_irqs())
5848ad2f 1310 irq = RTC_IRQ;
a1e23a42 1311#endif
8766ad0c 1312 return cmos_do_probe(&pnp->dev,
a1e23a42
HG
1313 pnp_get_resource(pnp, IORESOURCE_IO, 0), irq);
1314 } else {
6cd8fa87 1315 return cmos_do_probe(&pnp->dev,
8766ad0c
BH
1316 pnp_get_resource(pnp, IORESOURCE_IO, 0),
1317 pnp_irq(pnp, 0));
a1e23a42 1318 }
7be2c7c9
DB
1319}
1320
a3a0673b 1321static void cmos_pnp_remove(struct pnp_dev *pnp)
7be2c7c9
DB
1322{
1323 cmos_do_remove(&pnp->dev);
1324}
1325
004731b2 1326static void cmos_pnp_shutdown(struct pnp_dev *pnp)
74c4633d 1327{
31632dbd
MR
1328 struct device *dev = &pnp->dev;
1329 struct cmos_rtc *cmos = dev_get_drvdata(dev);
1330
88b8d33b
AH
1331 if (system_state == SYSTEM_POWER_OFF) {
1332 int retval = cmos_poweroff(dev);
1333
1334 if (cmos_aie_poweroff(dev) < 0 && !retval)
1335 return;
1336 }
74c4633d 1337
31632dbd 1338 cmos_do_shutdown(cmos->irq);
74c4633d 1339}
7be2c7c9
DB
1340
1341static const struct pnp_device_id rtc_ids[] = {
1342 { .id = "PNP0b00", },
1343 { .id = "PNP0b01", },
1344 { .id = "PNP0b02", },
1345 { },
1346};
1347MODULE_DEVICE_TABLE(pnp, rtc_ids);
1348
1349static struct pnp_driver cmos_pnp_driver = {
8d4e59ec 1350 .name = driver_name,
7be2c7c9
DB
1351 .id_table = rtc_ids,
1352 .probe = cmos_pnp_probe,
a3a0673b 1353 .remove = cmos_pnp_remove,
004731b2 1354 .shutdown = cmos_pnp_shutdown,
7be2c7c9
DB
1355
1356 /* flag ensures resume() gets called, and stops syslog spam */
1357 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
a8a3808b
SK
1358 .driver = {
1359 .pm = &cmos_pm_ops,
1360 },
7be2c7c9
DB
1361};
1362
1da2e3d6 1363#endif /* CONFIG_PNP */
7be2c7c9 1364
3bcbaf6e
SAS
1365#ifdef CONFIG_OF
1366static const struct of_device_id of_cmos_match[] = {
1367 {
1368 .compatible = "motorola,mc146818",
1369 },
1370 { },
1371};
1372MODULE_DEVICE_TABLE(of, of_cmos_match);
1373
1374static __init void cmos_of_init(struct platform_device *pdev)
1375{
1376 struct device_node *node = pdev->dev.of_node;
3bcbaf6e
SAS
1377 const __be32 *val;
1378
1379 if (!node)
1380 return;
1381
1382 val = of_get_property(node, "ctrl-reg", NULL);
1383 if (val)
1384 CMOS_WRITE(be32_to_cpup(val), RTC_CONTROL);
1385
1386 val = of_get_property(node, "freq-reg", NULL);
1387 if (val)
1388 CMOS_WRITE(be32_to_cpup(val), RTC_FREQ_SELECT);
3bcbaf6e
SAS
1389}
1390#else
1391static inline void cmos_of_init(struct platform_device *pdev) {}
3bcbaf6e 1392#endif
7be2c7c9
DB
1393/*----------------------------------------------------------------*/
1394
41ac8df9 1395/* Platform setup should have set up an RTC device, when PNP is
bcd9b89c 1396 * unavailable ... this could happen even on (older) PCs.
7be2c7c9
DB
1397 */
1398
1399static int __init cmos_platform_probe(struct platform_device *pdev)
1400{
31632dbd
MR
1401 struct resource *resource;
1402 int irq;
1403
3bcbaf6e 1404 cmos_of_init(pdev);
a474aaed 1405 cmos_wake_setup(&pdev->dev);
31632dbd
MR
1406
1407 if (RTC_IOMAPPED)
1408 resource = platform_get_resource(pdev, IORESOURCE_IO, 0);
1409 else
1410 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1411 irq = platform_get_irq(pdev, 0);
1412 if (irq < 0)
1413 irq = -1;
1414
1415 return cmos_do_probe(&pdev->dev, resource, irq);
7be2c7c9
DB
1416}
1417
a3a0673b 1418static int cmos_platform_remove(struct platform_device *pdev)
7be2c7c9
DB
1419{
1420 cmos_do_remove(&pdev->dev);
1421 return 0;
1422}
1423
1424static void cmos_platform_shutdown(struct platform_device *pdev)
1425{
31632dbd
MR
1426 struct device *dev = &pdev->dev;
1427 struct cmos_rtc *cmos = dev_get_drvdata(dev);
1428
88b8d33b
AH
1429 if (system_state == SYSTEM_POWER_OFF) {
1430 int retval = cmos_poweroff(dev);
1431
1432 if (cmos_aie_poweroff(dev) < 0 && !retval)
1433 return;
1434 }
74c4633d 1435
31632dbd 1436 cmos_do_shutdown(cmos->irq);
7be2c7c9
DB
1437}
1438
ad28a07b
KS
1439/* work with hotplug and coldplug */
1440MODULE_ALIAS("platform:rtc_cmos");
1441
7be2c7c9 1442static struct platform_driver cmos_platform_driver = {
a3a0673b 1443 .remove = cmos_platform_remove,
7be2c7c9
DB
1444 .shutdown = cmos_platform_shutdown,
1445 .driver = {
c823a202 1446 .name = driver_name,
2fb08e6c 1447 .pm = &cmos_pm_ops,
c8a6046e 1448 .of_match_table = of_match_ptr(of_cmos_match),
7be2c7c9
DB
1449 }
1450};
1451
65909814
TLSC
1452#ifdef CONFIG_PNP
1453static bool pnp_driver_registered;
1454#endif
1455static bool platform_driver_registered;
1456
7be2c7c9
DB
1457static int __init cmos_init(void)
1458{
72f22b1e
BH
1459 int retval = 0;
1460
1da2e3d6 1461#ifdef CONFIG_PNP
65909814
TLSC
1462 retval = pnp_register_driver(&cmos_pnp_driver);
1463 if (retval == 0)
1464 pnp_driver_registered = true;
72f22b1e
BH
1465#endif
1466
65909814 1467 if (!cmos_rtc.dev) {
72f22b1e
BH
1468 retval = platform_driver_probe(&cmos_platform_driver,
1469 cmos_platform_probe);
65909814
TLSC
1470 if (retval == 0)
1471 platform_driver_registered = true;
1472 }
72f22b1e
BH
1473
1474 if (retval == 0)
1475 return 0;
1476
1477#ifdef CONFIG_PNP
65909814
TLSC
1478 if (pnp_driver_registered)
1479 pnp_unregister_driver(&cmos_pnp_driver);
72f22b1e
BH
1480#endif
1481 return retval;
7be2c7c9
DB
1482}
1483module_init(cmos_init);
1484
1485static void __exit cmos_exit(void)
1486{
1da2e3d6 1487#ifdef CONFIG_PNP
65909814
TLSC
1488 if (pnp_driver_registered)
1489 pnp_unregister_driver(&cmos_pnp_driver);
72f22b1e 1490#endif
65909814
TLSC
1491 if (platform_driver_registered)
1492 platform_driver_unregister(&cmos_platform_driver);
7be2c7c9
DB
1493}
1494module_exit(cmos_exit);
1495
1496
7be2c7c9
DB
1497MODULE_AUTHOR("David Brownell");
1498MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs");
1499MODULE_LICENSE("GPL");