[linux-block.git] / drivers / rtc / rtc-at91sam9.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * "RTT as Real Time Clock" driver for AT91SAM9 SoC family
 *
 * (C) 2007 Michel Benoit
 *
 * Based on rtc-at91rm9200.c by Rick Bronson
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/ioctl.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/suspend.h>
#include <linux/time.h>

/*
 * This driver uses two configurable hardware resources that live in the
 * AT91SAM9 backup power domain (intended to be powered at all times)
 * to implement the Real Time Clock interfaces
 *
 *  - A "Real-time Timer" (RTT) counts up in seconds from a base time.
 *    We can't assign the counter value (CRTV) ... but we can reset it.
 *
 *  - One of the "General Purpose Backup Registers" (GPBRs) holds the
 *    base time, normally an offset from the beginning of the POSIX
 *    epoch (1970-Jan-1 00:00:00 UTC).  Some systems also include the
 *    local timezone's offset.
 *
 * The RTC's value is the RTT counter plus that offset.  The RTC's alarm
 * is likewise a base (ALMV) plus that offset.
 *
 * Not all RTTs will be used as RTCs; some systems have multiple RTTs to
 * choose from, or a "real" RTC module.  All systems have multiple GPBR
 * registers available, likewise usable for more than "RTC" support.
 */

#define AT91_RTT_MR		0x00			/* Real-time Mode Register */
#define AT91_RTT_RTPRES		(0xffff << 0)		/* Real-time Timer Prescaler Value */
#define AT91_RTT_ALMIEN		(1 << 16)		/* Alarm Interrupt Enable */
#define AT91_RTT_RTTINCIEN	(1 << 17)		/* Real Time Timer Increment Interrupt Enable */
#define AT91_RTT_RTTRST		(1 << 18)		/* Real Time Timer Restart */

#define AT91_RTT_AR		0x04			/* Real-time Alarm Register */
#define AT91_RTT_ALMV		(0xffffffff)		/* Alarm Value */

#define AT91_RTT_VR		0x08			/* Real-time Value Register */
#define AT91_RTT_CRTV		(0xffffffff)		/* Current Real-time Value */

#define AT91_RTT_SR		0x0c			/* Real-time Status Register */
#define AT91_RTT_ALMS		(1 << 0)		/* Real-time Alarm Status */
#define AT91_RTT_RTTINC		(1 << 1)		/* Real-time Timer Increment */

/*
 * We store ALARM_DISABLED in ALMV to record that no alarm is set.
 * It's also the reset value for that field.
 */
#define ALARM_DISABLED	((u32)~0)


struct sam9_rtc {
	void __iomem		*rtt;
	struct rtc_device	*rtcdev;
	u32			imr;
	struct regmap		*gpbr;
	unsigned int		gpbr_offset;
	int 			irq;
	struct clk		*sclk;
	bool			suspended;
	unsigned long		events;
	spinlock_t		lock;
};

#define rtt_readl(rtc, field) \
	readl((rtc)->rtt + AT91_RTT_ ## field)
#define rtt_writel(rtc, field, val) \
	writel((val), (rtc)->rtt + AT91_RTT_ ## field)

static inline unsigned int gpbr_readl(struct sam9_rtc *rtc)
{
	unsigned int val;

	regmap_read(rtc->gpbr, rtc->gpbr_offset, &val);

	return val;
}

static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val)
{
	regmap_write(rtc->gpbr, rtc->gpbr_offset, val);
}

/*
 * Read current time and date in RTC
 */
static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	u32 secs, secs2;
	u32 offset;

	/* read current time offset */
	offset = gpbr_readl(rtc);
	if (offset == 0)
		return -EILSEQ;

	/* reread the counter to help sync the two clock domains */
	secs = rtt_readl(rtc, VR);
	secs2 = rtt_readl(rtc, VR);
	if (secs != secs2)
		secs = rtt_readl(rtc, VR);

	rtc_time64_to_tm(offset + secs, tm);

	dev_dbg(dev, "%s: %ptR\n", __func__, tm);

	return 0;
}

/*
 * Set current time and date in RTC
 */
static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	u32 offset, alarm, mr;
	unsigned long secs;

	dev_dbg(dev, "%s: %ptR\n", __func__, tm);

	secs = rtc_tm_to_time64(tm);

	mr = rtt_readl(rtc, MR);

	/* disable interrupts */
	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));

	/* read current time offset */
	offset = gpbr_readl(rtc);

	/* store the new base time in a battery backup register */
	secs += 1;
	gpbr_writel(rtc, secs);

	/* adjust the alarm time for the new base */
	alarm = rtt_readl(rtc, AR);
	if (alarm != ALARM_DISABLED) {
		if (offset > secs) {
			/* time jumped backwards, increase time until alarm */
			alarm += (offset - secs);
		} else if ((alarm + offset) > secs) {
			/* time jumped forwards, decrease time until alarm */
			alarm -= (secs - offset);
		} else {
			/* time jumped past the alarm, disable alarm */
			alarm = ALARM_DISABLED;
			mr &= ~AT91_RTT_ALMIEN;
		}
		rtt_writel(rtc, AR, alarm);
	}

	/* reset the timer, and re-enable interrupts */
	rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST);

	return 0;
}

static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	u32 alarm = rtt_readl(rtc, AR);
	u32 offset;

	offset = gpbr_readl(rtc);
	if (offset == 0)
		return -EILSEQ;

	memset(alrm, 0, sizeof(*alrm));
	if (alarm != ALARM_DISABLED && offset != 0) {
		rtc_time64_to_tm(offset + alarm, tm);

		dev_dbg(dev, "%s: %ptR\n", __func__, tm);

		if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
			alrm->enabled = 1;
	}

	return 0;
}

static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	struct rtc_time *tm = &alrm->time;
	unsigned long secs;
	u32 offset;
	u32 mr;

	secs = rtc_tm_to_time64(tm);

	offset = gpbr_readl(rtc);
	if (offset == 0) {
		/* time is not set */
		return -EILSEQ;
	}
	mr = rtt_readl(rtc, MR);
	rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);

	/* alarm in the past? finish and leave disabled */
	if (secs <= offset) {
		rtt_writel(rtc, AR, ALARM_DISABLED);
		return 0;
	}

	/* else set alarm and maybe enable it */
	rtt_writel(rtc, AR, secs - offset);
	if (alrm->enabled)
		rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);

	dev_dbg(dev, "%s: %ptR\n", __func__, tm);

	return 0;
}

static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	u32 mr = rtt_readl(rtc, MR);

	dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
	if (enabled)
		rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
	else
		rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
	return 0;
}

/*
 * Provide additional RTC information in /proc/driver/rtc
 */
static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
{
	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	u32 mr = rtt_readl(rtc, MR);

	seq_printf(seq, "update_IRQ\t: %s\n",
			(mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
	return 0;
}

static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc)
{
	u32 sr, mr;

	/* Shared interrupt may be for another device.  Note: reading
	 * SR clears it, so we must only read it in this irq handler!
	 */
	mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	sr = rtt_readl(rtc, SR) & (mr >> 16);
	if (!sr)
		return IRQ_NONE;

	/* alarm status */
	if (sr & AT91_RTT_ALMS)
		rtc->events |= (RTC_AF | RTC_IRQF);

	/* timer update/increment */
	if (sr & AT91_RTT_RTTINC)
		rtc->events |= (RTC_UF | RTC_IRQF);

	return IRQ_HANDLED;
}

static void at91_rtc_flush_events(struct sam9_rtc *rtc)
{
	if (!rtc->events)
		return;

	rtc_update_irq(rtc->rtcdev, 1, rtc->events);
	rtc->events = 0;

	pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
		rtc->events >> 8, rtc->events & 0x000000FF);
}

/*
 * IRQ handler for the RTC
 */
static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
{
	struct sam9_rtc *rtc = _rtc;
	int ret;

	spin_lock(&rtc->lock);

	ret = at91_rtc_cache_events(rtc);

	/* We're called in suspended state */
	if (rtc->suspended) {
		/* Mask irqs coming from this peripheral */
		rtt_writel(rtc, MR,
			   rtt_readl(rtc, MR) &
			   ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
		/* Trigger a system wakeup */
		pm_system_wakeup();
	} else {
		at91_rtc_flush_events(rtc);
	}

	spin_unlock(&rtc->lock);

	return ret;
}

static const struct rtc_class_ops at91_rtc_ops = {
	.read_time	= at91_rtc_readtime,
	.set_time	= at91_rtc_settime,
	.read_alarm	= at91_rtc_readalarm,
	.set_alarm	= at91_rtc_setalarm,
	.proc		= at91_rtc_proc,
	.alarm_irq_enable = at91_rtc_alarm_irq_enable,
};

/*
 * Initialize and install RTC driver
 */
static int at91_rtc_probe(struct platform_device *pdev)
{
	struct resource	*r;
	struct sam9_rtc	*rtc;
	int		ret, irq;
	u32		mr;
	unsigned int	sclk_rate;
	struct of_phandle_args args;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "failed to get interrupt resource\n");
		return irq;
	}

	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
	if (!rtc)
		return -ENOMEM;

	spin_lock_init(&rtc->lock);
	rtc->irq = irq;

	/* platform setup code should have handled this; sigh */
	if (!device_can_wakeup(&pdev->dev))
		device_init_wakeup(&pdev->dev, 1);

	platform_set_drvdata(pdev, rtc);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	rtc->rtt = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(rtc->rtt))
		return PTR_ERR(rtc->rtt);

	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
					"atmel,rtt-rtc-time-reg", 1, 0,
					&args);
	if (ret)
		return ret;

	rtc->gpbr = syscon_node_to_regmap(args.np);
	rtc->gpbr_offset = args.args[0];
	if (IS_ERR(rtc->gpbr)) {
		dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n");
		return -ENOMEM;
	}

	rtc->sclk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(rtc->sclk))
		return PTR_ERR(rtc->sclk);

	ret = clk_prepare_enable(rtc->sclk);
	if (ret) {
		dev_err(&pdev->dev, "Could not enable slow clock\n");
		return ret;
	}

	sclk_rate = clk_get_rate(rtc->sclk);
	if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) {
		dev_err(&pdev->dev, "Invalid slow clock rate\n");
		ret = -EINVAL;
		goto err_clk;
	}

	mr = rtt_readl(rtc, MR);

	/* unless RTT is counting at 1 Hz, re-initialize it */
	if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
		mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES);
		gpbr_writel(rtc, 0);
	}

	/* disable all interrupts (same as on shutdown path) */
	mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	rtt_writel(rtc, MR, mr);

	rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc->rtcdev)) {
		ret = PTR_ERR(rtc->rtcdev);
		goto err_clk;
	}

	rtc->rtcdev->ops = &at91_rtc_ops;
	rtc->rtcdev->range_max = U32_MAX;

	/* register irq handler after we know what name we'll use */
	ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
			       IRQF_SHARED | IRQF_COND_SUSPEND,
			       dev_name(&rtc->rtcdev->dev), rtc);
	if (ret) {
		dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
		goto err_clk;
	}

	/* NOTE:  sam9260 rev A silicon has a ROM bug which resets the
	 * RTT on at least some reboots.  If you have that chip, you must
	 * initialize the time from some external source like a GPS, wall
	 * clock, discrete RTC, etc
	 */

	if (gpbr_readl(rtc) == 0)
		dev_warn(&pdev->dev, "%s: SET TIME!\n",
				dev_name(&rtc->rtcdev->dev));

	return rtc_register_device(rtc->rtcdev);

err_clk:
	clk_disable_unprepare(rtc->sclk);

	return ret;
}

/*
 * Disable and remove the RTC driver
 */
static int at91_rtc_remove(struct platform_device *pdev)
{
	struct sam9_rtc	*rtc = platform_get_drvdata(pdev);
	u32		mr = rtt_readl(rtc, MR);

	/* disable all interrupts */
	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));

	clk_disable_unprepare(rtc->sclk);

	return 0;
}

static void at91_rtc_shutdown(struct platform_device *pdev)
{
	struct sam9_rtc	*rtc = platform_get_drvdata(pdev);
	u32		mr = rtt_readl(rtc, MR);

	rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	rtt_writel(rtc, MR, mr & ~rtc->imr);
}

#ifdef CONFIG_PM_SLEEP

/* AT91SAM9 RTC Power management control */

static int at91_rtc_suspend(struct device *dev)
{
	struct sam9_rtc	*rtc = dev_get_drvdata(dev);
	u32		mr = rtt_readl(rtc, MR);

	/*
	 * This IRQ is shared with DBGU and other hardware which isn't
	 * necessarily a wakeup event source.
	 */
	rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
	if (rtc->imr) {
		if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
			unsigned long flags;

			enable_irq_wake(rtc->irq);
			spin_lock_irqsave(&rtc->lock, flags);
			rtc->suspended = true;
			spin_unlock_irqrestore(&rtc->lock, flags);
			/* don't let RTTINC cause wakeups */
			if (mr & AT91_RTT_RTTINCIEN)
				rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
		} else
			rtt_writel(rtc, MR, mr & ~rtc->imr);
	}

	return 0;
}

static int at91_rtc_resume(struct device *dev)
{
	struct sam9_rtc	*rtc = dev_get_drvdata(dev);
	u32		mr;

	if (rtc->imr) {
		unsigned long flags;

		if (device_may_wakeup(dev))
			disable_irq_wake(rtc->irq);
		mr = rtt_readl(rtc, MR);
		rtt_writel(rtc, MR, mr | rtc->imr);

		spin_lock_irqsave(&rtc->lock, flags);
		rtc->suspended = false;
		at91_rtc_cache_events(rtc);
		at91_rtc_flush_events(rtc);
		spin_unlock_irqrestore(&rtc->lock, flags);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);

static const struct of_device_id at91_rtc_dt_ids[] = {
	{ .compatible = "atmel,at91sam9260-rtt" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);

static struct platform_driver at91_rtc_driver = {
	.probe		= at91_rtc_probe,
	.remove		= at91_rtc_remove,
	.shutdown	= at91_rtc_shutdown,
	.driver		= {
		.name	= "rtc-at91sam9",
		.pm	= &at91_rtc_pm_ops,
		.of_match_table = of_match_ptr(at91_rtc_dt_ids),
	},
};

module_platform_driver(at91_rtc_driver);

MODULE_AUTHOR("Michel Benoit");
MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
MODULE_LICENSE("GPL");
Commit	Line	Data
bc40072d	1	// SPDX-License-Identifier: GPL-2.0+
4cdf854f DB	2	/*
	3	* "RTT as Real Time Clock" driver for AT91SAM9 SoC family
	4	*
	5	* (C) 2007 Michel Benoit
	6	*
	7	* Based on rtc-at91rm9200.c by Rick Bronson
4cdf854f DB	8	*/
4cdf854f DB	9
6932ff53	10	#include <linux/clk.h>
4cdf854f DB	11	#include <linux/interrupt.h>
4cdf854f DB	12	#include <linux/ioctl.h>
9d42e465	13	#include <linux/io.h>
6932ff53	14	#include <linux/kernel.h>
43e112bb	15	#include <linux/mfd/syscon.h>
6932ff53	16	#include <linux/module.h>
1955f213	17	#include <linux/of.h>
6932ff53	18	#include <linux/platform_device.h>
43e112bb	19	#include <linux/regmap.h>
6932ff53 AB	20	#include <linux/rtc.h>
6932ff53 AB	21	#include <linux/slab.h>
603b1a23	22	#include <linux/suspend.h>
6932ff53	23	#include <linux/time.h>
4cdf854f	24
4cdf854f DB	25	/*
	26	* This driver uses two configurable hardware resources that live in the
	27	* AT91SAM9 backup power domain (intended to be powered at all times)
	28	* to implement the Real Time Clock interfaces
	29	*
	30	* - A "Real-time Timer" (RTT) counts up in seconds from a base time.
	31	* We can't assign the counter value (CRTV) ... but we can reset it.
	32	*
	33	* - One of the "General Purpose Backup Registers" (GPBRs) holds the
	34	* base time, normally an offset from the beginning of the POSIX
	35	* epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the
	36	* local timezone's offset.
	37	*
	38	* The RTC's value is the RTT counter plus that offset. The RTC's alarm
	39	* is likewise a base (ALMV) plus that offset.
	40	*
	41	* Not all RTTs will be used as RTCs; some systems have multiple RTTs to
	42	* choose from, or a "real" RTC module. All systems have multiple GPBR
	43	* registers available, likewise usable for more than "RTC" support.
	44	*/
	45
6575bd7c BB	46	#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
	47	#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
	48	#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
	49	#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
	50	#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
	51
	52	#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
	53	#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
	54
	55	#define AT91_RTT_VR 0x08 /* Real-time Value Register */
	56	#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
	57
	58	#define AT91_RTT_SR 0x0c /* Real-time Status Register */
	59	#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
	60	#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
	61
4cdf854f DB	62	/*
	63	* We store ALARM_DISABLED in ALMV to record that no alarm is set.
	64	* It's also the reset value for that field.
	65	*/
	66	#define ALARM_DISABLED ((u32)~0)
	67
	68
	69	struct sam9_rtc {
	70	void __iomem *rtt;
	71	struct rtc_device *rtcdev;
	72	u32 imr;
43e112bb BB	73	struct regmap *gpbr;
43e112bb BB	74	unsigned int gpbr_offset;
e402af6c	75	int irq;
a975f47f	76	struct clk *sclk;
603b1a23 BB	77	bool suspended;
	78	unsigned long events;
	79	spinlock_t lock;
4cdf854f DB	80	};
	81
	82	#define rtt_readl(rtc, field) \
272f1dfa	83	readl((rtc)->rtt + AT91_RTT_ ## field)
4cdf854f	84	#define rtt_writel(rtc, field, val) \
272f1dfa	85	writel((val), (rtc)->rtt + AT91_RTT_ ## field)
4cdf854f	86
43e112bb BB	87	static inline unsigned int gpbr_readl(struct sam9_rtc *rtc)
	88	{
	89	unsigned int val;
	90
	91	regmap_read(rtc->gpbr, rtc->gpbr_offset, &val);
	92
	93	return val;
	94	}
	95
	96	static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val)
	97	{
	98	regmap_write(rtc->gpbr, rtc->gpbr_offset, val);
	99	}
4cdf854f DB	100
	101	/*
	102	* Read current time and date in RTC
	103	*/
	104	static int at91_rtc_readtime(struct device dev, struct rtc_time tm)
	105	{
	106	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	107	u32 secs, secs2;
	108	u32 offset;
	109
	110	/* read current time offset */
	111	offset = gpbr_readl(rtc);
	112	if (offset == 0)
	113	return -EILSEQ;
	114
	115	/* reread the counter to help sync the two clock domains */
	116	secs = rtt_readl(rtc, VR);
	117	secs2 = rtt_readl(rtc, VR);
	118	if (secs != secs2)
	119	secs = rtt_readl(rtc, VR);
	120
8af760a3	121	rtc_time64_to_tm(offset + secs, tm);
4cdf854f	122
285166cb	123	dev_dbg(dev, "%s: %ptR\n", __func__, tm);
4cdf854f DB	124
	125	return 0;
	126	}
	127
	128	/*
	129	* Set current time and date in RTC
	130	*/
	131	static int at91_rtc_settime(struct device dev, struct rtc_time tm)
	132	{
	133	struct sam9_rtc *rtc = dev_get_drvdata(dev);
4cdf854f DB	134	u32 offset, alarm, mr;
	135	unsigned long secs;
	136
285166cb	137	dev_dbg(dev, "%s: %ptR\n", __func__, tm);
4cdf854f	138
8af760a3	139	secs = rtc_tm_to_time64(tm);
4cdf854f DB	140
	141	mr = rtt_readl(rtc, MR);
	142
	143	/* disable interrupts */
	144	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN));
	145
	146	/* read current time offset */
	147	offset = gpbr_readl(rtc);
	148
	149	/* store the new base time in a battery backup register */
	150	secs += 1;
	151	gpbr_writel(rtc, secs);
	152
	153	/* adjust the alarm time for the new base */
	154	alarm = rtt_readl(rtc, AR);
	155	if (alarm != ALARM_DISABLED) {
	156	if (offset > secs) {
	157	/* time jumped backwards, increase time until alarm */
	158	alarm += (offset - secs);
	159	} else if ((alarm + offset) > secs) {
	160	/* time jumped forwards, decrease time until alarm */
	161	alarm -= (secs - offset);
	162	} else {
	163	/* time jumped past the alarm, disable alarm */
	164	alarm = ALARM_DISABLED;
	165	mr &= ~AT91_RTT_ALMIEN;
	166	}
	167	rtt_writel(rtc, AR, alarm);
	168	}
	169
	170	/* reset the timer, and re-enable interrupts */
	171	rtt_writel(rtc, MR, mr \| AT91_RTT_RTTRST);
	172
	173	return 0;
	174	}
	175
	176	static int at91_rtc_readalarm(struct device dev, struct rtc_wkalrm alrm)
	177	{
	178	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	179	struct rtc_time *tm = &alrm->time;
	180	u32 alarm = rtt_readl(rtc, AR);
	181	u32 offset;
	182
	183	offset = gpbr_readl(rtc);
	184	if (offset == 0)
	185	return -EILSEQ;
	186
870a2761	187	memset(alrm, 0, sizeof(*alrm));
4cdf854f	188	if (alarm != ALARM_DISABLED && offset != 0) {
8af760a3	189	rtc_time64_to_tm(offset + alarm, tm);
4cdf854f	190
285166cb	191	dev_dbg(dev, "%s: %ptR\n", __func__, tm);
4cdf854f DB	192
	193	if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
	194	alrm->enabled = 1;
	195	}
	196
	197	return 0;
	198	}
	199
	200	static int at91_rtc_setalarm(struct device dev, struct rtc_wkalrm alrm)
	201	{
	202	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	203	struct rtc_time *tm = &alrm->time;
	204	unsigned long secs;
	205	u32 offset;
	206	u32 mr;
4cdf854f	207
8af760a3	208	secs = rtc_tm_to_time64(tm);
4cdf854f DB	209
	210	offset = gpbr_readl(rtc);
	211	if (offset == 0) {
	212	/* time is not set */
	213	return -EILSEQ;
	214	}
	215	mr = rtt_readl(rtc, MR);
	216	rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
	217
	218	/* alarm in the past? finish and leave disabled */
	219	if (secs <= offset) {
	220	rtt_writel(rtc, AR, ALARM_DISABLED);
	221	return 0;
	222	}
	223
	224	/* else set alarm and maybe enable it */
	225	rtt_writel(rtc, AR, secs - offset);
	226	if (alrm->enabled)
	227	rtt_writel(rtc, MR, mr \| AT91_RTT_ALMIEN);
	228
285166cb	229	dev_dbg(dev, "%s: %ptR\n", __func__, tm);
4cdf854f DB	230
	231	return 0;
	232	}
	233
16380c15 JS	234	static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	235	{
	236	struct sam9_rtc *rtc = dev_get_drvdata(dev);
	237	u32 mr = rtt_readl(rtc, MR);
	238
	239	dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
	240	if (enabled)
	241	rtt_writel(rtc, MR, mr \| AT91_RTT_ALMIEN);
	242	else
	243	rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
	244	return 0;
	245	}
	246
4cdf854f DB	247	/*
	248	* Provide additional RTC information in /proc/driver/rtc
	249	*/
	250	static int at91_rtc_proc(struct device dev, struct seq_file seq)
	251	{
	252	struct sam9_rtc *rtc = dev_get_drvdata(dev);
df2d741f	253	u32 mr = rtt_readl(rtc, MR);
4cdf854f DB	254
	255	seq_printf(seq, "update_IRQ\t: %s\n",
	256	(mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
	257	return 0;
	258	}
	259
603b1a23	260	static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc)
4cdf854f	261	{
4cdf854f	262	u32 sr, mr;
4cdf854f DB	263
	264	/* Shared interrupt may be for another device. Note: reading
	265	* SR clears it, so we must only read it in this irq handler!
	266	*/
	267	mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
9fedc9f1	268	sr = rtt_readl(rtc, SR) & (mr >> 16);
4cdf854f DB	269	if (!sr)
	270	return IRQ_NONE;
	271
	272	/* alarm status */
	273	if (sr & AT91_RTT_ALMS)
603b1a23	274	rtc->events \|= (RTC_AF \| RTC_IRQF);
4cdf854f DB	275
	276	/* timer update/increment */
	277	if (sr & AT91_RTT_RTTINC)
603b1a23 BB	278	rtc->events \|= (RTC_UF \| RTC_IRQF);
	279
	280	return IRQ_HANDLED;
	281	}
	282
	283	static void at91_rtc_flush_events(struct sam9_rtc *rtc)
	284	{
	285	if (!rtc->events)
	286	return;
4cdf854f	287
603b1a23 BB	288	rtc_update_irq(rtc->rtcdev, 1, rtc->events);
603b1a23 BB	289	rtc->events = 0;
4cdf854f	290
2a4e2b87	291	pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
603b1a23 BB	292	rtc->events >> 8, rtc->events & 0x000000FF);
603b1a23 BB	293	}
4cdf854f	294
603b1a23 BB	295	/*
	296	* IRQ handler for the RTC
	297	*/
	298	static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
	299	{
	300	struct sam9_rtc *rtc = _rtc;
	301	int ret;
	302
	303	spin_lock(&rtc->lock);
	304
	305	ret = at91_rtc_cache_events(rtc);
	306
	307	/* We're called in suspended state */
	308	if (rtc->suspended) {
	309	/* Mask irqs coming from this peripheral */
	310	rtt_writel(rtc, MR,
	311	rtt_readl(rtc, MR) &
	312	~(AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN));
	313	/* Trigger a system wakeup */
	314	pm_system_wakeup();
	315	} else {
	316	at91_rtc_flush_events(rtc);
	317	}
	318
	319	spin_unlock(&rtc->lock);
	320
	321	return ret;
4cdf854f DB	322	}
	323
	324	static const struct rtc_class_ops at91_rtc_ops = {
4cdf854f DB	325	.read_time = at91_rtc_readtime,
	326	.set_time = at91_rtc_settime,
	327	.read_alarm = at91_rtc_readalarm,
	328	.set_alarm = at91_rtc_setalarm,
	329	.proc = at91_rtc_proc,
d4035850	330	.alarm_irq_enable = at91_rtc_alarm_irq_enable,
4cdf854f DB	331	};
	332
	333	/*
	334	* Initialize and install RTC driver
	335	*/
5a167f45	336	static int at91_rtc_probe(struct platform_device *pdev)
4cdf854f	337	{
d41da3ee	338	struct resource *r;
4cdf854f	339	struct sam9_rtc *rtc;
e402af6c	340	int ret, irq;
4cdf854f	341	u32 mr;
a975f47f	342	unsigned int sclk_rate;
1a76a77c	343	struct of_phandle_args args;
4cdf854f	344
e402af6c LD	345	irq = platform_get_irq(pdev, 0);
	346	if (irq < 0) {
	347	dev_err(&pdev->dev, "failed to get interrupt resource\n");
	348	return irq;
	349	}
	350
9d42e465	351	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
4cdf854f DB	352	if (!rtc)
	353	return -ENOMEM;
	354
b7b17633	355	spin_lock_init(&rtc->lock);
e402af6c LD	356	rtc->irq = irq;
e402af6c LD	357
9fedc9f1 DB	358	/* platform setup code should have handled this; sigh */
	359	if (!device_can_wakeup(&pdev->dev))
	360	device_init_wakeup(&pdev->dev, 1);
	361
4cdf854f	362	platform_set_drvdata(pdev, rtc);
4cdf854f	363
d41da3ee BB	364	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	365	rtc->rtt = devm_ioremap_resource(&pdev->dev, r);
	366	if (IS_ERR(rtc->rtt))
	367	return PTR_ERR(rtc->rtt);
	368
1a76a77c AB	369	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
	370	"atmel,rtt-rtc-time-reg", 1, 0,
	371	&args);
	372	if (ret)
	373	return ret;
43e112bb	374
1a76a77c AB	375	rtc->gpbr = syscon_node_to_regmap(args.np);
1a76a77c AB	376	rtc->gpbr_offset = args.args[0];
43e112bb BB	377	if (IS_ERR(rtc->gpbr)) {
	378	dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n");
	379	return -ENOMEM;
	380	}
b3af8b49	381
a975f47f BB	382	rtc->sclk = devm_clk_get(&pdev->dev, NULL);
	383	if (IS_ERR(rtc->sclk))
	384	return PTR_ERR(rtc->sclk);
	385
a975f47f BB	386	ret = clk_prepare_enable(rtc->sclk);
	387	if (ret) {
	388	dev_err(&pdev->dev, "Could not enable slow clock\n");
	389	return ret;
	390	}
	391
8918bd8a AB	392	sclk_rate = clk_get_rate(rtc->sclk);
	393	if (!sclk_rate \|\| sclk_rate > AT91_RTT_RTPRES) {
	394	dev_err(&pdev->dev, "Invalid slow clock rate\n");
	395	ret = -EINVAL;
	396	goto err_clk;
	397	}
	398
4cdf854f DB	399	mr = rtt_readl(rtc, MR);
	400
	401	/* unless RTT is counting at 1 Hz, re-initialize it */
a975f47f BB	402	if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
a975f47f BB	403	mr = AT91_RTT_RTTRST \| (sclk_rate & AT91_RTT_RTPRES);
4cdf854f DB	404	gpbr_writel(rtc, 0);
	405	}
	406
	407	/* disable all interrupts (same as on shutdown path) */
	408	mr &= ~(AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
	409	rtt_writel(rtc, MR, mr);
	410
6c7293e7	411	rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
ffe60fcf AB	412	if (IS_ERR(rtc->rtcdev)) {
	413	ret = PTR_ERR(rtc->rtcdev);
	414	goto err_clk;
	415	}
4cdf854f	416
6c7293e7	417	rtc->rtcdev->ops = &at91_rtc_ops;
255c43ca	418	rtc->rtcdev->range_max = U32_MAX;
6c7293e7	419
4cdf854f	420	/* register irq handler after we know what name we'll use */
9d42e465	421	ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
603b1a23 BB	422	IRQF_SHARED \| IRQF_COND_SUSPEND,
603b1a23 BB	423	dev_name(&rtc->rtcdev->dev), rtc);
4cdf854f	424	if (ret) {
e402af6c	425	dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
ffe60fcf	426	goto err_clk;
4cdf854f DB	427	}
	428
	429	/* NOTE: sam9260 rev A silicon has a ROM bug which resets the
	430	* RTT on at least some reboots. If you have that chip, you must
	431	* initialize the time from some external source like a GPS, wall
	432	* clock, discrete RTC, etc
	433	*/
	434
	435	if (gpbr_readl(rtc) == 0)
	436	dev_warn(&pdev->dev, "%s: SET TIME!\n",
744bcb13	437	dev_name(&rtc->rtcdev->dev));
4cdf854f	438
6c7293e7	439	return rtc_register_device(rtc->rtcdev);
ffe60fcf AB	440
	441	err_clk:
	442	clk_disable_unprepare(rtc->sclk);
	443
	444	return ret;
4cdf854f DB	445	}
	446
	447	/*
	448	* Disable and remove the RTC driver
	449	*/
5a167f45	450	static int at91_rtc_remove(struct platform_device *pdev)
4cdf854f DB	451	{
	452	struct sam9_rtc *rtc = platform_get_drvdata(pdev);
	453	u32 mr = rtt_readl(rtc, MR);
	454
	455	/* disable all interrupts */
	456	rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN));
4cdf854f	457
73ab31ce	458	clk_disable_unprepare(rtc->sclk);
a975f47f	459
4cdf854f DB	460	return 0;
	461	}
	462
	463	static void at91_rtc_shutdown(struct platform_device *pdev)
	464	{
	465	struct sam9_rtc *rtc = platform_get_drvdata(pdev);
	466	u32 mr = rtt_readl(rtc, MR);
	467
	468	rtc->imr = mr & (AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
	469	rtt_writel(rtc, MR, mr & ~rtc->imr);
	470	}
	471
4dc8eb13	472	#ifdef CONFIG_PM_SLEEP
4cdf854f DB	473
	474	/* AT91SAM9 RTC Power management control */
	475
4dc8eb13	476	static int at91_rtc_suspend(struct device *dev)
4cdf854f	477	{
4dc8eb13	478	struct sam9_rtc *rtc = dev_get_drvdata(dev);
4cdf854f DB	479	u32 mr = rtt_readl(rtc, MR);
	480
	481	/*
	482	* This IRQ is shared with DBGU and other hardware which isn't
	483	* necessarily a wakeup event source.
	484	*/
	485	rtc->imr = mr & (AT91_RTT_ALMIEN \| AT91_RTT_RTTINCIEN);
	486	if (rtc->imr) {
4dc8eb13	487	if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
603b1a23 BB	488	unsigned long flags;
603b1a23 BB	489
e402af6c	490	enable_irq_wake(rtc->irq);
603b1a23 BB	491	spin_lock_irqsave(&rtc->lock, flags);
	492	rtc->suspended = true;
	493	spin_unlock_irqrestore(&rtc->lock, flags);
4cdf854f DB	494	/* don't let RTTINC cause wakeups */
	495	if (mr & AT91_RTT_RTTINCIEN)
	496	rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
	497	} else
	498	rtt_writel(rtc, MR, mr & ~rtc->imr);
	499	}
	500
	501	return 0;
	502	}
	503
4dc8eb13	504	static int at91_rtc_resume(struct device *dev)
4cdf854f	505	{
4dc8eb13	506	struct sam9_rtc *rtc = dev_get_drvdata(dev);
4cdf854f DB	507	u32 mr;
	508
	509	if (rtc->imr) {
603b1a23 BB	510	unsigned long flags;
603b1a23 BB	511
4dc8eb13	512	if (device_may_wakeup(dev))
e402af6c	513	disable_irq_wake(rtc->irq);
4cdf854f DB	514	mr = rtt_readl(rtc, MR);
4cdf854f DB	515	rtt_writel(rtc, MR, mr \| rtc->imr);
603b1a23 BB	516
	517	spin_lock_irqsave(&rtc->lock, flags);
	518	rtc->suspended = false;
	519	at91_rtc_cache_events(rtc);
	520	at91_rtc_flush_events(rtc);
	521	spin_unlock_irqrestore(&rtc->lock, flags);
4cdf854f DB	522	}
	523
	524	return 0;
	525	}
4cdf854f DB	526	#endif
4cdf854f DB	527
4dc8eb13 JH	528	static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
4dc8eb13 JH	529
07d4d724 BB	530	static const struct of_device_id at91_rtc_dt_ids[] = {
	531	{ .compatible = "atmel,at91sam9260-rtt" },
	532	{ /* sentinel */ }
	533	};
	534	MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
07d4d724	535
4cdf854f	536	static struct platform_driver at91_rtc_driver = {
205056a3	537	.probe = at91_rtc_probe,
5a167f45	538	.remove = at91_rtc_remove,
4cdf854f	539	.shutdown = at91_rtc_shutdown,
205056a3 JCPV	540	.driver = {
205056a3 JCPV	541	.name = "rtc-at91sam9",
4dc8eb13	542	.pm = &at91_rtc_pm_ops,
07d4d724	543	.of_match_table = of_match_ptr(at91_rtc_dt_ids),
205056a3	544	},
4cdf854f DB	545	};
4cdf854f DB	546
477d30d7	547	module_platform_driver(at91_rtc_driver);
4cdf854f DB	548
	549	MODULE_AUTHOR("Michel Benoit");
	550	MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
	551	MODULE_LICENSE("GPL");