Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
788b1fc6 AV |
2 | /* |
3 | * Real Time Clock interface for Linux on Atmel AT91RM9200 | |
4 | * | |
5 | * Copyright (C) 2002 Rick Bronson | |
6 | * | |
7 | * Converted to RTC class model by Andrew Victor | |
8 | * | |
9 | * Ported to Linux 2.6 by Steven Scholz | |
10 | * Based on s3c2410-rtc.c Simtec Electronics | |
11 | * | |
12 | * Based on sa1100-rtc.c by Nils Faerber | |
13 | * Based on rtc.c by Paul Gortmaker | |
788b1fc6 AV |
14 | */ |
15 | ||
788b1fc6 | 16 | #include <linux/bcd.h> |
3c7b90cb | 17 | #include <linux/bitfield.h> |
11f67a8b | 18 | #include <linux/clk.h> |
74000eb1 | 19 | #include <linux/completion.h> |
788b1fc6 AV |
20 | #include <linux/interrupt.h> |
21 | #include <linux/ioctl.h> | |
14070ade | 22 | #include <linux/io.h> |
74000eb1 AB |
23 | #include <linux/kernel.h> |
24 | #include <linux/module.h> | |
7c1b68d4 | 25 | #include <linux/of_device.h> |
74000eb1 AB |
26 | #include <linux/of.h> |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/rtc.h> | |
29 | #include <linux/spinlock.h> | |
dd1f1f39 | 30 | #include <linux/suspend.h> |
74000eb1 | 31 | #include <linux/time.h> |
8ecc0bf4 | 32 | #include <linux/uaccess.h> |
fb0d4ec4 | 33 | |
a1243b09 AB |
34 | #define AT91_RTC_CR 0x00 /* Control Register */ |
35 | #define AT91_RTC_UPDTIM BIT(0) /* Update Request Time Register */ | |
36 | #define AT91_RTC_UPDCAL BIT(1) /* Update Request Calendar Register */ | |
37 | ||
38 | #define AT91_RTC_MR 0x04 /* Mode Register */ | |
f6a46f8b AB |
39 | #define AT91_RTC_HRMOD BIT(0) /* 12/24 hour mode */ |
40 | #define AT91_RTC_NEGPPM BIT(4) /* Negative PPM correction */ | |
41 | #define AT91_RTC_CORRECTION GENMASK(14, 8) /* Slow clock correction */ | |
42 | #define AT91_RTC_HIGHPPM BIT(15) /* High PPM correction */ | |
a1243b09 AB |
43 | |
44 | #define AT91_RTC_TIMR 0x08 /* Time Register */ | |
45 | #define AT91_RTC_SEC GENMASK(6, 0) /* Current Second */ | |
46 | #define AT91_RTC_MIN GENMASK(14, 8) /* Current Minute */ | |
47 | #define AT91_RTC_HOUR GENMASK(21, 16) /* Current Hour */ | |
48 | #define AT91_RTC_AMPM BIT(22) /* Ante Meridiem Post Meridiem Indicator */ | |
49 | ||
50 | #define AT91_RTC_CALR 0x0c /* Calendar Register */ | |
51 | #define AT91_RTC_CENT GENMASK(6, 0) /* Current Century */ | |
52 | #define AT91_RTC_YEAR GENMASK(15, 8) /* Current Year */ | |
53 | #define AT91_RTC_MONTH GENMASK(20, 16) /* Current Month */ | |
54 | #define AT91_RTC_DAY GENMASK(23, 21) /* Current Day */ | |
55 | #define AT91_RTC_DATE GENMASK(29, 24) /* Current Date */ | |
56 | ||
57 | #define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */ | |
58 | #define AT91_RTC_SECEN BIT(7) /* Second Alarm Enable */ | |
59 | #define AT91_RTC_MINEN BIT(15) /* Minute Alarm Enable */ | |
60 | #define AT91_RTC_HOUREN BIT(23) /* Hour Alarm Enable */ | |
61 | ||
62 | #define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */ | |
63 | #define AT91_RTC_MTHEN BIT(23) /* Month Alarm Enable */ | |
64 | #define AT91_RTC_DATEEN BIT(31) /* Date Alarm Enable */ | |
65 | ||
66 | #define AT91_RTC_SR 0x18 /* Status Register */ | |
67 | #define AT91_RTC_ACKUPD BIT(0) /* Acknowledge for Update */ | |
68 | #define AT91_RTC_ALARM BIT(1) /* Alarm Flag */ | |
69 | #define AT91_RTC_SECEV BIT(2) /* Second Event */ | |
70 | #define AT91_RTC_TIMEV BIT(3) /* Time Event */ | |
71 | #define AT91_RTC_CALEV BIT(4) /* Calendar Event */ | |
72 | ||
73 | #define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */ | |
74 | #define AT91_RTC_IER 0x20 /* Interrupt Enable Register */ | |
75 | #define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */ | |
76 | #define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */ | |
77 | ||
78 | #define AT91_RTC_VER 0x2c /* Valid Entry Register */ | |
79 | #define AT91_RTC_NVTIM BIT(0) /* Non valid Time */ | |
80 | #define AT91_RTC_NVCAL BIT(1) /* Non valid Calendar */ | |
81 | #define AT91_RTC_NVTIMALR BIT(2) /* Non valid Time Alarm */ | |
82 | #define AT91_RTC_NVCALALR BIT(3) /* Non valid Calendar Alarm */ | |
d73e3cd7 | 83 | |
f6a46f8b AB |
84 | #define AT91_RTC_CORR_DIVIDEND 3906000 |
85 | #define AT91_RTC_CORR_LOW_RATIO 20 | |
86 | ||
d28bdfc5 | 87 | #define at91_rtc_read(field) \ |
6da7bb1e | 88 | readl_relaxed(at91_rtc_regs + field) |
d28bdfc5 | 89 | #define at91_rtc_write(field, val) \ |
6da7bb1e | 90 | writel_relaxed((val), at91_rtc_regs + field) |
788b1fc6 | 91 | |
de645475 | 92 | struct at91_rtc_config { |
e9f08bbe | 93 | bool use_shadow_imr; |
f6a46f8b | 94 | bool has_correction; |
de645475 JH |
95 | }; |
96 | ||
97 | static const struct at91_rtc_config *at91_rtc_config; | |
788b1fc6 | 98 | static DECLARE_COMPLETION(at91_rtc_updated); |
2fe121e1 | 99 | static DECLARE_COMPLETION(at91_rtc_upd_rdy); |
d28bdfc5 JCPV |
100 | static void __iomem *at91_rtc_regs; |
101 | static int irq; | |
e9f08bbe JH |
102 | static DEFINE_SPINLOCK(at91_rtc_lock); |
103 | static u32 at91_rtc_shadow_imr; | |
dd1f1f39 BB |
104 | static bool suspended; |
105 | static DEFINE_SPINLOCK(suspended_lock); | |
106 | static unsigned long cached_events; | |
107 | static u32 at91_rtc_imr; | |
11f67a8b | 108 | static struct clk *sclk; |
788b1fc6 | 109 | |
e304fcd0 JH |
110 | static void at91_rtc_write_ier(u32 mask) |
111 | { | |
e9f08bbe JH |
112 | unsigned long flags; |
113 | ||
114 | spin_lock_irqsave(&at91_rtc_lock, flags); | |
115 | at91_rtc_shadow_imr |= mask; | |
e304fcd0 | 116 | at91_rtc_write(AT91_RTC_IER, mask); |
e9f08bbe | 117 | spin_unlock_irqrestore(&at91_rtc_lock, flags); |
e304fcd0 JH |
118 | } |
119 | ||
120 | static void at91_rtc_write_idr(u32 mask) | |
121 | { | |
e9f08bbe JH |
122 | unsigned long flags; |
123 | ||
124 | spin_lock_irqsave(&at91_rtc_lock, flags); | |
e304fcd0 | 125 | at91_rtc_write(AT91_RTC_IDR, mask); |
e9f08bbe JH |
126 | /* |
127 | * Register read back (of any RTC-register) needed to make sure | |
128 | * IDR-register write has reached the peripheral before updating | |
129 | * shadow mask. | |
130 | * | |
131 | * Note that there is still a possibility that the mask is updated | |
132 | * before interrupts have actually been disabled in hardware. The only | |
2dc5e3fb | 133 | * way to be certain would be to poll the IMR-register, which is |
e9f08bbe JH |
134 | * the very register we are trying to emulate. The register read back |
135 | * is a reasonable heuristic. | |
136 | */ | |
137 | at91_rtc_read(AT91_RTC_SR); | |
138 | at91_rtc_shadow_imr &= ~mask; | |
139 | spin_unlock_irqrestore(&at91_rtc_lock, flags); | |
e304fcd0 JH |
140 | } |
141 | ||
142 | static u32 at91_rtc_read_imr(void) | |
143 | { | |
e9f08bbe JH |
144 | unsigned long flags; |
145 | u32 mask; | |
146 | ||
147 | if (at91_rtc_config->use_shadow_imr) { | |
148 | spin_lock_irqsave(&at91_rtc_lock, flags); | |
149 | mask = at91_rtc_shadow_imr; | |
150 | spin_unlock_irqrestore(&at91_rtc_lock, flags); | |
151 | } else { | |
152 | mask = at91_rtc_read(AT91_RTC_IMR); | |
153 | } | |
154 | ||
155 | return mask; | |
e304fcd0 JH |
156 | } |
157 | ||
788b1fc6 AV |
158 | /* |
159 | * Decode time/date into rtc_time structure | |
160 | */ | |
e7a8bb12 AM |
161 | static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg, |
162 | struct rtc_time *tm) | |
788b1fc6 AV |
163 | { |
164 | unsigned int time, date; | |
165 | ||
166 | /* must read twice in case it changes */ | |
167 | do { | |
d28bdfc5 JCPV |
168 | time = at91_rtc_read(timereg); |
169 | date = at91_rtc_read(calreg); | |
170 | } while ((time != at91_rtc_read(timereg)) || | |
171 | (date != at91_rtc_read(calreg))); | |
788b1fc6 | 172 | |
3c7b90cb AB |
173 | tm->tm_sec = bcd2bin(FIELD_GET(AT91_RTC_SEC, time)); |
174 | tm->tm_min = bcd2bin(FIELD_GET(AT91_RTC_MIN, time)); | |
175 | tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time)); | |
788b1fc6 AV |
176 | |
177 | /* | |
178 | * The Calendar Alarm register does not have a field for | |
eaa1dc7b | 179 | * the year - so these will return an invalid value. |
788b1fc6 | 180 | */ |
fe20ba70 | 181 | tm->tm_year = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */ |
3c7b90cb | 182 | tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */ |
788b1fc6 | 183 | |
3c7b90cb AB |
184 | tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1; /* day of the week [0-6], Sunday=0 */ |
185 | tm->tm_mon = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1; | |
186 | tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date)); | |
788b1fc6 AV |
187 | } |
188 | ||
189 | /* | |
190 | * Read current time and date in RTC | |
191 | */ | |
192 | static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) | |
193 | { | |
194 | at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm); | |
195 | tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); | |
196 | tm->tm_year = tm->tm_year - 1900; | |
197 | ||
d422f883 | 198 | dev_dbg(dev, "%s(): %ptR\n", __func__, tm); |
788b1fc6 AV |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* | |
204 | * Set current time and date in RTC | |
205 | */ | |
206 | static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) | |
207 | { | |
208 | unsigned long cr; | |
209 | ||
d422f883 | 210 | dev_dbg(dev, "%s(): %ptR\n", __func__, tm); |
788b1fc6 | 211 | |
2fe121e1 BB |
212 | wait_for_completion(&at91_rtc_upd_rdy); |
213 | ||
788b1fc6 | 214 | /* Stop Time/Calendar from counting */ |
d28bdfc5 JCPV |
215 | cr = at91_rtc_read(AT91_RTC_CR); |
216 | at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM); | |
788b1fc6 | 217 | |
e304fcd0 | 218 | at91_rtc_write_ier(AT91_RTC_ACKUPD); |
e7a8bb12 | 219 | wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */ |
e304fcd0 | 220 | at91_rtc_write_idr(AT91_RTC_ACKUPD); |
788b1fc6 | 221 | |
d28bdfc5 | 222 | at91_rtc_write(AT91_RTC_TIMR, |
3c7b90cb AB |
223 | FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec)) |
224 | | FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min)) | |
225 | | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour))); | |
788b1fc6 | 226 | |
d28bdfc5 | 227 | at91_rtc_write(AT91_RTC_CALR, |
3c7b90cb AB |
228 | FIELD_PREP(AT91_RTC_CENT, |
229 | bin2bcd((tm->tm_year + 1900) / 100)) | |
230 | | FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100)) | |
231 | | FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1)) | |
232 | | FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1)) | |
233 | | FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday))); | |
788b1fc6 AV |
234 | |
235 | /* Restart Time/Calendar */ | |
d28bdfc5 | 236 | cr = at91_rtc_read(AT91_RTC_CR); |
2fe121e1 | 237 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV); |
d28bdfc5 | 238 | at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM)); |
2fe121e1 | 239 | at91_rtc_write_ier(AT91_RTC_SECEV); |
788b1fc6 AV |
240 | |
241 | return 0; | |
242 | } | |
243 | ||
244 | /* | |
245 | * Read alarm time and date in RTC | |
246 | */ | |
247 | static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
248 | { | |
249 | struct rtc_time *tm = &alrm->time; | |
250 | ||
251 | at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm); | |
eaa1dc7b | 252 | tm->tm_year = -1; |
788b1fc6 | 253 | |
e304fcd0 | 254 | alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM) |
a2db8dfc DB |
255 | ? 1 : 0; |
256 | ||
d422f883 | 257 | dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm, |
eaa1dc7b | 258 | alrm->enabled ? "en" : "dis"); |
788b1fc6 AV |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263 | /* | |
264 | * Set alarm time and date in RTC | |
265 | */ | |
266 | static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
267 | { | |
565205d5 | 268 | struct rtc_time tm = alrm->time; |
788b1fc6 | 269 | |
e304fcd0 | 270 | at91_rtc_write_idr(AT91_RTC_ALARM); |
d28bdfc5 | 271 | at91_rtc_write(AT91_RTC_TIMALR, |
3c7b90cb AB |
272 | FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec)) |
273 | | FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min)) | |
274 | | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour)) | |
788b1fc6 | 275 | | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN); |
d28bdfc5 | 276 | at91_rtc_write(AT91_RTC_CALALR, |
3c7b90cb AB |
277 | FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1)) |
278 | | FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday)) | |
788b1fc6 AV |
279 | | AT91_RTC_DATEEN | AT91_RTC_MTHEN); |
280 | ||
449321b3 | 281 | if (alrm->enabled) { |
d28bdfc5 | 282 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
e304fcd0 | 283 | at91_rtc_write_ier(AT91_RTC_ALARM); |
449321b3 | 284 | } |
5d4675a8 | 285 | |
d422f883 | 286 | dev_dbg(dev, "%s(): %ptR\n", __func__, &tm); |
788b1fc6 AV |
287 | |
288 | return 0; | |
289 | } | |
290 | ||
16380c15 JS |
291 | static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
292 | { | |
6588208c | 293 | dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled); |
16380c15 JS |
294 | |
295 | if (enabled) { | |
d28bdfc5 | 296 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
e304fcd0 | 297 | at91_rtc_write_ier(AT91_RTC_ALARM); |
e24b0bfa | 298 | } else |
e304fcd0 | 299 | at91_rtc_write_idr(AT91_RTC_ALARM); |
16380c15 JS |
300 | |
301 | return 0; | |
302 | } | |
788b1fc6 | 303 | |
f6a46f8b AB |
304 | static int at91_rtc_readoffset(struct device *dev, long *offset) |
305 | { | |
306 | u32 mr = at91_rtc_read(AT91_RTC_MR); | |
307 | long val = FIELD_GET(AT91_RTC_CORRECTION, mr); | |
308 | ||
309 | if (!val) { | |
310 | *offset = 0; | |
311 | return 0; | |
312 | } | |
313 | ||
314 | val++; | |
315 | ||
316 | if (!(mr & AT91_RTC_NEGPPM)) | |
317 | val = -val; | |
318 | ||
319 | if (!(mr & AT91_RTC_HIGHPPM)) | |
320 | val *= AT91_RTC_CORR_LOW_RATIO; | |
321 | ||
322 | *offset = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, val); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int at91_rtc_setoffset(struct device *dev, long offset) | |
328 | { | |
329 | long corr; | |
330 | u32 mr; | |
331 | ||
332 | if (offset > AT91_RTC_CORR_DIVIDEND / 2) | |
333 | return -ERANGE; | |
334 | if (offset < -AT91_RTC_CORR_DIVIDEND / 2) | |
335 | return -ERANGE; | |
336 | ||
337 | mr = at91_rtc_read(AT91_RTC_MR); | |
338 | mr &= ~(AT91_RTC_NEGPPM | AT91_RTC_CORRECTION | AT91_RTC_HIGHPPM); | |
339 | ||
340 | if (offset > 0) | |
341 | mr |= AT91_RTC_NEGPPM; | |
342 | else | |
343 | offset = -offset; | |
344 | ||
345 | /* offset less than 764 ppb, disable correction*/ | |
346 | if (offset < 764) { | |
347 | at91_rtc_write(AT91_RTC_MR, mr & ~AT91_RTC_NEGPPM); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | /* | |
353 | * 29208 ppb is the perfect cutoff between low range and high range | |
354 | * low range values are never better than high range value after that. | |
355 | */ | |
356 | if (offset < 29208) { | |
357 | corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset * AT91_RTC_CORR_LOW_RATIO); | |
358 | } else { | |
359 | corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset); | |
360 | mr |= AT91_RTC_HIGHPPM; | |
361 | } | |
362 | ||
363 | if (corr > 128) | |
364 | corr = 128; | |
365 | ||
366 | mr |= FIELD_PREP(AT91_RTC_CORRECTION, corr - 1); | |
367 | ||
368 | at91_rtc_write(AT91_RTC_MR, mr); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
788b1fc6 AV |
373 | /* |
374 | * IRQ handler for the RTC | |
375 | */ | |
7d12e780 | 376 | static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id) |
788b1fc6 | 377 | { |
e7a8bb12 | 378 | struct platform_device *pdev = dev_id; |
788b1fc6 AV |
379 | struct rtc_device *rtc = platform_get_drvdata(pdev); |
380 | unsigned int rtsr; | |
381 | unsigned long events = 0; | |
dd1f1f39 | 382 | int ret = IRQ_NONE; |
788b1fc6 | 383 | |
dd1f1f39 | 384 | spin_lock(&suspended_lock); |
e304fcd0 | 385 | rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr(); |
788b1fc6 AV |
386 | if (rtsr) { /* this interrupt is shared! Is it ours? */ |
387 | if (rtsr & AT91_RTC_ALARM) | |
388 | events |= (RTC_AF | RTC_IRQF); | |
2fe121e1 BB |
389 | if (rtsr & AT91_RTC_SECEV) { |
390 | complete(&at91_rtc_upd_rdy); | |
391 | at91_rtc_write_idr(AT91_RTC_SECEV); | |
392 | } | |
788b1fc6 AV |
393 | if (rtsr & AT91_RTC_ACKUPD) |
394 | complete(&at91_rtc_updated); | |
395 | ||
d28bdfc5 | 396 | at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */ |
788b1fc6 | 397 | |
dd1f1f39 BB |
398 | if (!suspended) { |
399 | rtc_update_irq(rtc, 1, events); | |
788b1fc6 | 400 | |
dd1f1f39 BB |
401 | dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n", |
402 | __func__, events >> 8, events & 0x000000FF); | |
403 | } else { | |
404 | cached_events |= events; | |
405 | at91_rtc_write_idr(at91_rtc_imr); | |
406 | pm_system_wakeup(); | |
407 | } | |
788b1fc6 | 408 | |
dd1f1f39 | 409 | ret = IRQ_HANDLED; |
788b1fc6 | 410 | } |
88601683 | 411 | spin_unlock(&suspended_lock); |
dd1f1f39 BB |
412 | |
413 | return ret; | |
788b1fc6 AV |
414 | } |
415 | ||
de645475 JH |
416 | static const struct at91_rtc_config at91rm9200_config = { |
417 | }; | |
418 | ||
bba00e59 JH |
419 | static const struct at91_rtc_config at91sam9x5_config = { |
420 | .use_shadow_imr = true, | |
421 | }; | |
422 | ||
f6a46f8b AB |
423 | static const struct at91_rtc_config sama5d4_config = { |
424 | .has_correction = true, | |
425 | }; | |
426 | ||
de645475 JH |
427 | static const struct of_device_id at91_rtc_dt_ids[] = { |
428 | { | |
429 | .compatible = "atmel,at91rm9200-rtc", | |
430 | .data = &at91rm9200_config, | |
bba00e59 JH |
431 | }, { |
432 | .compatible = "atmel,at91sam9x5-rtc", | |
433 | .data = &at91sam9x5_config, | |
ca3fdc98 AB |
434 | }, { |
435 | .compatible = "atmel,sama5d4-rtc", | |
f6a46f8b | 436 | .data = &sama5d4_config, |
ca3fdc98 AB |
437 | }, { |
438 | .compatible = "atmel,sama5d2-rtc", | |
f6a46f8b | 439 | .data = &sama5d4_config, |
bfca1c92 AB |
440 | }, { |
441 | .compatible = "microchip,sam9x60-rtc", | |
442 | .data = &sama5d4_config, | |
de645475 JH |
443 | }, { |
444 | /* sentinel */ | |
445 | } | |
446 | }; | |
447 | MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids); | |
de645475 | 448 | |
ff8371ac | 449 | static const struct rtc_class_ops at91_rtc_ops = { |
788b1fc6 AV |
450 | .read_time = at91_rtc_readtime, |
451 | .set_time = at91_rtc_settime, | |
452 | .read_alarm = at91_rtc_readalarm, | |
453 | .set_alarm = at91_rtc_setalarm, | |
16380c15 | 454 | .alarm_irq_enable = at91_rtc_alarm_irq_enable, |
788b1fc6 AV |
455 | }; |
456 | ||
f6a46f8b AB |
457 | static const struct rtc_class_ops sama5d4_rtc_ops = { |
458 | .read_time = at91_rtc_readtime, | |
459 | .set_time = at91_rtc_settime, | |
460 | .read_alarm = at91_rtc_readalarm, | |
461 | .set_alarm = at91_rtc_setalarm, | |
462 | .alarm_irq_enable = at91_rtc_alarm_irq_enable, | |
463 | .set_offset = at91_rtc_setoffset, | |
464 | .read_offset = at91_rtc_readoffset, | |
465 | }; | |
466 | ||
788b1fc6 AV |
467 | /* |
468 | * Initialize and install RTC driver | |
469 | */ | |
470 | static int __init at91_rtc_probe(struct platform_device *pdev) | |
471 | { | |
472 | struct rtc_device *rtc; | |
d28bdfc5 JCPV |
473 | struct resource *regs; |
474 | int ret = 0; | |
788b1fc6 | 475 | |
288d9cf1 | 476 | at91_rtc_config = of_device_get_match_data(&pdev->dev); |
de645475 JH |
477 | if (!at91_rtc_config) |
478 | return -ENODEV; | |
479 | ||
d28bdfc5 JCPV |
480 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
481 | if (!regs) { | |
482 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
483 | return -ENXIO; | |
484 | } | |
485 | ||
486 | irq = platform_get_irq(pdev, 0); | |
faac9102 | 487 | if (irq < 0) |
d28bdfc5 | 488 | return -ENXIO; |
d28bdfc5 | 489 | |
f3766250 SK |
490 | at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start, |
491 | resource_size(regs)); | |
d28bdfc5 JCPV |
492 | if (!at91_rtc_regs) { |
493 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
494 | return -ENOMEM; | |
495 | } | |
496 | ||
735ae205 AB |
497 | rtc = devm_rtc_allocate_device(&pdev->dev); |
498 | if (IS_ERR(rtc)) | |
499 | return PTR_ERR(rtc); | |
500 | platform_set_drvdata(pdev, rtc); | |
501 | ||
11f67a8b AB |
502 | sclk = devm_clk_get(&pdev->dev, NULL); |
503 | if (IS_ERR(sclk)) | |
504 | return PTR_ERR(sclk); | |
505 | ||
506 | ret = clk_prepare_enable(sclk); | |
507 | if (ret) { | |
508 | dev_err(&pdev->dev, "Could not enable slow clock\n"); | |
509 | return ret; | |
510 | } | |
511 | ||
d28bdfc5 | 512 | at91_rtc_write(AT91_RTC_CR, 0); |
f6a46f8b | 513 | at91_rtc_write(AT91_RTC_MR, at91_rtc_read(AT91_RTC_MR) & ~AT91_RTC_HRMOD); |
788b1fc6 AV |
514 | |
515 | /* Disable all interrupts */ | |
e304fcd0 | 516 | at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM | |
e7a8bb12 AM |
517 | AT91_RTC_SECEV | AT91_RTC_TIMEV | |
518 | AT91_RTC_CALEV); | |
788b1fc6 | 519 | |
f3766250 | 520 | ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt, |
dd1f1f39 BB |
521 | IRQF_SHARED | IRQF_COND_SUSPEND, |
522 | "at91_rtc", pdev); | |
788b1fc6 | 523 | if (ret) { |
6588208c | 524 | dev_err(&pdev->dev, "IRQ %d already in use.\n", irq); |
11f67a8b | 525 | goto err_clk; |
788b1fc6 AV |
526 | } |
527 | ||
5d4675a8 DB |
528 | /* cpu init code should really have flagged this device as |
529 | * being wake-capable; if it didn't, do that here. | |
530 | */ | |
531 | if (!device_can_wakeup(&pdev->dev)) | |
532 | device_init_wakeup(&pdev->dev, 1); | |
533 | ||
f6a46f8b AB |
534 | if (at91_rtc_config->has_correction) |
535 | rtc->ops = &sama5d4_rtc_ops; | |
536 | else | |
537 | rtc->ops = &at91_rtc_ops; | |
538 | ||
6c78a872 AB |
539 | rtc->range_min = RTC_TIMESTAMP_BEGIN_1900; |
540 | rtc->range_max = RTC_TIMESTAMP_END_2099; | |
fdcfd854 | 541 | ret = devm_rtc_register_device(rtc); |
735ae205 | 542 | if (ret) |
11f67a8b | 543 | goto err_clk; |
788b1fc6 | 544 | |
2fe121e1 BB |
545 | /* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy |
546 | * completion. | |
547 | */ | |
548 | at91_rtc_write_ier(AT91_RTC_SECEV); | |
549 | ||
6588208c | 550 | dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n"); |
788b1fc6 | 551 | return 0; |
11f67a8b AB |
552 | |
553 | err_clk: | |
554 | clk_disable_unprepare(sclk); | |
555 | ||
556 | return ret; | |
788b1fc6 AV |
557 | } |
558 | ||
559 | /* | |
560 | * Disable and remove the RTC driver | |
561 | */ | |
5d4675a8 | 562 | static int __exit at91_rtc_remove(struct platform_device *pdev) |
788b1fc6 | 563 | { |
788b1fc6 | 564 | /* Disable all interrupts */ |
e304fcd0 | 565 | at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM | |
e7a8bb12 AM |
566 | AT91_RTC_SECEV | AT91_RTC_TIMEV | |
567 | AT91_RTC_CALEV); | |
788b1fc6 | 568 | |
11f67a8b AB |
569 | clk_disable_unprepare(sclk); |
570 | ||
788b1fc6 AV |
571 | return 0; |
572 | } | |
573 | ||
51a0d036 JH |
574 | static void at91_rtc_shutdown(struct platform_device *pdev) |
575 | { | |
576 | /* Disable all interrupts */ | |
577 | at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM | | |
578 | AT91_RTC_SECEV | AT91_RTC_TIMEV | | |
579 | AT91_RTC_CALEV); | |
580 | } | |
581 | ||
6975a9c1 | 582 | #ifdef CONFIG_PM_SLEEP |
788b1fc6 AV |
583 | |
584 | /* AT91RM9200 RTC Power management control */ | |
585 | ||
dac94d9e | 586 | static int at91_rtc_suspend(struct device *dev) |
788b1fc6 | 587 | { |
90b4d648 DB |
588 | /* this IRQ is shared with DBGU and other hardware which isn't |
589 | * necessarily doing PM like we are... | |
590 | */ | |
921372bf WY |
591 | at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
592 | ||
e304fcd0 | 593 | at91_rtc_imr = at91_rtc_read_imr() |
e24b0bfa JH |
594 | & (AT91_RTC_ALARM|AT91_RTC_SECEV); |
595 | if (at91_rtc_imr) { | |
dd1f1f39 BB |
596 | if (device_may_wakeup(dev)) { |
597 | unsigned long flags; | |
598 | ||
d28bdfc5 | 599 | enable_irq_wake(irq); |
dd1f1f39 BB |
600 | |
601 | spin_lock_irqsave(&suspended_lock, flags); | |
602 | suspended = true; | |
603 | spin_unlock_irqrestore(&suspended_lock, flags); | |
604 | } else { | |
e304fcd0 | 605 | at91_rtc_write_idr(at91_rtc_imr); |
dd1f1f39 | 606 | } |
e24b0bfa | 607 | } |
788b1fc6 AV |
608 | return 0; |
609 | } | |
610 | ||
dac94d9e | 611 | static int at91_rtc_resume(struct device *dev) |
788b1fc6 | 612 | { |
dd1f1f39 BB |
613 | struct rtc_device *rtc = dev_get_drvdata(dev); |
614 | ||
e24b0bfa | 615 | if (at91_rtc_imr) { |
dd1f1f39 BB |
616 | if (device_may_wakeup(dev)) { |
617 | unsigned long flags; | |
618 | ||
619 | spin_lock_irqsave(&suspended_lock, flags); | |
620 | ||
621 | if (cached_events) { | |
622 | rtc_update_irq(rtc, 1, cached_events); | |
623 | cached_events = 0; | |
624 | } | |
625 | ||
626 | suspended = false; | |
627 | spin_unlock_irqrestore(&suspended_lock, flags); | |
628 | ||
d28bdfc5 | 629 | disable_irq_wake(irq); |
dd1f1f39 BB |
630 | } |
631 | at91_rtc_write_ier(at91_rtc_imr); | |
90b4d648 | 632 | } |
788b1fc6 AV |
633 | return 0; |
634 | } | |
788b1fc6 AV |
635 | #endif |
636 | ||
6975a9c1 JH |
637 | static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume); |
638 | ||
788b1fc6 | 639 | static struct platform_driver at91_rtc_driver = { |
5d4675a8 | 640 | .remove = __exit_p(at91_rtc_remove), |
51a0d036 | 641 | .shutdown = at91_rtc_shutdown, |
788b1fc6 AV |
642 | .driver = { |
643 | .name = "at91_rtc", | |
6975a9c1 | 644 | .pm = &at91_rtc_pm_ops, |
7c1b68d4 | 645 | .of_match_table = of_match_ptr(at91_rtc_dt_ids), |
788b1fc6 AV |
646 | }, |
647 | }; | |
648 | ||
ac36960f | 649 | module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe); |
788b1fc6 AV |
650 | |
651 | MODULE_AUTHOR("Rick Bronson"); | |
652 | MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200"); | |
653 | MODULE_LICENSE("GPL"); | |
ad28a07b | 654 | MODULE_ALIAS("platform:at91_rtc"); |