[linux-block.git] / drivers / rtc / rtc-armada38x.c

/*
 * RTC driver for the Armada 38x Marvell SoCs
 *
 * Copyright (C) 2015 Marvell
 *
 * Gregory Clement <gregory.clement@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of the
 * License, or (at your option) any later version.
 *
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>

#define RTC_STATUS	    0x0
#define RTC_STATUS_ALARM1	    BIT(0)
#define RTC_STATUS_ALARM2	    BIT(1)
#define RTC_IRQ1_CONF	    0x4
#define RTC_IRQ2_CONF	    0x8
#define RTC_IRQ_AL_EN		    BIT(0)
#define RTC_IRQ_FREQ_EN		    BIT(1)
#define RTC_IRQ_FREQ_1HZ	    BIT(2)
#define RTC_CCR		    0x18
#define RTC_CCR_MODE		    BIT(15)
#define RTC_CONF_TEST	    0x1C
#define RTC_NOMINAL_TIMING	    BIT(13)

#define RTC_TIME	    0xC
#define RTC_ALARM1	    0x10
#define RTC_ALARM2	    0x14

/* Armada38x SoC registers  */
#define RTC_38X_BRIDGE_TIMING_CTL   0x0
#define RTC_38X_PERIOD_OFFS		0
#define RTC_38X_PERIOD_MASK		(0x3FF << RTC_38X_PERIOD_OFFS)
#define RTC_38X_READ_DELAY_OFFS		26
#define RTC_38X_READ_DELAY_MASK		(0x1F << RTC_38X_READ_DELAY_OFFS)

/* Armada 7K/8K registers  */
#define RTC_8K_BRIDGE_TIMING_CTL0    0x0
#define RTC_8K_WRCLK_PERIOD_OFFS	0
#define RTC_8K_WRCLK_PERIOD_MASK	(0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
#define RTC_8K_WRCLK_SETUP_OFFS		16
#define RTC_8K_WRCLK_SETUP_MASK		(0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
#define RTC_8K_BRIDGE_TIMING_CTL1   0x4
#define RTC_8K_READ_DELAY_OFFS		0
#define RTC_8K_READ_DELAY_MASK		(0xFFFF << RTC_8K_READ_DELAY_OFFS)

#define RTC_8K_ISR		    0x10
#define RTC_8K_IMR		    0x14
#define RTC_8K_ALARM2			BIT(0)

#define SOC_RTC_INTERRUPT	    0x8
#define SOC_RTC_ALARM1			BIT(0)
#define SOC_RTC_ALARM2			BIT(1)
#define SOC_RTC_ALARM1_MASK		BIT(2)
#define SOC_RTC_ALARM2_MASK		BIT(3)

#define SAMPLE_NR 100

struct value_to_freq {
	u32 value;
	u8 freq;
};

struct armada38x_rtc {
	struct rtc_device   *rtc_dev;
	void __iomem	    *regs;
	void __iomem	    *regs_soc;
	spinlock_t	    lock;
	int		    irq;
	bool		    initialized;
	struct value_to_freq *val_to_freq;
	struct armada38x_rtc_data *data;
};

#define ALARM1	0
#define ALARM2	1

#define ALARM_REG(base, alarm)	 ((base) + (alarm) * sizeof(u32))

struct armada38x_rtc_data {
	/* Initialize the RTC-MBUS bridge timing */
	void (*update_mbus_timing)(struct armada38x_rtc *rtc);
	u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
	void (*clear_isr)(struct armada38x_rtc *rtc);
	void (*unmask_interrupt)(struct armada38x_rtc *rtc);
	u32 alarm;
};

/*
 * According to the datasheet, the OS should wait 5us after every
 * register write to the RTC hard macro so that the required update
 * can occur without holding off the system bus
 * According to errata RES-3124064, Write to any RTC register
 * may fail. As a workaround, before writing to RTC
 * register, issue a dummy write of 0x0 twice to RTC Status
 * register.
 */

static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
{
	writel(0, rtc->regs + RTC_STATUS);
	writel(0, rtc->regs + RTC_STATUS);
	writel(val, rtc->regs + offset);
	udelay(5);
}

/* Update RTC-MBUS bridge timing parameters */
static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
{
	u32 reg;

	reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
	reg &= ~RTC_38X_PERIOD_MASK;
	reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
	reg &= ~RTC_38X_READ_DELAY_MASK;
	reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
	writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
}

static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
{
	u32 reg;

	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
	reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
	reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
	reg &= ~RTC_8K_WRCLK_SETUP_MASK;
	reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);

	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
	reg &= ~RTC_8K_READ_DELAY_MASK;
	reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
}

static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
{
	return readl(rtc->regs + rtc_reg);
}

static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
{
	int i, index_max = 0, max = 0;

	for (i = 0; i < SAMPLE_NR; i++) {
		rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
		rtc->val_to_freq[i].freq = 0;
	}

	for (i = 0; i < SAMPLE_NR; i++) {
		int j = 0;
		u32 value = rtc->val_to_freq[i].value;

		while (rtc->val_to_freq[j].freq) {
			if (rtc->val_to_freq[j].value == value) {
				rtc->val_to_freq[j].freq++;
				break;
			}
			j++;
		}

		if (!rtc->val_to_freq[j].freq) {
			rtc->val_to_freq[j].value = value;
			rtc->val_to_freq[j].freq = 1;
		}

		if (rtc->val_to_freq[j].freq > max) {
			index_max = j;
			max = rtc->val_to_freq[j].freq;
		}

		/*
		 * If a value already has half of the sample this is the most
		 * frequent one and we can stop the research right now
		 */
		if (max > SAMPLE_NR / 2)
			break;
	}

	return rtc->val_to_freq[index_max].value;
}

static void armada38x_clear_isr(struct armada38x_rtc *rtc)
{
	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);

	writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
}

static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
{
	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);

	writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
}

static void armada8k_clear_isr(struct armada38x_rtc *rtc)
{
	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
}

static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
{
	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
}

static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long time, flags;

	spin_lock_irqsave(&rtc->lock, flags);
	time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
	spin_unlock_irqrestore(&rtc->lock, flags);

	rtc_time_to_tm(time, tm);

	return 0;
}

static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
{
	u32 reg;

	reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
	/* If bits [7:0] are non-zero, assume RTC was uninitialized */
	if (reg & 0xff) {
		rtc_delayed_write(0, rtc, RTC_CONF_TEST);
		msleep(500); /* Oscillator startup time */
		rtc_delayed_write(0, rtc, RTC_TIME);
		rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc,
				  RTC_STATUS);
		rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
	}
	rtc->initialized = true;
}

static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	int ret = 0;
	unsigned long time, flags;

	ret = rtc_tm_to_time(tm, &time);

	if (ret)
		goto out;

	if (!rtc->initialized)
		armada38x_rtc_reset(rtc);

	spin_lock_irqsave(&rtc->lock, flags);
	rtc_delayed_write(time, rtc, RTC_TIME);
	spin_unlock_irqrestore(&rtc->lock, flags);

out:
	return ret;
}

static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long time, flags;
	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
	u32 val;

	spin_lock_irqsave(&rtc->lock, flags);

	time = rtc->data->read_rtc_reg(rtc, reg);
	val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;

	spin_unlock_irqrestore(&rtc->lock, flags);

	alrm->enabled = val ? 1 : 0;
	rtc_time_to_tm(time,  &alrm->time);

	return 0;
}

static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
	unsigned long time, flags;
	int ret = 0;

	ret = rtc_tm_to_time(&alrm->time, &time);

	if (ret)
		goto out;

	spin_lock_irqsave(&rtc->lock, flags);

	rtc_delayed_write(time, rtc, reg);

	if (alrm->enabled) {
		rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
		rtc->data->unmask_interrupt(rtc);
	}

	spin_unlock_irqrestore(&rtc->lock, flags);

out:
	return ret;
}

static int armada38x_rtc_alarm_irq_enable(struct device *dev,
					 unsigned int enabled)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
	unsigned long flags;

	spin_lock_irqsave(&rtc->lock, flags);

	if (enabled)
		rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
	else
		rtc_delayed_write(0, rtc, reg_irq);

	spin_unlock_irqrestore(&rtc->lock, flags);

	return 0;
}

static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
{
	struct armada38x_rtc *rtc = data;
	u32 val;
	int event = RTC_IRQF | RTC_AF;
	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);

	dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);

	spin_lock(&rtc->lock);

	rtc->data->clear_isr(rtc);
	val = rtc->data->read_rtc_reg(rtc, reg_irq);
	/* disable all the interrupts for alarm*/
	rtc_delayed_write(0, rtc, reg_irq);
	/* Ack the event */
	rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);

	spin_unlock(&rtc->lock);

	if (val & RTC_IRQ_FREQ_EN) {
		if (val & RTC_IRQ_FREQ_1HZ)
			event |= RTC_UF;
		else
			event |= RTC_PF;
	}

	rtc_update_irq(rtc->rtc_dev, 1, event);

	return IRQ_HANDLED;
}

/*
 * The information given in the Armada 388 functional spec is complex.
 * They give two different formulas for calculating the offset value,
 * but when considering "Offset" as an 8-bit signed integer, they both
 * reduce down to (we shall rename "Offset" as "val" here):
 *
 *   val = (f_ideal / f_measured - 1) / resolution   where f_ideal = 32768
 *
 * Converting to time, f = 1/t:
 *   val = (t_measured / t_ideal - 1) / resolution   where t_ideal = 1/32768
 *
 *   =>  t_measured / t_ideal = val * resolution + 1
 *
 * "offset" in the RTC interface is defined as:
 *   t = t0 * (1 + offset * 1e-9)
 * where t is the desired period, t0 is the measured period with a zero
 * offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
 *   offset = (t_ideal / t_measured - 1) / 1e-9
 *
 *   => t_ideal / t_measured = offset * 1e-9 + 1
 *
 * so:
 *
 *   offset * 1e-9 + 1 = 1 / (val * resolution + 1)
 *
 * We want "resolution" to be an integer, so resolution = R * 1e-9, giving
 *   offset = 1e18 / (val * R + 1e9) - 1e9
 *   val = (1e18 / (offset + 1e9) - 1e9) / R
 * with a common transformation:
 *   f(x) = 1e18 / (x + 1e9) - 1e9
 *   offset = f(val * R)
 *   val = f(offset) / R
 *
 * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
 */
static long armada38x_ppb_convert(long ppb)
{
	long div = ppb + 1000000000L;

	return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
}

static int armada38x_rtc_read_offset(struct device *dev, long *offset)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long ccr, flags;
	long ppb_cor;

	spin_lock_irqsave(&rtc->lock, flags);
	ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
	spin_unlock_irqrestore(&rtc->lock, flags);

	ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
	/* ppb_cor + 1000000000L can never be zero */
	*offset = armada38x_ppb_convert(ppb_cor);

	return 0;
}

static int armada38x_rtc_set_offset(struct device *dev, long offset)
{
	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	unsigned long ccr = 0;
	long ppb_cor, off;

	/*
	 * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
	 * need to clamp the input.  This equates to -484270 .. 488558.
	 * Not only is this to stop out of range "off" but also to
	 * avoid the division by zero in armada38x_ppb_convert().
	 */
	offset = clamp(offset, -484270L, 488558L);

	ppb_cor = armada38x_ppb_convert(offset);

	/*
	 * Use low update mode where possible, which gives a better
	 * resolution of correction.
	 */
	off = DIV_ROUND_CLOSEST(ppb_cor, 954);
	if (off > 127 || off < -128) {
		ccr = RTC_CCR_MODE;
		off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
	}

	/*
	 * Armada 388 requires a bit pattern in bits 14..8 depending on
	 * the sign bit: { 0, ~S, S, S, S, S, S }
	 */
	ccr |= (off & 0x3fff) ^ 0x2000;
	rtc_delayed_write(ccr, rtc, RTC_CCR);

	return 0;
}

static const struct rtc_class_ops armada38x_rtc_ops = {
	.read_time = armada38x_rtc_read_time,
	.set_time = armada38x_rtc_set_time,
	.read_alarm = armada38x_rtc_read_alarm,
	.set_alarm = armada38x_rtc_set_alarm,
	.alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
	.read_offset = armada38x_rtc_read_offset,
	.set_offset = armada38x_rtc_set_offset,
};

static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
	.read_time = armada38x_rtc_read_time,
	.set_time = armada38x_rtc_set_time,
	.read_alarm = armada38x_rtc_read_alarm,
	.read_offset = armada38x_rtc_read_offset,
	.set_offset = armada38x_rtc_set_offset,
};

static const struct armada38x_rtc_data armada38x_data = {
	.update_mbus_timing = rtc_update_38x_mbus_timing_params,
	.read_rtc_reg = read_rtc_register_38x_wa,
	.clear_isr = armada38x_clear_isr,
	.unmask_interrupt = armada38x_unmask_interrupt,
	.alarm = ALARM1,
};

static const struct armada38x_rtc_data armada8k_data = {
	.update_mbus_timing = rtc_update_8k_mbus_timing_params,
	.read_rtc_reg = read_rtc_register,
	.clear_isr = armada8k_clear_isr,
	.unmask_interrupt = armada8k_unmask_interrupt,
	.alarm = ALARM2,
};

#ifdef CONFIG_OF
static const struct of_device_id armada38x_rtc_of_match_table[] = {
	{
		.compatible = "marvell,armada-380-rtc",
		.data = &armada38x_data,
	},
	{
		.compatible = "marvell,armada-8k-rtc",
		.data = &armada8k_data,
	},
	{}
};
MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
#endif

static __init int armada38x_rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct armada38x_rtc *rtc;
	const struct of_device_id *match;
	int ret;

	match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev);
	if (!match)
		return -ENODEV;

	rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
			    GFP_KERNEL);
	if (!rtc)
		return -ENOMEM;

	rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
				sizeof(struct value_to_freq), GFP_KERNEL);
	if (!rtc->val_to_freq)
		return -ENOMEM;

	spin_lock_init(&rtc->lock);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
	rtc->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(rtc->regs))
		return PTR_ERR(rtc->regs);
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
	rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(rtc->regs_soc))
		return PTR_ERR(rtc->regs_soc);

	rtc->irq = platform_get_irq(pdev, 0);

	if (rtc->irq < 0) {
		dev_err(&pdev->dev, "no irq\n");
		return rtc->irq;
	}

	rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc->rtc_dev))
		return PTR_ERR(rtc->rtc_dev);

	if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
				0, pdev->name, rtc) < 0) {
		dev_warn(&pdev->dev, "Interrupt not available.\n");
		rtc->irq = -1;
	}
	platform_set_drvdata(pdev, rtc);

	if (rtc->irq != -1) {
		device_init_wakeup(&pdev->dev, 1);
		rtc->rtc_dev->ops = &armada38x_rtc_ops;
	} else {
		/*
		 * If there is no interrupt available then we can't
		 * use the alarm
		 */
		rtc->rtc_dev->ops = &armada38x_rtc_ops_noirq;
	}
	rtc->data = (struct armada38x_rtc_data *)match->data;

	/* Update RTC-MBUS bridge timing parameters */
	rtc->data->update_mbus_timing(rtc);

	ret = rtc_register_device(rtc->rtc_dev);
	if (ret)
		dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int armada38x_rtc_suspend(struct device *dev)
{
	if (device_may_wakeup(dev)) {
		struct armada38x_rtc *rtc = dev_get_drvdata(dev);

		return enable_irq_wake(rtc->irq);
	}

	return 0;
}

static int armada38x_rtc_resume(struct device *dev)
{
	if (device_may_wakeup(dev)) {
		struct armada38x_rtc *rtc = dev_get_drvdata(dev);

		/* Update RTC-MBUS bridge timing parameters */
		rtc->data->update_mbus_timing(rtc);

		return disable_irq_wake(rtc->irq);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
			 armada38x_rtc_suspend, armada38x_rtc_resume);

static struct platform_driver armada38x_rtc_driver = {
	.driver		= {
		.name	= "armada38x-rtc",
		.pm	= &armada38x_rtc_pm_ops,
		.of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
	},
};

module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);

MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a3a42806 GC	1	/*
	2	* RTC driver for the Armada 38x Marvell SoCs
	3	*
	4	* Copyright (C) 2015 Marvell
	5	*
	6	* Gregory Clement <gregory.clement@free-electrons.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of the
	11	* License, or (at your option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
75faea91	19	#include <linux/of_device.h>
a3a42806 GC	20	#include <linux/platform_device.h>
	21	#include <linux/rtc.h>
	22
	23	#define RTC_STATUS 0x0
	24	#define RTC_STATUS_ALARM1 BIT(0)
	25	#define RTC_STATUS_ALARM2 BIT(1)
	26	#define RTC_IRQ1_CONF 0x4
34f54f57	27	#define RTC_IRQ2_CONF 0x8
75faea91 GC	28	#define RTC_IRQ_AL_EN BIT(0)
	29	#define RTC_IRQ_FREQ_EN BIT(1)
	30	#define RTC_IRQ_FREQ_1HZ BIT(2)
f94ffbc2 RK	31	#define RTC_CCR 0x18
f94ffbc2 RK	32	#define RTC_CCR_MODE BIT(15)
1a990fef BS	33	#define RTC_CONF_TEST 0x1C
1a990fef BS	34	#define RTC_NOMINAL_TIMING BIT(13)
75faea91	35
a3a42806 GC	36	#define RTC_TIME 0xC
a3a42806 GC	37	#define RTC_ALARM1 0x10
34f54f57 GC	38	#define RTC_ALARM2 0x14
	39
	40	/* Armada38x SoC registers */
75faea91 GC	41	#define RTC_38X_BRIDGE_TIMING_CTL 0x0
	42	#define RTC_38X_PERIOD_OFFS 0
	43	#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS)
	44	#define RTC_38X_READ_DELAY_OFFS 26
	45	#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS)
	46
34f54f57 GC	47	/* Armada 7K/8K registers */
	48	#define RTC_8K_BRIDGE_TIMING_CTL0 0x0
	49	#define RTC_8K_WRCLK_PERIOD_OFFS 0
	50	#define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
	51	#define RTC_8K_WRCLK_SETUP_OFFS 16
	52	#define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
	53	#define RTC_8K_BRIDGE_TIMING_CTL1 0x4
	54	#define RTC_8K_READ_DELAY_OFFS 0
	55	#define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS)
	56
	57	#define RTC_8K_ISR 0x10
	58	#define RTC_8K_IMR 0x14
	59	#define RTC_8K_ALARM2 BIT(0)
	60
75faea91 GC	61	#define SOC_RTC_INTERRUPT 0x8
	62	#define SOC_RTC_ALARM1 BIT(0)
	63	#define SOC_RTC_ALARM2 BIT(1)
	64	#define SOC_RTC_ALARM1_MASK BIT(2)
	65	#define SOC_RTC_ALARM2_MASK BIT(3)
a3a42806	66
844a3073 GC	67	#define SAMPLE_NR 100
	68
	69	struct value_to_freq {
	70	u32 value;
	71	u8 freq;
	72	};
	73
a3a42806 GC	74	struct armada38x_rtc {
	75	struct rtc_device *rtc_dev;
	76	void __iomem *regs;
	77	void __iomem *regs_soc;
	78	spinlock_t lock;
	79	int irq;
1a990fef	80	bool initialized;
844a3073	81	struct value_to_freq *val_to_freq;
75faea91 GC	82	struct armada38x_rtc_data *data;
	83	};
	84
	85	#define ALARM1 0
34f54f57 GC	86	#define ALARM2 1
34f54f57 GC	87
75faea91 GC	88	#define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32))
	89
	90	struct armada38x_rtc_data {
	91	/* Initialize the RTC-MBUS bridge timing */
	92	void (update_mbus_timing)(struct armada38x_rtc rtc);
	93	u32 (read_rtc_reg)(struct armada38x_rtc rtc, u8 rtc_reg);
	94	void (clear_isr)(struct armada38x_rtc rtc);
	95	void (unmask_interrupt)(struct armada38x_rtc rtc);
	96	u32 alarm;
a3a42806 GC	97	};
	98
	99	/*
	100	* According to the datasheet, the OS should wait 5us after every
	101	* register write to the RTC hard macro so that the required update
	102	* can occur without holding off the system bus
844a3073 GC	103	* According to errata RES-3124064, Write to any RTC register
	104	* may fail. As a workaround, before writing to RTC
	105	* register, issue a dummy write of 0x0 twice to RTC Status
	106	* register.
a3a42806	107	*/
844a3073	108
a3a42806 GC	109	static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
a3a42806 GC	110	{
844a3073 GC	111	writel(0, rtc->regs + RTC_STATUS);
844a3073 GC	112	writel(0, rtc->regs + RTC_STATUS);
a3a42806 GC	113	writel(val, rtc->regs + offset);
	114	udelay(5);
	115	}
	116
844a3073	117	/* Update RTC-MBUS bridge timing parameters */
75faea91	118	static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
844a3073 GC	119	{
	120	u32 reg;
	121
75faea91 GC	122	reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
	123	reg &= ~RTC_38X_PERIOD_MASK;
	124	reg \|= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
	125	reg &= ~RTC_38X_READ_DELAY_MASK;
	126	reg \|= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
	127	writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
844a3073 GC	128	}
844a3073 GC	129
34f54f57 GC	130	static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
	131	{
	132	u32 reg;
	133
	134	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
	135	reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
	136	reg \|= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
	137	reg &= ~RTC_8K_WRCLK_SETUP_MASK;
	138	reg \|= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
	139	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
	140
	141	reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
	142	reg &= ~RTC_8K_READ_DELAY_MASK;
	143	reg \|= 0x3F << RTC_8K_READ_DELAY_OFFS;
	144	writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
	145	}
	146
	147	static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
	148	{
	149	return readl(rtc->regs + rtc_reg);
	150	}
	151
75faea91	152	static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
844a3073 GC	153	{
	154	int i, index_max = 0, max = 0;
	155
	156	for (i = 0; i < SAMPLE_NR; i++) {
	157	rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
	158	rtc->val_to_freq[i].freq = 0;
	159	}
	160
	161	for (i = 0; i < SAMPLE_NR; i++) {
	162	int j = 0;
	163	u32 value = rtc->val_to_freq[i].value;
	164
	165	while (rtc->val_to_freq[j].freq) {
	166	if (rtc->val_to_freq[j].value == value) {
	167	rtc->val_to_freq[j].freq++;
	168	break;
	169	}
	170	j++;
	171	}
	172
	173	if (!rtc->val_to_freq[j].freq) {
	174	rtc->val_to_freq[j].value = value;
	175	rtc->val_to_freq[j].freq = 1;
	176	}
	177
	178	if (rtc->val_to_freq[j].freq > max) {
	179	index_max = j;
	180	max = rtc->val_to_freq[j].freq;
	181	}
	182
	183	/*
	184	* If a value already has half of the sample this is the most
	185	* frequent one and we can stop the research right now
	186	*/
	187	if (max > SAMPLE_NR / 2)
	188	break;
	189	}
	190
	191	return rtc->val_to_freq[index_max].value;
	192	}
	193
75faea91 GC	194	static void armada38x_clear_isr(struct armada38x_rtc *rtc)
	195	{
	196	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
	197
	198	writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
	199	}
	200
	201	static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
	202	{
	203	u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
	204
	205	writel(val \| SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
	206	}
34f54f57 GC	207
	208	static void armada8k_clear_isr(struct armada38x_rtc *rtc)
	209	{
	210	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
	211	}
	212
	213	static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
	214	{
	215	writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
	216	}
	217
a3a42806 GC	218	static int armada38x_rtc_read_time(struct device dev, struct rtc_time tm)
	219	{
	220	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
844a3073	221	unsigned long time, flags;
a3a42806	222
0c6e7183	223	spin_lock_irqsave(&rtc->lock, flags);
75faea91	224	time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
0c6e7183	225	spin_unlock_irqrestore(&rtc->lock, flags);
a3a42806	226
844a3073	227	rtc_time_to_tm(time, tm);
a3a42806 GC	228
	229	return 0;
	230	}
	231
1a990fef BS	232	static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
	233	{
	234	u32 reg;
	235
	236	reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
	237	/* If bits [7:0] are non-zero, assume RTC was uninitialized */
	238	if (reg & 0xff) {
	239	rtc_delayed_write(0, rtc, RTC_CONF_TEST);
	240	msleep(500); /* Oscillator startup time */
	241	rtc_delayed_write(0, rtc, RTC_TIME);
	242	rtc_delayed_write(SOC_RTC_ALARM1 \| SOC_RTC_ALARM2, rtc,
	243	RTC_STATUS);
	244	rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
	245	}
	246	rtc->initialized = true;
	247	}
	248
a3a42806 GC	249	static int armada38x_rtc_set_time(struct device dev, struct rtc_time tm)
	250	{
	251	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	252	int ret = 0;
0c6e7183	253	unsigned long time, flags;
a3a42806 GC	254
	255	ret = rtc_tm_to_time(tm, &time);
	256
	257	if (ret)
	258	goto out;
844a3073	259
1a990fef BS	260	if (!rtc->initialized)
	261	armada38x_rtc_reset(rtc);
	262
0c6e7183	263	spin_lock_irqsave(&rtc->lock, flags);
a3a42806	264	rtc_delayed_write(time, rtc, RTC_TIME);
0c6e7183	265	spin_unlock_irqrestore(&rtc->lock, flags);
a3a42806	266
a3a42806 GC	267	out:
	268	return ret;
	269	}
	270
	271	static int armada38x_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	272	{
	273	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	274	unsigned long time, flags;
75faea91 GC	275	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
75faea91 GC	276	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	277	u32 val;
	278
	279	spin_lock_irqsave(&rtc->lock, flags);
	280
75faea91 GC	281	time = rtc->data->read_rtc_reg(rtc, reg);
75faea91 GC	282	val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
a3a42806 GC	283
	284	spin_unlock_irqrestore(&rtc->lock, flags);
	285
	286	alrm->enabled = val ? 1 : 0;
	287	rtc_time_to_tm(time, &alrm->time);
	288
	289	return 0;
	290	}
	291
	292	static int armada38x_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	293	{
	294	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
75faea91 GC	295	u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
75faea91 GC	296	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	297	unsigned long time, flags;
a3a42806 GC	298	int ret = 0;
a3a42806 GC	299
	300	ret = rtc_tm_to_time(&alrm->time, &time);
	301
	302	if (ret)
	303	goto out;
	304
	305	spin_lock_irqsave(&rtc->lock, flags);
	306
75faea91	307	rtc_delayed_write(time, rtc, reg);
a3a42806 GC	308
a3a42806 GC	309	if (alrm->enabled) {
75faea91 GC	310	rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
75faea91 GC	311	rtc->data->unmask_interrupt(rtc);
a3a42806 GC	312	}
	313
	314	spin_unlock_irqrestore(&rtc->lock, flags);
	315
	316	out:
	317	return ret;
	318	}
	319
	320	static int armada38x_rtc_alarm_irq_enable(struct device *dev,
	321	unsigned int enabled)
	322	{
	323	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
75faea91	324	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	325	unsigned long flags;
	326
	327	spin_lock_irqsave(&rtc->lock, flags);
	328
	329	if (enabled)
75faea91	330	rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
a3a42806	331	else
75faea91	332	rtc_delayed_write(0, rtc, reg_irq);
a3a42806 GC	333
	334	spin_unlock_irqrestore(&rtc->lock, flags);
	335
	336	return 0;
	337	}
	338
	339	static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
	340	{
	341	struct armada38x_rtc *rtc = data;
	342	u32 val;
	343	int event = RTC_IRQF \| RTC_AF;
75faea91	344	u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
a3a42806 GC	345
	346	dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
	347
	348	spin_lock(&rtc->lock);
	349
75faea91 GC	350	rtc->data->clear_isr(rtc);
	351	val = rtc->data->read_rtc_reg(rtc, reg_irq);
	352	/* disable all the interrupts for alarm*/
	353	rtc_delayed_write(0, rtc, reg_irq);
a3a42806	354	/* Ack the event */
75faea91	355	rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
a3a42806 GC	356
	357	spin_unlock(&rtc->lock);
	358
75faea91 GC	359	if (val & RTC_IRQ_FREQ_EN) {
75faea91 GC	360	if (val & RTC_IRQ_FREQ_1HZ)
a3a42806 GC	361	event \|= RTC_UF;
	362	else
	363	event \|= RTC_PF;
	364	}
	365
	366	rtc_update_irq(rtc->rtc_dev, 1, event);
	367
	368	return IRQ_HANDLED;
	369	}
	370
f94ffbc2 RK	371	/*
	372	* The information given in the Armada 388 functional spec is complex.
	373	* They give two different formulas for calculating the offset value,
	374	* but when considering "Offset" as an 8-bit signed integer, they both
	375	* reduce down to (we shall rename "Offset" as "val" here):
	376	*
	377	* val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768
	378	*
	379	* Converting to time, f = 1/t:
	380	* val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768
	381	*
	382	* => t_measured / t_ideal = val * resolution + 1
	383	*
	384	* "offset" in the RTC interface is defined as:
	385	* t = t0 * (1 + offset * 1e-9)
	386	* where t is the desired period, t0 is the measured period with a zero
	387	* offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
	388	* offset = (t_ideal / t_measured - 1) / 1e-9
	389	*
	390	* => t_ideal / t_measured = offset * 1e-9 + 1
	391	*
	392	* so:
	393	*
	394	* offset * 1e-9 + 1 = 1 / (val * resolution + 1)
	395	*
	396	* We want "resolution" to be an integer, so resolution = R * 1e-9, giving
	397	* offset = 1e18 / (val * R + 1e9) - 1e9
	398	* val = (1e18 / (offset + 1e9) - 1e9) / R
	399	* with a common transformation:
	400	* f(x) = 1e18 / (x + 1e9) - 1e9
	401	* offset = f(val * R)
	402	* val = f(offset) / R
	403	*
	404	* Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
	405	*/
	406	static long armada38x_ppb_convert(long ppb)
	407	{
	408	long div = ppb + 1000000000L;
	409
	410	return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
	411	}
	412
	413	static int armada38x_rtc_read_offset(struct device dev, long offset)
	414	{
	415	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	416	unsigned long ccr, flags;
	417	long ppb_cor;
	418
	419	spin_lock_irqsave(&rtc->lock, flags);
	420	ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
	421	spin_unlock_irqrestore(&rtc->lock, flags);
	422
	423	ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
	424	/* ppb_cor + 1000000000L can never be zero */
	425	*offset = armada38x_ppb_convert(ppb_cor);
	426
	427	return 0;
	428	}
	429
	430	static int armada38x_rtc_set_offset(struct device *dev, long offset)
	431	{
	432	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	433	unsigned long ccr = 0;
	434	long ppb_cor, off;
435
436	/*
437	* The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
438	* need to clamp the input. This equates to -484270 .. 488558.
439	* Not only is this to stop out of range "off" but also to
440	* avoid the division by zero in armada38x_ppb_convert().
441	*/
442	offset = clamp(offset, -484270L, 488558L);
443
444	ppb_cor = armada38x_ppb_convert(offset);
445
446	/*
447	* Use low update mode where possible, which gives a better
448	* resolution of correction.
449	*/
450	off = DIV_ROUND_CLOSEST(ppb_cor, 954);
451	if (off > 127 \|\| off < -128) {
452	ccr = RTC_CCR_MODE;
453	off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
454	}
455
456	/*
457	* Armada 388 requires a bit pattern in bits 14..8 depending on
458	* the sign bit: { 0, ~S, S, S, S, S, S }
459	*/
460	ccr \|= (off & 0x3fff) ^ 0x2000;
461	rtc_delayed_write(ccr, rtc, RTC_CCR);
462
463	return 0;
464	}
465
d748c981	466	static const struct rtc_class_ops armada38x_rtc_ops = {
a3a42806 GC	467	.read_time = armada38x_rtc_read_time,
	468	.set_time = armada38x_rtc_set_time,
	469	.read_alarm = armada38x_rtc_read_alarm,
	470	.set_alarm = armada38x_rtc_set_alarm,
	471	.alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
f94ffbc2 RK	472	.read_offset = armada38x_rtc_read_offset,
f94ffbc2 RK	473	.set_offset = armada38x_rtc_set_offset,
a3a42806 GC	474	};
a3a42806 GC	475
d748c981 RK	476	static const struct rtc_class_ops armada38x_rtc_ops_noirq = {
	477	.read_time = armada38x_rtc_read_time,
	478	.set_time = armada38x_rtc_set_time,
	479	.read_alarm = armada38x_rtc_read_alarm,
f94ffbc2 RK	480	.read_offset = armada38x_rtc_read_offset,
f94ffbc2 RK	481	.set_offset = armada38x_rtc_set_offset,
d748c981 RK	482	};
d748c981 RK	483
75faea91 GC	484	static const struct armada38x_rtc_data armada38x_data = {
	485	.update_mbus_timing = rtc_update_38x_mbus_timing_params,
	486	.read_rtc_reg = read_rtc_register_38x_wa,
	487	.clear_isr = armada38x_clear_isr,
	488	.unmask_interrupt = armada38x_unmask_interrupt,
	489	.alarm = ALARM1,
	490	};
	491
34f54f57 GC	492	static const struct armada38x_rtc_data armada8k_data = {
	493	.update_mbus_timing = rtc_update_8k_mbus_timing_params,
	494	.read_rtc_reg = read_rtc_register,
	495	.clear_isr = armada8k_clear_isr,
	496	.unmask_interrupt = armada8k_unmask_interrupt,
	497	.alarm = ALARM2,
	498	};
	499
75faea91 GC	500	#ifdef CONFIG_OF
	501	static const struct of_device_id armada38x_rtc_of_match_table[] = {
	502	{
	503	.compatible = "marvell,armada-380-rtc",
	504	.data = &armada38x_data,
	505	},
34f54f57 GC	506	{
	507	.compatible = "marvell,armada-8k-rtc",
	508	.data = &armada8k_data,
	509	},
75faea91 GC	510	{}
	511	};
	512	MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
	513	#endif
	514
a3a42806 GC	515	static __init int armada38x_rtc_probe(struct platform_device *pdev)
	516	{
	517	struct resource *res;
	518	struct armada38x_rtc *rtc;
75faea91	519	const struct of_device_id *match;
a3a42806 GC	520	int ret;
a3a42806 GC	521
75faea91 GC	522	match = of_match_device(armada38x_rtc_of_match_table, &pdev->dev);
	523	if (!match)
	524	return -ENODEV;
	525
a3a42806 GC	526	rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
	527	GFP_KERNEL);
	528	if (!rtc)
	529	return -ENOMEM;
	530
844a3073 GC	531	rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
	532	sizeof(struct value_to_freq), GFP_KERNEL);
	533	if (!rtc->val_to_freq)
	534	return -ENOMEM;
	535
a3a42806 GC	536	spin_lock_init(&rtc->lock);
	537
	538	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
	539	rtc->regs = devm_ioremap_resource(&pdev->dev, res);
	540	if (IS_ERR(rtc->regs))
	541	return PTR_ERR(rtc->regs);
	542	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
	543	rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
	544	if (IS_ERR(rtc->regs_soc))
	545	return PTR_ERR(rtc->regs_soc);
	546
	547	rtc->irq = platform_get_irq(pdev, 0);
	548
	549	if (rtc->irq < 0) {
	550	dev_err(&pdev->dev, "no irq\n");
	551	return rtc->irq;
	552	}
7d61cbb9 AB	553
	554	rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
	555	if (IS_ERR(rtc->rtc_dev))
	556	return PTR_ERR(rtc->rtc_dev);
	557
a3a42806 GC	558	if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
	559	0, pdev->name, rtc) < 0) {
	560	dev_warn(&pdev->dev, "Interrupt not available.\n");
	561	rtc->irq = -1;
d748c981 RK	562	}
	563	platform_set_drvdata(pdev, rtc);
	564
	565	if (rtc->irq != -1) {
	566	device_init_wakeup(&pdev->dev, 1);
7d61cbb9	567	rtc->rtc_dev->ops = &armada38x_rtc_ops;
d748c981	568	} else {
a3a42806 GC	569	/*
	570	* If there is no interrupt available then we can't
	571	* use the alarm
	572	*/
7d61cbb9	573	rtc->rtc_dev->ops = &armada38x_rtc_ops_noirq;
a3a42806	574	}
75faea91 GC	575	rtc->data = (struct armada38x_rtc_data *)match->data;
75faea91 GC	576
844a3073	577	/* Update RTC-MBUS bridge timing parameters */
75faea91	578	rtc->data->update_mbus_timing(rtc);
844a3073	579
7d61cbb9 AB	580	ret = rtc_register_device(rtc->rtc_dev);
7d61cbb9 AB	581	if (ret)
a3a42806	582	dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
7d61cbb9 AB	583
7d61cbb9 AB	584	return ret;
a3a42806 GC	585	}
	586
	587	#ifdef CONFIG_PM_SLEEP
	588	static int armada38x_rtc_suspend(struct device *dev)
	589	{
	590	if (device_may_wakeup(dev)) {
	591	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	592
	593	return enable_irq_wake(rtc->irq);
	594	}
	595
	596	return 0;
	597	}
	598
	599	static int armada38x_rtc_resume(struct device *dev)
	600	{
	601	if (device_may_wakeup(dev)) {
	602	struct armada38x_rtc *rtc = dev_get_drvdata(dev);
	603
844a3073	604	/* Update RTC-MBUS bridge timing parameters */
75faea91	605	rtc->data->update_mbus_timing(rtc);
844a3073	606
a3a42806 GC	607	return disable_irq_wake(rtc->irq);
	608	}
	609
	610	return 0;
	611	}
	612	#endif
	613
	614	static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
	615	armada38x_rtc_suspend, armada38x_rtc_resume);
	616
a3a42806 GC	617	static struct platform_driver armada38x_rtc_driver = {
	618	.driver = {
	619	.name = "armada38x-rtc",
	620	.pm = &armada38x_rtc_pm_ops,
	621	.of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
	622	},
	623	};
	624
	625	module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
	626
	627	MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
	628	MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
	629	MODULE_LICENSE("GPL");