Commit | Line | Data |
---|---|---|
2fcdf5fd | 1 | // SPDX-License-Identifier: GPL-2.0 |
4d61ff6b PDM |
2 | /* |
3 | * A driver for the I2C members of the Abracon AB x8xx RTC family, | |
4 | * and compatible: AB 1805 and AB 0805 | |
5 | * | |
6 | * Copyright 2014-2015 Macq S.A. | |
7 | * | |
8 | * Author: Philippe De Muyter <phdm@macqel.be> | |
7d1e5bfe | 9 | * Author: Alexandre Belloni <alexandre.belloni@bootlin.com> |
4d61ff6b | 10 | * |
4d61ff6b PDM |
11 | */ |
12 | ||
13 | #include <linux/bcd.h> | |
14 | #include <linux/i2c.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/rtc.h> | |
749e36d0 | 17 | #include <linux/watchdog.h> |
4d61ff6b PDM |
18 | |
19 | #define ABX8XX_REG_HTH 0x00 | |
20 | #define ABX8XX_REG_SC 0x01 | |
21 | #define ABX8XX_REG_MN 0x02 | |
22 | #define ABX8XX_REG_HR 0x03 | |
23 | #define ABX8XX_REG_DA 0x04 | |
24 | #define ABX8XX_REG_MO 0x05 | |
25 | #define ABX8XX_REG_YR 0x06 | |
26 | #define ABX8XX_REG_WD 0x07 | |
27 | ||
718a820a AB |
28 | #define ABX8XX_REG_AHTH 0x08 |
29 | #define ABX8XX_REG_ASC 0x09 | |
30 | #define ABX8XX_REG_AMN 0x0a | |
31 | #define ABX8XX_REG_AHR 0x0b | |
32 | #define ABX8XX_REG_ADA 0x0c | |
33 | #define ABX8XX_REG_AMO 0x0d | |
34 | #define ABX8XX_REG_AWD 0x0e | |
35 | ||
36 | #define ABX8XX_REG_STATUS 0x0f | |
37 | #define ABX8XX_STATUS_AF BIT(2) | |
ffe1c5a2 | 38 | #define ABX8XX_STATUS_BLF BIT(4) |
749e36d0 | 39 | #define ABX8XX_STATUS_WDT BIT(6) |
718a820a | 40 | |
4d61ff6b | 41 | #define ABX8XX_REG_CTRL1 0x10 |
5f1b2f77 | 42 | #define ABX8XX_CTRL_WRITE BIT(0) |
718a820a | 43 | #define ABX8XX_CTRL_ARST BIT(2) |
4d61ff6b PDM |
44 | #define ABX8XX_CTRL_12_24 BIT(6) |
45 | ||
75455e25 MV |
46 | #define ABX8XX_REG_CTRL2 0x11 |
47 | #define ABX8XX_CTRL2_RSVD BIT(5) | |
48 | ||
718a820a AB |
49 | #define ABX8XX_REG_IRQ 0x12 |
50 | #define ABX8XX_IRQ_AIE BIT(2) | |
51 | #define ABX8XX_IRQ_IM_1_4 (0x3 << 5) | |
52 | ||
53 | #define ABX8XX_REG_CD_TIMER_CTL 0x18 | |
54 | ||
59a8383a MJ |
55 | #define ABX8XX_REG_OSC 0x1c |
56 | #define ABX8XX_OSC_FOS BIT(3) | |
57 | #define ABX8XX_OSC_BOS BIT(4) | |
58 | #define ABX8XX_OSC_ACAL_512 BIT(5) | |
59 | #define ABX8XX_OSC_ACAL_1024 BIT(6) | |
60 | ||
61 | #define ABX8XX_OSC_OSEL BIT(7) | |
62 | ||
63 | #define ABX8XX_REG_OSS 0x1d | |
ee087744 | 64 | #define ABX8XX_OSS_OF BIT(1) |
59a8383a MJ |
65 | #define ABX8XX_OSS_OMODE BIT(4) |
66 | ||
749e36d0 JG |
67 | #define ABX8XX_REG_WDT 0x1b |
68 | #define ABX8XX_WDT_WDS BIT(7) | |
69 | #define ABX8XX_WDT_BMB_MASK 0x7c | |
70 | #define ABX8XX_WDT_BMB_SHIFT 2 | |
71 | #define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT) | |
72 | #define ABX8XX_WDT_WRB_MASK 0x03 | |
73 | #define ABX8XX_WDT_WRB_1HZ 0x02 | |
74 | ||
4d61ff6b | 75 | #define ABX8XX_REG_CFG_KEY 0x1f |
59a8383a | 76 | #define ABX8XX_CFG_KEY_OSC 0xa1 |
4d61ff6b PDM |
77 | #define ABX8XX_CFG_KEY_MISC 0x9d |
78 | ||
79 | #define ABX8XX_REG_ID0 0x28 | |
80 | ||
75455e25 MV |
81 | #define ABX8XX_REG_OUT_CTRL 0x30 |
82 | #define ABX8XX_OUT_CTRL_EXDS BIT(4) | |
83 | ||
4d61ff6b PDM |
84 | #define ABX8XX_REG_TRICKLE 0x20 |
85 | #define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0 | |
86 | #define ABX8XX_TRICKLE_STANDARD_DIODE 0x8 | |
87 | #define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4 | |
88 | ||
89 | static u8 trickle_resistors[] = {0, 3, 6, 11}; | |
90 | ||
91 | enum abx80x_chip {AB0801, AB0803, AB0804, AB0805, | |
75455e25 | 92 | AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X}; |
4d61ff6b PDM |
93 | |
94 | struct abx80x_cap { | |
95 | u16 pn; | |
96 | bool has_tc; | |
749e36d0 | 97 | bool has_wdog; |
4d61ff6b PDM |
98 | }; |
99 | ||
100 | static struct abx80x_cap abx80x_caps[] = { | |
101 | [AB0801] = {.pn = 0x0801}, | |
102 | [AB0803] = {.pn = 0x0803}, | |
749e36d0 JG |
103 | [AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true}, |
104 | [AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true}, | |
4d61ff6b PDM |
105 | [AB1801] = {.pn = 0x1801}, |
106 | [AB1803] = {.pn = 0x1803}, | |
749e36d0 JG |
107 | [AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true}, |
108 | [AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true}, | |
75455e25 | 109 | [RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true}, |
4d61ff6b PDM |
110 | [ABX80X] = {.pn = 0} |
111 | }; | |
112 | ||
af69f9a7 JG |
113 | struct abx80x_priv { |
114 | struct rtc_device *rtc; | |
115 | struct i2c_client *client; | |
749e36d0 | 116 | struct watchdog_device wdog; |
af69f9a7 JG |
117 | }; |
118 | ||
59a8383a MJ |
119 | static int abx80x_is_rc_mode(struct i2c_client *client) |
120 | { | |
121 | int flags = 0; | |
122 | ||
123 | flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS); | |
124 | if (flags < 0) { | |
125 | dev_err(&client->dev, | |
126 | "Failed to read autocalibration attribute\n"); | |
127 | return flags; | |
128 | } | |
129 | ||
130 | return (flags & ABX8XX_OSS_OMODE) ? 1 : 0; | |
131 | } | |
132 | ||
4d61ff6b PDM |
133 | static int abx80x_enable_trickle_charger(struct i2c_client *client, |
134 | u8 trickle_cfg) | |
135 | { | |
136 | int err; | |
137 | ||
138 | /* | |
139 | * Write the configuration key register to enable access to the Trickle | |
140 | * register | |
141 | */ | |
142 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, | |
143 | ABX8XX_CFG_KEY_MISC); | |
144 | if (err < 0) { | |
145 | dev_err(&client->dev, "Unable to write configuration key\n"); | |
146 | return -EIO; | |
147 | } | |
148 | ||
149 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_TRICKLE, | |
150 | ABX8XX_TRICKLE_CHARGE_ENABLE | | |
151 | trickle_cfg); | |
152 | if (err < 0) { | |
153 | dev_err(&client->dev, "Unable to write trickle register\n"); | |
154 | return -EIO; | |
155 | } | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static int abx80x_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
161 | { | |
162 | struct i2c_client *client = to_i2c_client(dev); | |
163 | unsigned char buf[8]; | |
ee087744 MJ |
164 | int err, flags, rc_mode = 0; |
165 | ||
166 | /* Read the Oscillator Failure only in XT mode */ | |
167 | rc_mode = abx80x_is_rc_mode(client); | |
168 | if (rc_mode < 0) | |
169 | return rc_mode; | |
170 | ||
171 | if (!rc_mode) { | |
172 | flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS); | |
173 | if (flags < 0) | |
174 | return flags; | |
175 | ||
176 | if (flags & ABX8XX_OSS_OF) { | |
177 | dev_err(dev, "Oscillator failure, data is invalid.\n"); | |
178 | return -EINVAL; | |
179 | } | |
180 | } | |
4d61ff6b PDM |
181 | |
182 | err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_HTH, | |
183 | sizeof(buf), buf); | |
184 | if (err < 0) { | |
185 | dev_err(&client->dev, "Unable to read date\n"); | |
186 | return -EIO; | |
187 | } | |
188 | ||
189 | tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F); | |
190 | tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F); | |
191 | tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F); | |
192 | tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7; | |
193 | tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F); | |
194 | tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F) - 1; | |
195 | tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 100; | |
196 | ||
fbfd36fd | 197 | return 0; |
4d61ff6b PDM |
198 | } |
199 | ||
200 | static int abx80x_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
201 | { | |
202 | struct i2c_client *client = to_i2c_client(dev); | |
203 | unsigned char buf[8]; | |
ee087744 | 204 | int err, flags; |
4d61ff6b PDM |
205 | |
206 | if (tm->tm_year < 100) | |
207 | return -EINVAL; | |
208 | ||
209 | buf[ABX8XX_REG_HTH] = 0; | |
210 | buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec); | |
211 | buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min); | |
212 | buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour); | |
213 | buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday); | |
214 | buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon + 1); | |
215 | buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 100); | |
216 | buf[ABX8XX_REG_WD] = tm->tm_wday; | |
217 | ||
218 | err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_HTH, | |
219 | sizeof(buf), buf); | |
220 | if (err < 0) { | |
221 | dev_err(&client->dev, "Unable to write to date registers\n"); | |
222 | return -EIO; | |
223 | } | |
224 | ||
ee087744 MJ |
225 | /* Clear the OF bit of Oscillator Status Register */ |
226 | flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS); | |
227 | if (flags < 0) | |
228 | return flags; | |
229 | ||
230 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSS, | |
231 | flags & ~ABX8XX_OSS_OF); | |
232 | if (err < 0) { | |
233 | dev_err(&client->dev, "Unable to write oscillator status register\n"); | |
234 | return err; | |
235 | } | |
236 | ||
4d61ff6b PDM |
237 | return 0; |
238 | } | |
239 | ||
718a820a AB |
240 | static irqreturn_t abx80x_handle_irq(int irq, void *dev_id) |
241 | { | |
242 | struct i2c_client *client = dev_id; | |
af69f9a7 JG |
243 | struct abx80x_priv *priv = i2c_get_clientdata(client); |
244 | struct rtc_device *rtc = priv->rtc; | |
718a820a AB |
245 | int status; |
246 | ||
247 | status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS); | |
248 | if (status < 0) | |
249 | return IRQ_NONE; | |
250 | ||
251 | if (status & ABX8XX_STATUS_AF) | |
252 | rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF); | |
253 | ||
749e36d0 JG |
254 | /* |
255 | * It is unclear if we'll get an interrupt before the external | |
256 | * reset kicks in. | |
257 | */ | |
258 | if (status & ABX8XX_STATUS_WDT) | |
259 | dev_alert(&client->dev, "watchdog timeout interrupt.\n"); | |
260 | ||
718a820a AB |
261 | i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0); |
262 | ||
263 | return IRQ_HANDLED; | |
264 | } | |
265 | ||
266 | static int abx80x_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
267 | { | |
268 | struct i2c_client *client = to_i2c_client(dev); | |
269 | unsigned char buf[7]; | |
270 | ||
271 | int irq_mask, err; | |
272 | ||
273 | if (client->irq <= 0) | |
274 | return -EINVAL; | |
275 | ||
276 | err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ASC, | |
277 | sizeof(buf), buf); | |
278 | if (err) | |
279 | return err; | |
280 | ||
281 | irq_mask = i2c_smbus_read_byte_data(client, ABX8XX_REG_IRQ); | |
282 | if (irq_mask < 0) | |
283 | return irq_mask; | |
284 | ||
285 | t->time.tm_sec = bcd2bin(buf[0] & 0x7F); | |
286 | t->time.tm_min = bcd2bin(buf[1] & 0x7F); | |
287 | t->time.tm_hour = bcd2bin(buf[2] & 0x3F); | |
288 | t->time.tm_mday = bcd2bin(buf[3] & 0x3F); | |
289 | t->time.tm_mon = bcd2bin(buf[4] & 0x1F) - 1; | |
290 | t->time.tm_wday = buf[5] & 0x7; | |
291 | ||
292 | t->enabled = !!(irq_mask & ABX8XX_IRQ_AIE); | |
293 | t->pending = (buf[6] & ABX8XX_STATUS_AF) && t->enabled; | |
294 | ||
295 | return err; | |
296 | } | |
297 | ||
298 | static int abx80x_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |
299 | { | |
300 | struct i2c_client *client = to_i2c_client(dev); | |
301 | u8 alarm[6]; | |
302 | int err; | |
303 | ||
304 | if (client->irq <= 0) | |
305 | return -EINVAL; | |
306 | ||
307 | alarm[0] = 0x0; | |
308 | alarm[1] = bin2bcd(t->time.tm_sec); | |
309 | alarm[2] = bin2bcd(t->time.tm_min); | |
310 | alarm[3] = bin2bcd(t->time.tm_hour); | |
311 | alarm[4] = bin2bcd(t->time.tm_mday); | |
312 | alarm[5] = bin2bcd(t->time.tm_mon + 1); | |
313 | ||
314 | err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_AHTH, | |
315 | sizeof(alarm), alarm); | |
316 | if (err < 0) { | |
317 | dev_err(&client->dev, "Unable to write alarm registers\n"); | |
318 | return -EIO; | |
319 | } | |
320 | ||
321 | if (t->enabled) { | |
322 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ, | |
323 | (ABX8XX_IRQ_IM_1_4 | | |
324 | ABX8XX_IRQ_AIE)); | |
325 | if (err) | |
326 | return err; | |
327 | } | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
59a8383a MJ |
332 | static int abx80x_rtc_set_autocalibration(struct device *dev, |
333 | int autocalibration) | |
334 | { | |
335 | struct i2c_client *client = to_i2c_client(dev); | |
336 | int retval, flags = 0; | |
337 | ||
338 | if ((autocalibration != 0) && (autocalibration != 1024) && | |
339 | (autocalibration != 512)) { | |
340 | dev_err(dev, "autocalibration value outside permitted range\n"); | |
341 | return -EINVAL; | |
342 | } | |
343 | ||
344 | flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC); | |
345 | if (flags < 0) | |
346 | return flags; | |
347 | ||
348 | if (autocalibration == 0) { | |
349 | flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024); | |
350 | } else if (autocalibration == 1024) { | |
351 | /* 1024 autocalibration is 0x10 */ | |
352 | flags |= ABX8XX_OSC_ACAL_1024; | |
353 | flags &= ~(ABX8XX_OSC_ACAL_512); | |
354 | } else { | |
355 | /* 512 autocalibration is 0x11 */ | |
356 | flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512); | |
357 | } | |
358 | ||
359 | /* Unlock write access to Oscillator Control Register */ | |
360 | retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, | |
361 | ABX8XX_CFG_KEY_OSC); | |
362 | if (retval < 0) { | |
363 | dev_err(dev, "Failed to write CONFIG_KEY register\n"); | |
364 | return retval; | |
365 | } | |
366 | ||
367 | retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags); | |
368 | ||
369 | return retval; | |
370 | } | |
371 | ||
372 | static int abx80x_rtc_get_autocalibration(struct device *dev) | |
373 | { | |
374 | struct i2c_client *client = to_i2c_client(dev); | |
375 | int flags = 0, autocalibration; | |
376 | ||
377 | flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC); | |
378 | if (flags < 0) | |
379 | return flags; | |
380 | ||
381 | if (flags & ABX8XX_OSC_ACAL_512) | |
382 | autocalibration = 512; | |
383 | else if (flags & ABX8XX_OSC_ACAL_1024) | |
384 | autocalibration = 1024; | |
385 | else | |
386 | autocalibration = 0; | |
387 | ||
388 | return autocalibration; | |
389 | } | |
390 | ||
391 | static ssize_t autocalibration_store(struct device *dev, | |
392 | struct device_attribute *attr, | |
393 | const char *buf, size_t count) | |
394 | { | |
395 | int retval; | |
396 | unsigned long autocalibration = 0; | |
397 | ||
398 | retval = kstrtoul(buf, 10, &autocalibration); | |
399 | if (retval < 0) { | |
400 | dev_err(dev, "Failed to store RTC autocalibration attribute\n"); | |
401 | return -EINVAL; | |
402 | } | |
403 | ||
559e883e | 404 | retval = abx80x_rtc_set_autocalibration(dev->parent, autocalibration); |
59a8383a MJ |
405 | |
406 | return retval ? retval : count; | |
407 | } | |
408 | ||
409 | static ssize_t autocalibration_show(struct device *dev, | |
410 | struct device_attribute *attr, char *buf) | |
411 | { | |
412 | int autocalibration = 0; | |
413 | ||
559e883e | 414 | autocalibration = abx80x_rtc_get_autocalibration(dev->parent); |
59a8383a MJ |
415 | if (autocalibration < 0) { |
416 | dev_err(dev, "Failed to read RTC autocalibration\n"); | |
417 | sprintf(buf, "0\n"); | |
418 | return autocalibration; | |
419 | } | |
420 | ||
421 | return sprintf(buf, "%d\n", autocalibration); | |
422 | } | |
423 | ||
424 | static DEVICE_ATTR_RW(autocalibration); | |
425 | ||
426 | static ssize_t oscillator_store(struct device *dev, | |
427 | struct device_attribute *attr, | |
428 | const char *buf, size_t count) | |
429 | { | |
559e883e | 430 | struct i2c_client *client = to_i2c_client(dev->parent); |
59a8383a MJ |
431 | int retval, flags, rc_mode = 0; |
432 | ||
433 | if (strncmp(buf, "rc", 2) == 0) { | |
434 | rc_mode = 1; | |
435 | } else if (strncmp(buf, "xtal", 4) == 0) { | |
436 | rc_mode = 0; | |
437 | } else { | |
438 | dev_err(dev, "Oscillator selection value outside permitted ones\n"); | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC); | |
443 | if (flags < 0) | |
444 | return flags; | |
445 | ||
446 | if (rc_mode == 0) | |
447 | flags &= ~(ABX8XX_OSC_OSEL); | |
448 | else | |
449 | flags |= (ABX8XX_OSC_OSEL); | |
450 | ||
451 | /* Unlock write access on Oscillator Control register */ | |
452 | retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, | |
453 | ABX8XX_CFG_KEY_OSC); | |
454 | if (retval < 0) { | |
455 | dev_err(dev, "Failed to write CONFIG_KEY register\n"); | |
456 | return retval; | |
457 | } | |
458 | ||
459 | retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags); | |
460 | if (retval < 0) { | |
461 | dev_err(dev, "Failed to write Oscillator Control register\n"); | |
462 | return retval; | |
463 | } | |
464 | ||
465 | return retval ? retval : count; | |
466 | } | |
467 | ||
468 | static ssize_t oscillator_show(struct device *dev, | |
469 | struct device_attribute *attr, char *buf) | |
470 | { | |
471 | int rc_mode = 0; | |
559e883e | 472 | struct i2c_client *client = to_i2c_client(dev->parent); |
59a8383a MJ |
473 | |
474 | rc_mode = abx80x_is_rc_mode(client); | |
475 | ||
476 | if (rc_mode < 0) { | |
477 | dev_err(dev, "Failed to read RTC oscillator selection\n"); | |
478 | sprintf(buf, "\n"); | |
479 | return rc_mode; | |
480 | } | |
481 | ||
482 | if (rc_mode) | |
483 | return sprintf(buf, "rc\n"); | |
484 | else | |
485 | return sprintf(buf, "xtal\n"); | |
486 | } | |
487 | ||
488 | static DEVICE_ATTR_RW(oscillator); | |
489 | ||
490 | static struct attribute *rtc_calib_attrs[] = { | |
491 | &dev_attr_autocalibration.attr, | |
492 | &dev_attr_oscillator.attr, | |
493 | NULL, | |
494 | }; | |
495 | ||
496 | static const struct attribute_group rtc_calib_attr_group = { | |
497 | .attrs = rtc_calib_attrs, | |
498 | }; | |
499 | ||
718a820a AB |
500 | static int abx80x_alarm_irq_enable(struct device *dev, unsigned int enabled) |
501 | { | |
502 | struct i2c_client *client = to_i2c_client(dev); | |
503 | int err; | |
504 | ||
505 | if (enabled) | |
506 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ, | |
507 | (ABX8XX_IRQ_IM_1_4 | | |
508 | ABX8XX_IRQ_AIE)); | |
509 | else | |
510 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ, | |
511 | ABX8XX_IRQ_IM_1_4); | |
512 | return err; | |
513 | } | |
514 | ||
ffe1c5a2 MV |
515 | static int abx80x_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) |
516 | { | |
517 | struct i2c_client *client = to_i2c_client(dev); | |
518 | int status, tmp; | |
519 | ||
520 | switch (cmd) { | |
521 | case RTC_VL_READ: | |
522 | status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS); | |
523 | if (status < 0) | |
524 | return status; | |
525 | ||
526 | tmp = !!(status & ABX8XX_STATUS_BLF); | |
527 | ||
528 | if (copy_to_user((void __user *)arg, &tmp, sizeof(int))) | |
529 | return -EFAULT; | |
530 | ||
531 | return 0; | |
532 | ||
533 | case RTC_VL_CLR: | |
534 | status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS); | |
535 | if (status < 0) | |
536 | return status; | |
537 | ||
538 | status &= ~ABX8XX_STATUS_BLF; | |
539 | ||
540 | tmp = i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0); | |
541 | if (tmp < 0) | |
542 | return tmp; | |
543 | ||
544 | return 0; | |
545 | ||
546 | default: | |
547 | return -ENOIOCTLCMD; | |
548 | } | |
549 | } | |
550 | ||
4d61ff6b PDM |
551 | static const struct rtc_class_ops abx80x_rtc_ops = { |
552 | .read_time = abx80x_rtc_read_time, | |
553 | .set_time = abx80x_rtc_set_time, | |
718a820a AB |
554 | .read_alarm = abx80x_read_alarm, |
555 | .set_alarm = abx80x_set_alarm, | |
556 | .alarm_irq_enable = abx80x_alarm_irq_enable, | |
ffe1c5a2 | 557 | .ioctl = abx80x_ioctl, |
4d61ff6b PDM |
558 | }; |
559 | ||
560 | static int abx80x_dt_trickle_cfg(struct device_node *np) | |
561 | { | |
562 | const char *diode; | |
563 | int trickle_cfg = 0; | |
564 | int i, ret; | |
565 | u32 tmp; | |
566 | ||
567 | ret = of_property_read_string(np, "abracon,tc-diode", &diode); | |
568 | if (ret) | |
569 | return ret; | |
570 | ||
571 | if (!strcmp(diode, "standard")) | |
572 | trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE; | |
573 | else if (!strcmp(diode, "schottky")) | |
574 | trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE; | |
575 | else | |
576 | return -EINVAL; | |
577 | ||
578 | ret = of_property_read_u32(np, "abracon,tc-resistor", &tmp); | |
579 | if (ret) | |
580 | return ret; | |
581 | ||
582 | for (i = 0; i < sizeof(trickle_resistors); i++) | |
583 | if (trickle_resistors[i] == tmp) | |
584 | break; | |
585 | ||
586 | if (i == sizeof(trickle_resistors)) | |
587 | return -EINVAL; | |
588 | ||
589 | return (trickle_cfg | i); | |
590 | } | |
591 | ||
749e36d0 JG |
592 | #ifdef CONFIG_WATCHDOG |
593 | ||
594 | static inline u8 timeout_bits(unsigned int timeout) | |
595 | { | |
596 | return ((timeout << ABX8XX_WDT_BMB_SHIFT) & ABX8XX_WDT_BMB_MASK) | | |
597 | ABX8XX_WDT_WRB_1HZ; | |
598 | } | |
599 | ||
600 | static int __abx80x_wdog_set_timeout(struct watchdog_device *wdog, | |
601 | unsigned int timeout) | |
602 | { | |
603 | struct abx80x_priv *priv = watchdog_get_drvdata(wdog); | |
604 | u8 val = ABX8XX_WDT_WDS | timeout_bits(timeout); | |
605 | ||
606 | /* | |
607 | * Writing any timeout to the WDT register resets the watchdog timer. | |
608 | * Writing 0 disables it. | |
609 | */ | |
610 | return i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_WDT, val); | |
611 | } | |
612 | ||
613 | static int abx80x_wdog_set_timeout(struct watchdog_device *wdog, | |
614 | unsigned int new_timeout) | |
615 | { | |
616 | int err = 0; | |
617 | ||
618 | if (watchdog_hw_running(wdog)) | |
619 | err = __abx80x_wdog_set_timeout(wdog, new_timeout); | |
620 | ||
621 | if (err == 0) | |
622 | wdog->timeout = new_timeout; | |
623 | ||
624 | return err; | |
625 | } | |
626 | ||
627 | static int abx80x_wdog_ping(struct watchdog_device *wdog) | |
628 | { | |
629 | return __abx80x_wdog_set_timeout(wdog, wdog->timeout); | |
630 | } | |
631 | ||
632 | static int abx80x_wdog_start(struct watchdog_device *wdog) | |
633 | { | |
634 | return __abx80x_wdog_set_timeout(wdog, wdog->timeout); | |
635 | } | |
636 | ||
637 | static int abx80x_wdog_stop(struct watchdog_device *wdog) | |
638 | { | |
639 | return __abx80x_wdog_set_timeout(wdog, 0); | |
640 | } | |
641 | ||
642 | static const struct watchdog_info abx80x_wdog_info = { | |
643 | .identity = "abx80x watchdog", | |
644 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | |
645 | }; | |
646 | ||
647 | static const struct watchdog_ops abx80x_wdog_ops = { | |
648 | .owner = THIS_MODULE, | |
649 | .start = abx80x_wdog_start, | |
650 | .stop = abx80x_wdog_stop, | |
651 | .ping = abx80x_wdog_ping, | |
652 | .set_timeout = abx80x_wdog_set_timeout, | |
653 | }; | |
654 | ||
655 | static int abx80x_setup_watchdog(struct abx80x_priv *priv) | |
656 | { | |
657 | priv->wdog.parent = &priv->client->dev; | |
658 | priv->wdog.ops = &abx80x_wdog_ops; | |
659 | priv->wdog.info = &abx80x_wdog_info; | |
660 | priv->wdog.min_timeout = 1; | |
661 | priv->wdog.max_timeout = ABX8XX_WDT_MAX_TIME; | |
662 | priv->wdog.timeout = ABX8XX_WDT_MAX_TIME; | |
663 | ||
664 | watchdog_set_drvdata(&priv->wdog, priv); | |
665 | ||
666 | return devm_watchdog_register_device(&priv->client->dev, &priv->wdog); | |
667 | } | |
668 | #else | |
669 | static int abx80x_setup_watchdog(struct abx80x_priv *priv) | |
670 | { | |
671 | return 0; | |
672 | } | |
673 | #endif | |
674 | ||
4d61ff6b PDM |
675 | static int abx80x_probe(struct i2c_client *client, |
676 | const struct i2c_device_id *id) | |
677 | { | |
678 | struct device_node *np = client->dev.of_node; | |
af69f9a7 | 679 | struct abx80x_priv *priv; |
4d61ff6b PDM |
680 | int i, data, err, trickle_cfg = -EINVAL; |
681 | char buf[7]; | |
682 | unsigned int part = id->driver_data; | |
683 | unsigned int partnumber; | |
684 | unsigned int majrev, minrev; | |
685 | unsigned int lot; | |
686 | unsigned int wafer; | |
687 | unsigned int uid; | |
688 | ||
689 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) | |
690 | return -ENODEV; | |
691 | ||
692 | err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ID0, | |
693 | sizeof(buf), buf); | |
694 | if (err < 0) { | |
695 | dev_err(&client->dev, "Unable to read partnumber\n"); | |
696 | return -EIO; | |
697 | } | |
698 | ||
699 | partnumber = (buf[0] << 8) | buf[1]; | |
700 | majrev = buf[2] >> 3; | |
701 | minrev = buf[2] & 0x7; | |
702 | lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3]; | |
703 | uid = ((buf[4] & 0x7f) << 8) | buf[5]; | |
704 | wafer = (buf[6] & 0x7c) >> 2; | |
705 | dev_info(&client->dev, "model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n", | |
706 | partnumber, majrev, minrev, lot, wafer, uid); | |
707 | ||
708 | data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL1); | |
709 | if (data < 0) { | |
710 | dev_err(&client->dev, "Unable to read control register\n"); | |
711 | return -EIO; | |
712 | } | |
713 | ||
714 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL1, | |
718a820a AB |
715 | ((data & ~(ABX8XX_CTRL_12_24 | |
716 | ABX8XX_CTRL_ARST)) | | |
4d61ff6b PDM |
717 | ABX8XX_CTRL_WRITE)); |
718 | if (err < 0) { | |
719 | dev_err(&client->dev, "Unable to write control register\n"); | |
720 | return -EIO; | |
721 | } | |
722 | ||
75455e25 MV |
723 | /* Configure RV1805 specifics */ |
724 | if (part == RV1805) { | |
725 | /* | |
726 | * Avoid accidentally entering test mode. This can happen | |
727 | * on the RV1805 in case the reserved bit 5 in control2 | |
728 | * register is set. RV-1805-C3 datasheet indicates that | |
729 | * the bit should be cleared in section 11h - Control2. | |
730 | */ | |
731 | data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL2); | |
732 | if (data < 0) { | |
733 | dev_err(&client->dev, | |
734 | "Unable to read control2 register\n"); | |
735 | return -EIO; | |
736 | } | |
737 | ||
738 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL2, | |
739 | data & ~ABX8XX_CTRL2_RSVD); | |
740 | if (err < 0) { | |
741 | dev_err(&client->dev, | |
742 | "Unable to write control2 register\n"); | |
743 | return -EIO; | |
744 | } | |
745 | ||
746 | /* | |
747 | * Avoid extra power leakage. The RV1805 uses smaller | |
748 | * 10pin package and the EXTI input is not present. | |
749 | * Disable it to avoid leakage. | |
750 | */ | |
751 | data = i2c_smbus_read_byte_data(client, ABX8XX_REG_OUT_CTRL); | |
752 | if (data < 0) { | |
753 | dev_err(&client->dev, | |
754 | "Unable to read output control register\n"); | |
755 | return -EIO; | |
756 | } | |
757 | ||
758 | /* | |
759 | * Write the configuration key register to enable access to | |
760 | * the config2 register | |
761 | */ | |
762 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, | |
763 | ABX8XX_CFG_KEY_MISC); | |
764 | if (err < 0) { | |
765 | dev_err(&client->dev, | |
766 | "Unable to write configuration key\n"); | |
767 | return -EIO; | |
768 | } | |
769 | ||
770 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OUT_CTRL, | |
771 | data | ABX8XX_OUT_CTRL_EXDS); | |
772 | if (err < 0) { | |
773 | dev_err(&client->dev, | |
774 | "Unable to write output control register\n"); | |
775 | return -EIO; | |
776 | } | |
777 | } | |
778 | ||
4d61ff6b PDM |
779 | /* part autodetection */ |
780 | if (part == ABX80X) { | |
781 | for (i = 0; abx80x_caps[i].pn; i++) | |
782 | if (partnumber == abx80x_caps[i].pn) | |
783 | break; | |
784 | if (abx80x_caps[i].pn == 0) { | |
785 | dev_err(&client->dev, "Unknown part: %04x\n", | |
786 | partnumber); | |
787 | return -EINVAL; | |
788 | } | |
789 | part = i; | |
790 | } | |
791 | ||
792 | if (partnumber != abx80x_caps[part].pn) { | |
793 | dev_err(&client->dev, "partnumber mismatch %04x != %04x\n", | |
794 | partnumber, abx80x_caps[part].pn); | |
795 | return -EINVAL; | |
796 | } | |
797 | ||
798 | if (np && abx80x_caps[part].has_tc) | |
799 | trickle_cfg = abx80x_dt_trickle_cfg(np); | |
800 | ||
801 | if (trickle_cfg > 0) { | |
802 | dev_info(&client->dev, "Enabling trickle charger: %02x\n", | |
803 | trickle_cfg); | |
804 | abx80x_enable_trickle_charger(client, trickle_cfg); | |
805 | } | |
806 | ||
718a820a AB |
807 | err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CD_TIMER_CTL, |
808 | BIT(2)); | |
809 | if (err) | |
810 | return err; | |
811 | ||
af69f9a7 JG |
812 | priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); |
813 | if (priv == NULL) | |
814 | return -ENOMEM; | |
815 | ||
816 | priv->rtc = devm_rtc_allocate_device(&client->dev); | |
817 | if (IS_ERR(priv->rtc)) | |
818 | return PTR_ERR(priv->rtc); | |
4d61ff6b | 819 | |
af69f9a7 JG |
820 | priv->rtc->ops = &abx80x_rtc_ops; |
821 | priv->client = client; | |
9360a6a8 | 822 | |
af69f9a7 | 823 | i2c_set_clientdata(client, priv); |
4d61ff6b | 824 | |
749e36d0 JG |
825 | if (abx80x_caps[part].has_wdog) { |
826 | err = abx80x_setup_watchdog(priv); | |
827 | if (err) | |
828 | return err; | |
829 | } | |
830 | ||
718a820a AB |
831 | if (client->irq > 0) { |
832 | dev_info(&client->dev, "IRQ %d supplied\n", client->irq); | |
833 | err = devm_request_threaded_irq(&client->dev, client->irq, NULL, | |
834 | abx80x_handle_irq, | |
835 | IRQF_SHARED | IRQF_ONESHOT, | |
836 | "abx8xx", | |
837 | client); | |
838 | if (err) { | |
839 | dev_err(&client->dev, "unable to request IRQ, alarms disabled\n"); | |
840 | client->irq = 0; | |
841 | } | |
842 | } | |
843 | ||
559e883e | 844 | err = rtc_add_group(priv->rtc, &rtc_calib_attr_group); |
59a8383a MJ |
845 | if (err) { |
846 | dev_err(&client->dev, "Failed to create sysfs group: %d\n", | |
847 | err); | |
848 | return err; | |
849 | } | |
850 | ||
559e883e | 851 | return rtc_register_device(priv->rtc); |
4d61ff6b PDM |
852 | } |
853 | ||
4d61ff6b PDM |
854 | static const struct i2c_device_id abx80x_id[] = { |
855 | { "abx80x", ABX80X }, | |
856 | { "ab0801", AB0801 }, | |
857 | { "ab0803", AB0803 }, | |
858 | { "ab0804", AB0804 }, | |
859 | { "ab0805", AB0805 }, | |
860 | { "ab1801", AB1801 }, | |
861 | { "ab1803", AB1803 }, | |
862 | { "ab1804", AB1804 }, | |
863 | { "ab1805", AB1805 }, | |
75455e25 | 864 | { "rv1805", RV1805 }, |
4d61ff6b PDM |
865 | { } |
866 | }; | |
867 | MODULE_DEVICE_TABLE(i2c, abx80x_id); | |
868 | ||
869 | static struct i2c_driver abx80x_driver = { | |
870 | .driver = { | |
871 | .name = "rtc-abx80x", | |
872 | }, | |
873 | .probe = abx80x_probe, | |
4d61ff6b PDM |
874 | .id_table = abx80x_id, |
875 | }; | |
876 | ||
877 | module_i2c_driver(abx80x_driver); | |
878 | ||
879 | MODULE_AUTHOR("Philippe De Muyter <phdm@macqel.be>"); | |
7d1e5bfe | 880 | MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>"); |
4d61ff6b PDM |
881 | MODULE_DESCRIPTION("Abracon ABX80X RTC driver"); |
882 | MODULE_LICENSE("GPL v2"); |