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mfd: kempld-core: Constify variables that point to const structure
[linux-2.6-block.git] / drivers / rtc / rtc-ab-b5ze-s3.c
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0b2f6228
AE		 1/*
2 * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
3 * I2C RTC / Alarm chip
4 *
5 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
6 *
7 * Detailed datasheet of the chip is available here:
8 *
9 * http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
10 *
11 * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24#include <linux/module.h>
25#include <linux/mutex.h>
26#include <linux/rtc.h>
27#include <linux/i2c.h>
28#include <linux/bcd.h>
29#include <linux/of.h>
30#include <linux/regmap.h>
31#include <linux/interrupt.h>
32
33#define DRV_NAME "rtc-ab-b5ze-s3"
34
35/* Control section */
36#define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
37#define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
38#define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
39#define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
40#define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
41#define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
42#define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
43#define ABB5ZES3_REG_CTRL1_CAP BIT(7)
44
45#define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
46#define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
47#define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
48#define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
49#define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
50#define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
51#define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
52#define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
53#define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
54
55#define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
56#define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
57#define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
58#define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
59#define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
60#define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
61#define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
62#define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
63
64#define ABB5ZES3_CTRL_SEC_LEN 3
65
66/* RTC section */
67#define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
68#define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
69#define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
70#define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
71#define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
72#define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
73#define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
74#define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
75#define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
76
77#define ABB5ZES3_RTC_SEC_LEN 7
78
79/* Alarm section (enable bits are all active low) */
80#define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
81#define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
82#define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
83#define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
84#define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
85#define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
86#define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
87#define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
88
89#define ABB5ZES3_ALRM_SEC_LEN 4
90
91/* Frequency offset section */
92#define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
93#define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
94
95/* CLOCKOUT section */
96#define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
97#define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
98#define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
99#define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
100#define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
101#define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
102#define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
103#define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
104#define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
105
106/* Timer A Section */
107#define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
108#define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
109#define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
110#define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
111#define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
112
113#define ABB5ZES3_TIMA_SEC_LEN 2
114
115/* Timer B Section */
116#define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
117#define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
118#define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
119#define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
120#define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
121#define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
122#define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
123#define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
124#define ABB5ZES3_TIMB_SEC_LEN 2
125
126#define ABB5ZES3_MEM_MAP_LEN 0x14
127
128struct abb5zes3_rtc_data {
129 struct rtc_device *rtc;
130 struct regmap *regmap;
131 struct mutex lock;
132
133 int irq;
134
135 bool battery_low;
c8a1d8a5 136 bool timer_alarm; /* current alarm is via timer A */
0b2f6228
AE		 137};
138
139/*
140 * Try and match register bits w/ fixed null values to see whether we
141 * are dealing with an ABB5ZES3. Note: this function is called early
142 * during init and hence does need mutex protection.
143 */
144static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
145{
146 u8 regs[ABB5ZES3_MEM_MAP_LEN];
147 static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
148 0x80, 0xc0, 0xc0, 0xf8,
149 0xe0, 0x00, 0x00, 0x40,
150 0x40, 0x78, 0x00, 0x00,
151 0xf8, 0x00, 0x88, 0x00 };
152 int ret, i;
153
154 ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
155 if (ret)
156 return ret;
157
158 for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
159 if (regs[i] & mask[i]) /* check if bits are cleared */
160 return -ENODEV;
161 }
162
163 return 0;
164}
165
166/* Clear alarm status bit. */
167static int _abb5zes3_rtc_clear_alarm(struct device *dev)
168{
169 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
170 int ret;
171
172 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
173 ABB5ZES3_REG_CTRL2_AF, 0);
174 if (ret)
175 dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
176
177 return ret;
178}
179
180/* Enable or disable alarm (i.e. alarm interrupt generation) */
181static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
182{
183 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
184 int ret;
185
186 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
187 ABB5ZES3_REG_CTRL1_AIE,
188 enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
189 if (ret)
190 dev_err(dev, "%s: writing alarm INT failed (%d)\n",
191 __func__, ret);
192
193 return ret;
194}
195
c8a1d8a5
AE		 196/* Enable or disable timer (watchdog timer A interrupt generation) */
197static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
198{
199 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
200 int ret;
201
202 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
203 ABB5ZES3_REG_CTRL2_WTAIE,
204 enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
205 if (ret)
206 dev_err(dev, "%s: writing timer INT failed (%d)\n",
207 __func__, ret);
208
209 return ret;
210}
211
0b2f6228
AE		 212/*
213 * Note: we only read, so regmap inner lock protection is sufficient, i.e.
214 * we do not need driver's main lock protection.
215 */
216static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
217{
218 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
219 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
ce2e5a76 220 int ret = 0;
0b2f6228
AE		 221
222 /*
223 * As we need to read CTRL1 register anyway to access 24/12h
224 * mode bit, we do a single bulk read of both control and RTC
225 * sections (they are consecutive). This also ease indexing
226 * of register values after bulk read.
227 */
228 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
229 sizeof(regs));
230 if (ret) {
231 dev_err(dev, "%s: reading RTC time failed (%d)\n",
232 __func__, ret);
233 goto err;
234 }
235
236 /* If clock integrity is not guaranteed, do not return a time value */
237 if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC) {
238 ret = -ENODATA;
239 goto err;
240 }
241
242 tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
243 tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
244
245 if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
246 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
247 if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
248 tm->tm_hour += 12;
249 } else { /* 24hr mode */
250 tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
251 }
252
253 tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
254 tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
255 tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
256 tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
257
0b2f6228
AE		 258err:
259 return ret;
260}
261
262static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
263{
264 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
265 u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
266 int ret;
267
0b2f6228
AE		 268 regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
269 regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
270 regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
271 regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
272 regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
273 regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
274 regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
275
276 mutex_lock(&data->lock);
277 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
278 regs + ABB5ZES3_REG_RTC_SC,
279 ABB5ZES3_RTC_SEC_LEN);
280 mutex_unlock(&data->lock);
281
282
283 return ret;
284}
285
c8a1d8a5
AE		 286/*
287 * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
288 * given number of seconds.
289 */
290static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
291{
292 *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
293 *timer_a = secs;
294}
295
296/*
297 * Return current number of seconds in Timer A. As we only use
298 * timer A with a 1Hz freq, this is what we expect to have.
299 */
300static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
301{
302 if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
303 return -EINVAL;
304
305 *secs = timer_a;
306
307 return 0;
308}
309
310/*
311 * Read alarm currently configured via a watchdog timer using timer A. This
312 * is done by reading current RTC time and adding remaining timer time.
313 */
314static int _abb5zes3_rtc_read_timer(struct device *dev,
315 struct rtc_wkalrm *alarm)
316{
317 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
318 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
319 u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
320 unsigned long rtc_secs;
321 unsigned int reg;
322 u8 timer_secs;
323 int ret;
324
325 /*
326 * Instead of doing two separate calls, because they are consecutive,
327 * we grab both clockout register and Timer A section. The latter is
328 * used to decide if timer A is enabled (as a watchdog timer).
329 */
330 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
331 ABB5ZES3_TIMA_SEC_LEN + 1);
332 if (ret) {
333 dev_err(dev, "%s: reading Timer A section failed (%d)\n",
334 __func__, ret);
335 goto err;
336 }
337
338 /* get current time ... */
339 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
340 if (ret)
341 goto err;
342
343 /* ... convert to seconds ... */
344 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
345 if (ret)
346 goto err;
347
348 /* ... add remaining timer A time ... */
349 ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
350 if (ret)
351 goto err;
352
353 /* ... and convert back. */
354 rtc_time_to_tm(rtc_secs + timer_secs, alarm_tm);
355
356 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, &reg);
357 if (ret) {
358 dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
359 __func__, ret);
360 goto err;
361 }
362
363 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
364
365err:
366 return ret;
367}
368
369/* Read alarm currently configured via a RTC alarm registers. */
370static int _abb5zes3_rtc_read_alarm(struct device *dev,
371 struct rtc_wkalrm *alarm)
0b2f6228
AE		 372{
373 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
374 struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
375 unsigned long rtc_secs, alarm_secs;
376 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
377 unsigned int reg;
378 int ret;
379
0b2f6228
AE		 380 ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
381 ABB5ZES3_ALRM_SEC_LEN);
382 if (ret) {
383 dev_err(dev, "%s: reading alarm section failed (%d)\n",
384 __func__, ret);
385 goto err;
386 }
387
388 alarm_tm->tm_sec = 0;
389 alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f);
390 alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
391 alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
392 alarm_tm->tm_wday = -1;
393
394 /*
395 * The alarm section does not store year/month. We use the ones in rtc
396 * section as a basis and increment month and then year if needed to get
397 * alarm after current time.
398 */
399 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
400 if (ret)
401 goto err;
402
403 alarm_tm->tm_year = rtc_tm.tm_year;
404 alarm_tm->tm_mon = rtc_tm.tm_mon;
405
406 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
407 if (ret)
408 goto err;
409
410 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
411 if (ret)
412 goto err;
413
414 if (alarm_secs < rtc_secs) {
415 if (alarm_tm->tm_mon == 11) {
416 alarm_tm->tm_mon = 0;
417 alarm_tm->tm_year += 1;
418 } else {
419 alarm_tm->tm_mon += 1;
420 }
421 }
422
423 ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, &reg);
424 if (ret) {
425 dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
426 __func__, ret);
427 goto err;
428 }
429
430 alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
431
432err:
c8a1d8a5
AE		 433 return ret;
434}
435
436/*
437 * As the Alarm mechanism supported by the chip is only accurate to the
438 * minute, we use the watchdog timer mechanism provided by timer A
439 * (up to 256 seconds w/ a second accuracy) for low alarm values (below
440 * 4 minutes). Otherwise, we use the common alarm mechanism provided
441 * by the chip. In order for that to work, we keep track of currently
442 * configured timer type via 'timer_alarm' flag in our private data
443 * structure.
444 */
445static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
446{
447 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
448 int ret;
449
450 mutex_lock(&data->lock);
451 if (data->timer_alarm)
452 ret = _abb5zes3_rtc_read_timer(dev, alarm);
453 else
454 ret = _abb5zes3_rtc_read_alarm(dev, alarm);
0b2f6228
AE		 455 mutex_unlock(&data->lock);
456
457 return ret;
458}
459
c8a1d8a5
AE		 460/*
461 * Set alarm using chip alarm mechanism. It is only accurate to the
462 * minute (not the second). The function expects alarm interrupt to
463 * be disabled.
464 */
465static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0b2f6228
AE		 466{
467 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
468 struct rtc_time *alarm_tm = &alarm->time;
469 unsigned long rtc_secs, alarm_secs;
470 u8 regs[ABB5ZES3_ALRM_SEC_LEN];
471 struct rtc_time rtc_tm;
472 int ret, enable = 1;
473
0b2f6228
AE		 474 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
475 if (ret)
476 goto err;
477
478 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
479 if (ret)
480 goto err;
481
482 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
483 if (ret)
484 goto err;
485
486 /* If alarm time is before current time, disable the alarm */
487 if (!alarm->enabled || alarm_secs <= rtc_secs) {
488 enable = 0;
489 } else {
490 /*
491 * Chip only support alarms up to one month in the future. Let's
492 * return an error if we get something after that limit.
493 * Comparison is done by incrementing rtc_tm month field by one
494 * and checking alarm value is still below.
495 */
496 if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
497 rtc_tm.tm_mon = 0;
498 rtc_tm.tm_year += 1;
499 } else {
500 rtc_tm.tm_mon += 1;
501 }
502
503 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
504 if (ret)
505 goto err;
506
507 if (alarm_secs > rtc_secs) {
508 dev_err(dev, "%s: alarm maximum is one month in the "
509 "future (%d)\n", __func__, ret);
510 ret = -EINVAL;
511 goto err;
512 }
513 }
514
c8a1d8a5
AE		 515 /*
516 * Program all alarm registers but DW one. For each register, setting
517 * MSB to 0 enables associated alarm.
518 */
519 regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
520 regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
521 regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
0b2f6228
AE		 522 regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
523
524 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
525 ABB5ZES3_ALRM_SEC_LEN);
526 if (ret < 0) {
527 dev_err(dev, "%s: writing ALARM section failed (%d)\n",
528 __func__, ret);
529 goto err;
530 }
531
c8a1d8a5
AE		 532 /* Record currently configured alarm is not a timer */
533 data->timer_alarm = 0;
534
535 /* Enable or disable alarm interrupt generation */
0b2f6228
AE		 536 ret = _abb5zes3_rtc_update_alarm(dev, enable);
537
538err:
c8a1d8a5
AE		 539 return ret;
540}
541
542/*
543 * Set alarm using timer watchdog (via timer A) mechanism. The function expects
544 * timer A interrupt to be disabled.
545 */
546static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
547 u8 secs)
548{
549 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
550 u8 regs[ABB5ZES3_TIMA_SEC_LEN];
551 u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
552 int ret = 0;
553
554 /* Program given number of seconds to Timer A registers */
555 sec_to_timer_a(secs, &regs[0], &regs[1]);
556 ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
557 ABB5ZES3_TIMA_SEC_LEN);
558 if (ret < 0) {
559 dev_err(dev, "%s: writing timer section failed\n", __func__);
560 goto err;
561 }
562
563 /* Configure Timer A as a watchdog timer */
564 ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
565 mask, ABB5ZES3_REG_TIM_CLK_TAC1);
566 if (ret)
567 dev_err(dev, "%s: failed to update timer\n", __func__);
568
569 /* Record currently configured alarm is a timer */
570 data->timer_alarm = 1;
0b2f6228 571
c8a1d8a5
AE		 572 /* Enable or disable timer interrupt generation */
573 ret = _abb5zes3_rtc_update_timer(dev, alarm->enabled);
574
575err:
0b2f6228
AE		 576 return ret;
577}
578
c8a1d8a5
AE		 579/*
580 * The chip has an alarm which is only accurate to the minute. In order to
581 * handle alarms below that limit, we use the watchdog timer function of
582 * timer A. More precisely, the timer method is used for alarms below 240
583 * seconds.
584 */
585static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
586{
587 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
588 struct rtc_time *alarm_tm = &alarm->time;
589 unsigned long rtc_secs, alarm_secs;
590 struct rtc_time rtc_tm;
591 int ret;
592
593 mutex_lock(&data->lock);
594 ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
595 if (ret)
596 goto err;
597
598 ret = rtc_tm_to_time(&rtc_tm, &rtc_secs);
599 if (ret)
600 goto err;
601
602 ret = rtc_tm_to_time(alarm_tm, &alarm_secs);
603 if (ret)
604 goto err;
605
606 /* Let's first disable both the alarm and the timer interrupts */
607 ret = _abb5zes3_rtc_update_alarm(dev, false);
608 if (ret < 0) {
609 dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
610 ret);
611 goto err;
612 }
613 ret = _abb5zes3_rtc_update_timer(dev, false);
614 if (ret < 0) {
615 dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
616 ret);
617 goto err;
618 }
619
620 data->timer_alarm = 0;
621
622 /*
623 * Let's now configure the alarm; if we are expected to ring in
624 * more than 240s, then we setup an alarm. Otherwise, a timer.
625 */
626 if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
627 ret = _abb5zes3_rtc_set_timer(dev, alarm,
628 alarm_secs - rtc_secs);
629 else
630 ret = _abb5zes3_rtc_set_alarm(dev, alarm);
631
632 err:
633 mutex_unlock(&data->lock);
634
635 if (ret)
636 dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
637 ret);
638
639 return ret;
447a5647 640}
0b2f6228
AE		 641
642/* Enable or disable battery low irq generation */
643static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
644 bool enable)
645{
646 return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
647 ABB5ZES3_REG_CTRL3_BLIE,
648 enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
649}
650
651/*
652 * Check current RTC status and enable/disable what needs to be. Return 0 if
653 * everything went ok and a negative value upon error. Note: this function
654 * is called early during init and hence does need mutex protection.
655 */
656static int abb5zes3_rtc_check_setup(struct device *dev)
657{
658 struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
c8a1d8a5 659 struct regmap *regmap = data->regmap;
0b2f6228
AE		 660 unsigned int reg;
661 int ret;
662 u8 mask;
663
664 /*
665 * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
666 * is disabled here to prevent polluting the interrupt line and
667 * uselessly triggering the IRQ handler we install for alarm and battery
668 * low events. Note: this is done before clearing int. status below
669 * in this function.
670 * We also disable all timers and set timer interrupt to permanent (not
671 * pulsed).
672 */
673 mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
674 ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
675 ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
676 ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
677 ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
678 ABB5ZES3_REG_TIM_CLK_COF0 | ABB5ZES3_REG_TIM_CLK_COF1 |
679 ABB5ZES3_REG_TIM_CLK_COF2);
680 if (ret < 0) {
681 dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
682 __func__, ret);
683 return ret;
684 }
685
686 /*
687 * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
688 * individually by clearing/setting MSB of each associated register. So,
689 * we set all alarm enable bits to disable current alarm setting.
690 */
691 mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
692 ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
693 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
694 if (ret < 0) {
695 dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
696 __func__, ret);
697 return ret;
698 }
699
700 /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
701 mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
702 ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
703 ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
704 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
705 if (ret < 0) {
706 dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
707 __func__, ret);
708 return ret;
709 }
710
711 /*
712 * Set Control 2 register (timer int. disabled, alarm status cleared).
713 * WTAF is read-only and cleared automatically by reading the register.
714 */
715 mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
716 ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
717 ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
718 ABB5ZES3_REG_CTRL2_CTAF);
719 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
720 if (ret < 0) {
721 dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
722 __func__, ret);
723 return ret;
724 }
725
726 /*
727 * Enable battery low detection function and battery switchover function
728 * (standard mode). Disable associated interrupts. Clear battery
729 * switchover flag but not battery low flag. The latter is checked
730 * later below.
731 */
732 mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 |
733 ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE |
734 ABB5ZES3_REG_CTRL3_BSIE| ABB5ZES3_REG_CTRL3_BSF);
735 ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
736 if (ret < 0) {
737 dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
738 __func__, ret);
739 return ret;
740 }
741
742 /* Check oscillator integrity flag */
743 ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, &reg);
744 if (ret < 0) {
745 dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
746 __func__, ret);
747 return ret;
748 }
749
750 if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
751 dev_err(dev, "clock integrity not guaranteed. Osc. has stopped "
752 "or has been interrupted.\n");
753 dev_err(dev, "change battery (if not already done) and "
754 "then set time to reset osc. failure flag.\n");
755 }
756
757 /*
758 * Check battery low flag at startup: this allows reporting battery
759 * is low at startup when IRQ line is not connected. Note: we record
760 * current status to avoid reenabling this interrupt later in probe
761 * function if battery is low.
762 */
763 ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, &reg);
764 if (ret < 0) {
765 dev_err(dev, "%s: unable to read battery low flag (%d)\n",
766 __func__, ret);
767 return ret;
768 }
769
770 data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
771 if (data->battery_low) {
772 dev_err(dev, "RTC battery is low; please, consider "
773 "changing it!\n");
774
775 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
776 if (ret)
777 dev_err(dev, "%s: disabling battery low interrupt "
778 "generation failed (%d)\n", __func__, ret);
779 }
780
781 return ret;
782}
783
784static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
785 unsigned int enable)
786{
787 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
788 int ret = 0;
789
790 if (rtc_data->irq) {
791 mutex_lock(&rtc_data->lock);
c8a1d8a5
AE		 792 if (rtc_data->timer_alarm)
793 ret = _abb5zes3_rtc_update_timer(dev, enable);
794 else
795 ret = _abb5zes3_rtc_update_alarm(dev, enable);
0b2f6228
AE		 796 mutex_unlock(&rtc_data->lock);
797 }
798
799 return ret;
800}
801
802static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
803{
804 struct i2c_client *client = data;
805 struct device *dev = &client->dev;
806 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
807 struct rtc_device *rtc = rtc_data->rtc;
808 u8 regs[ABB5ZES3_CTRL_SEC_LEN];
809 int ret, handled = IRQ_NONE;
810
811 ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
812 ABB5ZES3_CTRL_SEC_LEN);
813 if (ret) {
814 dev_err(dev, "%s: unable to read control section (%d)!\n",
815 __func__, ret);
816 return handled;
817 }
818
819 /*
820 * Check battery low detection flag and disable battery low interrupt
821 * generation if flag is set (interrupt can only be cleared when
822 * battery is replaced).
823 */
824 if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
825 dev_err(dev, "RTC battery is low; please change it!\n");
826
827 _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
828
829 handled = IRQ_HANDLED;
830 }
831
832 /* Check alarm flag */
833 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
834 dev_dbg(dev, "RTC alarm!\n");
835
836 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
837
838 /* Acknowledge and disable the alarm */
839 _abb5zes3_rtc_clear_alarm(dev);
840 _abb5zes3_rtc_update_alarm(dev, 0);
841
842 handled = IRQ_HANDLED;
843 }
844
c8a1d8a5
AE		 845 /* Check watchdog Timer A flag */
846 if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
847 dev_dbg(dev, "RTC timer!\n");
848
849 rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
850
851 /*
852 * Acknowledge and disable the alarm. Note: WTAF
853 * flag had been cleared when reading CTRL2
854 */
855 _abb5zes3_rtc_update_timer(dev, 0);
856
857 rtc_data->timer_alarm = 0;
858
859 handled = IRQ_HANDLED;
860 }
861
0b2f6228
AE		 862 return handled;
863}
864
865static const struct rtc_class_ops rtc_ops = {
866 .read_time = _abb5zes3_rtc_read_time,
867 .set_time = abb5zes3_rtc_set_time,
868 .read_alarm = abb5zes3_rtc_read_alarm,
869 .set_alarm = abb5zes3_rtc_set_alarm,
870 .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
871};
872
ac2a2726 873static const struct regmap_config abb5zes3_rtc_regmap_config = {
0b2f6228
AE		 874 .reg_bits = 8,
875 .val_bits = 8,
876};
877
878static int abb5zes3_probe(struct i2c_client *client,
879 const struct i2c_device_id *id)
880{
881 struct abb5zes3_rtc_data *data = NULL;
882 struct device *dev = &client->dev;
883 struct regmap *regmap;
884 int ret;
885
886 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
887 I2C_FUNC_SMBUS_BYTE_DATA |
888 I2C_FUNC_SMBUS_I2C_BLOCK)) {
889 ret = -ENODEV;
890 goto err;
891 }
892
893 regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
894 if (IS_ERR(regmap)) {
895 ret = PTR_ERR(regmap);
896 dev_err(dev, "%s: regmap allocation failed: %d\n",
897 __func__, ret);
898 goto err;
899 }
900
901 ret = abb5zes3_i2c_validate_chip(regmap);
902 if (ret)
903 goto err;
904
905 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
906 if (!data) {
907 ret = -ENOMEM;
908 goto err;
909 }
910
911 mutex_init(&data->lock);
912 data->regmap = regmap;
913 dev_set_drvdata(dev, data);
914
915 ret = abb5zes3_rtc_check_setup(dev);
916 if (ret)
917 goto err;
918
8bde032b
AB		 919 data->rtc = devm_rtc_allocate_device(dev);
920 ret = PTR_ERR_OR_ZERO(data->rtc);
921 if (ret) {
922 dev_err(dev, "%s: unable to allocate RTC device (%d)\n",
923 __func__, ret);
924 goto err;
925 }
926
0b2f6228
AE		 927 if (client->irq > 0) {
928 ret = devm_request_threaded_irq(dev, client->irq, NULL,
929 _abb5zes3_rtc_interrupt,
930 IRQF_SHARED|IRQF_ONESHOT,
931 DRV_NAME, client);
932 if (!ret) {
933 device_init_wakeup(dev, true);
934 data->irq = client->irq;
935 dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
936 client->irq);
937 } else {
938 dev_err(dev, "%s: irq %d unavailable (%d)\n",
939 __func__, client->irq, ret);
940 goto err;
941 }
942 }
943
8bde032b 944 data->rtc->ops = &rtc_ops;
c402f8ea
AB		 945 data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
946 data->rtc->range_max = RTC_TIMESTAMP_END_2099;
0b2f6228 947
0b2f6228
AE		 948 /* Enable battery low detection interrupt if battery not already low */
949 if (!data->battery_low && data->irq) {
950 ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
951 if (ret) {
952 dev_err(dev, "%s: enabling battery low interrupt "
953 "generation failed (%d)\n", __func__, ret);
954 goto err;
955 }
956 }
957
8bde032b
AB		 958 ret = rtc_register_device(data->rtc);
959
0b2f6228
AE		 960err:
961 if (ret && data && data->irq)
962 device_init_wakeup(dev, false);
963 return ret;
964}
965
966static int abb5zes3_remove(struct i2c_client *client)
967{
968 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(&client->dev);
969
970 if (rtc_data->irq > 0)
971 device_init_wakeup(&client->dev, false);
972
973 return 0;
974}
975
976#ifdef CONFIG_PM_SLEEP
977static int abb5zes3_rtc_suspend(struct device *dev)
978{
979 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
980
981 if (device_may_wakeup(dev))
982 return enable_irq_wake(rtc_data->irq);
983
984 return 0;
985}
986
987static int abb5zes3_rtc_resume(struct device *dev)
988{
989 struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
990
991 if (device_may_wakeup(dev))
992 return disable_irq_wake(rtc_data->irq);
993
994 return 0;
995}
996#endif
997
998static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
999 abb5zes3_rtc_resume);
1000
1001#ifdef CONFIG_OF
1002static const struct of_device_id abb5zes3_dt_match[] = {
1003 { .compatible = "abracon,abb5zes3" },
1004 { },
1005};
1c4fc295 1006MODULE_DEVICE_TABLE(of, abb5zes3_dt_match);
0b2f6228
AE		 1007#endif
1008
1009static const struct i2c_device_id abb5zes3_id[] = {
1010 { "abb5zes3", 0 },
1011 { }
1012};
1013MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
1014
1015static struct i2c_driver abb5zes3_driver = {
1016 .driver = {
1017 .name = DRV_NAME,
0b2f6228
AE		 1018 .pm = &abb5zes3_rtc_pm_ops,
1019 .of_match_table = of_match_ptr(abb5zes3_dt_match),
1020 },
1021 .probe = abb5zes3_probe,
1022 .remove = abb5zes3_remove,
1023 .id_table = abb5zes3_id,
1024};
1025module_i2c_driver(abb5zes3_driver);
1026
1027MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
1028MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
1029MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)