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84369fbe | 1 | // SPDX-License-Identifier: GPL-2.0 |
caf989c3 BA |
2 | /* |
3 | * Copyright (c) 2016, Linaro Ltd | |
caf989c3 BA |
4 | */ |
5 | ||
6 | #include <linux/io.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/of.h> | |
9 | #include <linux/of_address.h> | |
f424d1cb | 10 | #include <linux/of_irq.h> |
caf989c3 BA |
11 | #include <linux/interrupt.h> |
12 | #include <linux/platform_device.h> | |
f424d1cb | 13 | #include <linux/mailbox_client.h> |
caf989c3 BA |
14 | #include <linux/mfd/syscon.h> |
15 | #include <linux/slab.h> | |
16 | #include <linux/rpmsg.h> | |
17 | #include <linux/idr.h> | |
18 | #include <linux/circ_buf.h> | |
19 | #include <linux/soc/qcom/smem.h> | |
20 | #include <linux/sizes.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/workqueue.h> | |
24 | #include <linux/list.h> | |
25 | ||
caf989c3 BA |
26 | #include <linux/rpmsg/qcom_glink.h> |
27 | ||
28 | #include "qcom_glink_native.h" | |
29 | ||
30 | #define FIFO_FULL_RESERVE 8 | |
31 | #define FIFO_ALIGNMENT 8 | |
32 | #define TX_BLOCKED_CMD_RESERVE 8 /* size of struct read_notif_request */ | |
33 | ||
34 | #define SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR 478 | |
35 | #define SMEM_GLINK_NATIVE_XPRT_FIFO_0 479 | |
36 | #define SMEM_GLINK_NATIVE_XPRT_FIFO_1 480 | |
37 | ||
ab9fdd41 BA |
38 | struct qcom_glink_smem { |
39 | struct device dev; | |
40 | ||
f424d1cb | 41 | int irq; |
ab9fdd41 BA |
42 | struct qcom_glink *glink; |
43 | ||
f424d1cb BA |
44 | struct mbox_client mbox_client; |
45 | struct mbox_chan *mbox_chan; | |
46 | ||
ab9fdd41 BA |
47 | u32 remote_pid; |
48 | }; | |
49 | ||
caf989c3 BA |
50 | struct glink_smem_pipe { |
51 | struct qcom_glink_pipe native; | |
52 | ||
53 | __le32 *tail; | |
54 | __le32 *head; | |
55 | ||
56 | void *fifo; | |
57 | ||
ab9fdd41 | 58 | struct qcom_glink_smem *smem; |
caf989c3 BA |
59 | }; |
60 | ||
61 | #define to_smem_pipe(p) container_of(p, struct glink_smem_pipe, native) | |
62 | ||
63 | static size_t glink_smem_rx_avail(struct qcom_glink_pipe *np) | |
64 | { | |
65 | struct glink_smem_pipe *pipe = to_smem_pipe(np); | |
ab9fdd41 | 66 | struct qcom_glink_smem *smem = pipe->smem; |
caf989c3 BA |
67 | size_t len; |
68 | void *fifo; | |
69 | u32 head; | |
70 | u32 tail; | |
71 | ||
72 | if (!pipe->fifo) { | |
ab9fdd41 | 73 | fifo = qcom_smem_get(smem->remote_pid, |
caf989c3 BA |
74 | SMEM_GLINK_NATIVE_XPRT_FIFO_1, &len); |
75 | if (IS_ERR(fifo)) { | |
76 | pr_err("failed to acquire RX fifo handle: %ld\n", | |
77 | PTR_ERR(fifo)); | |
78 | return 0; | |
79 | } | |
80 | ||
81 | pipe->fifo = fifo; | |
82 | pipe->native.length = len; | |
83 | } | |
84 | ||
85 | head = le32_to_cpu(*pipe->head); | |
86 | tail = le32_to_cpu(*pipe->tail); | |
87 | ||
88 | if (head < tail) | |
89 | return pipe->native.length - tail + head; | |
90 | else | |
91 | return head - tail; | |
92 | } | |
93 | ||
a8f500c6 | 94 | static void glink_smem_rx_peek(struct qcom_glink_pipe *np, |
b88eee97 | 95 | void *data, unsigned int offset, size_t count) |
caf989c3 BA |
96 | { |
97 | struct glink_smem_pipe *pipe = to_smem_pipe(np); | |
98 | size_t len; | |
99 | u32 tail; | |
100 | ||
101 | tail = le32_to_cpu(*pipe->tail); | |
b88eee97 BA |
102 | tail += offset; |
103 | if (tail >= pipe->native.length) | |
104 | tail -= pipe->native.length; | |
caf989c3 BA |
105 | |
106 | len = min_t(size_t, count, pipe->native.length - tail); | |
928002a5 AKN |
107 | if (len) |
108 | memcpy_fromio(data, pipe->fifo + tail, len); | |
caf989c3 | 109 | |
928002a5 AKN |
110 | if (len != count) |
111 | memcpy_fromio(data + len, pipe->fifo, (count - len)); | |
caf989c3 BA |
112 | } |
113 | ||
114 | static void glink_smem_rx_advance(struct qcom_glink_pipe *np, | |
115 | size_t count) | |
116 | { | |
117 | struct glink_smem_pipe *pipe = to_smem_pipe(np); | |
118 | u32 tail; | |
119 | ||
120 | tail = le32_to_cpu(*pipe->tail); | |
121 | ||
122 | tail += count; | |
4623e8bf | 123 | if (tail >= pipe->native.length) |
caf989c3 BA |
124 | tail -= pipe->native.length; |
125 | ||
126 | *pipe->tail = cpu_to_le32(tail); | |
127 | } | |
128 | ||
129 | static size_t glink_smem_tx_avail(struct qcom_glink_pipe *np) | |
130 | { | |
131 | struct glink_smem_pipe *pipe = to_smem_pipe(np); | |
132 | u32 head; | |
133 | u32 tail; | |
134 | u32 avail; | |
135 | ||
136 | head = le32_to_cpu(*pipe->head); | |
137 | tail = le32_to_cpu(*pipe->tail); | |
138 | ||
139 | if (tail <= head) | |
140 | avail = pipe->native.length - head + tail; | |
141 | else | |
142 | avail = tail - head; | |
143 | ||
144 | if (avail < (FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE)) | |
145 | avail = 0; | |
146 | else | |
147 | avail -= FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE; | |
148 | ||
149 | return avail; | |
150 | } | |
151 | ||
152 | static unsigned int glink_smem_tx_write_one(struct glink_smem_pipe *pipe, | |
153 | unsigned int head, | |
154 | const void *data, size_t count) | |
155 | { | |
156 | size_t len; | |
157 | ||
158 | len = min_t(size_t, count, pipe->native.length - head); | |
159 | if (len) | |
160 | memcpy(pipe->fifo + head, data, len); | |
161 | ||
162 | if (len != count) | |
163 | memcpy(pipe->fifo, data + len, count - len); | |
164 | ||
165 | head += count; | |
166 | if (head >= pipe->native.length) | |
167 | head -= pipe->native.length; | |
168 | ||
169 | return head; | |
170 | } | |
171 | ||
172 | static void glink_smem_tx_write(struct qcom_glink_pipe *glink_pipe, | |
173 | const void *hdr, size_t hlen, | |
174 | const void *data, size_t dlen) | |
175 | { | |
176 | struct glink_smem_pipe *pipe = to_smem_pipe(glink_pipe); | |
177 | unsigned int head; | |
178 | ||
179 | head = le32_to_cpu(*pipe->head); | |
180 | ||
181 | head = glink_smem_tx_write_one(pipe, head, hdr, hlen); | |
182 | head = glink_smem_tx_write_one(pipe, head, data, dlen); | |
183 | ||
184 | /* Ensure head is always aligned to 8 bytes */ | |
185 | head = ALIGN(head, 8); | |
186 | if (head >= pipe->native.length) | |
187 | head -= pipe->native.length; | |
188 | ||
9d324973 BA |
189 | /* Ensure ordering of fifo and head update */ |
190 | wmb(); | |
191 | ||
caf989c3 BA |
192 | *pipe->head = cpu_to_le32(head); |
193 | } | |
194 | ||
f424d1cb BA |
195 | static void glink_smem_tx_kick(struct qcom_glink_pipe *glink_pipe) |
196 | { | |
197 | struct glink_smem_pipe *pipe = to_smem_pipe(glink_pipe); | |
198 | struct qcom_glink_smem *smem = pipe->smem; | |
199 | ||
200 | mbox_send_message(smem->mbox_chan, NULL); | |
201 | mbox_client_txdone(smem->mbox_chan, 0); | |
202 | } | |
203 | ||
204 | static irqreturn_t qcom_glink_smem_intr(int irq, void *data) | |
205 | { | |
206 | struct qcom_glink_smem *smem = data; | |
207 | ||
208 | qcom_glink_native_rx(smem->glink); | |
209 | ||
210 | return IRQ_HANDLED; | |
211 | } | |
212 | ||
caf989c3 BA |
213 | static void qcom_glink_smem_release(struct device *dev) |
214 | { | |
ab9fdd41 BA |
215 | struct qcom_glink_smem *smem = container_of(dev, struct qcom_glink_smem, dev); |
216 | ||
217 | kfree(smem); | |
caf989c3 BA |
218 | } |
219 | ||
ab9fdd41 BA |
220 | struct qcom_glink_smem *qcom_glink_smem_register(struct device *parent, |
221 | struct device_node *node) | |
caf989c3 BA |
222 | { |
223 | struct glink_smem_pipe *rx_pipe; | |
224 | struct glink_smem_pipe *tx_pipe; | |
ab9fdd41 | 225 | struct qcom_glink_smem *smem; |
caf989c3 BA |
226 | struct qcom_glink *glink; |
227 | struct device *dev; | |
228 | u32 remote_pid; | |
229 | __le32 *descs; | |
230 | size_t size; | |
231 | int ret; | |
232 | ||
ab9fdd41 BA |
233 | smem = kzalloc(sizeof(*smem), GFP_KERNEL); |
234 | if (!smem) | |
caf989c3 BA |
235 | return ERR_PTR(-ENOMEM); |
236 | ||
ab9fdd41 BA |
237 | dev = &smem->dev; |
238 | ||
caf989c3 BA |
239 | dev->parent = parent; |
240 | dev->of_node = node; | |
241 | dev->release = qcom_glink_smem_release; | |
9fe69a72 | 242 | dev_set_name(dev, "%s:%pOFn", dev_name(parent->parent), node); |
caf989c3 BA |
243 | ret = device_register(dev); |
244 | if (ret) { | |
245 | pr_err("failed to register glink edge\n"); | |
a9011726 | 246 | put_device(dev); |
caf989c3 BA |
247 | return ERR_PTR(ret); |
248 | } | |
249 | ||
250 | ret = of_property_read_u32(dev->of_node, "qcom,remote-pid", | |
251 | &remote_pid); | |
252 | if (ret) { | |
253 | dev_err(dev, "failed to parse qcom,remote-pid\n"); | |
254 | goto err_put_dev; | |
255 | } | |
256 | ||
ab9fdd41 BA |
257 | smem->remote_pid = remote_pid; |
258 | ||
caf989c3 BA |
259 | rx_pipe = devm_kzalloc(dev, sizeof(*rx_pipe), GFP_KERNEL); |
260 | tx_pipe = devm_kzalloc(dev, sizeof(*tx_pipe), GFP_KERNEL); | |
261 | if (!rx_pipe || !tx_pipe) { | |
262 | ret = -ENOMEM; | |
263 | goto err_put_dev; | |
264 | } | |
265 | ||
266 | ret = qcom_smem_alloc(remote_pid, | |
267 | SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, 32); | |
268 | if (ret && ret != -EEXIST) { | |
269 | dev_err(dev, "failed to allocate glink descriptors\n"); | |
270 | goto err_put_dev; | |
271 | } | |
272 | ||
273 | descs = qcom_smem_get(remote_pid, | |
274 | SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, &size); | |
275 | if (IS_ERR(descs)) { | |
276 | dev_err(dev, "failed to acquire xprt descriptor\n"); | |
277 | ret = PTR_ERR(descs); | |
278 | goto err_put_dev; | |
279 | } | |
280 | ||
281 | if (size != 32) { | |
282 | dev_err(dev, "glink descriptor of invalid size\n"); | |
283 | ret = -EINVAL; | |
284 | goto err_put_dev; | |
285 | } | |
286 | ||
287 | tx_pipe->tail = &descs[0]; | |
288 | tx_pipe->head = &descs[1]; | |
289 | rx_pipe->tail = &descs[2]; | |
290 | rx_pipe->head = &descs[3]; | |
291 | ||
292 | ret = qcom_smem_alloc(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0, | |
293 | SZ_16K); | |
294 | if (ret && ret != -EEXIST) { | |
295 | dev_err(dev, "failed to allocate TX fifo\n"); | |
296 | goto err_put_dev; | |
297 | } | |
298 | ||
299 | tx_pipe->fifo = qcom_smem_get(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0, | |
300 | &tx_pipe->native.length); | |
301 | if (IS_ERR(tx_pipe->fifo)) { | |
302 | dev_err(dev, "failed to acquire TX fifo\n"); | |
303 | ret = PTR_ERR(tx_pipe->fifo); | |
304 | goto err_put_dev; | |
305 | } | |
306 | ||
f424d1cb BA |
307 | smem->irq = of_irq_get(smem->dev.of_node, 0); |
308 | ret = devm_request_irq(&smem->dev, smem->irq, qcom_glink_smem_intr, | |
309 | IRQF_NO_SUSPEND | IRQF_NO_AUTOEN, | |
310 | "glink-smem", smem); | |
311 | if (ret) { | |
312 | dev_err(&smem->dev, "failed to request IRQ\n"); | |
313 | goto err_put_dev; | |
314 | } | |
315 | ||
316 | smem->mbox_client.dev = &smem->dev; | |
317 | smem->mbox_client.knows_txdone = true; | |
318 | smem->mbox_chan = mbox_request_channel(&smem->mbox_client, 0); | |
319 | if (IS_ERR(smem->mbox_chan)) { | |
320 | ret = dev_err_probe(&smem->dev, PTR_ERR(smem->mbox_chan), | |
321 | "failed to acquire IPC channel\n"); | |
322 | goto err_put_dev; | |
323 | } | |
324 | ||
ab9fdd41 | 325 | rx_pipe->smem = smem; |
caf989c3 | 326 | rx_pipe->native.avail = glink_smem_rx_avail; |
a8f500c6 | 327 | rx_pipe->native.peek = glink_smem_rx_peek; |
caf989c3 | 328 | rx_pipe->native.advance = glink_smem_rx_advance; |
caf989c3 | 329 | |
ab9fdd41 | 330 | tx_pipe->smem = smem; |
caf989c3 BA |
331 | tx_pipe->native.avail = glink_smem_tx_avail; |
332 | tx_pipe->native.write = glink_smem_tx_write; | |
f424d1cb | 333 | tx_pipe->native.kick = glink_smem_tx_kick; |
caf989c3 BA |
334 | |
335 | *rx_pipe->tail = 0; | |
336 | *tx_pipe->head = 0; | |
337 | ||
338 | glink = qcom_glink_native_probe(dev, | |
933b45da S |
339 | GLINK_FEATURE_INTENT_REUSE, |
340 | &rx_pipe->native, &tx_pipe->native, | |
341 | false); | |
caf989c3 BA |
342 | if (IS_ERR(glink)) { |
343 | ret = PTR_ERR(glink); | |
f424d1cb | 344 | goto err_free_mbox; |
caf989c3 BA |
345 | } |
346 | ||
ab9fdd41 BA |
347 | smem->glink = glink; |
348 | ||
f424d1cb BA |
349 | enable_irq(smem->irq); |
350 | ||
ab9fdd41 BA |
351 | return smem; |
352 | ||
f424d1cb BA |
353 | err_free_mbox: |
354 | mbox_free_channel(smem->mbox_chan); | |
caf989c3 BA |
355 | |
356 | err_put_dev: | |
a9011726 | 357 | device_unregister(dev); |
caf989c3 BA |
358 | |
359 | return ERR_PTR(ret); | |
360 | } | |
361 | EXPORT_SYMBOL_GPL(qcom_glink_smem_register); | |
362 | ||
ab9fdd41 | 363 | void qcom_glink_smem_unregister(struct qcom_glink_smem *smem) |
caf989c3 | 364 | { |
ab9fdd41 BA |
365 | struct qcom_glink *glink = smem->glink; |
366 | ||
f424d1cb BA |
367 | disable_irq(smem->irq); |
368 | ||
caf989c3 | 369 | qcom_glink_native_remove(glink); |
f424d1cb BA |
370 | |
371 | mbox_free_channel(smem->mbox_chan); | |
372 | device_unregister(&smem->dev); | |
caf989c3 BA |
373 | } |
374 | EXPORT_SYMBOL_GPL(qcom_glink_smem_unregister); | |
375 | ||
376 | MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@linaro.org>"); | |
377 | MODULE_DESCRIPTION("Qualcomm GLINK SMEM driver"); | |
378 | MODULE_LICENSE("GPL v2"); |