[linux-2.6-block.git] / drivers / rpmsg / qcom_glink_smem.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2016, Linaro Ltd
 */

#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <linux/slab.h>
#include <linux/rpmsg.h>
#include <linux/idr.h>
#include <linux/circ_buf.h>
#include <linux/soc/qcom/smem.h>
#include <linux/sizes.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/workqueue.h>
#include <linux/list.h>

#include <linux/rpmsg/qcom_glink.h>

#include "qcom_glink_native.h"

#define FIFO_FULL_RESERVE 8
#define FIFO_ALIGNMENT 8
#define TX_BLOCKED_CMD_RESERVE 8 /* size of struct read_notif_request */

#define SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR	478
#define SMEM_GLINK_NATIVE_XPRT_FIFO_0		479
#define SMEM_GLINK_NATIVE_XPRT_FIFO_1		480

struct qcom_glink_smem {
	struct device dev;

	struct qcom_glink *glink;

	u32 remote_pid;
};

struct glink_smem_pipe {
	struct qcom_glink_pipe native;

	__le32 *tail;
	__le32 *head;

	void *fifo;

	struct qcom_glink_smem *smem;
};

#define to_smem_pipe(p) container_of(p, struct glink_smem_pipe, native)

static size_t glink_smem_rx_avail(struct qcom_glink_pipe *np)
{
	struct glink_smem_pipe *pipe = to_smem_pipe(np);
	struct qcom_glink_smem *smem = pipe->smem;
	size_t len;
	void *fifo;
	u32 head;
	u32 tail;

	if (!pipe->fifo) {
		fifo = qcom_smem_get(smem->remote_pid,
				     SMEM_GLINK_NATIVE_XPRT_FIFO_1, &len);
		if (IS_ERR(fifo)) {
			pr_err("failed to acquire RX fifo handle: %ld\n",
			       PTR_ERR(fifo));
			return 0;
		}

		pipe->fifo = fifo;
		pipe->native.length = len;
	}

	head = le32_to_cpu(*pipe->head);
	tail = le32_to_cpu(*pipe->tail);

	if (head < tail)
		return pipe->native.length - tail + head;
	else
		return head - tail;
}

static void glink_smem_rx_peak(struct qcom_glink_pipe *np,
			       void *data, unsigned int offset, size_t count)
{
	struct glink_smem_pipe *pipe = to_smem_pipe(np);
	size_t len;
	u32 tail;

	tail = le32_to_cpu(*pipe->tail);
	tail += offset;
	if (tail >= pipe->native.length)
		tail -= pipe->native.length;

	len = min_t(size_t, count, pipe->native.length - tail);
	if (len)
		memcpy_fromio(data, pipe->fifo + tail, len);

	if (len != count)
		memcpy_fromio(data + len, pipe->fifo, (count - len));
}

static void glink_smem_rx_advance(struct qcom_glink_pipe *np,
				  size_t count)
{
	struct glink_smem_pipe *pipe = to_smem_pipe(np);
	u32 tail;

	tail = le32_to_cpu(*pipe->tail);

	tail += count;
	if (tail >= pipe->native.length)
		tail -= pipe->native.length;

	*pipe->tail = cpu_to_le32(tail);
}

static size_t glink_smem_tx_avail(struct qcom_glink_pipe *np)
{
	struct glink_smem_pipe *pipe = to_smem_pipe(np);
	u32 head;
	u32 tail;
	u32 avail;

	head = le32_to_cpu(*pipe->head);
	tail = le32_to_cpu(*pipe->tail);

	if (tail <= head)
		avail = pipe->native.length - head + tail;
	else
		avail = tail - head;

	if (avail < (FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE))
		avail = 0;
	else
		avail -= FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE;

	return avail;
}

static unsigned int glink_smem_tx_write_one(struct glink_smem_pipe *pipe,
					    unsigned int head,
					    const void *data, size_t count)
{
	size_t len;

	len = min_t(size_t, count, pipe->native.length - head);
	if (len)
		memcpy(pipe->fifo + head, data, len);

	if (len != count)
		memcpy(pipe->fifo, data + len, count - len);

	head += count;
	if (head >= pipe->native.length)
		head -= pipe->native.length;

	return head;
}

static void glink_smem_tx_write(struct qcom_glink_pipe *glink_pipe,
				const void *hdr, size_t hlen,
				const void *data, size_t dlen)
{
	struct glink_smem_pipe *pipe = to_smem_pipe(glink_pipe);
	unsigned int head;

	head = le32_to_cpu(*pipe->head);

	head = glink_smem_tx_write_one(pipe, head, hdr, hlen);
	head = glink_smem_tx_write_one(pipe, head, data, dlen);

	/* Ensure head is always aligned to 8 bytes */
	head = ALIGN(head, 8);
	if (head >= pipe->native.length)
		head -= pipe->native.length;

	/* Ensure ordering of fifo and head update */
	wmb();

	*pipe->head = cpu_to_le32(head);
}

static void qcom_glink_smem_release(struct device *dev)
{
	struct qcom_glink_smem *smem = container_of(dev, struct qcom_glink_smem, dev);

	kfree(smem);
}

struct qcom_glink_smem *qcom_glink_smem_register(struct device *parent,
						 struct device_node *node)
{
	struct glink_smem_pipe *rx_pipe;
	struct glink_smem_pipe *tx_pipe;
	struct qcom_glink_smem *smem;
	struct qcom_glink *glink;
	struct device *dev;
	u32 remote_pid;
	__le32 *descs;
	size_t size;
	int ret;

	smem = kzalloc(sizeof(*smem), GFP_KERNEL);
	if (!smem)
		return ERR_PTR(-ENOMEM);

	dev = &smem->dev;

	dev->parent = parent;
	dev->of_node = node;
	dev->release = qcom_glink_smem_release;
	dev_set_name(dev, "%s:%pOFn", dev_name(parent->parent), node);
	ret = device_register(dev);
	if (ret) {
		pr_err("failed to register glink edge\n");
		put_device(dev);
		return ERR_PTR(ret);
	}

	ret = of_property_read_u32(dev->of_node, "qcom,remote-pid",
				   &remote_pid);
	if (ret) {
		dev_err(dev, "failed to parse qcom,remote-pid\n");
		goto err_put_dev;
	}

	smem->remote_pid = remote_pid;

	rx_pipe = devm_kzalloc(dev, sizeof(*rx_pipe), GFP_KERNEL);
	tx_pipe = devm_kzalloc(dev, sizeof(*tx_pipe), GFP_KERNEL);
	if (!rx_pipe || !tx_pipe) {
		ret = -ENOMEM;
		goto err_put_dev;
	}

	ret = qcom_smem_alloc(remote_pid,
			      SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, 32);
	if (ret && ret != -EEXIST) {
		dev_err(dev, "failed to allocate glink descriptors\n");
		goto err_put_dev;
	}

	descs = qcom_smem_get(remote_pid,
			      SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, &size);
	if (IS_ERR(descs)) {
		dev_err(dev, "failed to acquire xprt descriptor\n");
		ret = PTR_ERR(descs);
		goto err_put_dev;
	}

	if (size != 32) {
		dev_err(dev, "glink descriptor of invalid size\n");
		ret = -EINVAL;
		goto err_put_dev;
	}

	tx_pipe->tail = &descs[0];
	tx_pipe->head = &descs[1];
	rx_pipe->tail = &descs[2];
	rx_pipe->head = &descs[3];

	ret = qcom_smem_alloc(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
			      SZ_16K);
	if (ret && ret != -EEXIST) {
		dev_err(dev, "failed to allocate TX fifo\n");
		goto err_put_dev;
	}

	tx_pipe->fifo = qcom_smem_get(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
				      &tx_pipe->native.length);
	if (IS_ERR(tx_pipe->fifo)) {
		dev_err(dev, "failed to acquire TX fifo\n");
		ret = PTR_ERR(tx_pipe->fifo);
		goto err_put_dev;
	}

	rx_pipe->smem = smem;
	rx_pipe->native.avail = glink_smem_rx_avail;
	rx_pipe->native.peak = glink_smem_rx_peak;
	rx_pipe->native.advance = glink_smem_rx_advance;

	tx_pipe->smem = smem;
	tx_pipe->native.avail = glink_smem_tx_avail;
	tx_pipe->native.write = glink_smem_tx_write;

	*rx_pipe->tail = 0;
	*tx_pipe->head = 0;

	glink = qcom_glink_native_probe(dev,
					GLINK_FEATURE_INTENT_REUSE,
					&rx_pipe->native, &tx_pipe->native,
					false);
	if (IS_ERR(glink)) {
		ret = PTR_ERR(glink);
		goto err_put_dev;
	}

	smem->glink = glink;

	return smem;


err_put_dev:
	device_unregister(dev);

	return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(qcom_glink_smem_register);

void qcom_glink_smem_unregister(struct qcom_glink_smem *smem)
{
	struct qcom_glink *glink = smem->glink;

	qcom_glink_native_remove(glink);
	qcom_glink_native_unregister(glink);
}
EXPORT_SYMBOL_GPL(qcom_glink_smem_unregister);

MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@linaro.org>");
MODULE_DESCRIPTION("Qualcomm GLINK SMEM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
84369fbe	1	// SPDX-License-Identifier: GPL-2.0
caf989c3 BA	2	/*
caf989c3 BA	3	* Copyright (c) 2016, Linaro Ltd
caf989c3 BA	4	*/
	5
	6	#include <linux/io.h>
	7	#include <linux/module.h>
	8	#include <linux/of.h>
	9	#include <linux/of_address.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/mfd/syscon.h>
	13	#include <linux/slab.h>
	14	#include <linux/rpmsg.h>
	15	#include <linux/idr.h>
	16	#include <linux/circ_buf.h>
	17	#include <linux/soc/qcom/smem.h>
	18	#include <linux/sizes.h>
	19	#include <linux/delay.h>
	20	#include <linux/regmap.h>
	21	#include <linux/workqueue.h>
	22	#include <linux/list.h>
	23
caf989c3 BA	24	#include <linux/rpmsg/qcom_glink.h>
	25
	26	#include "qcom_glink_native.h"
	27
	28	#define FIFO_FULL_RESERVE 8
	29	#define FIFO_ALIGNMENT 8
	30	#define TX_BLOCKED_CMD_RESERVE 8 /* size of struct read_notif_request */
	31
	32	#define SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR 478
	33	#define SMEM_GLINK_NATIVE_XPRT_FIFO_0 479
	34	#define SMEM_GLINK_NATIVE_XPRT_FIFO_1 480
	35
ab9fdd41 BA	36	struct qcom_glink_smem {
	37	struct device dev;
	38
	39	struct qcom_glink *glink;
	40
	41	u32 remote_pid;
	42	};
	43
caf989c3 BA	44	struct glink_smem_pipe {
	45	struct qcom_glink_pipe native;
	46
	47	__le32 *tail;
	48	__le32 *head;
	49
	50	void *fifo;
	51
ab9fdd41	52	struct qcom_glink_smem *smem;
caf989c3 BA	53	};
	54
	55	#define to_smem_pipe(p) container_of(p, struct glink_smem_pipe, native)
	56
	57	static size_t glink_smem_rx_avail(struct qcom_glink_pipe *np)
	58	{
	59	struct glink_smem_pipe *pipe = to_smem_pipe(np);
ab9fdd41	60	struct qcom_glink_smem *smem = pipe->smem;
caf989c3 BA	61	size_t len;
	62	void *fifo;
	63	u32 head;
	64	u32 tail;
	65
	66	if (!pipe->fifo) {
ab9fdd41	67	fifo = qcom_smem_get(smem->remote_pid,
caf989c3 BA	68	SMEM_GLINK_NATIVE_XPRT_FIFO_1, &len);
	69	if (IS_ERR(fifo)) {
	70	pr_err("failed to acquire RX fifo handle: %ld\n",
	71	PTR_ERR(fifo));
	72	return 0;
	73	}
	74
	75	pipe->fifo = fifo;
	76	pipe->native.length = len;
	77	}
	78
	79	head = le32_to_cpu(*pipe->head);
	80	tail = le32_to_cpu(*pipe->tail);
	81
	82	if (head < tail)
	83	return pipe->native.length - tail + head;
	84	else
	85	return head - tail;
	86	}
	87
	88	static void glink_smem_rx_peak(struct qcom_glink_pipe *np,
b88eee97	89	void *data, unsigned int offset, size_t count)
caf989c3 BA	90	{
	91	struct glink_smem_pipe *pipe = to_smem_pipe(np);
	92	size_t len;
	93	u32 tail;
	94
	95	tail = le32_to_cpu(*pipe->tail);
b88eee97 BA	96	tail += offset;
	97	if (tail >= pipe->native.length)
	98	tail -= pipe->native.length;
caf989c3 BA	99
caf989c3 BA	100	len = min_t(size_t, count, pipe->native.length - tail);
928002a5 AKN	101	if (len)
928002a5 AKN	102	memcpy_fromio(data, pipe->fifo + tail, len);
caf989c3	103
928002a5 AKN	104	if (len != count)
928002a5 AKN	105	memcpy_fromio(data + len, pipe->fifo, (count - len));
caf989c3 BA	106	}
	107
	108	static void glink_smem_rx_advance(struct qcom_glink_pipe *np,
	109	size_t count)
	110	{
	111	struct glink_smem_pipe *pipe = to_smem_pipe(np);
	112	u32 tail;
	113
	114	tail = le32_to_cpu(*pipe->tail);
	115
	116	tail += count;
4623e8bf	117	if (tail >= pipe->native.length)
caf989c3 BA	118	tail -= pipe->native.length;
	119
	120	*pipe->tail = cpu_to_le32(tail);
	121	}
	122
	123	static size_t glink_smem_tx_avail(struct qcom_glink_pipe *np)
	124	{
	125	struct glink_smem_pipe *pipe = to_smem_pipe(np);
	126	u32 head;
	127	u32 tail;
	128	u32 avail;
	129
	130	head = le32_to_cpu(*pipe->head);
	131	tail = le32_to_cpu(*pipe->tail);
	132
	133	if (tail <= head)
	134	avail = pipe->native.length - head + tail;
	135	else
	136	avail = tail - head;
	137
	138	if (avail < (FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE))
	139	avail = 0;
	140	else
	141	avail -= FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE;
	142
	143	return avail;
	144	}
	145
	146	static unsigned int glink_smem_tx_write_one(struct glink_smem_pipe *pipe,
	147	unsigned int head,
	148	const void *data, size_t count)
	149	{
	150	size_t len;
	151
	152	len = min_t(size_t, count, pipe->native.length - head);
	153	if (len)
	154	memcpy(pipe->fifo + head, data, len);
	155
	156	if (len != count)
	157	memcpy(pipe->fifo, data + len, count - len);
	158
	159	head += count;
	160	if (head >= pipe->native.length)
	161	head -= pipe->native.length;
	162
	163	return head;
	164	}
	165
	166	static void glink_smem_tx_write(struct qcom_glink_pipe *glink_pipe,
	167	const void *hdr, size_t hlen,
	168	const void *data, size_t dlen)
	169	{
	170	struct glink_smem_pipe *pipe = to_smem_pipe(glink_pipe);
	171	unsigned int head;
	172
	173	head = le32_to_cpu(*pipe->head);
	174
	175	head = glink_smem_tx_write_one(pipe, head, hdr, hlen);
	176	head = glink_smem_tx_write_one(pipe, head, data, dlen);
	177
	178	/* Ensure head is always aligned to 8 bytes */
	179	head = ALIGN(head, 8);
	180	if (head >= pipe->native.length)
	181	head -= pipe->native.length;
182
9d324973 BA	183	/* Ensure ordering of fifo and head update */
	184	wmb();
	185
caf989c3 BA	186	*pipe->head = cpu_to_le32(head);
	187	}
	188
	189	static void qcom_glink_smem_release(struct device *dev)
	190	{
ab9fdd41 BA	191	struct qcom_glink_smem *smem = container_of(dev, struct qcom_glink_smem, dev);
	192
	193	kfree(smem);
caf989c3 BA	194	}
caf989c3 BA	195
ab9fdd41 BA	196	struct qcom_glink_smem qcom_glink_smem_register(struct device parent,
ab9fdd41 BA	197	struct device_node *node)
caf989c3 BA	198	{
	199	struct glink_smem_pipe *rx_pipe;
	200	struct glink_smem_pipe *tx_pipe;
ab9fdd41	201	struct qcom_glink_smem *smem;
caf989c3 BA	202	struct qcom_glink *glink;
	203	struct device *dev;
	204	u32 remote_pid;
	205	__le32 *descs;
	206	size_t size;
	207	int ret;
	208
ab9fdd41 BA	209	smem = kzalloc(sizeof(*smem), GFP_KERNEL);
ab9fdd41 BA	210	if (!smem)
caf989c3 BA	211	return ERR_PTR(-ENOMEM);
caf989c3 BA	212
ab9fdd41 BA	213	dev = &smem->dev;
ab9fdd41 BA	214
caf989c3 BA	215	dev->parent = parent;
	216	dev->of_node = node;
	217	dev->release = qcom_glink_smem_release;
9fe69a72	218	dev_set_name(dev, "%s:%pOFn", dev_name(parent->parent), node);
caf989c3 BA	219	ret = device_register(dev);
	220	if (ret) {
	221	pr_err("failed to register glink edge\n");
a9011726	222	put_device(dev);
caf989c3 BA	223	return ERR_PTR(ret);
	224	}
	225
	226	ret = of_property_read_u32(dev->of_node, "qcom,remote-pid",
	227	&remote_pid);
	228	if (ret) {
	229	dev_err(dev, "failed to parse qcom,remote-pid\n");
	230	goto err_put_dev;
	231	}
	232
ab9fdd41 BA	233	smem->remote_pid = remote_pid;
ab9fdd41 BA	234
caf989c3 BA	235	rx_pipe = devm_kzalloc(dev, sizeof(*rx_pipe), GFP_KERNEL);
	236	tx_pipe = devm_kzalloc(dev, sizeof(*tx_pipe), GFP_KERNEL);
	237	if (!rx_pipe \|\| !tx_pipe) {
	238	ret = -ENOMEM;
	239	goto err_put_dev;
	240	}
	241
	242	ret = qcom_smem_alloc(remote_pid,
	243	SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, 32);
	244	if (ret && ret != -EEXIST) {
	245	dev_err(dev, "failed to allocate glink descriptors\n");
	246	goto err_put_dev;
	247	}
	248
	249	descs = qcom_smem_get(remote_pid,
	250	SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, &size);
	251	if (IS_ERR(descs)) {
	252	dev_err(dev, "failed to acquire xprt descriptor\n");
	253	ret = PTR_ERR(descs);
	254	goto err_put_dev;
	255	}
	256
	257	if (size != 32) {
	258	dev_err(dev, "glink descriptor of invalid size\n");
	259	ret = -EINVAL;
	260	goto err_put_dev;
	261	}
	262
	263	tx_pipe->tail = &descs[0];
	264	tx_pipe->head = &descs[1];
	265	rx_pipe->tail = &descs[2];
	266	rx_pipe->head = &descs[3];
	267
	268	ret = qcom_smem_alloc(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
	269	SZ_16K);
	270	if (ret && ret != -EEXIST) {
	271	dev_err(dev, "failed to allocate TX fifo\n");
	272	goto err_put_dev;
	273	}
	274
	275	tx_pipe->fifo = qcom_smem_get(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
	276	&tx_pipe->native.length);
	277	if (IS_ERR(tx_pipe->fifo)) {
	278	dev_err(dev, "failed to acquire TX fifo\n");
	279	ret = PTR_ERR(tx_pipe->fifo);
	280	goto err_put_dev;
	281	}
	282
ab9fdd41	283	rx_pipe->smem = smem;
caf989c3 BA	284	rx_pipe->native.avail = glink_smem_rx_avail;
	285	rx_pipe->native.peak = glink_smem_rx_peak;
	286	rx_pipe->native.advance = glink_smem_rx_advance;
caf989c3	287
ab9fdd41	288	tx_pipe->smem = smem;
caf989c3 BA	289	tx_pipe->native.avail = glink_smem_tx_avail;
caf989c3 BA	290	tx_pipe->native.write = glink_smem_tx_write;
caf989c3 BA	291
	292	*rx_pipe->tail = 0;
	293	*tx_pipe->head = 0;
	294
	295	glink = qcom_glink_native_probe(dev,
933b45da S	296	GLINK_FEATURE_INTENT_REUSE,
	297	&rx_pipe->native, &tx_pipe->native,
	298	false);
caf989c3 BA	299	if (IS_ERR(glink)) {
	300	ret = PTR_ERR(glink);
	301	goto err_put_dev;
	302	}
	303
ab9fdd41 BA	304	smem->glink = glink;
	305
	306	return smem;
	307
caf989c3 BA	308
caf989c3 BA	309	err_put_dev:
a9011726	310	device_unregister(dev);
caf989c3 BA	311
	312	return ERR_PTR(ret);
	313	}
	314	EXPORT_SYMBOL_GPL(qcom_glink_smem_register);
	315
ab9fdd41	316	void qcom_glink_smem_unregister(struct qcom_glink_smem *smem)
caf989c3	317	{
ab9fdd41 BA	318	struct qcom_glink *glink = smem->glink;
ab9fdd41 BA	319
caf989c3 BA	320	qcom_glink_native_remove(glink);
	321	qcom_glink_native_unregister(glink);
	322	}
	323	EXPORT_SYMBOL_GPL(qcom_glink_smem_unregister);
	324
	325	MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@linaro.org>");
	326	MODULE_DESCRIPTION("Qualcomm GLINK SMEM driver");
	327	MODULE_LICENSE("GPL v2");