[linux-block.git] / drivers / reset / reset-zynqmp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018 Xilinx, Inc.
 *
 */

#include <linux/err.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/firmware/xlnx-zynqmp.h>
#include <linux/of_device.h>

#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
#define VERSAL_NR_RESETS	95

struct zynqmp_reset_soc_data {
	u32 reset_id;
	u32 num_resets;
};

struct zynqmp_reset_data {
	struct reset_controller_dev rcdev;
	const struct zynqmp_reset_soc_data *data;
};

static inline struct zynqmp_reset_data *
to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
{
	return container_of(rcdev, struct zynqmp_reset_data, rcdev);
}

static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
			       unsigned long id)
{
	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);

	return zynqmp_pm_reset_assert(priv->data->reset_id + id,
				      PM_RESET_ACTION_ASSERT);
}

static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
				 unsigned long id)
{
	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);

	return zynqmp_pm_reset_assert(priv->data->reset_id + id,
				      PM_RESET_ACTION_RELEASE);
}

static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
			       unsigned long id)
{
	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
	int val, err;

	err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val);
	if (err)
		return err;

	return val;
}

static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
			      unsigned long id)
{
	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);

	return zynqmp_pm_reset_assert(priv->data->reset_id + id,
				      PM_RESET_ACTION_PULSE);
}

static int zynqmp_reset_of_xlate(struct reset_controller_dev *rcdev,
				 const struct of_phandle_args *reset_spec)
{
	return reset_spec->args[0];
}

static const struct zynqmp_reset_soc_data zynqmp_reset_data = {
	.reset_id = ZYNQMP_RESET_ID,
	.num_resets = ZYNQMP_NR_RESETS,
};

static const struct zynqmp_reset_soc_data versal_reset_data = {
        .reset_id = 0,
        .num_resets = VERSAL_NR_RESETS,
};

static const struct reset_control_ops zynqmp_reset_ops = {
	.reset = zynqmp_reset_reset,
	.assert = zynqmp_reset_assert,
	.deassert = zynqmp_reset_deassert,
	.status = zynqmp_reset_status,
};

static int zynqmp_reset_probe(struct platform_device *pdev)
{
	struct zynqmp_reset_data *priv;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->data = of_device_get_match_data(&pdev->dev);
	if (!priv->data)
		return -EINVAL;

	platform_set_drvdata(pdev, priv);

	priv->rcdev.ops = &zynqmp_reset_ops;
	priv->rcdev.owner = THIS_MODULE;
	priv->rcdev.of_node = pdev->dev.of_node;
	priv->rcdev.nr_resets = priv->data->num_resets;
	priv->rcdev.of_reset_n_cells = 1;
	priv->rcdev.of_xlate = zynqmp_reset_of_xlate;

	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
}

static const struct of_device_id zynqmp_reset_dt_ids[] = {
	{ .compatible = "xlnx,zynqmp-reset", .data = &zynqmp_reset_data, },
	{ .compatible = "xlnx,versal-reset", .data = &versal_reset_data, },
	{ /* sentinel */ },
};

static struct platform_driver zynqmp_reset_driver = {
	.probe	= zynqmp_reset_probe,
	.driver = {
		.name		= KBUILD_MODNAME,
		.of_match_table	= zynqmp_reset_dt_ids,
	},
};

static int __init zynqmp_reset_init(void)
{
	return platform_driver_register(&zynqmp_reset_driver);
}

arch_initcall(zynqmp_reset_init);
Commit	Line	Data
62f0d7dc NM	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018 Xilinx, Inc.
	4	*
	5	*/
	6
	7	#include <linux/err.h>
	8	#include <linux/of.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/reset-controller.h>
	11	#include <linux/firmware/xlnx-zynqmp.h>
552f388b	12	#include <linux/of_device.h>
62f0d7dc NM	13
	14	#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
	15	#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
552f388b SKP	16	#define VERSAL_NR_RESETS 95
	17
	18	struct zynqmp_reset_soc_data {
	19	u32 reset_id;
	20	u32 num_resets;
	21	};
62f0d7dc NM	22
	23	struct zynqmp_reset_data {
	24	struct reset_controller_dev rcdev;
552f388b	25	const struct zynqmp_reset_soc_data *data;
62f0d7dc NM	26	};
	27
	28	static inline struct zynqmp_reset_data *
	29	to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
	30	{
	31	return container_of(rcdev, struct zynqmp_reset_data, rcdev);
	32	}
	33
	34	static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
	35	unsigned long id)
	36	{
552f388b SKP	37	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
	38
	39	return zynqmp_pm_reset_assert(priv->data->reset_id + id,
cf23ec35	40	PM_RESET_ACTION_ASSERT);
62f0d7dc NM	41	}
	42
	43	static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
	44	unsigned long id)
	45	{
552f388b SKP	46	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
	47
	48	return zynqmp_pm_reset_assert(priv->data->reset_id + id,
cf23ec35	49	PM_RESET_ACTION_RELEASE);
62f0d7dc NM	50	}
	51
	52	static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
	53	unsigned long id)
	54	{
552f388b	55	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
62f0d7dc NM	56	int val, err;
62f0d7dc NM	57
552f388b	58	err = zynqmp_pm_reset_get_status(priv->data->reset_id + id, &val);
62f0d7dc NM	59	if (err)
	60	return err;
	61
	62	return val;
	63	}
	64
	65	static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
	66	unsigned long id)
	67	{
552f388b SKP	68	struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
	69
	70	return zynqmp_pm_reset_assert(priv->data->reset_id + id,
cf23ec35	71	PM_RESET_ACTION_PULSE);
62f0d7dc NM	72	}
62f0d7dc NM	73
552f388b SKP	74	static int zynqmp_reset_of_xlate(struct reset_controller_dev *rcdev,
	75	const struct of_phandle_args *reset_spec)
	76	{
	77	return reset_spec->args[0];
	78	}
	79
	80	static const struct zynqmp_reset_soc_data zynqmp_reset_data = {
	81	.reset_id = ZYNQMP_RESET_ID,
	82	.num_resets = ZYNQMP_NR_RESETS,
	83	};
	84
	85	static const struct zynqmp_reset_soc_data versal_reset_data = {
	86	.reset_id = 0,
	87	.num_resets = VERSAL_NR_RESETS,
	88	};
	89
c1b065b4	90	static const struct reset_control_ops zynqmp_reset_ops = {
62f0d7dc NM	91	.reset = zynqmp_reset_reset,
	92	.assert = zynqmp_reset_assert,
	93	.deassert = zynqmp_reset_deassert,
	94	.status = zynqmp_reset_status,
	95	};
	96
	97	static int zynqmp_reset_probe(struct platform_device *pdev)
	98	{
	99	struct zynqmp_reset_data *priv;
	100
	101	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	102	if (!priv)
	103	return -ENOMEM;
	104
552f388b SKP	105	priv->data = of_device_get_match_data(&pdev->dev);
	106	if (!priv->data)
	107	return -EINVAL;
	108
3d031378	109	platform_set_drvdata(pdev, priv);
62f0d7dc NM	110
	111	priv->rcdev.ops = &zynqmp_reset_ops;
	112	priv->rcdev.owner = THIS_MODULE;
	113	priv->rcdev.of_node = pdev->dev.of_node;
552f388b SKP	114	priv->rcdev.nr_resets = priv->data->num_resets;
	115	priv->rcdev.of_reset_n_cells = 1;
	116	priv->rcdev.of_xlate = zynqmp_reset_of_xlate;
62f0d7dc NM	117
	118	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
	119	}
	120
	121	static const struct of_device_id zynqmp_reset_dt_ids[] = {
552f388b SKP	122	{ .compatible = "xlnx,zynqmp-reset", .data = &zynqmp_reset_data, },
552f388b SKP	123	{ .compatible = "xlnx,versal-reset", .data = &versal_reset_data, },
62f0d7dc NM	124	{ /* sentinel */ },
	125	};
	126
	127	static struct platform_driver zynqmp_reset_driver = {
	128	.probe = zynqmp_reset_probe,
	129	.driver = {
	130	.name = KBUILD_MODNAME,
	131	.of_match_table = zynqmp_reset_dt_ids,
	132	},
	133	};
	134
	135	static int __init zynqmp_reset_init(void)
	136	{
	137	return platform_driver_register(&zynqmp_reset_driver);
	138	}
	139
	140	arch_initcall(zynqmp_reset_init);