[linux-2.6-block.git] / drivers / reset / reset-uniphier.c

/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>

struct uniphier_reset_data {
	unsigned int id;
	unsigned int reg;
	unsigned int bit;
	unsigned int flags;
#define UNIPHIER_RESET_ACTIVE_LOW		BIT(0)
};

#define UNIPHIER_RESET_ID_END		(unsigned int)(-1)

#define UNIPHIER_RESET_END				\
	{ .id = UNIPHIER_RESET_ID_END }

#define UNIPHIER_RESET(_id, _reg, _bit)			\
	{						\
		.id = (_id),				\
		.reg = (_reg),				\
		.bit = (_bit),				\
	}

#define UNIPHIER_RESETX(_id, _reg, _bit)		\
	{						\
		.id = (_id),				\
		.reg = (_reg),				\
		.bit = (_bit),				\
		.flags = UNIPHIER_RESET_ACTIVE_LOW,	\
	}

/* System reset data */
static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC (Ether, HSC, MIO) */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC (HSC, MIO, RLE) */
	UNIPHIER_RESETX(12, 0x2000, 6),		/* GIO (Ether, SATA, USB3) */
	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC (HSC) */
	UNIPHIER_RESETX(12, 0x2000, 6),		/* GIO (PCIe, USB3) */
	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC (HSC, RLE) */
	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
	UNIPHIER_RESETX(16, 0x2014, 4),		/* USB30-PHY0 */
	UNIPHIER_RESETX(17, 0x2014, 0),		/* USB30-PHY1 */
	UNIPHIER_RESETX(18, 0x2014, 2),		/* USB30-PHY2 */
	UNIPHIER_RESETX(20, 0x2014, 5),		/* USB31-PHY0 */
	UNIPHIER_RESETX(21, 0x2014, 1),		/* USB31-PHY1 */
	UNIPHIER_RESETX(28, 0x2014, 12),	/* SATA */
	UNIPHIER_RESET(29, 0x2014, 8),		/* SATA-PHY (active high) */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
	UNIPHIER_RESETX(2, 0x200c, 0),		/* NAND */
	UNIPHIER_RESETX(4, 0x200c, 2),		/* eMMC */
	UNIPHIER_RESETX(8, 0x200c, 8),		/* STDMAC (HSC, MIO) */
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
	UNIPHIER_RESETX(2, 0x200c, 0),		/* NAND */
	UNIPHIER_RESETX(4, 0x200c, 2),		/* eMMC */
	UNIPHIER_RESETX(8, 0x200c, 8),		/* STDMAC (HSC) */
	UNIPHIER_RESETX(12, 0x200c, 5),		/* GIO (PCIe, USB3) */
	UNIPHIER_RESETX(16, 0x200c, 12),	/* USB30-PHY0 */
	UNIPHIER_RESETX(17, 0x200c, 13),	/* USB30-PHY1 */
	UNIPHIER_RESETX(18, 0x200c, 14),	/* USB30-PHY2 */
	UNIPHIER_RESETX(19, 0x200c, 15),	/* USB30-PHY3 */
	UNIPHIER_RESET_END,
};

/* Media I/O reset data */
#define UNIPHIER_MIO_RESET_SD(id, ch)			\
	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)

#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch)		\
	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)

#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch)	\
	UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)

#define UNIPHIER_MIO_RESET_USB2(id, ch)			\
	UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)

#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch)		\
	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)

#define UNIPHIER_MIO_RESET_DMAC(id)			\
	UNIPHIER_RESETX((id), 0x110, 17)

static const struct uniphier_reset_data uniphier_ld4_mio_reset_data[] = {
	UNIPHIER_MIO_RESET_SD(0, 0),
	UNIPHIER_MIO_RESET_SD(1, 1),
	UNIPHIER_MIO_RESET_SD(2, 2),
	UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
	UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
	UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	UNIPHIER_MIO_RESET_DMAC(7),
	UNIPHIER_MIO_RESET_USB2(8, 0),
	UNIPHIER_MIO_RESET_USB2(9, 1),
	UNIPHIER_MIO_RESET_USB2(10, 2),
	UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
	UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
	UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
	UNIPHIER_MIO_RESET_SD(0, 0),
	UNIPHIER_MIO_RESET_SD(1, 1),
	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	UNIPHIER_RESET_END,
};

/* Peripheral reset data */
#define UNIPHIER_PERI_RESET_UART(id, ch)		\
	UNIPHIER_RESETX((id), 0x114, 19 + (ch))

#define UNIPHIER_PERI_RESET_I2C(id, ch)			\
	UNIPHIER_RESETX((id), 0x114, 5 + (ch))

#define UNIPHIER_PERI_RESET_FI2C(id, ch)		\
	UNIPHIER_RESETX((id), 0x114, 24 + (ch))

static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
	UNIPHIER_PERI_RESET_UART(0, 0),
	UNIPHIER_PERI_RESET_UART(1, 1),
	UNIPHIER_PERI_RESET_UART(2, 2),
	UNIPHIER_PERI_RESET_UART(3, 3),
	UNIPHIER_PERI_RESET_I2C(4, 0),
	UNIPHIER_PERI_RESET_I2C(5, 1),
	UNIPHIER_PERI_RESET_I2C(6, 2),
	UNIPHIER_PERI_RESET_I2C(7, 3),
	UNIPHIER_PERI_RESET_I2C(8, 4),
	UNIPHIER_RESET_END,
};

static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
	UNIPHIER_PERI_RESET_UART(0, 0),
	UNIPHIER_PERI_RESET_UART(1, 1),
	UNIPHIER_PERI_RESET_UART(2, 2),
	UNIPHIER_PERI_RESET_UART(3, 3),
	UNIPHIER_PERI_RESET_FI2C(4, 0),
	UNIPHIER_PERI_RESET_FI2C(5, 1),
	UNIPHIER_PERI_RESET_FI2C(6, 2),
	UNIPHIER_PERI_RESET_FI2C(7, 3),
	UNIPHIER_PERI_RESET_FI2C(8, 4),
	UNIPHIER_PERI_RESET_FI2C(9, 5),
	UNIPHIER_PERI_RESET_FI2C(10, 6),
	UNIPHIER_RESET_END,
};

/* core implementaton */
struct uniphier_reset_priv {
	struct reset_controller_dev rcdev;
	struct device *dev;
	struct regmap *regmap;
	const struct uniphier_reset_data *data;
};

#define to_uniphier_reset_priv(_rcdev) \
			container_of(_rcdev, struct uniphier_reset_priv, rcdev)

static int uniphier_reset_update(struct reset_controller_dev *rcdev,
				 unsigned long id, int assert)
{
	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
	const struct uniphier_reset_data *p;

	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
		unsigned int mask, val;

		if (p->id != id)
			continue;

		mask = BIT(p->bit);

		if (assert)
			val = mask;
		else
			val = ~mask;

		if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
			val = ~val;

		return regmap_write_bits(priv->regmap, p->reg, mask, val);
	}

	dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
	return -EINVAL;
}

static int uniphier_reset_assert(struct reset_controller_dev *rcdev,
				 unsigned long id)
{
	return uniphier_reset_update(rcdev, id, 1);
}

static int uniphier_reset_deassert(struct reset_controller_dev *rcdev,
				   unsigned long id)
{
	return uniphier_reset_update(rcdev, id, 0);
}

static int uniphier_reset_status(struct reset_controller_dev *rcdev,
				 unsigned long id)
{
	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
	const struct uniphier_reset_data *p;

	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
		unsigned int val;
		int ret, asserted;

		if (p->id != id)
			continue;

		ret = regmap_read(priv->regmap, p->reg, &val);
		if (ret)
			return ret;

		asserted = !!(val & BIT(p->bit));

		if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
			asserted = !asserted;

		return asserted;
	}

	dev_err(priv->dev, "reset_id=%lu was not found\n", id);
	return -EINVAL;
}

static const struct reset_control_ops uniphier_reset_ops = {
	.assert = uniphier_reset_assert,
	.deassert = uniphier_reset_deassert,
	.status = uniphier_reset_status,
};

static int uniphier_reset_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct uniphier_reset_priv *priv;
	const struct uniphier_reset_data *p, *data;
	struct regmap *regmap;
	struct device_node *parent;
	unsigned int nr_resets = 0;

	data = of_device_get_match_data(dev);
	if (WARN_ON(!data))
		return -EINVAL;

	parent = of_get_parent(dev->of_node); /* parent should be syscon node */
	regmap = syscon_node_to_regmap(parent);
	of_node_put(parent);
	if (IS_ERR(regmap)) {
		dev_err(dev, "failed to get regmap (error %ld)\n",
			PTR_ERR(regmap));
		return PTR_ERR(regmap);
	}

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	for (p = data; p->id != UNIPHIER_RESET_ID_END; p++)
		nr_resets = max(nr_resets, p->id + 1);

	priv->rcdev.ops = &uniphier_reset_ops;
	priv->rcdev.owner = dev->driver->owner;
	priv->rcdev.of_node = dev->of_node;
	priv->rcdev.nr_resets = nr_resets;
	priv->dev = dev;
	priv->regmap = regmap;
	priv->data = data;

	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
}

static const struct of_device_id uniphier_reset_match[] = {
	/* System reset */
	{
		.compatible = "socionext,uniphier-ld4-reset",
		.data = uniphier_ld4_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-reset",
		.data = uniphier_pro4_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-reset",
		.data = uniphier_ld4_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-reset",
		.data = uniphier_pro5_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-reset",
		.data = uniphier_pxs2_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-reset",
		.data = uniphier_ld11_sys_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-reset",
		.data = uniphier_ld20_sys_reset_data,
	},
	/* Media I/O reset, SD reset */
	{
		.compatible = "socionext,uniphier-ld4-mio-reset",
		.data = uniphier_ld4_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-mio-reset",
		.data = uniphier_ld4_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-mio-reset",
		.data = uniphier_ld4_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-mio-reset",
		.data = uniphier_ld4_mio_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-sd-reset",
		.data = uniphier_pro5_sd_reset_data,
	},
	/* Peripheral reset */
	{
		.compatible = "socionext,uniphier-ld4-peri-reset",
		.data = uniphier_ld4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro4-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-sld8-peri-reset",
		.data = uniphier_ld4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pro5-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-pxs2-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld11-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{
		.compatible = "socionext,uniphier-ld20-peri-reset",
		.data = uniphier_pro4_peri_reset_data,
	},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_reset_match);

static struct platform_driver uniphier_reset_driver = {
	.probe = uniphier_reset_probe,
	.driver = {
		.name = "uniphier-reset",
		.of_match_table = uniphier_reset_match,
	},
};
module_platform_driver(uniphier_reset_driver);

MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier Reset Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
54e991b5 MY	1	/*
	2	* Copyright (C) 2016 Socionext Inc.
	3	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/mfd/syscon.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
	19	#include <linux/of_device.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/regmap.h>
	22	#include <linux/reset-controller.h>
	23
	24	struct uniphier_reset_data {
	25	unsigned int id;
	26	unsigned int reg;
	27	unsigned int bit;
	28	unsigned int flags;
	29	#define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
	30	};
	31
	32	#define UNIPHIER_RESET_ID_END (unsigned int)(-1)
	33
	34	#define UNIPHIER_RESET_END \
	35	{ .id = UNIPHIER_RESET_ID_END }
	36
	37	#define UNIPHIER_RESET(_id, _reg, _bit) \
	38	{ \
	39	.id = (_id), \
	40	.reg = (_reg), \
	41	.bit = (_bit), \
	42	}
	43
	44	#define UNIPHIER_RESETX(_id, _reg, _bit) \
	45	{ \
	46	.id = (_id), \
	47	.reg = (_reg), \
	48	.bit = (_bit), \
	49	.flags = UNIPHIER_RESET_ACTIVE_LOW, \
	50	}
	51
	52	/* System reset data */
5281036a MY	53	static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
	54	UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
	55	UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
54e991b5 MY	56	UNIPHIER_RESET_END,
	57	};
	58
716adfe3	59	static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
5281036a MY	60	UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
5281036a MY	61	UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
dec173cc MY	62	UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
	63	UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
	64	UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
54e991b5 MY	65	UNIPHIER_RESET_END,
	66	};
	67
716adfe3	68	static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
5281036a MY	69	UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
5281036a MY	70	UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC) */
dec173cc MY	71	UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */
	72	UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
	73	UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
54e991b5 MY	74	UNIPHIER_RESET_END,
	75	};
	76
716adfe3	77	static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
5281036a MY	78	UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
5281036a MY	79	UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, RLE) */
dec173cc MY	80	UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
dec173cc MY	81	UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
54e991b5 MY	82	UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
	83	UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
	84	UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
	85	UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
	86	UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
	87	UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
	88	UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
	89	UNIPHIER_RESET_END,
	90	};
	91
716adfe3	92	static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
dec173cc MY	93	UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
	94	UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
	95	UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC, MIO) */
54e991b5 MY	96	UNIPHIER_RESET_END,
	97	};
	98
716adfe3	99	static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
dec173cc MY	100	UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
	101	UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
	102	UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
	103	UNIPHIER_RESETX(12, 0x200c, 5), /* GIO (PCIe, USB3) */
54e991b5 MY	104	UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
	105	UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
	106	UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
	107	UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
	108	UNIPHIER_RESET_END,
	109	};
	110
	111	/* Media I/O reset data */
	112	#define UNIPHIER_MIO_RESET_SD(id, ch) \
	113	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
	114
	115	#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
	116	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
	117
	118	#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
	119	UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
	120
	121	#define UNIPHIER_MIO_RESET_USB2(id, ch) \
	122	UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
	123
	124	#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
	125	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
	126
	127	#define UNIPHIER_MIO_RESET_DMAC(id) \
	128	UNIPHIER_RESETX((id), 0x110, 17)
	129
5281036a	130	static const struct uniphier_reset_data uniphier_ld4_mio_reset_data[] = {
54e991b5 MY	131	UNIPHIER_MIO_RESET_SD(0, 0),
	132	UNIPHIER_MIO_RESET_SD(1, 1),
	133	UNIPHIER_MIO_RESET_SD(2, 2),
	134	UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
	135	UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
	136	UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
	137	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	138	UNIPHIER_MIO_RESET_DMAC(7),
	139	UNIPHIER_MIO_RESET_USB2(8, 0),
	140	UNIPHIER_MIO_RESET_USB2(9, 1),
	141	UNIPHIER_MIO_RESET_USB2(10, 2),
54e991b5 MY	142	UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
	143	UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
	144	UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
54e991b5 MY	145	UNIPHIER_RESET_END,
	146	};
	147
716adfe3	148	static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = {
54e991b5 MY	149	UNIPHIER_MIO_RESET_SD(0, 0),
	150	UNIPHIER_MIO_RESET_SD(1, 1),
	151	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
	152	UNIPHIER_RESET_END,
	153	};
	154
	155	/* Peripheral reset data */
	156	#define UNIPHIER_PERI_RESET_UART(id, ch) \
	157	UNIPHIER_RESETX((id), 0x114, 19 + (ch))
	158
	159	#define UNIPHIER_PERI_RESET_I2C(id, ch) \
	160	UNIPHIER_RESETX((id), 0x114, 5 + (ch))
	161
	162	#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
	163	UNIPHIER_RESETX((id), 0x114, 24 + (ch))
	164
716adfe3	165	static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
54e991b5 MY	166	UNIPHIER_PERI_RESET_UART(0, 0),
	167	UNIPHIER_PERI_RESET_UART(1, 1),
	168	UNIPHIER_PERI_RESET_UART(2, 2),
	169	UNIPHIER_PERI_RESET_UART(3, 3),
	170	UNIPHIER_PERI_RESET_I2C(4, 0),
	171	UNIPHIER_PERI_RESET_I2C(5, 1),
	172	UNIPHIER_PERI_RESET_I2C(6, 2),
	173	UNIPHIER_PERI_RESET_I2C(7, 3),
	174	UNIPHIER_PERI_RESET_I2C(8, 4),
	175	UNIPHIER_RESET_END,
	176	};
	177
716adfe3	178	static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
54e991b5 MY	179	UNIPHIER_PERI_RESET_UART(0, 0),
	180	UNIPHIER_PERI_RESET_UART(1, 1),
	181	UNIPHIER_PERI_RESET_UART(2, 2),
	182	UNIPHIER_PERI_RESET_UART(3, 3),
	183	UNIPHIER_PERI_RESET_FI2C(4, 0),
	184	UNIPHIER_PERI_RESET_FI2C(5, 1),
	185	UNIPHIER_PERI_RESET_FI2C(6, 2),
	186	UNIPHIER_PERI_RESET_FI2C(7, 3),
	187	UNIPHIER_PERI_RESET_FI2C(8, 4),
	188	UNIPHIER_PERI_RESET_FI2C(9, 5),
	189	UNIPHIER_PERI_RESET_FI2C(10, 6),
	190	UNIPHIER_RESET_END,
	191	};
	192
	193	/* core implementaton */
	194	struct uniphier_reset_priv {
	195	struct reset_controller_dev rcdev;
	196	struct device *dev;
	197	struct regmap *regmap;
	198	const struct uniphier_reset_data *data;
	199	};
	200
	201	#define to_uniphier_reset_priv(_rcdev) \
	202	container_of(_rcdev, struct uniphier_reset_priv, rcdev)
	203
	204	static int uniphier_reset_update(struct reset_controller_dev *rcdev,
	205	unsigned long id, int assert)
	206	{
	207	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
	208	const struct uniphier_reset_data *p;
	209
	210	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
	211	unsigned int mask, val;
	212
	213	if (p->id != id)
	214	continue;
	215
	216	mask = BIT(p->bit);
	217
	218	if (assert)
	219	val = mask;
	220	else
	221	val = ~mask;
	222
	223	if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
	224	val = ~val;
	225
	226	return regmap_write_bits(priv->regmap, p->reg, mask, val);
	227	}
	228
	229	dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
	230	return -EINVAL;
	231	}
	232
	233	static int uniphier_reset_assert(struct reset_controller_dev *rcdev,
	234	unsigned long id)
	235	{
	236	return uniphier_reset_update(rcdev, id, 1);
	237	}
	238
	239	static int uniphier_reset_deassert(struct reset_controller_dev *rcdev,
	240	unsigned long id)
	241	{
	242	return uniphier_reset_update(rcdev, id, 0);
243	}
244
245	static int uniphier_reset_status(struct reset_controller_dev *rcdev,
246	unsigned long id)
247	{
248	struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev);
249	const struct uniphier_reset_data *p;
250
251	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
252	unsigned int val;
253	int ret, asserted;
254
255	if (p->id != id)
256	continue;
257
258	ret = regmap_read(priv->regmap, p->reg, &val);
259	if (ret)
260	return ret;
261
262	asserted = !!(val & BIT(p->bit));
263
264	if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
265	asserted = !asserted;
266
267	return asserted;
268	}
269
270	dev_err(priv->dev, "reset_id=%lu was not found\n", id);
271	return -EINVAL;
272	}
273
274	static const struct reset_control_ops uniphier_reset_ops = {
275	.assert = uniphier_reset_assert,
276	.deassert = uniphier_reset_deassert,
277	.status = uniphier_reset_status,
278	};
279
280	static int uniphier_reset_probe(struct platform_device *pdev)
281	{
282	struct device *dev = &pdev->dev;
283	struct uniphier_reset_priv *priv;
284	const struct uniphier_reset_data p, data;
285	struct regmap *regmap;
286	struct device_node *parent;
287	unsigned int nr_resets = 0;
288
289	data = of_device_get_match_data(dev);
290	if (WARN_ON(!data))
291	return -EINVAL;
292
293	parent = of_get_parent(dev->of_node); /* parent should be syscon node */
294	regmap = syscon_node_to_regmap(parent);
295	of_node_put(parent);
296	if (IS_ERR(regmap)) {
297	dev_err(dev, "failed to get regmap (error %ld)\n",
298	PTR_ERR(regmap));
299	return PTR_ERR(regmap);
300	}
301
302	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
303	if (!priv)
304	return -ENOMEM;
305
306	for (p = data; p->id != UNIPHIER_RESET_ID_END; p++)
307	nr_resets = max(nr_resets, p->id + 1);
308
309	priv->rcdev.ops = &uniphier_reset_ops;
310	priv->rcdev.owner = dev->driver->owner;
311	priv->rcdev.of_node = dev->of_node;
312	priv->rcdev.nr_resets = nr_resets;
313	priv->dev = dev;
314	priv->regmap = regmap;
315	priv->data = data;
316
317	return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
318	}
319
320	static const struct of_device_id uniphier_reset_match[] = {
321	/* System reset */
54e991b5 MY	322	{
54e991b5 MY	323	.compatible = "socionext,uniphier-ld4-reset",
5281036a	324	.data = uniphier_ld4_sys_reset_data,
54e991b5 MY	325	},
	326	{
	327	.compatible = "socionext,uniphier-pro4-reset",
	328	.data = uniphier_pro4_sys_reset_data,
	329	},
	330	{
	331	.compatible = "socionext,uniphier-sld8-reset",
5281036a	332	.data = uniphier_ld4_sys_reset_data,
54e991b5 MY	333	},
	334	{
	335	.compatible = "socionext,uniphier-pro5-reset",
	336	.data = uniphier_pro5_sys_reset_data,
	337	},
	338	{
	339	.compatible = "socionext,uniphier-pxs2-reset",
	340	.data = uniphier_pxs2_sys_reset_data,
	341	},
	342	{
	343	.compatible = "socionext,uniphier-ld11-reset",
	344	.data = uniphier_ld11_sys_reset_data,
	345	},
	346	{
	347	.compatible = "socionext,uniphier-ld20-reset",
	348	.data = uniphier_ld20_sys_reset_data,
	349	},
19eb4a47	350	/* Media I/O reset, SD reset */
54e991b5 MY	351	{
54e991b5 MY	352	.compatible = "socionext,uniphier-ld4-mio-reset",
5281036a	353	.data = uniphier_ld4_mio_reset_data,
54e991b5 MY	354	},
	355	{
	356	.compatible = "socionext,uniphier-pro4-mio-reset",
5281036a	357	.data = uniphier_ld4_mio_reset_data,
54e991b5 MY	358	},
	359	{
	360	.compatible = "socionext,uniphier-sld8-mio-reset",
5281036a	361	.data = uniphier_ld4_mio_reset_data,
54e991b5 MY	362	},
54e991b5 MY	363	{
19eb4a47 MY	364	.compatible = "socionext,uniphier-pro5-sd-reset",
19eb4a47 MY	365	.data = uniphier_pro5_sd_reset_data,
54e991b5 MY	366	},
54e991b5 MY	367	{
19eb4a47 MY	368	.compatible = "socionext,uniphier-pxs2-sd-reset",
19eb4a47 MY	369	.data = uniphier_pro5_sd_reset_data,
54e991b5 MY	370	},
	371	{
	372	.compatible = "socionext,uniphier-ld11-mio-reset",
5281036a	373	.data = uniphier_ld4_mio_reset_data,
54e991b5	374	},
88a7f523 MY	375	{
	376	.compatible = "socionext,uniphier-ld11-sd-reset",
	377	.data = uniphier_pro5_sd_reset_data,
	378	},
54e991b5	379	{
19eb4a47 MY	380	.compatible = "socionext,uniphier-ld20-sd-reset",
19eb4a47 MY	381	.data = uniphier_pro5_sd_reset_data,
54e991b5 MY	382	},
	383	/* Peripheral reset */
	384	{
	385	.compatible = "socionext,uniphier-ld4-peri-reset",
	386	.data = uniphier_ld4_peri_reset_data,
	387	},
	388	{
	389	.compatible = "socionext,uniphier-pro4-peri-reset",
	390	.data = uniphier_pro4_peri_reset_data,
	391	},
	392	{
	393	.compatible = "socionext,uniphier-sld8-peri-reset",
	394	.data = uniphier_ld4_peri_reset_data,
	395	},
	396	{
	397	.compatible = "socionext,uniphier-pro5-peri-reset",
	398	.data = uniphier_pro4_peri_reset_data,
	399	},
	400	{
	401	.compatible = "socionext,uniphier-pxs2-peri-reset",
	402	.data = uniphier_pro4_peri_reset_data,
	403	},
	404	{
	405	.compatible = "socionext,uniphier-ld11-peri-reset",
	406	.data = uniphier_pro4_peri_reset_data,
	407	},
	408	{
	409	.compatible = "socionext,uniphier-ld20-peri-reset",
	410	.data = uniphier_pro4_peri_reset_data,
	411	},
	412	{ /* sentinel */ }
	413	};
	414	MODULE_DEVICE_TABLE(of, uniphier_reset_match);
	415
	416	static struct platform_driver uniphier_reset_driver = {
	417	.probe = uniphier_reset_probe,
	418	.driver = {
	419	.name = "uniphier-reset",
	420	.of_match_table = uniphier_reset_match,
	421	},
	422	};
	423	module_platform_driver(uniphier_reset_driver);
	424
	425	MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
	426	MODULE_DESCRIPTION("UniPhier Reset Controller Driver");
	427	MODULE_LICENSE("GPL");