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54e991b5 MY |
1 | /* |
2 | * Copyright (C) 2016 Socionext Inc. | |
3 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/mfd/syscon.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_device.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/reset-controller.h> | |
23 | ||
24 | struct uniphier_reset_data { | |
25 | unsigned int id; | |
26 | unsigned int reg; | |
27 | unsigned int bit; | |
28 | unsigned int flags; | |
29 | #define UNIPHIER_RESET_ACTIVE_LOW BIT(0) | |
30 | }; | |
31 | ||
32 | #define UNIPHIER_RESET_ID_END (unsigned int)(-1) | |
33 | ||
34 | #define UNIPHIER_RESET_END \ | |
35 | { .id = UNIPHIER_RESET_ID_END } | |
36 | ||
37 | #define UNIPHIER_RESET(_id, _reg, _bit) \ | |
38 | { \ | |
39 | .id = (_id), \ | |
40 | .reg = (_reg), \ | |
41 | .bit = (_bit), \ | |
42 | } | |
43 | ||
44 | #define UNIPHIER_RESETX(_id, _reg, _bit) \ | |
45 | { \ | |
46 | .id = (_id), \ | |
47 | .reg = (_reg), \ | |
48 | .bit = (_bit), \ | |
49 | .flags = UNIPHIER_RESET_ACTIVE_LOW, \ | |
50 | } | |
51 | ||
52 | /* System reset data */ | |
5281036a MY |
53 | static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = { |
54 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ | |
55 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */ | |
54e991b5 MY |
56 | UNIPHIER_RESET_END, |
57 | }; | |
58 | ||
716adfe3 | 59 | static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { |
5281036a | 60 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
4c05c4a5 | 61 | UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */ |
5281036a | 62 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */ |
dec173cc MY |
63 | UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */ |
64 | UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ | |
65 | UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ | |
78636717 KH |
66 | UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */ |
67 | UNIPHIER_RESETX(29, 0x2004, 18), /* SATA1 */ | |
68 | UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */ | |
b06b631c | 69 | UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ |
54e991b5 MY |
70 | UNIPHIER_RESET_END, |
71 | }; | |
72 | ||
716adfe3 | 73 | static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { |
5281036a MY |
74 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
75 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC) */ | |
dec173cc MY |
76 | UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */ |
77 | UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ | |
78 | UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ | |
fdc0f235 | 79 | UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */ |
b06b631c | 80 | UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ |
54e991b5 MY |
81 | UNIPHIER_RESET_END, |
82 | }; | |
83 | ||
716adfe3 | 84 | static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { |
5281036a | 85 | UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
4c05c4a5 | 86 | UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */ |
5281036a | 87 | UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, RLE) */ |
dec173cc MY |
88 | UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ |
89 | UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ | |
54e991b5 MY |
90 | UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */ |
91 | UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */ | |
92 | UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */ | |
93 | UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */ | |
94 | UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */ | |
95 | UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */ | |
78636717 | 96 | UNIPHIER_RESET(30, 0x2014, 8), /* SATA-PHY (active high) */ |
b06b631c | 97 | UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ |
54e991b5 MY |
98 | UNIPHIER_RESET_END, |
99 | }; | |
100 | ||
716adfe3 | 101 | static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { |
dec173cc MY |
102 | UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ |
103 | UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ | |
4c05c4a5 | 104 | UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */ |
dec173cc | 105 | UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC, MIO) */ |
d7bab65b | 106 | UNIPHIER_RESETX(9, 0x200c, 9), /* HSC */ |
94e10c22 KS |
107 | UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */ |
108 | UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */ | |
0f195435 | 109 | UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */ |
54e991b5 MY |
110 | UNIPHIER_RESET_END, |
111 | }; | |
112 | ||
716adfe3 | 113 | static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { |
dec173cc MY |
114 | UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ |
115 | UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ | |
4c05c4a5 | 116 | UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */ |
dec173cc | 117 | UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */ |
d7bab65b | 118 | UNIPHIER_RESETX(9, 0x200c, 9), /* HSC */ |
e6914365 | 119 | UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */ |
54e991b5 MY |
120 | UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ |
121 | UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ | |
122 | UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ | |
123 | UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */ | |
fdc0f235 | 124 | UNIPHIER_RESETX(24, 0x200c, 4), /* PCIe */ |
94e10c22 KS |
125 | UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */ |
126 | UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */ | |
0f195435 | 127 | UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */ |
54e991b5 MY |
128 | UNIPHIER_RESET_END, |
129 | }; | |
130 | ||
2a158f88 MY |
131 | static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { |
132 | UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ | |
133 | UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ | |
5573fe85 KH |
134 | UNIPHIER_RESETX(6, 0x200c, 9), /* Ether0 */ |
135 | UNIPHIER_RESETX(7, 0x200c, 10), /* Ether1 */ | |
2a158f88 | 136 | UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ |
e6914365 MY |
137 | UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */ |
138 | UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */ | |
2a158f88 MY |
139 | UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */ |
140 | UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */ | |
141 | UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */ | |
142 | UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ | |
143 | UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ | |
fdc0f235 | 144 | UNIPHIER_RESETX(24, 0x200c, 3), /* PCIe */ |
78636717 KH |
145 | UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */ |
146 | UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */ | |
147 | UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */ | |
2a158f88 MY |
148 | UNIPHIER_RESET_END, |
149 | }; | |
150 | ||
54e991b5 MY |
151 | /* Media I/O reset data */ |
152 | #define UNIPHIER_MIO_RESET_SD(id, ch) \ | |
153 | UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) | |
154 | ||
155 | #define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ | |
156 | UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26) | |
157 | ||
158 | #define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ | |
159 | UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0) | |
160 | ||
161 | #define UNIPHIER_MIO_RESET_USB2(id, ch) \ | |
162 | UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0) | |
163 | ||
164 | #define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ | |
165 | UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24) | |
166 | ||
167 | #define UNIPHIER_MIO_RESET_DMAC(id) \ | |
168 | UNIPHIER_RESETX((id), 0x110, 17) | |
169 | ||
5281036a | 170 | static const struct uniphier_reset_data uniphier_ld4_mio_reset_data[] = { |
54e991b5 MY |
171 | UNIPHIER_MIO_RESET_SD(0, 0), |
172 | UNIPHIER_MIO_RESET_SD(1, 1), | |
173 | UNIPHIER_MIO_RESET_SD(2, 2), | |
174 | UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0), | |
175 | UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1), | |
176 | UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2), | |
177 | UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), | |
178 | UNIPHIER_MIO_RESET_DMAC(7), | |
179 | UNIPHIER_MIO_RESET_USB2(8, 0), | |
180 | UNIPHIER_MIO_RESET_USB2(9, 1), | |
181 | UNIPHIER_MIO_RESET_USB2(10, 2), | |
54e991b5 MY |
182 | UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0), |
183 | UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1), | |
184 | UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2), | |
54e991b5 MY |
185 | UNIPHIER_RESET_END, |
186 | }; | |
187 | ||
716adfe3 | 188 | static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { |
54e991b5 MY |
189 | UNIPHIER_MIO_RESET_SD(0, 0), |
190 | UNIPHIER_MIO_RESET_SD(1, 1), | |
191 | UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), | |
192 | UNIPHIER_RESET_END, | |
193 | }; | |
194 | ||
195 | /* Peripheral reset data */ | |
196 | #define UNIPHIER_PERI_RESET_UART(id, ch) \ | |
197 | UNIPHIER_RESETX((id), 0x114, 19 + (ch)) | |
198 | ||
199 | #define UNIPHIER_PERI_RESET_I2C(id, ch) \ | |
200 | UNIPHIER_RESETX((id), 0x114, 5 + (ch)) | |
201 | ||
202 | #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ | |
203 | UNIPHIER_RESETX((id), 0x114, 24 + (ch)) | |
204 | ||
6b39fd59 KH |
205 | #define UNIPHIER_PERI_RESET_SCSSI(id) \ |
206 | UNIPHIER_RESETX((id), 0x110, 17) | |
207 | ||
208 | #define UNIPHIER_PERI_RESET_MCSSI(id) \ | |
209 | UNIPHIER_RESETX((id), 0x114, 14) | |
210 | ||
716adfe3 | 211 | static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { |
54e991b5 MY |
212 | UNIPHIER_PERI_RESET_UART(0, 0), |
213 | UNIPHIER_PERI_RESET_UART(1, 1), | |
214 | UNIPHIER_PERI_RESET_UART(2, 2), | |
215 | UNIPHIER_PERI_RESET_UART(3, 3), | |
216 | UNIPHIER_PERI_RESET_I2C(4, 0), | |
217 | UNIPHIER_PERI_RESET_I2C(5, 1), | |
218 | UNIPHIER_PERI_RESET_I2C(6, 2), | |
219 | UNIPHIER_PERI_RESET_I2C(7, 3), | |
220 | UNIPHIER_PERI_RESET_I2C(8, 4), | |
6b39fd59 | 221 | UNIPHIER_PERI_RESET_SCSSI(11), |
54e991b5 MY |
222 | UNIPHIER_RESET_END, |
223 | }; | |
224 | ||
716adfe3 | 225 | static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { |
54e991b5 MY |
226 | UNIPHIER_PERI_RESET_UART(0, 0), |
227 | UNIPHIER_PERI_RESET_UART(1, 1), | |
228 | UNIPHIER_PERI_RESET_UART(2, 2), | |
229 | UNIPHIER_PERI_RESET_UART(3, 3), | |
230 | UNIPHIER_PERI_RESET_FI2C(4, 0), | |
231 | UNIPHIER_PERI_RESET_FI2C(5, 1), | |
232 | UNIPHIER_PERI_RESET_FI2C(6, 2), | |
233 | UNIPHIER_PERI_RESET_FI2C(7, 3), | |
234 | UNIPHIER_PERI_RESET_FI2C(8, 4), | |
235 | UNIPHIER_PERI_RESET_FI2C(9, 5), | |
236 | UNIPHIER_PERI_RESET_FI2C(10, 6), | |
6b39fd59 KH |
237 | UNIPHIER_PERI_RESET_SCSSI(11), |
238 | UNIPHIER_PERI_RESET_MCSSI(12), | |
54e991b5 MY |
239 | UNIPHIER_RESET_END, |
240 | }; | |
241 | ||
ac0c735a KS |
242 | /* Analog signal amplifiers reset data */ |
243 | static const struct uniphier_reset_data uniphier_ld11_adamv_reset_data[] = { | |
244 | UNIPHIER_RESETX(0, 0x10, 6), /* EVEA */ | |
245 | UNIPHIER_RESET_END, | |
246 | }; | |
247 | ||
54e991b5 MY |
248 | /* core implementaton */ |
249 | struct uniphier_reset_priv { | |
250 | struct reset_controller_dev rcdev; | |
251 | struct device *dev; | |
252 | struct regmap *regmap; | |
253 | const struct uniphier_reset_data *data; | |
254 | }; | |
255 | ||
256 | #define to_uniphier_reset_priv(_rcdev) \ | |
257 | container_of(_rcdev, struct uniphier_reset_priv, rcdev) | |
258 | ||
259 | static int uniphier_reset_update(struct reset_controller_dev *rcdev, | |
260 | unsigned long id, int assert) | |
261 | { | |
262 | struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev); | |
263 | const struct uniphier_reset_data *p; | |
264 | ||
265 | for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) { | |
266 | unsigned int mask, val; | |
267 | ||
268 | if (p->id != id) | |
269 | continue; | |
270 | ||
271 | mask = BIT(p->bit); | |
272 | ||
273 | if (assert) | |
274 | val = mask; | |
275 | else | |
276 | val = ~mask; | |
277 | ||
278 | if (p->flags & UNIPHIER_RESET_ACTIVE_LOW) | |
279 | val = ~val; | |
280 | ||
281 | return regmap_write_bits(priv->regmap, p->reg, mask, val); | |
282 | } | |
283 | ||
284 | dev_err(priv->dev, "reset_id=%lu was not handled\n", id); | |
285 | return -EINVAL; | |
286 | } | |
287 | ||
288 | static int uniphier_reset_assert(struct reset_controller_dev *rcdev, | |
289 | unsigned long id) | |
290 | { | |
291 | return uniphier_reset_update(rcdev, id, 1); | |
292 | } | |
293 | ||
294 | static int uniphier_reset_deassert(struct reset_controller_dev *rcdev, | |
295 | unsigned long id) | |
296 | { | |
297 | return uniphier_reset_update(rcdev, id, 0); | |
298 | } | |
299 | ||
300 | static int uniphier_reset_status(struct reset_controller_dev *rcdev, | |
301 | unsigned long id) | |
302 | { | |
303 | struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev); | |
304 | const struct uniphier_reset_data *p; | |
305 | ||
306 | for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) { | |
307 | unsigned int val; | |
308 | int ret, asserted; | |
309 | ||
310 | if (p->id != id) | |
311 | continue; | |
312 | ||
313 | ret = regmap_read(priv->regmap, p->reg, &val); | |
314 | if (ret) | |
315 | return ret; | |
316 | ||
317 | asserted = !!(val & BIT(p->bit)); | |
318 | ||
319 | if (p->flags & UNIPHIER_RESET_ACTIVE_LOW) | |
320 | asserted = !asserted; | |
321 | ||
322 | return asserted; | |
323 | } | |
324 | ||
325 | dev_err(priv->dev, "reset_id=%lu was not found\n", id); | |
326 | return -EINVAL; | |
327 | } | |
328 | ||
329 | static const struct reset_control_ops uniphier_reset_ops = { | |
330 | .assert = uniphier_reset_assert, | |
331 | .deassert = uniphier_reset_deassert, | |
332 | .status = uniphier_reset_status, | |
333 | }; | |
334 | ||
335 | static int uniphier_reset_probe(struct platform_device *pdev) | |
336 | { | |
337 | struct device *dev = &pdev->dev; | |
338 | struct uniphier_reset_priv *priv; | |
339 | const struct uniphier_reset_data *p, *data; | |
340 | struct regmap *regmap; | |
341 | struct device_node *parent; | |
342 | unsigned int nr_resets = 0; | |
343 | ||
344 | data = of_device_get_match_data(dev); | |
345 | if (WARN_ON(!data)) | |
346 | return -EINVAL; | |
347 | ||
348 | parent = of_get_parent(dev->of_node); /* parent should be syscon node */ | |
349 | regmap = syscon_node_to_regmap(parent); | |
350 | of_node_put(parent); | |
351 | if (IS_ERR(regmap)) { | |
352 | dev_err(dev, "failed to get regmap (error %ld)\n", | |
353 | PTR_ERR(regmap)); | |
354 | return PTR_ERR(regmap); | |
355 | } | |
356 | ||
357 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
358 | if (!priv) | |
359 | return -ENOMEM; | |
360 | ||
361 | for (p = data; p->id != UNIPHIER_RESET_ID_END; p++) | |
362 | nr_resets = max(nr_resets, p->id + 1); | |
363 | ||
364 | priv->rcdev.ops = &uniphier_reset_ops; | |
365 | priv->rcdev.owner = dev->driver->owner; | |
366 | priv->rcdev.of_node = dev->of_node; | |
367 | priv->rcdev.nr_resets = nr_resets; | |
368 | priv->dev = dev; | |
369 | priv->regmap = regmap; | |
370 | priv->data = data; | |
371 | ||
372 | return devm_reset_controller_register(&pdev->dev, &priv->rcdev); | |
373 | } | |
374 | ||
375 | static const struct of_device_id uniphier_reset_match[] = { | |
376 | /* System reset */ | |
54e991b5 MY |
377 | { |
378 | .compatible = "socionext,uniphier-ld4-reset", | |
5281036a | 379 | .data = uniphier_ld4_sys_reset_data, |
54e991b5 MY |
380 | }, |
381 | { | |
382 | .compatible = "socionext,uniphier-pro4-reset", | |
383 | .data = uniphier_pro4_sys_reset_data, | |
384 | }, | |
385 | { | |
386 | .compatible = "socionext,uniphier-sld8-reset", | |
5281036a | 387 | .data = uniphier_ld4_sys_reset_data, |
54e991b5 MY |
388 | }, |
389 | { | |
390 | .compatible = "socionext,uniphier-pro5-reset", | |
391 | .data = uniphier_pro5_sys_reset_data, | |
392 | }, | |
393 | { | |
394 | .compatible = "socionext,uniphier-pxs2-reset", | |
395 | .data = uniphier_pxs2_sys_reset_data, | |
396 | }, | |
397 | { | |
398 | .compatible = "socionext,uniphier-ld11-reset", | |
399 | .data = uniphier_ld11_sys_reset_data, | |
400 | }, | |
401 | { | |
402 | .compatible = "socionext,uniphier-ld20-reset", | |
403 | .data = uniphier_ld20_sys_reset_data, | |
404 | }, | |
2a158f88 MY |
405 | { |
406 | .compatible = "socionext,uniphier-pxs3-reset", | |
407 | .data = uniphier_pxs3_sys_reset_data, | |
408 | }, | |
19eb4a47 | 409 | /* Media I/O reset, SD reset */ |
54e991b5 MY |
410 | { |
411 | .compatible = "socionext,uniphier-ld4-mio-reset", | |
5281036a | 412 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 MY |
413 | }, |
414 | { | |
415 | .compatible = "socionext,uniphier-pro4-mio-reset", | |
5281036a | 416 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 MY |
417 | }, |
418 | { | |
419 | .compatible = "socionext,uniphier-sld8-mio-reset", | |
5281036a | 420 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 MY |
421 | }, |
422 | { | |
19eb4a47 MY |
423 | .compatible = "socionext,uniphier-pro5-sd-reset", |
424 | .data = uniphier_pro5_sd_reset_data, | |
54e991b5 MY |
425 | }, |
426 | { | |
19eb4a47 MY |
427 | .compatible = "socionext,uniphier-pxs2-sd-reset", |
428 | .data = uniphier_pro5_sd_reset_data, | |
54e991b5 MY |
429 | }, |
430 | { | |
431 | .compatible = "socionext,uniphier-ld11-mio-reset", | |
5281036a | 432 | .data = uniphier_ld4_mio_reset_data, |
54e991b5 | 433 | }, |
88a7f523 MY |
434 | { |
435 | .compatible = "socionext,uniphier-ld11-sd-reset", | |
436 | .data = uniphier_pro5_sd_reset_data, | |
437 | }, | |
54e991b5 | 438 | { |
19eb4a47 MY |
439 | .compatible = "socionext,uniphier-ld20-sd-reset", |
440 | .data = uniphier_pro5_sd_reset_data, | |
54e991b5 | 441 | }, |
2a158f88 MY |
442 | { |
443 | .compatible = "socionext,uniphier-pxs3-sd-reset", | |
444 | .data = uniphier_pro5_sd_reset_data, | |
445 | }, | |
54e991b5 MY |
446 | /* Peripheral reset */ |
447 | { | |
448 | .compatible = "socionext,uniphier-ld4-peri-reset", | |
449 | .data = uniphier_ld4_peri_reset_data, | |
450 | }, | |
451 | { | |
452 | .compatible = "socionext,uniphier-pro4-peri-reset", | |
453 | .data = uniphier_pro4_peri_reset_data, | |
454 | }, | |
455 | { | |
456 | .compatible = "socionext,uniphier-sld8-peri-reset", | |
457 | .data = uniphier_ld4_peri_reset_data, | |
458 | }, | |
459 | { | |
460 | .compatible = "socionext,uniphier-pro5-peri-reset", | |
461 | .data = uniphier_pro4_peri_reset_data, | |
462 | }, | |
463 | { | |
464 | .compatible = "socionext,uniphier-pxs2-peri-reset", | |
465 | .data = uniphier_pro4_peri_reset_data, | |
466 | }, | |
467 | { | |
468 | .compatible = "socionext,uniphier-ld11-peri-reset", | |
469 | .data = uniphier_pro4_peri_reset_data, | |
470 | }, | |
471 | { | |
472 | .compatible = "socionext,uniphier-ld20-peri-reset", | |
473 | .data = uniphier_pro4_peri_reset_data, | |
474 | }, | |
2a158f88 MY |
475 | { |
476 | .compatible = "socionext,uniphier-pxs3-peri-reset", | |
477 | .data = uniphier_pro4_peri_reset_data, | |
478 | }, | |
ac0c735a KS |
479 | /* Analog signal amplifiers reset */ |
480 | { | |
481 | .compatible = "socionext,uniphier-ld11-adamv-reset", | |
482 | .data = uniphier_ld11_adamv_reset_data, | |
483 | }, | |
484 | { | |
485 | .compatible = "socionext,uniphier-ld20-adamv-reset", | |
486 | .data = uniphier_ld11_adamv_reset_data, | |
487 | }, | |
54e991b5 MY |
488 | { /* sentinel */ } |
489 | }; | |
490 | MODULE_DEVICE_TABLE(of, uniphier_reset_match); | |
491 | ||
492 | static struct platform_driver uniphier_reset_driver = { | |
493 | .probe = uniphier_reset_probe, | |
494 | .driver = { | |
495 | .name = "uniphier-reset", | |
496 | .of_match_table = uniphier_reset_match, | |
497 | }, | |
498 | }; | |
499 | module_platform_driver(uniphier_reset_driver); | |
500 | ||
501 | MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); | |
502 | MODULE_DESCRIPTION("UniPhier Reset Controller Driver"); | |
503 | MODULE_LICENSE("GPL"); |