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81c22ad0 PZ |
1 | /* |
2 | * Simple Reset Controller Driver | |
3 | * | |
4 | * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de> | |
5 | * | |
6 | * Based on Allwinner SoCs Reset Controller driver | |
7 | * | |
8 | * Copyright 2013 Maxime Ripard | |
9 | * | |
10 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | */ | |
17 | ||
18 | #include <linux/device.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/reset-controller.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
27 | #include "reset-simple.h" | |
28 | ||
29 | static inline struct reset_simple_data * | |
30 | to_reset_simple_data(struct reset_controller_dev *rcdev) | |
31 | { | |
32 | return container_of(rcdev, struct reset_simple_data, rcdev); | |
33 | } | |
34 | ||
35 | static int reset_simple_update(struct reset_controller_dev *rcdev, | |
36 | unsigned long id, bool assert) | |
37 | { | |
38 | struct reset_simple_data *data = to_reset_simple_data(rcdev); | |
39 | int reg_width = sizeof(u32); | |
40 | int bank = id / (reg_width * BITS_PER_BYTE); | |
41 | int offset = id % (reg_width * BITS_PER_BYTE); | |
42 | unsigned long flags; | |
43 | u32 reg; | |
44 | ||
45 | spin_lock_irqsave(&data->lock, flags); | |
46 | ||
47 | reg = readl(data->membase + (bank * reg_width)); | |
48 | if (assert ^ data->active_low) | |
49 | reg |= BIT(offset); | |
50 | else | |
51 | reg &= ~BIT(offset); | |
52 | writel(reg, data->membase + (bank * reg_width)); | |
53 | ||
54 | spin_unlock_irqrestore(&data->lock, flags); | |
55 | ||
56 | return 0; | |
57 | } | |
58 | ||
59 | static int reset_simple_assert(struct reset_controller_dev *rcdev, | |
60 | unsigned long id) | |
61 | { | |
62 | return reset_simple_update(rcdev, id, true); | |
63 | } | |
64 | ||
65 | static int reset_simple_deassert(struct reset_controller_dev *rcdev, | |
66 | unsigned long id) | |
67 | { | |
68 | return reset_simple_update(rcdev, id, false); | |
69 | } | |
70 | ||
adf20d7c PZ |
71 | static int reset_simple_status(struct reset_controller_dev *rcdev, |
72 | unsigned long id) | |
73 | { | |
74 | struct reset_simple_data *data = to_reset_simple_data(rcdev); | |
75 | int reg_width = sizeof(u32); | |
76 | int bank = id / (reg_width * BITS_PER_BYTE); | |
77 | int offset = id % (reg_width * BITS_PER_BYTE); | |
78 | u32 reg; | |
79 | ||
80 | reg = readl(data->membase + (bank * reg_width)); | |
81 | ||
82 | return !(reg & BIT(offset)) ^ !data->status_active_low; | |
83 | } | |
84 | ||
81c22ad0 PZ |
85 | const struct reset_control_ops reset_simple_ops = { |
86 | .assert = reset_simple_assert, | |
87 | .deassert = reset_simple_deassert, | |
adf20d7c | 88 | .status = reset_simple_status, |
81c22ad0 PZ |
89 | }; |
90 | ||
91 | /** | |
92 | * struct reset_simple_devdata - simple reset controller properties | |
adf20d7c PZ |
93 | * @reg_offset: offset between base address and first reset register. |
94 | * @nr_resets: number of resets. If not set, default to resource size in bits. | |
81c22ad0 PZ |
95 | * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits |
96 | * are set to assert the reset. | |
adf20d7c PZ |
97 | * @status_active_low: if true, bits read back as cleared while the reset is |
98 | * asserted. Otherwise, bits read back as set while the | |
99 | * reset is asserted. | |
81c22ad0 PZ |
100 | */ |
101 | struct reset_simple_devdata { | |
adf20d7c PZ |
102 | u32 reg_offset; |
103 | u32 nr_resets; | |
81c22ad0 | 104 | bool active_low; |
adf20d7c PZ |
105 | bool status_active_low; |
106 | }; | |
107 | ||
108 | #define SOCFPGA_NR_BANKS 8 | |
109 | ||
110 | static const struct reset_simple_devdata reset_simple_socfpga = { | |
111 | .reg_offset = 0x10, | |
112 | .nr_resets = SOCFPGA_NR_BANKS * 32, | |
113 | .status_active_low = true, | |
81c22ad0 PZ |
114 | }; |
115 | ||
116 | static const struct reset_simple_devdata reset_simple_active_low = { | |
117 | .active_low = true, | |
adf20d7c | 118 | .status_active_low = true, |
81c22ad0 PZ |
119 | }; |
120 | ||
121 | static const struct of_device_id reset_simple_dt_ids[] = { | |
adf20d7c | 122 | { .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga }, |
81c22ad0 PZ |
123 | { .compatible = "allwinner,sun6i-a31-clock-reset", |
124 | .data = &reset_simple_active_low }, | |
125 | { /* sentinel */ }, | |
126 | }; | |
127 | ||
128 | static int reset_simple_probe(struct platform_device *pdev) | |
129 | { | |
130 | struct device *dev = &pdev->dev; | |
131 | const struct reset_simple_devdata *devdata; | |
132 | struct reset_simple_data *data; | |
133 | void __iomem *membase; | |
134 | struct resource *res; | |
adf20d7c | 135 | u32 reg_offset = 0; |
81c22ad0 PZ |
136 | |
137 | devdata = of_device_get_match_data(dev); | |
138 | ||
139 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
140 | if (!data) | |
141 | return -ENOMEM; | |
142 | ||
143 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
144 | membase = devm_ioremap_resource(dev, res); | |
145 | if (IS_ERR(membase)) | |
146 | return PTR_ERR(membase); | |
147 | ||
148 | spin_lock_init(&data->lock); | |
149 | data->membase = membase; | |
150 | data->rcdev.owner = THIS_MODULE; | |
151 | data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE; | |
152 | data->rcdev.ops = &reset_simple_ops; | |
153 | data->rcdev.of_node = dev->of_node; | |
154 | ||
adf20d7c PZ |
155 | if (devdata) { |
156 | reg_offset = devdata->reg_offset; | |
157 | if (devdata->nr_resets) | |
158 | data->rcdev.nr_resets = devdata->nr_resets; | |
81c22ad0 | 159 | data->active_low = devdata->active_low; |
adf20d7c PZ |
160 | data->status_active_low = devdata->status_active_low; |
161 | } | |
162 | ||
163 | if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") && | |
164 | of_property_read_u32(dev->of_node, "altr,modrst-offset", | |
165 | ®_offset)) { | |
166 | dev_warn(dev, | |
167 | "missing altr,modrst-offset property, assuming 0x%x!\n", | |
168 | reg_offset); | |
169 | } | |
170 | ||
171 | data->membase += reg_offset; | |
81c22ad0 PZ |
172 | |
173 | return devm_reset_controller_register(dev, &data->rcdev); | |
174 | } | |
175 | ||
176 | static struct platform_driver reset_simple_driver = { | |
177 | .probe = reset_simple_probe, | |
178 | .driver = { | |
179 | .name = "simple-reset", | |
180 | .of_match_table = reset_simple_dt_ids, | |
181 | }, | |
182 | }; | |
183 | builtin_platform_driver(reset_simple_driver); |