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abf97755 AS |
1 | /* |
2 | * Copyright (c) 2017, Impinj, Inc. | |
3 | * | |
4 | * i.MX7 System Reset Controller (SRC) driver | |
5 | * | |
6 | * Author: Andrey Smirnov <andrew.smirnov@gmail.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/mfd/syscon.h> | |
ac316725 | 19 | #include <linux/mod_devicetable.h> |
10590358 | 20 | #include <linux/of_device.h> |
abf97755 AS |
21 | #include <linux/platform_device.h> |
22 | #include <linux/reset-controller.h> | |
23 | #include <linux/regmap.h> | |
24 | #include <dt-bindings/reset/imx7-reset.h> | |
c979dbf5 | 25 | #include <dt-bindings/reset/imx8mq-reset.h> |
abf97755 | 26 | |
10590358 AS |
27 | struct imx7_src_signal { |
28 | unsigned int offset, bit; | |
29 | }; | |
30 | ||
31 | struct imx7_src_variant { | |
32 | const struct imx7_src_signal *signals; | |
33 | unsigned int signals_num; | |
34 | struct reset_control_ops ops; | |
35 | }; | |
36 | ||
abf97755 AS |
37 | struct imx7_src { |
38 | struct reset_controller_dev rcdev; | |
39 | struct regmap *regmap; | |
10590358 | 40 | const struct imx7_src_signal *signals; |
abf97755 AS |
41 | }; |
42 | ||
43 | enum imx7_src_registers { | |
44 | SRC_A7RCR0 = 0x0004, | |
45 | SRC_M4RCR = 0x000c, | |
46 | SRC_ERCR = 0x0014, | |
47 | SRC_HSICPHY_RCR = 0x001c, | |
48 | SRC_USBOPHY1_RCR = 0x0020, | |
49 | SRC_USBOPHY2_RCR = 0x0024, | |
50 | SRC_MIPIPHY_RCR = 0x0028, | |
51 | SRC_PCIEPHY_RCR = 0x002c, | |
52 | SRC_DDRC_RCR = 0x1000, | |
53 | }; | |
54 | ||
10590358 AS |
55 | static int imx7_reset_update(struct imx7_src *imx7src, |
56 | unsigned long id, unsigned int value) | |
57 | { | |
58 | const struct imx7_src_signal *signal = &imx7src->signals[id]; | |
59 | ||
60 | return regmap_update_bits(imx7src->regmap, | |
61 | signal->offset, signal->bit, value); | |
62 | } | |
abf97755 AS |
63 | |
64 | static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { | |
65 | [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, | |
66 | [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) }, | |
67 | [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) }, | |
68 | [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) }, | |
69 | [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) }, | |
70 | [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) }, | |
71 | [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) }, | |
72 | [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) }, | |
73 | [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) }, | |
74 | [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) }, | |
75 | [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, | |
76 | [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, | |
77 | [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) }, | |
78 | [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) }, | |
79 | [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) }, | |
80 | [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) }, | |
81 | [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) }, | |
82 | [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) }, | |
83 | [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) }, | |
84 | [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) }, | |
85 | [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, | |
86 | [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, | |
87 | [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, | |
de248327 | 88 | [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, |
abf97755 AS |
89 | [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) }, |
90 | [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, | |
91 | }; | |
92 | ||
93 | static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev) | |
94 | { | |
95 | return container_of(rcdev, struct imx7_src, rcdev); | |
96 | } | |
97 | ||
98 | static int imx7_reset_set(struct reset_controller_dev *rcdev, | |
99 | unsigned long id, bool assert) | |
100 | { | |
101 | struct imx7_src *imx7src = to_imx7_src(rcdev); | |
10590358 AS |
102 | const unsigned int bit = imx7src->signals[id].bit; |
103 | unsigned int value = assert ? bit : 0; | |
abf97755 AS |
104 | |
105 | switch (id) { | |
106 | case IMX7_RESET_PCIEPHY: | |
107 | /* | |
108 | * wait for more than 10us to release phy g_rst and | |
109 | * btnrst | |
110 | */ | |
111 | if (!assert) | |
112 | udelay(10); | |
113 | break; | |
114 | ||
115 | case IMX7_RESET_PCIE_CTRL_APPS_EN: | |
10590358 | 116 | value = assert ? 0 : bit; |
abf97755 AS |
117 | break; |
118 | } | |
119 | ||
10590358 | 120 | return imx7_reset_update(imx7src, id, value); |
abf97755 AS |
121 | } |
122 | ||
123 | static int imx7_reset_assert(struct reset_controller_dev *rcdev, | |
124 | unsigned long id) | |
125 | { | |
126 | return imx7_reset_set(rcdev, id, true); | |
127 | } | |
128 | ||
129 | static int imx7_reset_deassert(struct reset_controller_dev *rcdev, | |
130 | unsigned long id) | |
131 | { | |
132 | return imx7_reset_set(rcdev, id, false); | |
133 | } | |
134 | ||
10590358 AS |
135 | static const struct imx7_src_variant variant_imx7 = { |
136 | .signals = imx7_src_signals, | |
137 | .signals_num = ARRAY_SIZE(imx7_src_signals), | |
138 | .ops = { | |
139 | .assert = imx7_reset_assert, | |
140 | .deassert = imx7_reset_deassert, | |
141 | }, | |
abf97755 AS |
142 | }; |
143 | ||
c979dbf5 AS |
144 | enum imx8mq_src_registers { |
145 | SRC_A53RCR0 = 0x0004, | |
146 | SRC_HDMI_RCR = 0x0030, | |
147 | SRC_DISP_RCR = 0x0034, | |
148 | SRC_GPU_RCR = 0x0040, | |
149 | SRC_VPU_RCR = 0x0044, | |
150 | SRC_PCIE2_RCR = 0x0048, | |
151 | SRC_MIPIPHY1_RCR = 0x004c, | |
152 | SRC_MIPIPHY2_RCR = 0x0050, | |
153 | SRC_DDRC2_RCR = 0x1004, | |
154 | }; | |
155 | ||
156 | static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { | |
157 | [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, | |
158 | [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, | |
159 | [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, | |
160 | [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, | |
161 | [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, | |
162 | [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, | |
163 | [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, | |
164 | [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, | |
165 | [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, | |
166 | [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, | |
167 | [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, | |
168 | [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, | |
169 | [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, | |
170 | [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, | |
171 | [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, | |
172 | [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, | |
173 | [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, | |
174 | [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, | |
175 | [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) }, | |
176 | [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, | |
177 | [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, | |
178 | [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, | |
179 | [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, | |
180 | [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, | |
181 | [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, | |
182 | [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, | |
183 | [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, | |
184 | BIT(2) | BIT(1) }, | |
185 | [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, | |
186 | [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, | |
187 | [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, | |
188 | [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, | |
189 | [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) }, | |
190 | [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, | |
191 | [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, | |
192 | [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR, | |
193 | BIT(2) | BIT(1) }, | |
194 | [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) }, | |
195 | [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) }, | |
196 | [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) }, | |
197 | [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) }, | |
198 | [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) }, | |
199 | [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) }, | |
200 | [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) }, | |
201 | [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) }, | |
202 | [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) }, | |
203 | [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) }, | |
204 | [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) }, | |
205 | [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) }, | |
206 | [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) }, | |
207 | [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) }, | |
208 | [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, | |
209 | }; | |
210 | ||
211 | static int imx8mq_reset_set(struct reset_controller_dev *rcdev, | |
212 | unsigned long id, bool assert) | |
213 | { | |
214 | struct imx7_src *imx7src = to_imx7_src(rcdev); | |
215 | const unsigned int bit = imx7src->signals[id].bit; | |
216 | unsigned int value = assert ? bit : 0; | |
217 | ||
218 | switch (id) { | |
219 | case IMX8MQ_RESET_PCIEPHY: | |
220 | case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */ | |
221 | /* | |
222 | * wait for more than 10us to release phy g_rst and | |
223 | * btnrst | |
224 | */ | |
225 | if (!assert) | |
226 | udelay(10); | |
227 | break; | |
228 | ||
229 | case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: | |
230 | case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ | |
231 | case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */ | |
232 | case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */ | |
233 | case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */ | |
234 | case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ | |
235 | case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ | |
236 | value = assert ? 0 : bit; | |
237 | break; | |
238 | } | |
239 | ||
240 | return imx7_reset_update(imx7src, id, value); | |
241 | } | |
242 | ||
243 | static int imx8mq_reset_assert(struct reset_controller_dev *rcdev, | |
244 | unsigned long id) | |
245 | { | |
246 | return imx8mq_reset_set(rcdev, id, true); | |
247 | } | |
248 | ||
249 | static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev, | |
250 | unsigned long id) | |
251 | { | |
252 | return imx8mq_reset_set(rcdev, id, false); | |
253 | } | |
254 | ||
255 | static const struct imx7_src_variant variant_imx8mq = { | |
256 | .signals = imx8mq_src_signals, | |
257 | .signals_num = ARRAY_SIZE(imx8mq_src_signals), | |
258 | .ops = { | |
259 | .assert = imx8mq_reset_assert, | |
260 | .deassert = imx8mq_reset_deassert, | |
261 | }, | |
262 | }; | |
263 | ||
abf97755 AS |
264 | static int imx7_reset_probe(struct platform_device *pdev) |
265 | { | |
266 | struct imx7_src *imx7src; | |
267 | struct device *dev = &pdev->dev; | |
268 | struct regmap_config config = { .name = "src" }; | |
10590358 | 269 | const struct imx7_src_variant *variant = of_device_get_match_data(dev); |
abf97755 AS |
270 | |
271 | imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL); | |
272 | if (!imx7src) | |
273 | return -ENOMEM; | |
274 | ||
10590358 | 275 | imx7src->signals = variant->signals; |
abf97755 AS |
276 | imx7src->regmap = syscon_node_to_regmap(dev->of_node); |
277 | if (IS_ERR(imx7src->regmap)) { | |
278 | dev_err(dev, "Unable to get imx7-src regmap"); | |
279 | return PTR_ERR(imx7src->regmap); | |
280 | } | |
281 | regmap_attach_dev(dev, imx7src->regmap, &config); | |
282 | ||
283 | imx7src->rcdev.owner = THIS_MODULE; | |
10590358 AS |
284 | imx7src->rcdev.nr_resets = variant->signals_num; |
285 | imx7src->rcdev.ops = &variant->ops; | |
abf97755 AS |
286 | imx7src->rcdev.of_node = dev->of_node; |
287 | ||
288 | return devm_reset_controller_register(dev, &imx7src->rcdev); | |
289 | } | |
290 | ||
291 | static const struct of_device_id imx7_reset_dt_ids[] = { | |
10590358 | 292 | { .compatible = "fsl,imx7d-src", .data = &variant_imx7 }, |
c979dbf5 | 293 | { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq }, |
abf97755 AS |
294 | { /* sentinel */ }, |
295 | }; | |
296 | ||
297 | static struct platform_driver imx7_reset_driver = { | |
298 | .probe = imx7_reset_probe, | |
299 | .driver = { | |
300 | .name = KBUILD_MODNAME, | |
301 | .of_match_table = imx7_reset_dt_ids, | |
302 | }, | |
303 | }; | |
304 | builtin_platform_driver(imx7_reset_driver); |