[linux-2.6-block.git] / drivers / reset / reset-hsdk.c

/*
 * Copyright (C) 2017 Synopsys.
 *
 * Synopsys HSDK Development platform reset driver.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/types.h>

#define to_hsdk_rst(p)	container_of((p), struct hsdk_rst, rcdev)

struct hsdk_rst {
	void __iomem			*regs_ctl;
	void __iomem			*regs_rst;
	spinlock_t			lock;
	struct reset_controller_dev	rcdev;
};

static const u32 rst_map[] = {
	BIT(16), /* APB_RST  */
	BIT(17), /* AXI_RST  */
	BIT(18), /* ETH_RST  */
	BIT(19), /* USB_RST  */
	BIT(20), /* SDIO_RST */
	BIT(21), /* HDMI_RST */
	BIT(22), /* GFX_RST  */
	BIT(25), /* DMAC_RST */
	BIT(31), /* EBI_RST  */
};

#define HSDK_MAX_RESETS			ARRAY_SIZE(rst_map)

#define CGU_SYS_RST_CTRL		0x0
#define CGU_IP_SW_RESET			0x0
#define CGU_IP_SW_RESET_DELAY_SHIFT	16
#define CGU_IP_SW_RESET_DELAY_MASK	GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
#define CGU_IP_SW_RESET_DELAY		0
#define CGU_IP_SW_RESET_RESET		BIT(0)
#define SW_RESET_TIMEOUT		10000

static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
{
	writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
}

static int hsdk_reset_do(struct hsdk_rst *rst)
{
	u32 reg;

	reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
	reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
	reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
	reg |= CGU_IP_SW_RESET_RESET;
	writel(reg, rst->regs_rst + CGU_IP_SW_RESET);

	/* wait till reset bit is back to 0 */
	return readl_poll_timeout_atomic(rst->regs_rst + CGU_IP_SW_RESET, reg,
		!(reg & CGU_IP_SW_RESET_RESET), 5, SW_RESET_TIMEOUT);
}

static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
			      unsigned long id)
{
	struct hsdk_rst *rst = to_hsdk_rst(rcdev);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&rst->lock, flags);
	hsdk_reset_config(rst, id);
	ret = hsdk_reset_do(rst);
	spin_unlock_irqrestore(&rst->lock, flags);

	return ret;
}

static const struct reset_control_ops hsdk_reset_ops = {
	.reset	= hsdk_reset_reset,
	.deassert = hsdk_reset_reset,
};

static int hsdk_reset_probe(struct platform_device *pdev)
{
	struct hsdk_rst *rst;

	rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
	if (!rst)
		return -ENOMEM;

	rst->regs_ctl = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(rst->regs_ctl))
		return PTR_ERR(rst->regs_ctl);

	rst->regs_rst = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(rst->regs_rst))
		return PTR_ERR(rst->regs_rst);

	spin_lock_init(&rst->lock);

	rst->rcdev.owner = THIS_MODULE;
	rst->rcdev.ops = &hsdk_reset_ops;
	rst->rcdev.of_node = pdev->dev.of_node;
	rst->rcdev.nr_resets = HSDK_MAX_RESETS;
	rst->rcdev.of_reset_n_cells = 1;

	return reset_controller_register(&rst->rcdev);
}

static const struct of_device_id hsdk_reset_dt_match[] = {
	{ .compatible = "snps,hsdk-reset" },
	{ },
};

static struct platform_driver hsdk_reset_driver = {
	.probe	= hsdk_reset_probe,
	.driver	= {
		.name = "hsdk-reset",
		.of_match_table = hsdk_reset_dt_match,
	},
};
builtin_platform_driver(hsdk_reset_driver);

MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
MODULE_DESCRIPTION("Synopsys HSDK SDP reset driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
e0be864f EP	1	/*
	2	* Copyright (C) 2017 Synopsys.
	3	*
13541226	4	* Synopsys HSDK Development platform reset driver.
e0be864f EP	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/delay.h>
	12	#include <linux/io.h>
	13	#include <linux/iopoll.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/reset-controller.h>
	18	#include <linux/slab.h>
	19	#include <linux/types.h>
	20
13541226	21	#define to_hsdk_rst(p) container_of((p), struct hsdk_rst, rcdev)
e0be864f	22
13541226	23	struct hsdk_rst {
e0be864f EP	24	void __iomem *regs_ctl;
	25	void __iomem *regs_rst;
	26	spinlock_t lock;
	27	struct reset_controller_dev rcdev;
	28	};
	29
	30	static const u32 rst_map[] = {
	31	BIT(16), /* APB_RST */
	32	BIT(17), /* AXI_RST */
	33	BIT(18), /* ETH_RST */
	34	BIT(19), /* USB_RST */
	35	BIT(20), /* SDIO_RST */
	36	BIT(21), /* HDMI_RST */
	37	BIT(22), /* GFX_RST */
	38	BIT(25), /* DMAC_RST */
	39	BIT(31), /* EBI_RST */
	40	};
	41
	42	#define HSDK_MAX_RESETS ARRAY_SIZE(rst_map)
	43
	44	#define CGU_SYS_RST_CTRL 0x0
	45	#define CGU_IP_SW_RESET 0x0
	46	#define CGU_IP_SW_RESET_DELAY_SHIFT 16
	47	#define CGU_IP_SW_RESET_DELAY_MASK GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
	48	#define CGU_IP_SW_RESET_DELAY 0
	49	#define CGU_IP_SW_RESET_RESET BIT(0)
	50	#define SW_RESET_TIMEOUT 10000
	51
13541226	52	static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
e0be864f EP	53	{
	54	writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
	55	}
	56
13541226	57	static int hsdk_reset_do(struct hsdk_rst *rst)
e0be864f EP	58	{
	59	u32 reg;
	60
	61	reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
	62	reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
	63	reg \|= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
	64	reg \|= CGU_IP_SW_RESET_RESET;
	65	writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
	66
	67	/* wait till reset bit is back to 0 */
	68	return readl_poll_timeout_atomic(rst->regs_rst + CGU_IP_SW_RESET, reg,
	69	!(reg & CGU_IP_SW_RESET_RESET), 5, SW_RESET_TIMEOUT);
	70	}
	71
13541226	72	static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
e0be864f EP	73	unsigned long id)
e0be864f EP	74	{
13541226	75	struct hsdk_rst *rst = to_hsdk_rst(rcdev);
e0be864f EP	76	unsigned long flags;
	77	int ret;
	78
	79	spin_lock_irqsave(&rst->lock, flags);
13541226 VG	80	hsdk_reset_config(rst, id);
13541226 VG	81	ret = hsdk_reset_do(rst);
e0be864f EP	82	spin_unlock_irqrestore(&rst->lock, flags);
	83
	84	return ret;
	85	}
	86
13541226 VG	87	static const struct reset_control_ops hsdk_reset_ops = {
13541226 VG	88	.reset = hsdk_reset_reset,
42f03ab3	89	.deassert = hsdk_reset_reset,
e0be864f EP	90	};
e0be864f EP	91
13541226	92	static int hsdk_reset_probe(struct platform_device *pdev)
e0be864f	93	{
13541226	94	struct hsdk_rst *rst;
e0be864f EP	95
	96	rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
	97	if (!rst)
	98	return -ENOMEM;
	99
1d81ba35	100	rst->regs_ctl = devm_platform_ioremap_resource(pdev, 0);
e0be864f EP	101	if (IS_ERR(rst->regs_ctl))
	102	return PTR_ERR(rst->regs_ctl);
	103
1d81ba35	104	rst->regs_rst = devm_platform_ioremap_resource(pdev, 1);
e0be864f EP	105	if (IS_ERR(rst->regs_rst))
	106	return PTR_ERR(rst->regs_rst);
	107
	108	spin_lock_init(&rst->lock);
	109
	110	rst->rcdev.owner = THIS_MODULE;
13541226	111	rst->rcdev.ops = &hsdk_reset_ops;
e0be864f EP	112	rst->rcdev.of_node = pdev->dev.of_node;
	113	rst->rcdev.nr_resets = HSDK_MAX_RESETS;
	114	rst->rcdev.of_reset_n_cells = 1;
	115
	116	return reset_controller_register(&rst->rcdev);
	117	}
	118
13541226 VG	119	static const struct of_device_id hsdk_reset_dt_match[] = {
13541226 VG	120	{ .compatible = "snps,hsdk-reset" },
e0be864f EP	121	{ },
	122	};
	123
13541226 VG	124	static struct platform_driver hsdk_reset_driver = {
13541226 VG	125	.probe = hsdk_reset_probe,
e0be864f	126	.driver = {
13541226 VG	127	.name = "hsdk-reset",
13541226 VG	128	.of_match_table = hsdk_reset_dt_match,
e0be864f EP	129	},
e0be864f EP	130	};
13541226	131	builtin_platform_driver(hsdk_reset_driver);
e0be864f EP	132
e0be864f EP	133	MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
13541226	134	MODULE_DESCRIPTION("Synopsys HSDK SDP reset driver");
e0be864f	135	MODULE_LICENSE("GPL v2");