Commit | Line | Data |
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61fc4131 PZ |
1 | config ARCH_HAS_RESET_CONTROLLER |
2 | bool | |
3 | ||
4 | menuconfig RESET_CONTROLLER | |
5 | bool "Reset Controller Support" | |
6 | default y if ARCH_HAS_RESET_CONTROLLER | |
7 | help | |
8 | Generic Reset Controller support. | |
9 | ||
10 | This framework is designed to abstract reset handling of devices | |
11 | via GPIOs or SoC-internal reset controller modules. | |
12 | ||
13 | If unsure, say no. | |
e5d76075 | 14 | |
998cd463 MY |
15 | if RESET_CONTROLLER |
16 | ||
62700682 TT |
17 | config RESET_A10SR |
18 | tristate "Altera Arria10 System Resource Reset" | |
19 | depends on MFD_ALTERA_A10SR | |
20 | help | |
21 | This option enables support for the external reset functions for | |
22 | peripheral PHYs on the Altera Arria10 System Resource Chip. | |
23 | ||
e27b4a6e PZ |
24 | config RESET_ATH79 |
25 | bool "AR71xx Reset Driver" if COMPILE_TEST | |
26 | default ATH79 | |
27 | help | |
28 | This enables the ATH79 reset controller driver that supports the | |
29 | AR71xx SoC reset controller. | |
30 | ||
37634923 EP |
31 | config RESET_AXS10X |
32 | bool "AXS10x Reset Driver" if COMPILE_TEST | |
33 | default ARC_PLAT_AXS10X | |
34 | help | |
35 | This enables the reset controller driver for AXS10x. | |
36 | ||
70d467ea PZ |
37 | config RESET_BERLIN |
38 | bool "Berlin Reset Driver" if COMPILE_TEST | |
39 | default ARCH_BERLIN | |
40 | help | |
41 | This enables the reset controller driver for Marvell Berlin SoCs. | |
42 | ||
13541226 VG |
43 | config RESET_HSDK |
44 | bool "Synopsys HSDK Reset Driver" | |
2d48a237 | 45 | depends on HAS_IOMEM |
544e3bf4 | 46 | depends on ARC_SOC_HSDK || COMPILE_TEST |
e0be864f | 47 | help |
13541226 | 48 | This enables the reset controller driver for HSDK board. |
e0be864f | 49 | |
abf97755 AS |
50 | config RESET_IMX7 |
51 | bool "i.MX7 Reset Driver" if COMPILE_TEST | |
8fa56620 | 52 | depends on HAS_IOMEM |
abf97755 AS |
53 | default SOC_IMX7D |
54 | select MFD_SYSCON | |
55 | help | |
56 | This enables the reset controller driver for i.MX7 SoCs. | |
57 | ||
79797b6f MB |
58 | config RESET_LANTIQ |
59 | bool "Lantiq XWAY Reset Driver" if COMPILE_TEST | |
60 | default SOC_TYPE_XWAY | |
61 | help | |
62 | This enables the reset controller driver for Lantiq / Intel XWAY SoCs. | |
63 | ||
cd7f4b81 PZ |
64 | config RESET_LPC18XX |
65 | bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST | |
66 | default ARCH_LPC18XX | |
67 | help | |
68 | This enables the reset controller driver for NXP LPC18xx/43xx SoCs. | |
69 | ||
44336c24 PZ |
70 | config RESET_MESON |
71 | bool "Meson Reset Driver" if COMPILE_TEST | |
72 | default ARCH_MESON | |
73 | help | |
74 | This enables the reset driver for Amlogic Meson SoCs. | |
75 | ||
d903779b JB |
76 | config RESET_MESON_AUDIO_ARB |
77 | tristate "Meson Audio Memory Arbiter Reset Driver" | |
78 | depends on ARCH_MESON || COMPILE_TEST | |
79 | help | |
80 | This enables the reset driver for Audio Memory Arbiter of | |
81 | Amlogic's A113 based SoCs | |
82 | ||
6e667fac NA |
83 | config RESET_OXNAS |
84 | bool | |
85 | ||
fab3f730 PZ |
86 | config RESET_PISTACHIO |
87 | bool "Pistachio Reset Driver" if COMPILE_TEST | |
88 | default MACH_PISTACHIO | |
89 | help | |
90 | This enables the reset driver for ImgTec Pistachio SoCs. | |
91 | ||
5ecb0651 SS |
92 | config RESET_QCOM_AOSS |
93 | bool "Qcom AOSS Reset Driver" | |
94 | depends on ARCH_QCOM || COMPILE_TEST | |
95 | help | |
96 | This enables the AOSS (always on subsystem) reset driver | |
97 | for Qualcomm SDM845 SoCs. Say Y if you want to control | |
98 | reset signals provided by AOSS for Modem, Venus, ADSP, | |
99 | GPU, Camera, Wireless, Display subsystem. Otherwise, say N. | |
100 | ||
eea2926b SS |
101 | config RESET_QCOM_PDC |
102 | tristate "Qualcomm PDC Reset Driver" | |
103 | depends on ARCH_QCOM || COMPILE_TEST | |
104 | help | |
105 | This enables the PDC (Power Domain Controller) reset driver | |
106 | for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want | |
107 | to control reset signals provided by PDC for Modem, Compute, | |
108 | Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. | |
109 | ||
81c22ad0 PZ |
110 | config RESET_SIMPLE |
111 | bool "Simple Reset Controller Driver" if COMPILE_TEST | |
1d7592f8 | 112 | default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED |
81c22ad0 PZ |
113 | help |
114 | This enables a simple reset controller driver for reset lines that | |
115 | that can be asserted and deasserted by toggling bits in a contiguous, | |
116 | exclusive register space. | |
117 | ||
1d7592f8 JS |
118 | Currently this driver supports: |
119 | - Altera SoCFPGAs | |
120 | - ASPEED BMC SoCs | |
121 | - RCC reset controller in STM32 MCUs | |
122 | - Allwinner SoCs | |
123 | - ZTE's zx2967 family | |
7e0e901d | 124 | |
197858b6 GF |
125 | config RESET_STM32MP157 |
126 | bool "STM32MP157 Reset Driver" if COMPILE_TEST | |
127 | default MACH_STM32MP157 | |
128 | help | |
129 | This enables the RCC reset controller driver for STM32 MPUs. | |
130 | ||
0ae08419 PZ |
131 | config RESET_SUNXI |
132 | bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI | |
133 | default ARCH_SUNXI | |
e13c205a | 134 | select RESET_SIMPLE |
0ae08419 PZ |
135 | help |
136 | This enables the reset driver for Allwinner SoCs. | |
137 | ||
28df169b AD |
138 | config RESET_TI_SCI |
139 | tristate "TI System Control Interface (TI-SCI) reset driver" | |
140 | depends on TI_SCI_PROTOCOL | |
141 | help | |
142 | This enables the reset driver support over TI System Control Interface | |
143 | available on some new TI's SoCs. If you wish to use reset resources | |
144 | managed by the TI System Controller, say Y here. Otherwise, say N. | |
145 | ||
dd9bf863 | 146 | config RESET_TI_SYSCON |
cc7c2bb1 AD |
147 | tristate "TI SYSCON Reset Driver" |
148 | depends on HAS_IOMEM | |
149 | select MFD_SYSCON | |
150 | help | |
151 | This enables the reset driver support for TI devices with | |
152 | memory-mapped reset registers as part of a syscon device node. If | |
153 | you wish to use the reset framework for such memory-mapped devices, | |
154 | say Y here. Otherwise, say N. | |
155 | ||
54e991b5 MY |
156 | config RESET_UNIPHIER |
157 | tristate "Reset controller driver for UniPhier SoCs" | |
158 | depends on ARCH_UNIPHIER || COMPILE_TEST | |
159 | depends on OF && MFD_SYSCON | |
160 | default ARCH_UNIPHIER | |
161 | help | |
162 | Support for reset controllers on UniPhier SoCs. | |
163 | Say Y if you want to control reset signals provided by System Control | |
164 | block, Media I/O block, Peripheral Block. | |
165 | ||
499fef09 KH |
166 | config RESET_UNIPHIER_USB3 |
167 | tristate "USB3 reset driver for UniPhier SoCs" | |
168 | depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF | |
169 | default ARCH_UNIPHIER | |
170 | select RESET_SIMPLE | |
171 | help | |
172 | Support for the USB3 core reset on UniPhier SoCs. | |
173 | Say Y if you want to control reset signals provided by | |
174 | USB3 glue layer. | |
175 | ||
6f51b860 PZ |
176 | config RESET_ZYNQ |
177 | bool "ZYNQ Reset Driver" if COMPILE_TEST | |
178 | default ARCH_ZYNQ | |
179 | help | |
180 | This enables the reset controller driver for Xilinx Zynq SoCs. | |
181 | ||
e5d76075 | 182 | source "drivers/reset/sti/Kconfig" |
f59d23c2 | 183 | source "drivers/reset/hisilicon/Kconfig" |
dc606c52 | 184 | source "drivers/reset/tegra/Kconfig" |
998cd463 MY |
185 | |
186 | endif |