Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
61fc4131 PZ |
2 | config ARCH_HAS_RESET_CONTROLLER |
3 | bool | |
4 | ||
5 | menuconfig RESET_CONTROLLER | |
6 | bool "Reset Controller Support" | |
7 | default y if ARCH_HAS_RESET_CONTROLLER | |
8 | help | |
9 | Generic Reset Controller support. | |
10 | ||
11 | This framework is designed to abstract reset handling of devices | |
12 | via GPIOs or SoC-internal reset controller modules. | |
13 | ||
14 | If unsure, say no. | |
e5d76075 | 15 | |
998cd463 MY |
16 | if RESET_CONTROLLER |
17 | ||
62700682 TT |
18 | config RESET_A10SR |
19 | tristate "Altera Arria10 System Resource Reset" | |
20 | depends on MFD_ALTERA_A10SR | |
21 | help | |
22 | This option enables support for the external reset functions for | |
23 | peripheral PHYs on the Altera Arria10 System Resource Chip. | |
24 | ||
e27b4a6e PZ |
25 | config RESET_ATH79 |
26 | bool "AR71xx Reset Driver" if COMPILE_TEST | |
27 | default ATH79 | |
28 | help | |
29 | This enables the ATH79 reset controller driver that supports the | |
30 | AR71xx SoC reset controller. | |
31 | ||
37634923 EP |
32 | config RESET_AXS10X |
33 | bool "AXS10x Reset Driver" if COMPILE_TEST | |
34 | default ARC_PLAT_AXS10X | |
35 | help | |
36 | This enables the reset controller driver for AXS10x. | |
37 | ||
aac02543 ÁFR |
38 | config RESET_BCM6345 |
39 | bool "BCM6345 Reset Controller" | |
40 | depends on BMIPS_GENERIC || COMPILE_TEST | |
41 | default BMIPS_GENERIC | |
42 | help | |
43 | This enables the reset controller driver for BCM6345 SoCs. | |
44 | ||
70d467ea | 45 | config RESET_BERLIN |
5e787cdf JZ |
46 | tristate "Berlin Reset Driver" |
47 | depends on ARCH_BERLIN || COMPILE_TEST | |
48 | default m if ARCH_BERLIN | |
70d467ea PZ |
49 | help |
50 | This enables the reset controller driver for Marvell Berlin SoCs. | |
51 | ||
77750bc0 FF |
52 | config RESET_BRCMSTB |
53 | tristate "Broadcom STB reset controller" | |
54 | depends on ARCH_BRCMSTB || COMPILE_TEST | |
55 | default ARCH_BRCMSTB | |
56 | help | |
57 | This enables the reset controller driver for Broadcom STB SoCs using | |
58 | a SUN_TOP_CTRL_SW_INIT style controller. | |
59 | ||
4cf176e5 | 60 | config RESET_BRCMSTB_RESCAL |
5694ca29 | 61 | tristate "Broadcom STB RESCAL reset controller" |
7fbcc535 | 62 | depends on HAS_IOMEM |
42f6a76f GU |
63 | depends on ARCH_BRCMSTB || COMPILE_TEST |
64 | default ARCH_BRCMSTB | |
4cf176e5 JQ |
65 | help |
66 | This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on | |
67 | BCM7216. | |
68 | ||
13541226 VG |
69 | config RESET_HSDK |
70 | bool "Synopsys HSDK Reset Driver" | |
2d48a237 | 71 | depends on HAS_IOMEM |
544e3bf4 | 72 | depends on ARC_SOC_HSDK || COMPILE_TEST |
e0be864f | 73 | help |
13541226 | 74 | This enables the reset controller driver for HSDK board. |
e0be864f | 75 | |
abf97755 | 76 | config RESET_IMX7 |
a442abbb | 77 | tristate "i.MX7/8 Reset Driver" |
8fa56620 | 78 | depends on HAS_IOMEM |
a442abbb AH |
79 | depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST |
80 | default y if SOC_IMX7D | |
abf97755 AS |
81 | select MFD_SYSCON |
82 | help | |
83 | This enables the reset controller driver for i.MX7 SoCs. | |
84 | ||
c9aef213 DK |
85 | config RESET_INTEL_GW |
86 | bool "Intel Reset Controller Driver" | |
6ab9d621 | 87 | depends on X86 || COMPILE_TEST |
b460e0a9 | 88 | depends on OF && HAS_IOMEM |
c9aef213 DK |
89 | select REGMAP_MMIO |
90 | help | |
91 | This enables the reset controller driver for Intel Gateway SoCs. | |
92 | Say Y to control the reset signals provided by reset controller. | |
93 | Otherwise, say N. | |
94 | ||
5a2308da DLM |
95 | config RESET_K210 |
96 | bool "Reset controller driver for Canaan Kendryte K210 SoC" | |
97 | depends on (SOC_CANAAN || COMPILE_TEST) && OF | |
98 | select MFD_SYSCON | |
99 | default SOC_CANAAN | |
100 | help | |
101 | Support for the Canaan Kendryte K210 RISC-V SoC reset controller. | |
102 | Say Y if you want to control reset signals provided by this | |
103 | controller. | |
104 | ||
79797b6f MB |
105 | config RESET_LANTIQ |
106 | bool "Lantiq XWAY Reset Driver" if COMPILE_TEST | |
107 | default SOC_TYPE_XWAY | |
108 | help | |
109 | This enables the reset controller driver for Lantiq / Intel XWAY SoCs. | |
110 | ||
cd7f4b81 PZ |
111 | config RESET_LPC18XX |
112 | bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST | |
113 | default ARCH_LPC18XX | |
114 | help | |
115 | This enables the reset controller driver for NXP LPC18xx/43xx SoCs. | |
116 | ||
453ed428 SH |
117 | config RESET_MCHP_SPARX5 |
118 | bool "Microchip Sparx5 reset driver" | |
8c81620a | 119 | depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST |
453ed428 SH |
120 | default y if SPARX5_SWITCH |
121 | select MFD_SYSCON | |
122 | help | |
123 | This driver supports switch core reset for the Microchip Sparx5 SoC. | |
124 | ||
44336c24 | 125 | config RESET_MESON |
3bfe8933 NA |
126 | tristate "Meson Reset Driver" |
127 | depends on ARCH_MESON || COMPILE_TEST | |
44336c24 PZ |
128 | default ARCH_MESON |
129 | help | |
130 | This enables the reset driver for Amlogic Meson SoCs. | |
131 | ||
d903779b JB |
132 | config RESET_MESON_AUDIO_ARB |
133 | tristate "Meson Audio Memory Arbiter Reset Driver" | |
134 | depends on ARCH_MESON || COMPILE_TEST | |
135 | help | |
136 | This enables the reset driver for Audio Memory Arbiter of | |
137 | Amlogic's A113 based SoCs | |
138 | ||
9c81b2cc TM |
139 | config RESET_NPCM |
140 | bool "NPCM BMC Reset Driver" if COMPILE_TEST | |
141 | default ARCH_NPCM | |
142 | help | |
143 | This enables the reset controller driver for Nuvoton NPCM | |
144 | BMC SoCs. | |
145 | ||
6e667fac NA |
146 | config RESET_OXNAS |
147 | bool | |
148 | ||
fab3f730 | 149 | config RESET_PISTACHIO |
4af16070 GU |
150 | bool "Pistachio Reset Driver" |
151 | depends on MIPS || COMPILE_TEST | |
fab3f730 PZ |
152 | help |
153 | This enables the reset driver for ImgTec Pistachio SoCs. | |
154 | ||
5ecb0651 | 155 | config RESET_QCOM_AOSS |
e2d5e833 | 156 | tristate "Qcom AOSS Reset Driver" |
5ecb0651 SS |
157 | depends on ARCH_QCOM || COMPILE_TEST |
158 | help | |
159 | This enables the AOSS (always on subsystem) reset driver | |
160 | for Qualcomm SDM845 SoCs. Say Y if you want to control | |
161 | reset signals provided by AOSS for Modem, Venus, ADSP, | |
162 | GPU, Camera, Wireless, Display subsystem. Otherwise, say N. | |
163 | ||
eea2926b SS |
164 | config RESET_QCOM_PDC |
165 | tristate "Qualcomm PDC Reset Driver" | |
166 | depends on ARCH_QCOM || COMPILE_TEST | |
167 | help | |
168 | This enables the PDC (Power Domain Controller) reset driver | |
169 | for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want | |
170 | to control reset signals provided by PDC for Modem, Compute, | |
171 | Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS. | |
172 | ||
abffc82a NSJ |
173 | config RESET_RASPBERRYPI |
174 | tristate "Raspberry Pi 4 Firmware Reset Driver" | |
175 | depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST) | |
176 | default USB_XHCI_PCI | |
177 | help | |
178 | Raspberry Pi 4's co-processor controls some of the board's HW | |
179 | initialization process, but it's up to Linux to trigger it when | |
180 | relevant. This driver provides a reset controller capable of | |
181 | interfacing with RPi4's co-processor and model these firmware | |
182 | initialization routines as reset lines. | |
183 | ||
bee08559 BD |
184 | config RESET_RZG2L_USBPHY_CTRL |
185 | tristate "Renesas RZ/G2L USBPHY control driver" | |
9fe7dd4e | 186 | depends on ARCH_RZG2L || COMPILE_TEST |
bee08559 BD |
187 | help |
188 | Support for USBPHY Control found on RZ/G2L family. It mainly | |
189 | controls reset and power down of the USB/PHY. | |
190 | ||
c8ae9c2d SH |
191 | config RESET_SCMI |
192 | tristate "Reset driver controlled via ARM SCMI interface" | |
193 | depends on ARM_SCMI_PROTOCOL || COMPILE_TEST | |
194 | default ARM_SCMI_PROTOCOL | |
195 | help | |
196 | This driver provides support for reset signal/domains that are | |
197 | controlled by firmware that implements the SCMI interface. | |
198 | ||
199 | This driver uses SCMI Message Protocol to interact with the | |
200 | firmware controlling all the reset signals. | |
201 | ||
81c22ad0 PZ |
202 | config RESET_SIMPLE |
203 | bool "Simple Reset Controller Driver" if COMPILE_TEST | |
4a9a1a56 | 204 | default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC |
81c22ad0 PZ |
205 | help |
206 | This enables a simple reset controller driver for reset lines that | |
207 | that can be asserted and deasserted by toggling bits in a contiguous, | |
208 | exclusive register space. | |
209 | ||
1d7592f8 JS |
210 | Currently this driver supports: |
211 | - Altera SoCFPGAs | |
212 | - ASPEED BMC SoCs | |
5ac33eeb | 213 | - Bitmain BM1880 SoC |
3ab831e5 | 214 | - Realtek SoCs |
1d7592f8 JS |
215 | - RCC reset controller in STM32 MCUs |
216 | - Allwinner SoCs | |
e4d368e0 | 217 | - SiFive FU740 SoCs |
7e0e901d | 218 | |
b3ca9888 | 219 | config RESET_SOCFPGA |
225c13f0 KK |
220 | bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) |
221 | default ARM && ARCH_INTEL_SOCFPGA | |
b3ca9888 DN |
222 | select RESET_SIMPLE |
223 | help | |
224 | This enables the reset driver for the SoCFPGA ARMv7 platforms. This | |
225 | driver gets initialized early during platform init calls. | |
226 | ||
0be3a159 ERB |
227 | config RESET_STARFIVE_JH7100 |
228 | bool "StarFive JH7100 Reset Driver" | |
229 | depends on SOC_STARFIVE || COMPILE_TEST | |
230 | default SOC_STARFIVE | |
231 | help | |
232 | This enables the reset controller driver for the StarFive JH7100 SoC. | |
233 | ||
0ae08419 PZ |
234 | config RESET_SUNXI |
235 | bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI | |
236 | default ARCH_SUNXI | |
e13c205a | 237 | select RESET_SIMPLE |
0ae08419 PZ |
238 | help |
239 | This enables the reset driver for Allwinner SoCs. | |
240 | ||
28df169b AD |
241 | config RESET_TI_SCI |
242 | tristate "TI System Control Interface (TI-SCI) reset driver" | |
a6af5041 | 243 | depends on TI_SCI_PROTOCOL || COMPILE_TEST |
28df169b AD |
244 | help |
245 | This enables the reset driver support over TI System Control Interface | |
246 | available on some new TI's SoCs. If you wish to use reset resources | |
247 | managed by the TI System Controller, say Y here. Otherwise, say N. | |
248 | ||
dd9bf863 | 249 | config RESET_TI_SYSCON |
cc7c2bb1 AD |
250 | tristate "TI SYSCON Reset Driver" |
251 | depends on HAS_IOMEM | |
252 | select MFD_SYSCON | |
253 | help | |
254 | This enables the reset driver support for TI devices with | |
255 | memory-mapped reset registers as part of a syscon device node. If | |
256 | you wish to use the reset framework for such memory-mapped devices, | |
257 | say Y here. Otherwise, say N. | |
258 | ||
5cd3921d RM |
259 | config RESET_TN48M_CPLD |
260 | tristate "Delta Networks TN48M switch CPLD reset controller" | |
261 | depends on MFD_TN48M_CPLD || COMPILE_TEST | |
262 | default MFD_TN48M_CPLD | |
263 | help | |
264 | This enables the reset controller driver for the Delta TN48M CPLD. | |
265 | It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X | |
266 | switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and | |
267 | Microchip PD69200 PoE PSE controller. | |
268 | ||
269 | This driver can also be built as a module. If so, the module will be | |
270 | called reset-tn48m. | |
271 | ||
54e991b5 MY |
272 | config RESET_UNIPHIER |
273 | tristate "Reset controller driver for UniPhier SoCs" | |
274 | depends on ARCH_UNIPHIER || COMPILE_TEST | |
275 | depends on OF && MFD_SYSCON | |
276 | default ARCH_UNIPHIER | |
277 | help | |
278 | Support for reset controllers on UniPhier SoCs. | |
279 | Say Y if you want to control reset signals provided by System Control | |
280 | block, Media I/O block, Peripheral Block. | |
281 | ||
3eb8f765 KH |
282 | config RESET_UNIPHIER_GLUE |
283 | tristate "Reset driver in glue layer for UniPhier SoCs" | |
499fef09 KH |
284 | depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF |
285 | default ARCH_UNIPHIER | |
286 | select RESET_SIMPLE | |
287 | help | |
3eb8f765 KH |
288 | Support for peripheral core reset included in its own glue layer |
289 | on UniPhier SoCs. Say Y if you want to control reset signals | |
290 | provided by the glue layer. | |
499fef09 | 291 | |
6f51b860 PZ |
292 | config RESET_ZYNQ |
293 | bool "ZYNQ Reset Driver" if COMPILE_TEST | |
294 | default ARCH_ZYNQ | |
295 | help | |
296 | This enables the reset controller driver for Xilinx Zynq SoCs. | |
297 | ||
e5d76075 | 298 | source "drivers/reset/sti/Kconfig" |
f59d23c2 | 299 | source "drivers/reset/hisilicon/Kconfig" |
dc606c52 | 300 | source "drivers/reset/tegra/Kconfig" |
998cd463 MY |
301 | |
302 | endif |