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6dedbd1d SA |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * TI K3 R5F (MCU) Remote Processor driver | |
4 | * | |
e3865c85 | 5 | * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/ |
6dedbd1d SA |
6 | * Suman Anna <s-anna@ti.com> |
7 | */ | |
8 | ||
9 | #include <linux/dma-mapping.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/mailbox_client.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_device.h> | |
17 | #include <linux/of_reserved_mem.h> | |
18 | #include <linux/omap-mailbox.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/pm_runtime.h> | |
21 | #include <linux/remoteproc.h> | |
22 | #include <linux/reset.h> | |
23 | #include <linux/slab.h> | |
24 | ||
25 | #include "omap_remoteproc.h" | |
26 | #include "remoteproc_internal.h" | |
27 | #include "ti_sci_proc.h" | |
28 | ||
29 | /* This address can either be for ATCM or BTCM with the other at address 0x0 */ | |
30 | #define K3_R5_TCM_DEV_ADDR 0x41010000 | |
31 | ||
32 | /* R5 TI-SCI Processor Configuration Flags */ | |
33 | #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001 | |
34 | #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002 | |
35 | #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100 | |
36 | #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200 | |
37 | #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400 | |
38 | #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800 | |
39 | #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000 | |
40 | #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000 | |
7508ea19 SA |
41 | /* Available from J7200 SoCs onwards */ |
42 | #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000 | |
ee99ee7c SA |
43 | /* Applicable to only AM64x SoCs */ |
44 | #define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000 | |
6dedbd1d SA |
45 | |
46 | /* R5 TI-SCI Processor Control Flags */ | |
47 | #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 | |
48 | ||
49 | /* R5 TI-SCI Processor Status Flags */ | |
50 | #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001 | |
51 | #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 | |
52 | #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004 | |
53 | #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100 | |
ee99ee7c SA |
54 | /* Applicable to only AM64x SoCs */ |
55 | #define PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY 0x00000200 | |
6dedbd1d SA |
56 | |
57 | /** | |
58 | * struct k3_r5_mem - internal memory structure | |
59 | * @cpu_addr: MPU virtual address of the memory region | |
60 | * @bus_addr: Bus address used to access the memory region | |
61 | * @dev_addr: Device address from remoteproc view | |
62 | * @size: Size of the memory region | |
63 | */ | |
64 | struct k3_r5_mem { | |
65 | void __iomem *cpu_addr; | |
66 | phys_addr_t bus_addr; | |
67 | u32 dev_addr; | |
68 | size_t size; | |
69 | }; | |
70 | ||
ee99ee7c SA |
71 | /* |
72 | * All cluster mode values are not applicable on all SoCs. The following | |
73 | * are the modes supported on various SoCs: | |
51723657 DT |
74 | * Split mode : AM65x, J721E, J7200 and AM64x SoCs |
75 | * LockStep mode : AM65x, J721E and J7200 SoCs | |
76 | * Single-CPU mode : AM64x SoCs only | |
77 | * Single-Core mode : AM62x, AM62A SoCs | |
ee99ee7c | 78 | */ |
6dedbd1d SA |
79 | enum cluster_mode { |
80 | CLUSTER_MODE_SPLIT = 0, | |
81 | CLUSTER_MODE_LOCKSTEP, | |
ee99ee7c | 82 | CLUSTER_MODE_SINGLECPU, |
51723657 | 83 | CLUSTER_MODE_SINGLECORE |
6dedbd1d SA |
84 | }; |
85 | ||
7508ea19 SA |
86 | /** |
87 | * struct k3_r5_soc_data - match data to handle SoC variations | |
c3c21b35 | 88 | * @tcm_is_double: flag to denote the larger unified TCMs in certain modes |
7508ea19 | 89 | * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC |
ee99ee7c | 90 | * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode |
51723657 | 91 | * @is_single_core: flag to denote if SoC/IP has only single core R5 |
7508ea19 SA |
92 | */ |
93 | struct k3_r5_soc_data { | |
c3c21b35 | 94 | bool tcm_is_double; |
7508ea19 | 95 | bool tcm_ecc_autoinit; |
ee99ee7c | 96 | bool single_cpu_mode; |
51723657 | 97 | bool is_single_core; |
7508ea19 SA |
98 | }; |
99 | ||
6dedbd1d SA |
100 | /** |
101 | * struct k3_r5_cluster - K3 R5F Cluster structure | |
102 | * @dev: cached device pointer | |
103 | * @mode: Mode to configure the Cluster - Split or LockStep | |
104 | * @cores: list of R5 cores within the cluster | |
7508ea19 | 105 | * @soc_data: SoC-specific feature data for a R5FSS |
6dedbd1d SA |
106 | */ |
107 | struct k3_r5_cluster { | |
108 | struct device *dev; | |
109 | enum cluster_mode mode; | |
110 | struct list_head cores; | |
7508ea19 | 111 | const struct k3_r5_soc_data *soc_data; |
6dedbd1d SA |
112 | }; |
113 | ||
114 | /** | |
115 | * struct k3_r5_core - K3 R5 core structure | |
116 | * @elem: linked list item | |
117 | * @dev: cached device pointer | |
118 | * @rproc: rproc handle representing this core | |
119 | * @mem: internal memory regions data | |
ea47c688 | 120 | * @sram: on-chip SRAM memory regions data |
6dedbd1d | 121 | * @num_mems: number of internal memory regions |
ea47c688 | 122 | * @num_sram: number of on-chip SRAM memory regions |
6dedbd1d SA |
123 | * @reset: reset control handle |
124 | * @tsp: TI-SCI processor control handle | |
125 | * @ti_sci: TI-SCI handle | |
126 | * @ti_sci_id: TI-SCI device identifier | |
127 | * @atcm_enable: flag to control ATCM enablement | |
128 | * @btcm_enable: flag to control BTCM enablement | |
129 | * @loczrama: flag to dictate which TCM is at device address 0x0 | |
130 | */ | |
131 | struct k3_r5_core { | |
132 | struct list_head elem; | |
133 | struct device *dev; | |
134 | struct rproc *rproc; | |
135 | struct k3_r5_mem *mem; | |
ea47c688 | 136 | struct k3_r5_mem *sram; |
6dedbd1d | 137 | int num_mems; |
ea47c688 | 138 | int num_sram; |
6dedbd1d SA |
139 | struct reset_control *reset; |
140 | struct ti_sci_proc *tsp; | |
141 | const struct ti_sci_handle *ti_sci; | |
142 | u32 ti_sci_id; | |
143 | u32 atcm_enable; | |
144 | u32 btcm_enable; | |
145 | u32 loczrama; | |
146 | }; | |
147 | ||
148 | /** | |
149 | * struct k3_r5_rproc - K3 remote processor state | |
150 | * @dev: cached device pointer | |
151 | * @cluster: cached pointer to parent cluster structure | |
152 | * @mbox: mailbox channel handle | |
153 | * @client: mailbox client to request the mailbox channel | |
154 | * @rproc: rproc handle | |
155 | * @core: cached pointer to r5 core structure being used | |
156 | * @rmem: reserved memory regions data | |
157 | * @num_rmems: number of reserved memory regions | |
158 | */ | |
159 | struct k3_r5_rproc { | |
160 | struct device *dev; | |
161 | struct k3_r5_cluster *cluster; | |
162 | struct mbox_chan *mbox; | |
163 | struct mbox_client client; | |
164 | struct rproc *rproc; | |
165 | struct k3_r5_core *core; | |
166 | struct k3_r5_mem *rmem; | |
167 | int num_rmems; | |
168 | }; | |
169 | ||
170 | /** | |
171 | * k3_r5_rproc_mbox_callback() - inbound mailbox message handler | |
172 | * @client: mailbox client pointer used for requesting the mailbox channel | |
173 | * @data: mailbox payload | |
174 | * | |
175 | * This handler is invoked by the OMAP mailbox driver whenever a mailbox | |
176 | * message is received. Usually, the mailbox payload simply contains | |
177 | * the index of the virtqueue that is kicked by the remote processor, | |
178 | * and we let remoteproc core handle it. | |
179 | * | |
180 | * In addition to virtqueue indices, we also have some out-of-band values | |
181 | * that indicate different events. Those values are deliberately very | |
182 | * large so they don't coincide with virtqueue indices. | |
183 | */ | |
184 | static void k3_r5_rproc_mbox_callback(struct mbox_client *client, void *data) | |
185 | { | |
186 | struct k3_r5_rproc *kproc = container_of(client, struct k3_r5_rproc, | |
187 | client); | |
188 | struct device *dev = kproc->rproc->dev.parent; | |
189 | const char *name = kproc->rproc->name; | |
190 | u32 msg = omap_mbox_message(data); | |
191 | ||
192 | dev_dbg(dev, "mbox msg: 0x%x\n", msg); | |
193 | ||
194 | switch (msg) { | |
195 | case RP_MBOX_CRASH: | |
196 | /* | |
197 | * remoteproc detected an exception, but error recovery is not | |
198 | * supported. So, just log this for now | |
199 | */ | |
200 | dev_err(dev, "K3 R5F rproc %s crashed\n", name); | |
201 | break; | |
202 | case RP_MBOX_ECHO_REPLY: | |
203 | dev_info(dev, "received echo reply from %s\n", name); | |
204 | break; | |
205 | default: | |
206 | /* silently handle all other valid messages */ | |
207 | if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG) | |
208 | return; | |
209 | if (msg > kproc->rproc->max_notifyid) { | |
210 | dev_dbg(dev, "dropping unknown message 0x%x", msg); | |
211 | return; | |
212 | } | |
213 | /* msg contains the index of the triggered vring */ | |
214 | if (rproc_vq_interrupt(kproc->rproc, msg) == IRQ_NONE) | |
215 | dev_dbg(dev, "no message was found in vqid %d\n", msg); | |
216 | } | |
217 | } | |
218 | ||
219 | /* kick a virtqueue */ | |
220 | static void k3_r5_rproc_kick(struct rproc *rproc, int vqid) | |
221 | { | |
222 | struct k3_r5_rproc *kproc = rproc->priv; | |
223 | struct device *dev = rproc->dev.parent; | |
224 | mbox_msg_t msg = (mbox_msg_t)vqid; | |
225 | int ret; | |
226 | ||
227 | /* send the index of the triggered virtqueue in the mailbox payload */ | |
228 | ret = mbox_send_message(kproc->mbox, (void *)msg); | |
229 | if (ret < 0) | |
230 | dev_err(dev, "failed to send mailbox message, status = %d\n", | |
231 | ret); | |
232 | } | |
233 | ||
234 | static int k3_r5_split_reset(struct k3_r5_core *core) | |
235 | { | |
236 | int ret; | |
237 | ||
238 | ret = reset_control_assert(core->reset); | |
239 | if (ret) { | |
240 | dev_err(core->dev, "local-reset assert failed, ret = %d\n", | |
241 | ret); | |
242 | return ret; | |
243 | } | |
244 | ||
245 | ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci, | |
246 | core->ti_sci_id); | |
247 | if (ret) { | |
248 | dev_err(core->dev, "module-reset assert failed, ret = %d\n", | |
249 | ret); | |
250 | if (reset_control_deassert(core->reset)) | |
251 | dev_warn(core->dev, "local-reset deassert back failed\n"); | |
252 | } | |
253 | ||
254 | return ret; | |
255 | } | |
256 | ||
257 | static int k3_r5_split_release(struct k3_r5_core *core) | |
258 | { | |
259 | int ret; | |
260 | ||
261 | ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci, | |
262 | core->ti_sci_id); | |
263 | if (ret) { | |
264 | dev_err(core->dev, "module-reset deassert failed, ret = %d\n", | |
265 | ret); | |
266 | return ret; | |
267 | } | |
268 | ||
269 | ret = reset_control_deassert(core->reset); | |
270 | if (ret) { | |
271 | dev_err(core->dev, "local-reset deassert failed, ret = %d\n", | |
272 | ret); | |
273 | if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci, | |
274 | core->ti_sci_id)) | |
275 | dev_warn(core->dev, "module-reset assert back failed\n"); | |
276 | } | |
277 | ||
278 | return ret; | |
279 | } | |
280 | ||
281 | static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster) | |
282 | { | |
283 | struct k3_r5_core *core; | |
284 | int ret; | |
285 | ||
286 | /* assert local reset on all applicable cores */ | |
287 | list_for_each_entry(core, &cluster->cores, elem) { | |
288 | ret = reset_control_assert(core->reset); | |
289 | if (ret) { | |
290 | dev_err(core->dev, "local-reset assert failed, ret = %d\n", | |
291 | ret); | |
292 | core = list_prev_entry(core, elem); | |
293 | goto unroll_local_reset; | |
294 | } | |
295 | } | |
296 | ||
297 | /* disable PSC modules on all applicable cores */ | |
298 | list_for_each_entry(core, &cluster->cores, elem) { | |
299 | ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci, | |
300 | core->ti_sci_id); | |
301 | if (ret) { | |
302 | dev_err(core->dev, "module-reset assert failed, ret = %d\n", | |
303 | ret); | |
304 | goto unroll_module_reset; | |
305 | } | |
306 | } | |
307 | ||
308 | return 0; | |
309 | ||
310 | unroll_module_reset: | |
311 | list_for_each_entry_continue_reverse(core, &cluster->cores, elem) { | |
312 | if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci, | |
313 | core->ti_sci_id)) | |
314 | dev_warn(core->dev, "module-reset assert back failed\n"); | |
315 | } | |
316 | core = list_last_entry(&cluster->cores, struct k3_r5_core, elem); | |
317 | unroll_local_reset: | |
318 | list_for_each_entry_from_reverse(core, &cluster->cores, elem) { | |
319 | if (reset_control_deassert(core->reset)) | |
320 | dev_warn(core->dev, "local-reset deassert back failed\n"); | |
321 | } | |
322 | ||
323 | return ret; | |
324 | } | |
325 | ||
326 | static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster) | |
327 | { | |
328 | struct k3_r5_core *core; | |
329 | int ret; | |
330 | ||
331 | /* enable PSC modules on all applicable cores */ | |
332 | list_for_each_entry_reverse(core, &cluster->cores, elem) { | |
333 | ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci, | |
334 | core->ti_sci_id); | |
335 | if (ret) { | |
336 | dev_err(core->dev, "module-reset deassert failed, ret = %d\n", | |
337 | ret); | |
338 | core = list_next_entry(core, elem); | |
339 | goto unroll_module_reset; | |
340 | } | |
341 | } | |
342 | ||
343 | /* deassert local reset on all applicable cores */ | |
344 | list_for_each_entry_reverse(core, &cluster->cores, elem) { | |
345 | ret = reset_control_deassert(core->reset); | |
346 | if (ret) { | |
347 | dev_err(core->dev, "module-reset deassert failed, ret = %d\n", | |
348 | ret); | |
349 | goto unroll_local_reset; | |
350 | } | |
351 | } | |
352 | ||
353 | return 0; | |
354 | ||
355 | unroll_local_reset: | |
356 | list_for_each_entry_continue(core, &cluster->cores, elem) { | |
357 | if (reset_control_assert(core->reset)) | |
358 | dev_warn(core->dev, "local-reset assert back failed\n"); | |
359 | } | |
360 | core = list_first_entry(&cluster->cores, struct k3_r5_core, elem); | |
361 | unroll_module_reset: | |
362 | list_for_each_entry_from(core, &cluster->cores, elem) { | |
363 | if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci, | |
364 | core->ti_sci_id)) | |
365 | dev_warn(core->dev, "module-reset assert back failed\n"); | |
366 | } | |
367 | ||
368 | return ret; | |
369 | } | |
370 | ||
371 | static inline int k3_r5_core_halt(struct k3_r5_core *core) | |
372 | { | |
373 | return ti_sci_proc_set_control(core->tsp, | |
374 | PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0); | |
375 | } | |
376 | ||
377 | static inline int k3_r5_core_run(struct k3_r5_core *core) | |
378 | { | |
379 | return ti_sci_proc_set_control(core->tsp, | |
380 | 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT); | |
381 | } | |
382 | ||
e3865c85 SA |
383 | static int k3_r5_rproc_request_mbox(struct rproc *rproc) |
384 | { | |
385 | struct k3_r5_rproc *kproc = rproc->priv; | |
386 | struct mbox_client *client = &kproc->client; | |
387 | struct device *dev = kproc->dev; | |
388 | int ret; | |
389 | ||
390 | client->dev = dev; | |
391 | client->tx_done = NULL; | |
392 | client->rx_callback = k3_r5_rproc_mbox_callback; | |
393 | client->tx_block = false; | |
394 | client->knows_txdone = false; | |
395 | ||
396 | kproc->mbox = mbox_request_channel(client, 0); | |
397 | if (IS_ERR(kproc->mbox)) { | |
398 | ret = -EBUSY; | |
399 | dev_err(dev, "mbox_request_channel failed: %ld\n", | |
400 | PTR_ERR(kproc->mbox)); | |
401 | return ret; | |
402 | } | |
403 | ||
404 | /* | |
405 | * Ping the remote processor, this is only for sanity-sake for now; | |
406 | * there is no functional effect whatsoever. | |
407 | * | |
408 | * Note that the reply will _not_ arrive immediately: this message | |
409 | * will wait in the mailbox fifo until the remote processor is booted. | |
410 | */ | |
411 | ret = mbox_send_message(kproc->mbox, (void *)RP_MBOX_ECHO_REQUEST); | |
412 | if (ret < 0) { | |
413 | dev_err(dev, "mbox_send_message failed: %d\n", ret); | |
414 | mbox_free_channel(kproc->mbox); | |
415 | return ret; | |
416 | } | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
6dedbd1d SA |
421 | /* |
422 | * The R5F cores have controls for both a reset and a halt/run. The code | |
423 | * execution from DDR requires the initial boot-strapping code to be run | |
424 | * from the internal TCMs. This function is used to release the resets on | |
425 | * applicable cores to allow loading into the TCMs. The .prepare() ops is | |
426 | * invoked by remoteproc core before any firmware loading, and is followed | |
427 | * by the .start() ops after loading to actually let the R5 cores run. | |
ee99ee7c SA |
428 | * |
429 | * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to | |
430 | * execute code, but combines the TCMs from both cores. The resets for both | |
431 | * cores need to be released to make this possible, as the TCMs are in general | |
432 | * private to each core. Only Core0 needs to be unhalted for running the | |
433 | * cluster in this mode. The function uses the same reset logic as LockStep | |
434 | * mode for this (though the behavior is agnostic of the reset release order). | |
1168af40 | 435 | * This callback is invoked only in remoteproc mode. |
6dedbd1d SA |
436 | */ |
437 | static int k3_r5_rproc_prepare(struct rproc *rproc) | |
438 | { | |
439 | struct k3_r5_rproc *kproc = rproc->priv; | |
440 | struct k3_r5_cluster *cluster = kproc->cluster; | |
441 | struct k3_r5_core *core = kproc->core; | |
442 | struct device *dev = kproc->dev; | |
7508ea19 SA |
443 | u32 ctrl = 0, cfg = 0, stat = 0; |
444 | u64 boot_vec = 0; | |
445 | bool mem_init_dis; | |
6dedbd1d SA |
446 | int ret; |
447 | ||
7508ea19 SA |
448 | ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, &stat); |
449 | if (ret < 0) | |
450 | return ret; | |
451 | mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS); | |
452 | ||
ee99ee7c SA |
453 | /* Re-use LockStep-mode reset logic for Single-CPU mode */ |
454 | ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP || | |
455 | cluster->mode == CLUSTER_MODE_SINGLECPU) ? | |
6dedbd1d | 456 | k3_r5_lockstep_release(cluster) : k3_r5_split_release(core); |
34f26536 | 457 | if (ret) { |
6dedbd1d SA |
458 | dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n", |
459 | ret); | |
34f26536 SA |
460 | return ret; |
461 | } | |
6dedbd1d | 462 | |
7508ea19 SA |
463 | /* |
464 | * Newer IP revisions like on J7200 SoCs support h/w auto-initialization | |
465 | * of TCMs, so there is no need to perform the s/w memzero. This bit is | |
466 | * configurable through System Firmware, the default value does perform | |
467 | * auto-init, but account for it in case it is disabled | |
468 | */ | |
469 | if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) { | |
470 | dev_dbg(dev, "leveraging h/w init for TCM memories\n"); | |
471 | return 0; | |
472 | } | |
473 | ||
34f26536 SA |
474 | /* |
475 | * Zero out both TCMs unconditionally (access from v8 Arm core is not | |
476 | * affected by ATCM & BTCM enable configuration values) so that ECC | |
477 | * can be effective on all TCM addresses. | |
478 | */ | |
479 | dev_dbg(dev, "zeroing out ATCM memory\n"); | |
480 | memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size); | |
481 | ||
482 | dev_dbg(dev, "zeroing out BTCM memory\n"); | |
483 | memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size); | |
484 | ||
485 | return 0; | |
6dedbd1d SA |
486 | } |
487 | ||
488 | /* | |
489 | * This function implements the .unprepare() ops and performs the complimentary | |
490 | * operations to that of the .prepare() ops. The function is used to assert the | |
491 | * resets on all applicable cores for the rproc device (depending on LockStep | |
492 | * or Split mode). This completes the second portion of powering down the R5F | |
493 | * cores. The cores themselves are only halted in the .stop() ops, and the | |
494 | * .unprepare() ops is invoked by the remoteproc core after the remoteproc is | |
495 | * stopped. | |
ee99ee7c SA |
496 | * |
497 | * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from | |
498 | * both cores. The access is made possible only with releasing the resets for | |
499 | * both cores, but with only Core0 unhalted. This function re-uses the same | |
500 | * reset assert logic as LockStep mode for this mode (though the behavior is | |
1168af40 SA |
501 | * agnostic of the reset assert order). This callback is invoked only in |
502 | * remoteproc mode. | |
6dedbd1d SA |
503 | */ |
504 | static int k3_r5_rproc_unprepare(struct rproc *rproc) | |
505 | { | |
506 | struct k3_r5_rproc *kproc = rproc->priv; | |
507 | struct k3_r5_cluster *cluster = kproc->cluster; | |
508 | struct k3_r5_core *core = kproc->core; | |
509 | struct device *dev = kproc->dev; | |
510 | int ret; | |
511 | ||
ee99ee7c SA |
512 | /* Re-use LockStep-mode reset logic for Single-CPU mode */ |
513 | ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP || | |
514 | cluster->mode == CLUSTER_MODE_SINGLECPU) ? | |
6dedbd1d SA |
515 | k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(core); |
516 | if (ret) | |
517 | dev_err(dev, "unable to disable cores, ret = %d\n", ret); | |
518 | ||
519 | return ret; | |
520 | } | |
521 | ||
522 | /* | |
523 | * The R5F start sequence includes two different operations | |
524 | * 1. Configure the boot vector for R5F core(s) | |
525 | * 2. Unhalt/Run the R5F core(s) | |
526 | * | |
527 | * The sequence is different between LockStep and Split modes. The LockStep | |
528 | * mode requires the boot vector to be configured only for Core0, and then | |
529 | * unhalt both the cores to start the execution - Core1 needs to be unhalted | |
530 | * first followed by Core0. The Split-mode requires that Core0 to be maintained | |
531 | * always in a higher power state that Core1 (implying Core1 needs to be started | |
532 | * always only after Core0 is started). | |
ee99ee7c SA |
533 | * |
534 | * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute | |
535 | * code, so only Core0 needs to be unhalted. The function uses the same logic | |
1168af40 SA |
536 | * flow as Split-mode for this. This callback is invoked only in remoteproc |
537 | * mode. | |
6dedbd1d SA |
538 | */ |
539 | static int k3_r5_rproc_start(struct rproc *rproc) | |
540 | { | |
541 | struct k3_r5_rproc *kproc = rproc->priv; | |
542 | struct k3_r5_cluster *cluster = kproc->cluster; | |
6dedbd1d SA |
543 | struct device *dev = kproc->dev; |
544 | struct k3_r5_core *core; | |
545 | u32 boot_addr; | |
546 | int ret; | |
547 | ||
e3865c85 SA |
548 | ret = k3_r5_rproc_request_mbox(rproc); |
549 | if (ret) | |
6dedbd1d | 550 | return ret; |
6dedbd1d SA |
551 | |
552 | boot_addr = rproc->bootaddr; | |
553 | /* TODO: add boot_addr sanity checking */ | |
554 | dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr); | |
555 | ||
556 | /* boot vector need not be programmed for Core1 in LockStep mode */ | |
557 | core = kproc->core; | |
558 | ret = ti_sci_proc_set_config(core->tsp, boot_addr, 0, 0); | |
559 | if (ret) | |
560 | goto put_mbox; | |
561 | ||
562 | /* unhalt/run all applicable cores */ | |
563 | if (cluster->mode == CLUSTER_MODE_LOCKSTEP) { | |
564 | list_for_each_entry_reverse(core, &cluster->cores, elem) { | |
565 | ret = k3_r5_core_run(core); | |
566 | if (ret) | |
567 | goto unroll_core_run; | |
568 | } | |
569 | } else { | |
570 | ret = k3_r5_core_run(core); | |
571 | if (ret) | |
572 | goto put_mbox; | |
573 | } | |
574 | ||
575 | return 0; | |
576 | ||
577 | unroll_core_run: | |
578 | list_for_each_entry_continue(core, &cluster->cores, elem) { | |
579 | if (k3_r5_core_halt(core)) | |
580 | dev_warn(core->dev, "core halt back failed\n"); | |
581 | } | |
582 | put_mbox: | |
583 | mbox_free_channel(kproc->mbox); | |
584 | return ret; | |
585 | } | |
586 | ||
587 | /* | |
588 | * The R5F stop function includes the following operations | |
589 | * 1. Halt R5F core(s) | |
590 | * | |
591 | * The sequence is different between LockStep and Split modes, and the order | |
592 | * of cores the operations are performed are also in general reverse to that | |
593 | * of the start function. The LockStep mode requires each operation to be | |
594 | * performed first on Core0 followed by Core1. The Split-mode requires that | |
595 | * Core0 to be maintained always in a higher power state that Core1 (implying | |
596 | * Core1 needs to be stopped first before Core0). | |
597 | * | |
ee99ee7c SA |
598 | * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute |
599 | * code, so only Core0 needs to be halted. The function uses the same logic | |
600 | * flow as Split-mode for this. | |
601 | * | |
6dedbd1d SA |
602 | * Note that the R5F halt operation in general is not effective when the R5F |
603 | * core is running, but is needed to make sure the core won't run after | |
604 | * deasserting the reset the subsequent time. The asserting of reset can | |
605 | * be done here, but is preferred to be done in the .unprepare() ops - this | |
606 | * maintains the symmetric behavior between the .start(), .stop(), .prepare() | |
607 | * and .unprepare() ops, and also balances them well between sysfs 'state' | |
1168af40 SA |
608 | * flow and device bind/unbind or module removal. This callback is invoked |
609 | * only in remoteproc mode. | |
6dedbd1d SA |
610 | */ |
611 | static int k3_r5_rproc_stop(struct rproc *rproc) | |
612 | { | |
613 | struct k3_r5_rproc *kproc = rproc->priv; | |
614 | struct k3_r5_cluster *cluster = kproc->cluster; | |
615 | struct k3_r5_core *core = kproc->core; | |
616 | int ret; | |
617 | ||
618 | /* halt all applicable cores */ | |
619 | if (cluster->mode == CLUSTER_MODE_LOCKSTEP) { | |
620 | list_for_each_entry(core, &cluster->cores, elem) { | |
621 | ret = k3_r5_core_halt(core); | |
622 | if (ret) { | |
623 | core = list_prev_entry(core, elem); | |
624 | goto unroll_core_halt; | |
625 | } | |
626 | } | |
627 | } else { | |
628 | ret = k3_r5_core_halt(core); | |
629 | if (ret) | |
630 | goto out; | |
631 | } | |
632 | ||
633 | mbox_free_channel(kproc->mbox); | |
634 | ||
635 | return 0; | |
636 | ||
637 | unroll_core_halt: | |
638 | list_for_each_entry_from_reverse(core, &cluster->cores, elem) { | |
639 | if (k3_r5_core_run(core)) | |
640 | dev_warn(core->dev, "core run back failed\n"); | |
641 | } | |
642 | out: | |
643 | return ret; | |
644 | } | |
645 | ||
1168af40 SA |
646 | /* |
647 | * Attach to a running R5F remote processor (IPC-only mode) | |
648 | * | |
649 | * The R5F attach callback only needs to request the mailbox, the remote | |
650 | * processor is already booted, so there is no need to issue any TI-SCI | |
651 | * commands to boot the R5F cores in IPC-only mode. This callback is invoked | |
652 | * only in IPC-only mode. | |
653 | */ | |
654 | static int k3_r5_rproc_attach(struct rproc *rproc) | |
655 | { | |
656 | struct k3_r5_rproc *kproc = rproc->priv; | |
657 | struct device *dev = kproc->dev; | |
658 | int ret; | |
659 | ||
660 | ret = k3_r5_rproc_request_mbox(rproc); | |
661 | if (ret) | |
662 | return ret; | |
663 | ||
664 | dev_info(dev, "R5F core initialized in IPC-only mode\n"); | |
665 | return 0; | |
666 | } | |
667 | ||
668 | /* | |
669 | * Detach from a running R5F remote processor (IPC-only mode) | |
670 | * | |
671 | * The R5F detach callback performs the opposite operation to attach callback | |
672 | * and only needs to release the mailbox, the R5F cores are not stopped and | |
673 | * will be left in booted state in IPC-only mode. This callback is invoked | |
674 | * only in IPC-only mode. | |
675 | */ | |
676 | static int k3_r5_rproc_detach(struct rproc *rproc) | |
677 | { | |
678 | struct k3_r5_rproc *kproc = rproc->priv; | |
679 | struct device *dev = kproc->dev; | |
680 | ||
681 | mbox_free_channel(kproc->mbox); | |
682 | dev_info(dev, "R5F core deinitialized in IPC-only mode\n"); | |
683 | return 0; | |
684 | } | |
685 | ||
686 | /* | |
687 | * This function implements the .get_loaded_rsc_table() callback and is used | |
688 | * to provide the resource table for the booted R5F in IPC-only mode. The K3 R5F | |
689 | * firmwares follow a design-by-contract approach and are expected to have the | |
690 | * resource table at the base of the DDR region reserved for firmware usage. | |
691 | * This provides flexibility for the remote processor to be booted by different | |
692 | * bootloaders that may or may not have the ability to publish the resource table | |
693 | * address and size through a DT property. This callback is invoked only in | |
694 | * IPC-only mode. | |
695 | */ | |
696 | static struct resource_table *k3_r5_get_loaded_rsc_table(struct rproc *rproc, | |
697 | size_t *rsc_table_sz) | |
698 | { | |
699 | struct k3_r5_rproc *kproc = rproc->priv; | |
700 | struct device *dev = kproc->dev; | |
701 | ||
702 | if (!kproc->rmem[0].cpu_addr) { | |
703 | dev_err(dev, "memory-region #1 does not exist, loaded rsc table can't be found"); | |
704 | return ERR_PTR(-ENOMEM); | |
705 | } | |
706 | ||
707 | /* | |
708 | * NOTE: The resource table size is currently hard-coded to a maximum | |
709 | * of 256 bytes. The most common resource table usage for K3 firmwares | |
710 | * is to only have the vdev resource entry and an optional trace entry. | |
711 | * The exact size could be computed based on resource table address, but | |
712 | * the hard-coded value suffices to support the IPC-only mode. | |
713 | */ | |
714 | *rsc_table_sz = 256; | |
715 | return (struct resource_table *)kproc->rmem[0].cpu_addr; | |
716 | } | |
717 | ||
6dedbd1d SA |
718 | /* |
719 | * Internal Memory translation helper | |
720 | * | |
721 | * Custom function implementing the rproc .da_to_va ops to provide address | |
722 | * translation (device address to kernel virtual address) for internal RAMs | |
723 | * present in a DSP or IPU device). The translated addresses can be used | |
724 | * either by the remoteproc core for loading, or by any rpmsg bus drivers. | |
725 | */ | |
40df0a91 | 726 | static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) |
6dedbd1d SA |
727 | { |
728 | struct k3_r5_rproc *kproc = rproc->priv; | |
729 | struct k3_r5_core *core = kproc->core; | |
730 | void __iomem *va = NULL; | |
731 | phys_addr_t bus_addr; | |
732 | u32 dev_addr, offset; | |
733 | size_t size; | |
734 | int i; | |
735 | ||
736 | if (len == 0) | |
737 | return NULL; | |
738 | ||
739 | /* handle both R5 and SoC views of ATCM and BTCM */ | |
740 | for (i = 0; i < core->num_mems; i++) { | |
741 | bus_addr = core->mem[i].bus_addr; | |
742 | dev_addr = core->mem[i].dev_addr; | |
743 | size = core->mem[i].size; | |
744 | ||
745 | /* handle R5-view addresses of TCMs */ | |
746 | if (da >= dev_addr && ((da + len) <= (dev_addr + size))) { | |
747 | offset = da - dev_addr; | |
748 | va = core->mem[i].cpu_addr + offset; | |
749 | return (__force void *)va; | |
750 | } | |
751 | ||
752 | /* handle SoC-view addresses of TCMs */ | |
753 | if (da >= bus_addr && ((da + len) <= (bus_addr + size))) { | |
754 | offset = da - bus_addr; | |
755 | va = core->mem[i].cpu_addr + offset; | |
756 | return (__force void *)va; | |
757 | } | |
758 | } | |
759 | ||
ea47c688 SA |
760 | /* handle any SRAM regions using SoC-view addresses */ |
761 | for (i = 0; i < core->num_sram; i++) { | |
762 | dev_addr = core->sram[i].dev_addr; | |
763 | size = core->sram[i].size; | |
764 | ||
765 | if (da >= dev_addr && ((da + len) <= (dev_addr + size))) { | |
766 | offset = da - dev_addr; | |
767 | va = core->sram[i].cpu_addr + offset; | |
768 | return (__force void *)va; | |
769 | } | |
770 | } | |
771 | ||
6dedbd1d SA |
772 | /* handle static DDR reserved memory regions */ |
773 | for (i = 0; i < kproc->num_rmems; i++) { | |
774 | dev_addr = kproc->rmem[i].dev_addr; | |
775 | size = kproc->rmem[i].size; | |
776 | ||
777 | if (da >= dev_addr && ((da + len) <= (dev_addr + size))) { | |
778 | offset = da - dev_addr; | |
779 | va = kproc->rmem[i].cpu_addr + offset; | |
780 | return (__force void *)va; | |
781 | } | |
782 | } | |
783 | ||
784 | return NULL; | |
785 | } | |
786 | ||
787 | static const struct rproc_ops k3_r5_rproc_ops = { | |
788 | .prepare = k3_r5_rproc_prepare, | |
789 | .unprepare = k3_r5_rproc_unprepare, | |
790 | .start = k3_r5_rproc_start, | |
791 | .stop = k3_r5_rproc_stop, | |
792 | .kick = k3_r5_rproc_kick, | |
793 | .da_to_va = k3_r5_rproc_da_to_va, | |
794 | }; | |
795 | ||
796 | /* | |
797 | * Internal R5F Core configuration | |
798 | * | |
799 | * Each R5FSS has a cluster-level setting for configuring the processor | |
800 | * subsystem either in a safety/fault-tolerant LockStep mode or a performance | |
ee99ee7c SA |
801 | * oriented Split mode on most SoCs. A fewer SoCs support a non-safety mode |
802 | * as an alternate for LockStep mode that exercises only a single R5F core | |
803 | * called Single-CPU mode. Each R5F core has a number of settings to either | |
6dedbd1d SA |
804 | * enable/disable each of the TCMs, control which TCM appears at the R5F core's |
805 | * address 0x0. These settings need to be configured before the resets for the | |
806 | * corresponding core are released. These settings are all protected and managed | |
807 | * by the System Processor. | |
808 | * | |
809 | * This function is used to pre-configure these settings for each R5F core, and | |
810 | * the configuration is all done through various ti_sci_proc functions that | |
811 | * communicate with the System Processor. The function also ensures that both | |
812 | * the cores are halted before the .prepare() step. | |
813 | * | |
814 | * The function is called from k3_r5_cluster_rproc_init() and is invoked either | |
ee99ee7c SA |
815 | * once (in LockStep mode or Single-CPU modes) or twice (in Split mode). Support |
816 | * for LockStep-mode is dictated by an eFUSE register bit, and the config | |
817 | * settings retrieved from DT are adjusted accordingly as per the permitted | |
818 | * cluster mode. Another eFUSE register bit dictates if the R5F cluster only | |
819 | * supports a Single-CPU mode. All cluster level settings like Cluster mode and | |
820 | * TEINIT (exception handling state dictating ARM or Thumb mode) can only be set | |
821 | * and retrieved using Core0. | |
6dedbd1d SA |
822 | * |
823 | * The function behavior is different based on the cluster mode. The R5F cores | |
824 | * are configured independently as per their individual settings in Split mode. | |
825 | * They are identically configured in LockStep mode using the primary Core0 | |
826 | * settings. However, some individual settings cannot be set in LockStep mode. | |
827 | * This is overcome by switching to Split-mode initially and then programming | |
828 | * both the cores with the same settings, before reconfiguing again for | |
829 | * LockStep mode. | |
830 | */ | |
831 | static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc) | |
832 | { | |
833 | struct k3_r5_cluster *cluster = kproc->cluster; | |
834 | struct device *dev = kproc->dev; | |
835 | struct k3_r5_core *core0, *core, *temp; | |
836 | u32 ctrl = 0, cfg = 0, stat = 0; | |
837 | u32 set_cfg = 0, clr_cfg = 0; | |
838 | u64 boot_vec = 0; | |
839 | bool lockstep_en; | |
ee99ee7c | 840 | bool single_cpu; |
6dedbd1d SA |
841 | int ret; |
842 | ||
843 | core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem); | |
ee99ee7c | 844 | if (cluster->mode == CLUSTER_MODE_LOCKSTEP || |
51723657 DT |
845 | cluster->mode == CLUSTER_MODE_SINGLECPU || |
846 | cluster->mode == CLUSTER_MODE_SINGLECORE) { | |
ee99ee7c SA |
847 | core = core0; |
848 | } else { | |
849 | core = kproc->core; | |
850 | } | |
6dedbd1d SA |
851 | |
852 | ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, | |
853 | &stat); | |
854 | if (ret < 0) | |
855 | return ret; | |
856 | ||
857 | dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n", | |
858 | boot_vec, cfg, ctrl, stat); | |
859 | ||
7f402919 DT |
860 | single_cpu = !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY); |
861 | lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED); | |
862 | ||
863 | /* Override to single CPU mode if set in status flag */ | |
864 | if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) { | |
865 | dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n"); | |
866 | cluster->mode = CLUSTER_MODE_SINGLECPU; | |
ee99ee7c SA |
867 | } |
868 | ||
7f402919 | 869 | /* Override to split mode if lockstep enable bit is not set in status flag */ |
6dedbd1d SA |
870 | if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) { |
871 | dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n"); | |
872 | cluster->mode = CLUSTER_MODE_SPLIT; | |
873 | } | |
874 | ||
875 | /* always enable ARM mode and set boot vector to 0 */ | |
876 | boot_vec = 0x0; | |
877 | if (core == core0) { | |
878 | clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT; | |
7f402919 DT |
879 | /* |
880 | * Single-CPU configuration bit can only be configured | |
881 | * on Core0 and system firmware will NACK any requests | |
882 | * with the bit configured, so program it only on | |
883 | * permitted cores | |
884 | */ | |
51723657 DT |
885 | if (cluster->mode == CLUSTER_MODE_SINGLECPU || |
886 | cluster->mode == CLUSTER_MODE_SINGLECORE) { | |
7f402919 | 887 | set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE; |
ee99ee7c SA |
888 | } else { |
889 | /* | |
890 | * LockStep configuration bit is Read-only on Split-mode | |
891 | * _only_ devices and system firmware will NACK any | |
892 | * requests with the bit configured, so program it only | |
893 | * on permitted devices | |
894 | */ | |
895 | if (lockstep_en) | |
896 | clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP; | |
897 | } | |
6dedbd1d SA |
898 | } |
899 | ||
900 | if (core->atcm_enable) | |
901 | set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN; | |
902 | else | |
903 | clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN; | |
904 | ||
905 | if (core->btcm_enable) | |
906 | set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN; | |
907 | else | |
908 | clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN; | |
909 | ||
910 | if (core->loczrama) | |
911 | set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE; | |
912 | else | |
913 | clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE; | |
914 | ||
915 | if (cluster->mode == CLUSTER_MODE_LOCKSTEP) { | |
916 | /* | |
917 | * work around system firmware limitations to make sure both | |
918 | * cores are programmed symmetrically in LockStep. LockStep | |
919 | * and TEINIT config is only allowed with Core0. | |
920 | */ | |
921 | list_for_each_entry(temp, &cluster->cores, elem) { | |
922 | ret = k3_r5_core_halt(temp); | |
923 | if (ret) | |
924 | goto out; | |
925 | ||
926 | if (temp != core) { | |
927 | clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP; | |
928 | clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT; | |
929 | } | |
930 | ret = ti_sci_proc_set_config(temp->tsp, boot_vec, | |
931 | set_cfg, clr_cfg); | |
932 | if (ret) | |
933 | goto out; | |
934 | } | |
935 | ||
936 | set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP; | |
937 | clr_cfg = 0; | |
938 | ret = ti_sci_proc_set_config(core->tsp, boot_vec, | |
939 | set_cfg, clr_cfg); | |
940 | } else { | |
941 | ret = k3_r5_core_halt(core); | |
942 | if (ret) | |
943 | goto out; | |
944 | ||
945 | ret = ti_sci_proc_set_config(core->tsp, boot_vec, | |
946 | set_cfg, clr_cfg); | |
947 | } | |
948 | ||
949 | out: | |
950 | return ret; | |
951 | } | |
952 | ||
953 | static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc) | |
954 | { | |
955 | struct device *dev = kproc->dev; | |
956 | struct device_node *np = dev_of_node(dev); | |
957 | struct device_node *rmem_np; | |
958 | struct reserved_mem *rmem; | |
959 | int num_rmems; | |
960 | int ret, i; | |
961 | ||
962 | num_rmems = of_property_count_elems_of_size(np, "memory-region", | |
963 | sizeof(phandle)); | |
964 | if (num_rmems <= 0) { | |
965 | dev_err(dev, "device does not have reserved memory regions, ret = %d\n", | |
966 | num_rmems); | |
967 | return -EINVAL; | |
968 | } | |
969 | if (num_rmems < 2) { | |
d6a33c5b | 970 | dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n", |
6dedbd1d SA |
971 | num_rmems); |
972 | return -EINVAL; | |
973 | } | |
974 | ||
975 | /* use reserved memory region 0 for vring DMA allocations */ | |
976 | ret = of_reserved_mem_device_init_by_idx(dev, np, 0); | |
977 | if (ret) { | |
978 | dev_err(dev, "device cannot initialize DMA pool, ret = %d\n", | |
979 | ret); | |
980 | return ret; | |
981 | } | |
982 | ||
983 | num_rmems--; | |
984 | kproc->rmem = kcalloc(num_rmems, sizeof(*kproc->rmem), GFP_KERNEL); | |
985 | if (!kproc->rmem) { | |
986 | ret = -ENOMEM; | |
987 | goto release_rmem; | |
988 | } | |
989 | ||
990 | /* use remaining reserved memory regions for static carveouts */ | |
991 | for (i = 0; i < num_rmems; i++) { | |
992 | rmem_np = of_parse_phandle(np, "memory-region", i + 1); | |
993 | if (!rmem_np) { | |
994 | ret = -EINVAL; | |
995 | goto unmap_rmem; | |
996 | } | |
997 | ||
998 | rmem = of_reserved_mem_lookup(rmem_np); | |
999 | if (!rmem) { | |
1000 | of_node_put(rmem_np); | |
1001 | ret = -EINVAL; | |
1002 | goto unmap_rmem; | |
1003 | } | |
1004 | of_node_put(rmem_np); | |
1005 | ||
1006 | kproc->rmem[i].bus_addr = rmem->base; | |
1007 | /* | |
1008 | * R5Fs do not have an MMU, but have a Region Address Translator | |
1009 | * (RAT) module that provides a fixed entry translation between | |
1010 | * the 32-bit processor addresses to 64-bit bus addresses. The | |
1011 | * RAT is programmable only by the R5F cores. Support for RAT | |
1012 | * is currently not supported, so 64-bit address regions are not | |
1013 | * supported. The absence of MMUs implies that the R5F device | |
1014 | * addresses/supported memory regions are restricted to 32-bit | |
1015 | * bus addresses, and are identical | |
1016 | */ | |
1017 | kproc->rmem[i].dev_addr = (u32)rmem->base; | |
1018 | kproc->rmem[i].size = rmem->size; | |
1019 | kproc->rmem[i].cpu_addr = ioremap_wc(rmem->base, rmem->size); | |
1020 | if (!kproc->rmem[i].cpu_addr) { | |
1021 | dev_err(dev, "failed to map reserved memory#%d at %pa of size %pa\n", | |
1022 | i + 1, &rmem->base, &rmem->size); | |
1023 | ret = -ENOMEM; | |
1024 | goto unmap_rmem; | |
1025 | } | |
1026 | ||
1027 | dev_dbg(dev, "reserved memory%d: bus addr %pa size 0x%zx va %pK da 0x%x\n", | |
1028 | i + 1, &kproc->rmem[i].bus_addr, | |
1029 | kproc->rmem[i].size, kproc->rmem[i].cpu_addr, | |
1030 | kproc->rmem[i].dev_addr); | |
1031 | } | |
1032 | kproc->num_rmems = num_rmems; | |
1033 | ||
1034 | return 0; | |
1035 | ||
1036 | unmap_rmem: | |
1037 | for (i--; i >= 0; i--) | |
1038 | iounmap(kproc->rmem[i].cpu_addr); | |
1039 | kfree(kproc->rmem); | |
1040 | release_rmem: | |
1041 | of_reserved_mem_device_release(dev); | |
1042 | return ret; | |
1043 | } | |
1044 | ||
1045 | static void k3_r5_reserved_mem_exit(struct k3_r5_rproc *kproc) | |
1046 | { | |
1047 | int i; | |
1048 | ||
1049 | for (i = 0; i < kproc->num_rmems; i++) | |
1050 | iounmap(kproc->rmem[i].cpu_addr); | |
1051 | kfree(kproc->rmem); | |
1052 | ||
1053 | of_reserved_mem_device_release(kproc->dev); | |
1054 | } | |
1055 | ||
c3c21b35 SA |
1056 | /* |
1057 | * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs, | |
1058 | * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both | |
1059 | * cores are usable in Split-mode, but only the Core0 TCMs can be used in | |
1060 | * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by | |
1061 | * leveraging the Core1 TCMs as well in certain modes where they would have | |
ee99ee7c SA |
1062 | * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs, Single-CPU mode on |
1063 | * AM64x SoCs). This is done by making a Core1 TCM visible immediately after the | |
1064 | * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for | |
1065 | * the Core0 TCMs, and the dts representation reflects this increased size on | |
1066 | * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only | |
1067 | * half the original size in Split mode. | |
c3c21b35 SA |
1068 | */ |
1069 | static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc) | |
1070 | { | |
1071 | struct k3_r5_cluster *cluster = kproc->cluster; | |
1072 | struct k3_r5_core *core = kproc->core; | |
1073 | struct device *cdev = core->dev; | |
1074 | struct k3_r5_core *core0; | |
1075 | ||
1076 | if (cluster->mode == CLUSTER_MODE_LOCKSTEP || | |
ee99ee7c | 1077 | cluster->mode == CLUSTER_MODE_SINGLECPU || |
51723657 | 1078 | cluster->mode == CLUSTER_MODE_SINGLECORE || |
c3c21b35 SA |
1079 | !cluster->soc_data->tcm_is_double) |
1080 | return; | |
1081 | ||
1082 | core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem); | |
1083 | if (core == core0) { | |
1084 | WARN_ON(core->mem[0].size != SZ_64K); | |
1085 | WARN_ON(core->mem[1].size != SZ_64K); | |
1086 | ||
1087 | core->mem[0].size /= 2; | |
1088 | core->mem[1].size /= 2; | |
1089 | ||
1090 | dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n", | |
1091 | core->mem[0].size, core->mem[1].size); | |
1092 | } | |
1093 | } | |
1094 | ||
1168af40 SA |
1095 | /* |
1096 | * This function checks and configures a R5F core for IPC-only or remoteproc | |
1097 | * mode. The driver is configured to be in IPC-only mode for a R5F core when | |
1098 | * the core has been loaded and started by a bootloader. The IPC-only mode is | |
1099 | * detected by querying the System Firmware for reset, power on and halt status | |
1100 | * and ensuring that the core is running. Any incomplete steps at bootloader | |
1101 | * are validated and errored out. | |
1102 | * | |
1103 | * In IPC-only mode, the driver state flags for ATCM, BTCM and LOCZRAMA settings | |
1104 | * and cluster mode parsed originally from kernel DT are updated to reflect the | |
1105 | * actual values configured by bootloader. The driver internal device memory | |
1106 | * addresses for TCMs are also updated. | |
1107 | */ | |
1108 | static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc) | |
1109 | { | |
1110 | struct k3_r5_cluster *cluster = kproc->cluster; | |
1111 | struct k3_r5_core *core = kproc->core; | |
1112 | struct device *cdev = core->dev; | |
7f402919 | 1113 | bool r_state = false, c_state = false, lockstep_en = false, single_cpu = false; |
1168af40 SA |
1114 | u32 ctrl = 0, cfg = 0, stat = 0, halted = 0; |
1115 | u64 boot_vec = 0; | |
1116 | u32 atcm_enable, btcm_enable, loczrama; | |
1117 | struct k3_r5_core *core0; | |
7f402919 | 1118 | enum cluster_mode mode = cluster->mode; |
1168af40 SA |
1119 | int ret; |
1120 | ||
1121 | core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem); | |
1122 | ||
1123 | ret = core->ti_sci->ops.dev_ops.is_on(core->ti_sci, core->ti_sci_id, | |
1124 | &r_state, &c_state); | |
1125 | if (ret) { | |
1126 | dev_err(cdev, "failed to get initial state, mode cannot be determined, ret = %d\n", | |
1127 | ret); | |
1128 | return ret; | |
1129 | } | |
1130 | if (r_state != c_state) { | |
1131 | dev_warn(cdev, "R5F core may have been powered on by a different host, programmed state (%d) != actual state (%d)\n", | |
1132 | r_state, c_state); | |
1133 | } | |
1134 | ||
1135 | ret = reset_control_status(core->reset); | |
1136 | if (ret < 0) { | |
1137 | dev_err(cdev, "failed to get initial local reset status, ret = %d\n", | |
1138 | ret); | |
1139 | return ret; | |
1140 | } | |
1141 | ||
1142 | ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, | |
1143 | &stat); | |
1144 | if (ret < 0) { | |
1145 | dev_err(cdev, "failed to get initial processor status, ret = %d\n", | |
1146 | ret); | |
1147 | return ret; | |
1148 | } | |
1149 | atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0; | |
1150 | btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0; | |
1151 | loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0; | |
7f402919 DT |
1152 | single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0; |
1153 | lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0; | |
1154 | ||
51723657 | 1155 | if (single_cpu && mode != CLUSTER_MODE_SINGLECORE) |
7f402919 DT |
1156 | mode = CLUSTER_MODE_SINGLECPU; |
1157 | if (lockstep_en) | |
1158 | mode = CLUSTER_MODE_LOCKSTEP; | |
1159 | ||
1168af40 SA |
1160 | halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT; |
1161 | ||
1162 | /* | |
1163 | * IPC-only mode detection requires both local and module resets to | |
1164 | * be deasserted and R5F core to be unhalted. Local reset status is | |
1165 | * irrelevant if module reset is asserted (POR value has local reset | |
1166 | * deasserted), and is deemed as remoteproc mode | |
1167 | */ | |
1168 | if (c_state && !ret && !halted) { | |
1169 | dev_info(cdev, "configured R5F for IPC-only mode\n"); | |
1170 | kproc->rproc->state = RPROC_DETACHED; | |
1171 | ret = 1; | |
1172 | /* override rproc ops with only required IPC-only mode ops */ | |
1173 | kproc->rproc->ops->prepare = NULL; | |
1174 | kproc->rproc->ops->unprepare = NULL; | |
1175 | kproc->rproc->ops->start = NULL; | |
1176 | kproc->rproc->ops->stop = NULL; | |
1177 | kproc->rproc->ops->attach = k3_r5_rproc_attach; | |
1178 | kproc->rproc->ops->detach = k3_r5_rproc_detach; | |
1179 | kproc->rproc->ops->get_loaded_rsc_table = | |
1180 | k3_r5_get_loaded_rsc_table; | |
1181 | } else if (!c_state) { | |
1182 | dev_info(cdev, "configured R5F for remoteproc mode\n"); | |
1183 | ret = 0; | |
1184 | } else { | |
1185 | dev_err(cdev, "mismatched mode: local_reset = %s, module_reset = %s, core_state = %s\n", | |
1186 | !ret ? "deasserted" : "asserted", | |
1187 | c_state ? "deasserted" : "asserted", | |
1188 | halted ? "halted" : "unhalted"); | |
1189 | ret = -EINVAL; | |
1190 | } | |
1191 | ||
1192 | /* fixup TCMs, cluster & core flags to actual values in IPC-only mode */ | |
1193 | if (ret > 0) { | |
1194 | if (core == core0) | |
1195 | cluster->mode = mode; | |
1196 | core->atcm_enable = atcm_enable; | |
1197 | core->btcm_enable = btcm_enable; | |
1198 | core->loczrama = loczrama; | |
1199 | core->mem[0].dev_addr = loczrama ? 0 : K3_R5_TCM_DEV_ADDR; | |
1200 | core->mem[1].dev_addr = loczrama ? K3_R5_TCM_DEV_ADDR : 0; | |
1201 | } | |
1202 | ||
1203 | return ret; | |
1204 | } | |
1205 | ||
6dedbd1d SA |
1206 | static int k3_r5_cluster_rproc_init(struct platform_device *pdev) |
1207 | { | |
1208 | struct k3_r5_cluster *cluster = platform_get_drvdata(pdev); | |
1209 | struct device *dev = &pdev->dev; | |
1210 | struct k3_r5_rproc *kproc; | |
1211 | struct k3_r5_core *core, *core1; | |
1212 | struct device *cdev; | |
1213 | const char *fw_name; | |
1214 | struct rproc *rproc; | |
1168af40 | 1215 | int ret, ret1; |
6dedbd1d SA |
1216 | |
1217 | core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem); | |
1218 | list_for_each_entry(core, &cluster->cores, elem) { | |
1219 | cdev = core->dev; | |
1220 | ret = rproc_of_parse_firmware(cdev, 0, &fw_name); | |
1221 | if (ret) { | |
1222 | dev_err(dev, "failed to parse firmware-name property, ret = %d\n", | |
1223 | ret); | |
1224 | goto out; | |
1225 | } | |
1226 | ||
1227 | rproc = rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops, | |
1228 | fw_name, sizeof(*kproc)); | |
1229 | if (!rproc) { | |
1230 | ret = -ENOMEM; | |
1231 | goto out; | |
1232 | } | |
1233 | ||
1234 | /* K3 R5s have a Region Address Translator (RAT) but no MMU */ | |
1235 | rproc->has_iommu = false; | |
1236 | /* error recovery is not supported at present */ | |
1237 | rproc->recovery_disabled = true; | |
1238 | ||
1239 | kproc = rproc->priv; | |
1240 | kproc->cluster = cluster; | |
1241 | kproc->core = core; | |
1242 | kproc->dev = cdev; | |
1243 | kproc->rproc = rproc; | |
1244 | core->rproc = rproc; | |
1245 | ||
1168af40 SA |
1246 | ret = k3_r5_rproc_configure_mode(kproc); |
1247 | if (ret < 0) | |
1248 | goto err_config; | |
1249 | if (ret) | |
1250 | goto init_rmem; | |
1251 | ||
6dedbd1d SA |
1252 | ret = k3_r5_rproc_configure(kproc); |
1253 | if (ret) { | |
1254 | dev_err(dev, "initial configure failed, ret = %d\n", | |
1255 | ret); | |
1256 | goto err_config; | |
1257 | } | |
1258 | ||
1168af40 | 1259 | init_rmem: |
c3c21b35 SA |
1260 | k3_r5_adjust_tcm_sizes(kproc); |
1261 | ||
6dedbd1d SA |
1262 | ret = k3_r5_reserved_mem_init(kproc); |
1263 | if (ret) { | |
1264 | dev_err(dev, "reserved memory init failed, ret = %d\n", | |
1265 | ret); | |
1266 | goto err_config; | |
1267 | } | |
1268 | ||
1269 | ret = rproc_add(rproc); | |
1270 | if (ret) { | |
1271 | dev_err(dev, "rproc_add failed, ret = %d\n", ret); | |
1272 | goto err_add; | |
1273 | } | |
1274 | ||
51723657 DT |
1275 | /* create only one rproc in lockstep, single-cpu or |
1276 | * single core mode | |
1277 | */ | |
ee99ee7c | 1278 | if (cluster->mode == CLUSTER_MODE_LOCKSTEP || |
51723657 DT |
1279 | cluster->mode == CLUSTER_MODE_SINGLECPU || |
1280 | cluster->mode == CLUSTER_MODE_SINGLECORE) | |
6dedbd1d SA |
1281 | break; |
1282 | } | |
1283 | ||
1284 | return 0; | |
1285 | ||
1286 | err_split: | |
1168af40 SA |
1287 | if (rproc->state == RPROC_ATTACHED) { |
1288 | ret1 = rproc_detach(rproc); | |
1289 | if (ret1) { | |
1290 | dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", | |
1291 | ret1); | |
1292 | return ret1; | |
1293 | } | |
1294 | } | |
1295 | ||
6dedbd1d SA |
1296 | rproc_del(rproc); |
1297 | err_add: | |
1298 | k3_r5_reserved_mem_exit(kproc); | |
1299 | err_config: | |
1300 | rproc_free(rproc); | |
1301 | core->rproc = NULL; | |
1302 | out: | |
1303 | /* undo core0 upon any failures on core1 in split-mode */ | |
1304 | if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) { | |
1305 | core = list_prev_entry(core, elem); | |
1306 | rproc = core->rproc; | |
1307 | kproc = rproc->priv; | |
1308 | goto err_split; | |
1309 | } | |
1310 | return ret; | |
1311 | } | |
1312 | ||
23168229 | 1313 | static void k3_r5_cluster_rproc_exit(void *data) |
6dedbd1d | 1314 | { |
23168229 | 1315 | struct k3_r5_cluster *cluster = platform_get_drvdata(data); |
6dedbd1d SA |
1316 | struct k3_r5_rproc *kproc; |
1317 | struct k3_r5_core *core; | |
1318 | struct rproc *rproc; | |
1168af40 | 1319 | int ret; |
6dedbd1d SA |
1320 | |
1321 | /* | |
ee99ee7c SA |
1322 | * lockstep mode and single-cpu modes have only one rproc associated |
1323 | * with first core, whereas split-mode has two rprocs associated with | |
1324 | * each core, and requires that core1 be powered down first | |
6dedbd1d | 1325 | */ |
ee99ee7c SA |
1326 | core = (cluster->mode == CLUSTER_MODE_LOCKSTEP || |
1327 | cluster->mode == CLUSTER_MODE_SINGLECPU) ? | |
6dedbd1d SA |
1328 | list_first_entry(&cluster->cores, struct k3_r5_core, elem) : |
1329 | list_last_entry(&cluster->cores, struct k3_r5_core, elem); | |
1330 | ||
1331 | list_for_each_entry_from_reverse(core, &cluster->cores, elem) { | |
1332 | rproc = core->rproc; | |
1333 | kproc = rproc->priv; | |
1334 | ||
1168af40 SA |
1335 | if (rproc->state == RPROC_ATTACHED) { |
1336 | ret = rproc_detach(rproc); | |
1337 | if (ret) { | |
1338 | dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", ret); | |
1339 | return; | |
1340 | } | |
1341 | } | |
1342 | ||
6dedbd1d SA |
1343 | rproc_del(rproc); |
1344 | ||
1345 | k3_r5_reserved_mem_exit(kproc); | |
1346 | ||
1347 | rproc_free(rproc); | |
1348 | core->rproc = NULL; | |
1349 | } | |
6dedbd1d SA |
1350 | } |
1351 | ||
1352 | static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev, | |
1353 | struct k3_r5_core *core) | |
1354 | { | |
1355 | static const char * const mem_names[] = {"atcm", "btcm"}; | |
1356 | struct device *dev = &pdev->dev; | |
1357 | struct resource *res; | |
1358 | int num_mems; | |
1359 | int i; | |
1360 | ||
1361 | num_mems = ARRAY_SIZE(mem_names); | |
1362 | core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL); | |
1363 | if (!core->mem) | |
1364 | return -ENOMEM; | |
1365 | ||
1366 | for (i = 0; i < num_mems; i++) { | |
1367 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1368 | mem_names[i]); | |
1369 | if (!res) { | |
1370 | dev_err(dev, "found no memory resource for %s\n", | |
1371 | mem_names[i]); | |
1372 | return -EINVAL; | |
1373 | } | |
1374 | if (!devm_request_mem_region(dev, res->start, | |
1375 | resource_size(res), | |
1376 | dev_name(dev))) { | |
1377 | dev_err(dev, "could not request %s region for resource\n", | |
1378 | mem_names[i]); | |
1379 | return -EBUSY; | |
1380 | } | |
1381 | ||
1382 | /* | |
1383 | * TCMs are designed in general to support RAM-like backing | |
1384 | * memories. So, map these as Normal Non-Cached memories. This | |
1385 | * also avoids/fixes any potential alignment faults due to | |
1386 | * unaligned data accesses when using memcpy() or memset() | |
1387 | * functions (normally seen with device type memory). | |
1388 | */ | |
1389 | core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start, | |
1390 | resource_size(res)); | |
1391 | if (!core->mem[i].cpu_addr) { | |
1392 | dev_err(dev, "failed to map %s memory\n", mem_names[i]); | |
1393 | return -ENOMEM; | |
1394 | } | |
1395 | core->mem[i].bus_addr = res->start; | |
1396 | ||
1397 | /* | |
1398 | * TODO: | |
1399 | * The R5F cores can place ATCM & BTCM anywhere in its address | |
1400 | * based on the corresponding Region Registers in the System | |
1401 | * Control coprocessor. For now, place ATCM and BTCM at | |
1402 | * addresses 0 and 0x41010000 (same as the bus address on AM65x | |
1403 | * SoCs) based on loczrama setting | |
1404 | */ | |
1405 | if (!strcmp(mem_names[i], "atcm")) { | |
1406 | core->mem[i].dev_addr = core->loczrama ? | |
1407 | 0 : K3_R5_TCM_DEV_ADDR; | |
1408 | } else { | |
1409 | core->mem[i].dev_addr = core->loczrama ? | |
1410 | K3_R5_TCM_DEV_ADDR : 0; | |
1411 | } | |
1412 | core->mem[i].size = resource_size(res); | |
1413 | ||
1414 | dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n", | |
1415 | mem_names[i], &core->mem[i].bus_addr, | |
1416 | core->mem[i].size, core->mem[i].cpu_addr, | |
1417 | core->mem[i].dev_addr); | |
1418 | } | |
1419 | core->num_mems = num_mems; | |
1420 | ||
1421 | return 0; | |
1422 | } | |
1423 | ||
ea47c688 SA |
1424 | static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev, |
1425 | struct k3_r5_core *core) | |
1426 | { | |
1427 | struct device_node *np = pdev->dev.of_node; | |
1428 | struct device *dev = &pdev->dev; | |
1429 | struct device_node *sram_np; | |
1430 | struct resource res; | |
1431 | int num_sram; | |
1432 | int i, ret; | |
1433 | ||
1434 | num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle)); | |
1435 | if (num_sram <= 0) { | |
1436 | dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n", | |
1437 | num_sram); | |
1438 | return 0; | |
1439 | } | |
1440 | ||
1441 | core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL); | |
1442 | if (!core->sram) | |
1443 | return -ENOMEM; | |
1444 | ||
1445 | for (i = 0; i < num_sram; i++) { | |
1446 | sram_np = of_parse_phandle(np, "sram", i); | |
1447 | if (!sram_np) | |
1448 | return -EINVAL; | |
1449 | ||
1450 | if (!of_device_is_available(sram_np)) { | |
1451 | of_node_put(sram_np); | |
1452 | return -EINVAL; | |
1453 | } | |
1454 | ||
1455 | ret = of_address_to_resource(sram_np, 0, &res); | |
1456 | of_node_put(sram_np); | |
1457 | if (ret) | |
1458 | return -EINVAL; | |
1459 | ||
1460 | core->sram[i].bus_addr = res.start; | |
1461 | core->sram[i].dev_addr = res.start; | |
1462 | core->sram[i].size = resource_size(&res); | |
1463 | core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start, | |
1464 | resource_size(&res)); | |
1465 | if (!core->sram[i].cpu_addr) { | |
1466 | dev_err(dev, "failed to parse and map sram%d memory at %pad\n", | |
1467 | i, &res.start); | |
1468 | return -ENOMEM; | |
1469 | } | |
1470 | ||
1471 | dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n", | |
1472 | i, &core->sram[i].bus_addr, | |
1473 | core->sram[i].size, core->sram[i].cpu_addr, | |
1474 | core->sram[i].dev_addr); | |
1475 | } | |
1476 | core->num_sram = num_sram; | |
1477 | ||
1478 | return 0; | |
1479 | } | |
1480 | ||
6dedbd1d SA |
1481 | static |
1482 | struct ti_sci_proc *k3_r5_core_of_get_tsp(struct device *dev, | |
1483 | const struct ti_sci_handle *sci) | |
1484 | { | |
1485 | struct ti_sci_proc *tsp; | |
1486 | u32 temp[2]; | |
1487 | int ret; | |
1488 | ||
1489 | ret = of_property_read_u32_array(dev_of_node(dev), "ti,sci-proc-ids", | |
1490 | temp, 2); | |
1491 | if (ret < 0) | |
1492 | return ERR_PTR(ret); | |
1493 | ||
1494 | tsp = devm_kzalloc(dev, sizeof(*tsp), GFP_KERNEL); | |
1495 | if (!tsp) | |
1496 | return ERR_PTR(-ENOMEM); | |
1497 | ||
1498 | tsp->dev = dev; | |
1499 | tsp->sci = sci; | |
1500 | tsp->ops = &sci->ops.proc_ops; | |
1501 | tsp->proc_id = temp[0]; | |
1502 | tsp->host_id = temp[1]; | |
1503 | ||
1504 | return tsp; | |
1505 | } | |
1506 | ||
1507 | static int k3_r5_core_of_init(struct platform_device *pdev) | |
1508 | { | |
1509 | struct device *dev = &pdev->dev; | |
1510 | struct device_node *np = dev_of_node(dev); | |
1511 | struct k3_r5_core *core; | |
1512 | int ret; | |
1513 | ||
1514 | if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL)) | |
1515 | return -ENOMEM; | |
1516 | ||
1517 | core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL); | |
1518 | if (!core) { | |
1519 | ret = -ENOMEM; | |
1520 | goto err; | |
1521 | } | |
1522 | ||
1523 | core->dev = dev; | |
1524 | /* | |
1525 | * Use SoC Power-on-Reset values as default if no DT properties are | |
1526 | * used to dictate the TCM configurations | |
1527 | */ | |
1528 | core->atcm_enable = 0; | |
1529 | core->btcm_enable = 1; | |
1530 | core->loczrama = 1; | |
1531 | ||
1532 | ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable); | |
1533 | if (ret < 0 && ret != -EINVAL) { | |
1534 | dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n", | |
1535 | ret); | |
1536 | goto err; | |
1537 | } | |
1538 | ||
1539 | ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable); | |
1540 | if (ret < 0 && ret != -EINVAL) { | |
1541 | dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n", | |
1542 | ret); | |
1543 | goto err; | |
1544 | } | |
1545 | ||
1546 | ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama); | |
1547 | if (ret < 0 && ret != -EINVAL) { | |
1548 | dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret); | |
1549 | goto err; | |
1550 | } | |
1551 | ||
1552 | core->ti_sci = devm_ti_sci_get_by_phandle(dev, "ti,sci"); | |
1553 | if (IS_ERR(core->ti_sci)) { | |
1554 | ret = PTR_ERR(core->ti_sci); | |
1555 | if (ret != -EPROBE_DEFER) { | |
1556 | dev_err(dev, "failed to get ti-sci handle, ret = %d\n", | |
1557 | ret); | |
1558 | } | |
1559 | core->ti_sci = NULL; | |
1560 | goto err; | |
1561 | } | |
1562 | ||
1563 | ret = of_property_read_u32(np, "ti,sci-dev-id", &core->ti_sci_id); | |
1564 | if (ret) { | |
1565 | dev_err(dev, "missing 'ti,sci-dev-id' property\n"); | |
1566 | goto err; | |
1567 | } | |
1568 | ||
1569 | core->reset = devm_reset_control_get_exclusive(dev, NULL); | |
1570 | if (IS_ERR_OR_NULL(core->reset)) { | |
1571 | ret = PTR_ERR_OR_ZERO(core->reset); | |
1572 | if (!ret) | |
1573 | ret = -ENODEV; | |
1574 | if (ret != -EPROBE_DEFER) { | |
1575 | dev_err(dev, "failed to get reset handle, ret = %d\n", | |
1576 | ret); | |
1577 | } | |
1578 | goto err; | |
1579 | } | |
1580 | ||
1581 | core->tsp = k3_r5_core_of_get_tsp(dev, core->ti_sci); | |
1582 | if (IS_ERR(core->tsp)) { | |
34c4da6d | 1583 | ret = PTR_ERR(core->tsp); |
6dedbd1d SA |
1584 | dev_err(dev, "failed to construct ti-sci proc control, ret = %d\n", |
1585 | ret); | |
6dedbd1d SA |
1586 | goto err; |
1587 | } | |
1588 | ||
1589 | ret = k3_r5_core_of_get_internal_memories(pdev, core); | |
1590 | if (ret) { | |
1591 | dev_err(dev, "failed to get internal memories, ret = %d\n", | |
1592 | ret); | |
1593 | goto err; | |
1594 | } | |
1595 | ||
ea47c688 SA |
1596 | ret = k3_r5_core_of_get_sram_memories(pdev, core); |
1597 | if (ret) { | |
1598 | dev_err(dev, "failed to get sram memories, ret = %d\n", ret); | |
1599 | goto err; | |
1600 | } | |
1601 | ||
6dedbd1d SA |
1602 | ret = ti_sci_proc_request(core->tsp); |
1603 | if (ret < 0) { | |
1604 | dev_err(dev, "ti_sci_proc_request failed, ret = %d\n", ret); | |
1605 | goto err; | |
1606 | } | |
1607 | ||
1608 | platform_set_drvdata(pdev, core); | |
1609 | devres_close_group(dev, k3_r5_core_of_init); | |
1610 | ||
1611 | return 0; | |
1612 | ||
1613 | err: | |
1614 | devres_release_group(dev, k3_r5_core_of_init); | |
1615 | return ret; | |
1616 | } | |
1617 | ||
1618 | /* | |
1619 | * free the resources explicitly since driver model is not being used | |
1620 | * for the child R5F devices | |
1621 | */ | |
1622 | static void k3_r5_core_of_exit(struct platform_device *pdev) | |
1623 | { | |
1624 | struct k3_r5_core *core = platform_get_drvdata(pdev); | |
1625 | struct device *dev = &pdev->dev; | |
1626 | int ret; | |
1627 | ||
1628 | ret = ti_sci_proc_release(core->tsp); | |
1629 | if (ret) | |
1630 | dev_err(dev, "failed to release proc, ret = %d\n", ret); | |
1631 | ||
1632 | platform_set_drvdata(pdev, NULL); | |
1633 | devres_release_group(dev, k3_r5_core_of_init); | |
1634 | } | |
1635 | ||
23168229 | 1636 | static void k3_r5_cluster_of_exit(void *data) |
6dedbd1d | 1637 | { |
23168229 | 1638 | struct k3_r5_cluster *cluster = platform_get_drvdata(data); |
6dedbd1d SA |
1639 | struct platform_device *cpdev; |
1640 | struct k3_r5_core *core, *temp; | |
1641 | ||
1642 | list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) { | |
1643 | list_del(&core->elem); | |
1644 | cpdev = to_platform_device(core->dev); | |
1645 | k3_r5_core_of_exit(cpdev); | |
1646 | } | |
1647 | } | |
1648 | ||
1649 | static int k3_r5_cluster_of_init(struct platform_device *pdev) | |
1650 | { | |
1651 | struct k3_r5_cluster *cluster = platform_get_drvdata(pdev); | |
1652 | struct device *dev = &pdev->dev; | |
1653 | struct device_node *np = dev_of_node(dev); | |
1654 | struct platform_device *cpdev; | |
1655 | struct device_node *child; | |
1656 | struct k3_r5_core *core; | |
1657 | int ret; | |
1658 | ||
1659 | for_each_available_child_of_node(np, child) { | |
1660 | cpdev = of_find_device_by_node(child); | |
1661 | if (!cpdev) { | |
1662 | ret = -ENODEV; | |
1663 | dev_err(dev, "could not get R5 core platform device\n"); | |
fa220c05 | 1664 | of_node_put(child); |
6dedbd1d SA |
1665 | goto fail; |
1666 | } | |
1667 | ||
1668 | ret = k3_r5_core_of_init(cpdev); | |
1669 | if (ret) { | |
1670 | dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n", | |
1671 | ret); | |
1672 | put_device(&cpdev->dev); | |
fa220c05 | 1673 | of_node_put(child); |
6dedbd1d SA |
1674 | goto fail; |
1675 | } | |
1676 | ||
1677 | core = platform_get_drvdata(cpdev); | |
1678 | put_device(&cpdev->dev); | |
1679 | list_add_tail(&core->elem, &cluster->cores); | |
1680 | } | |
1681 | ||
1682 | return 0; | |
1683 | ||
1684 | fail: | |
1685 | k3_r5_cluster_of_exit(pdev); | |
1686 | return ret; | |
1687 | } | |
1688 | ||
1689 | static int k3_r5_probe(struct platform_device *pdev) | |
1690 | { | |
1691 | struct device *dev = &pdev->dev; | |
1692 | struct device_node *np = dev_of_node(dev); | |
1693 | struct k3_r5_cluster *cluster; | |
7508ea19 | 1694 | const struct k3_r5_soc_data *data; |
6dedbd1d SA |
1695 | int ret; |
1696 | int num_cores; | |
1697 | ||
7508ea19 SA |
1698 | data = of_device_get_match_data(&pdev->dev); |
1699 | if (!data) { | |
1700 | dev_err(dev, "SoC-specific data is not defined\n"); | |
1701 | return -ENODEV; | |
1702 | } | |
1703 | ||
6dedbd1d SA |
1704 | cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL); |
1705 | if (!cluster) | |
1706 | return -ENOMEM; | |
1707 | ||
1708 | cluster->dev = dev; | |
7508ea19 | 1709 | cluster->soc_data = data; |
6dedbd1d SA |
1710 | INIT_LIST_HEAD(&cluster->cores); |
1711 | ||
1712 | ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode); | |
1713 | if (ret < 0 && ret != -EINVAL) { | |
1714 | dev_err(dev, "invalid format for ti,cluster-mode, ret = %d\n", | |
1715 | ret); | |
1716 | return ret; | |
1717 | } | |
1718 | ||
7f402919 DT |
1719 | if (ret == -EINVAL) { |
1720 | /* | |
1721 | * default to most common efuse configurations - Split-mode on AM64x | |
1722 | * and LockStep-mode on all others | |
51723657 DT |
1723 | * default to most common efuse configurations - |
1724 | * Split-mode on AM64x | |
1725 | * Single core on AM62x | |
1726 | * LockStep-mode on all others | |
7f402919 | 1727 | */ |
51723657 DT |
1728 | if (!data->is_single_core) |
1729 | cluster->mode = data->single_cpu_mode ? | |
7f402919 | 1730 | CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP; |
51723657 DT |
1731 | else |
1732 | cluster->mode = CLUSTER_MODE_SINGLECORE; | |
7f402919 DT |
1733 | } |
1734 | ||
51723657 DT |
1735 | if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) || |
1736 | (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core)) { | |
7f402919 DT |
1737 | dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode); |
1738 | return -EINVAL; | |
1739 | } | |
1740 | ||
6dedbd1d | 1741 | num_cores = of_get_available_child_count(np); |
51723657 DT |
1742 | if (num_cores != 2 && !data->is_single_core) { |
1743 | dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n", | |
1744 | num_cores); | |
1745 | return -ENODEV; | |
1746 | } | |
1747 | ||
1748 | if (num_cores != 1 && data->is_single_core) { | |
1749 | dev_err(dev, "SoC supports only single core R5 but num_cores is set to %d\n", | |
6dedbd1d SA |
1750 | num_cores); |
1751 | return -ENODEV; | |
1752 | } | |
1753 | ||
1754 | platform_set_drvdata(pdev, cluster); | |
1755 | ||
1756 | ret = devm_of_platform_populate(dev); | |
1757 | if (ret) { | |
1758 | dev_err(dev, "devm_of_platform_populate failed, ret = %d\n", | |
1759 | ret); | |
1760 | return ret; | |
1761 | } | |
1762 | ||
1763 | ret = k3_r5_cluster_of_init(pdev); | |
1764 | if (ret) { | |
1765 | dev_err(dev, "k3_r5_cluster_of_init failed, ret = %d\n", ret); | |
1766 | return ret; | |
1767 | } | |
1768 | ||
23168229 | 1769 | ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev); |
6dedbd1d SA |
1770 | if (ret) |
1771 | return ret; | |
1772 | ||
1773 | ret = k3_r5_cluster_rproc_init(pdev); | |
1774 | if (ret) { | |
1775 | dev_err(dev, "k3_r5_cluster_rproc_init failed, ret = %d\n", | |
1776 | ret); | |
1777 | return ret; | |
1778 | } | |
1779 | ||
23168229 | 1780 | ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev); |
6dedbd1d SA |
1781 | if (ret) |
1782 | return ret; | |
1783 | ||
1784 | return 0; | |
1785 | } | |
1786 | ||
7508ea19 | 1787 | static const struct k3_r5_soc_data am65_j721e_soc_data = { |
c3c21b35 | 1788 | .tcm_is_double = false, |
7508ea19 | 1789 | .tcm_ecc_autoinit = false, |
ee99ee7c | 1790 | .single_cpu_mode = false, |
51723657 | 1791 | .is_single_core = false, |
7508ea19 SA |
1792 | }; |
1793 | ||
b20dc021 | 1794 | static const struct k3_r5_soc_data j7200_j721s2_soc_data = { |
c3c21b35 | 1795 | .tcm_is_double = true, |
7508ea19 | 1796 | .tcm_ecc_autoinit = true, |
ee99ee7c | 1797 | .single_cpu_mode = false, |
51723657 | 1798 | .is_single_core = false, |
ee99ee7c SA |
1799 | }; |
1800 | ||
1801 | static const struct k3_r5_soc_data am64_soc_data = { | |
1802 | .tcm_is_double = true, | |
1803 | .tcm_ecc_autoinit = true, | |
1804 | .single_cpu_mode = true, | |
51723657 DT |
1805 | .is_single_core = false, |
1806 | }; | |
1807 | ||
1808 | static const struct k3_r5_soc_data am62_soc_data = { | |
1809 | .tcm_is_double = false, | |
1810 | .tcm_ecc_autoinit = true, | |
1811 | .single_cpu_mode = false, | |
1812 | .is_single_core = true, | |
7508ea19 SA |
1813 | }; |
1814 | ||
6dedbd1d | 1815 | static const struct of_device_id k3_r5_of_match[] = { |
7508ea19 SA |
1816 | { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, }, |
1817 | { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, }, | |
b20dc021 | 1818 | { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, }, |
ee99ee7c | 1819 | { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, }, |
51723657 | 1820 | { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, }, |
b20dc021 | 1821 | { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, }, |
6dedbd1d SA |
1822 | { /* sentinel */ }, |
1823 | }; | |
1824 | MODULE_DEVICE_TABLE(of, k3_r5_of_match); | |
1825 | ||
1826 | static struct platform_driver k3_r5_rproc_driver = { | |
1827 | .probe = k3_r5_probe, | |
1828 | .driver = { | |
1829 | .name = "k3_r5_rproc", | |
1830 | .of_match_table = k3_r5_of_match, | |
1831 | }, | |
1832 | }; | |
1833 | ||
1834 | module_platform_driver(k3_r5_rproc_driver); | |
1835 | ||
1836 | MODULE_LICENSE("GPL v2"); | |
1837 | MODULE_DESCRIPTION("TI K3 R5F remote processor driver"); | |
1838 | MODULE_AUTHOR("Suman Anna <s-anna@ti.com>"); |