[linux-2.6-block.git] / drivers / remoteproc / qcom_wcnss.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
 *
 * Copyright (C) 2016 Linaro Ltd
 * Copyright (C) 2014 Sony Mobile Communications AB
 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/qcom_scm.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/rpmsg/qcom_smd.h>

#include "qcom_common.h"
#include "remoteproc_internal.h"
#include "qcom_wcnss.h"

#define WCNSS_CRASH_REASON_SMEM		422
#define WCNSS_FIRMWARE_NAME		"wcnss.mdt"
#define WCNSS_PAS_ID			6
#define WCNSS_SSCTL_ID			0x13

#define WCNSS_SPARE_NVBIN_DLND		BIT(25)

#define WCNSS_PMU_IRIS_XO_CFG		BIT(3)
#define WCNSS_PMU_IRIS_XO_EN		BIT(4)
#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP	BIT(5)
#define WCNSS_PMU_IRIS_XO_CFG_STS	BIT(6) /* 1: in progress, 0: done */

#define WCNSS_PMU_IRIS_RESET		BIT(7)
#define WCNSS_PMU_IRIS_RESET_STS	BIT(8) /* 1: in progress, 0: done */
#define WCNSS_PMU_IRIS_XO_READ		BIT(9)
#define WCNSS_PMU_IRIS_XO_READ_STS	BIT(10)

#define WCNSS_PMU_XO_MODE_MASK		GENMASK(2, 1)
#define WCNSS_PMU_XO_MODE_19p2		0
#define WCNSS_PMU_XO_MODE_48		3

struct wcnss_data {
	size_t pmu_offset;
	size_t spare_offset;

	const struct wcnss_vreg_info *vregs;
	size_t num_vregs;
};

struct qcom_wcnss {
	struct device *dev;
	struct rproc *rproc;

	void __iomem *pmu_cfg;
	void __iomem *spare_out;

	bool use_48mhz_xo;

	int wdog_irq;
	int fatal_irq;
	int ready_irq;
	int handover_irq;
	int stop_ack_irq;

	struct qcom_smem_state *state;
	unsigned stop_bit;

	struct mutex iris_lock;
	struct qcom_iris *iris;

	struct regulator_bulk_data *vregs;
	size_t num_vregs;

	struct completion start_done;
	struct completion stop_done;

	phys_addr_t mem_phys;
	phys_addr_t mem_reloc;
	void *mem_region;
	size_t mem_size;

	struct qcom_rproc_subdev smd_subdev;
	struct qcom_sysmon *sysmon;
};

static const struct wcnss_data riva_data = {
	.pmu_offset = 0x28,
	.spare_offset = 0xb4,

	.vregs = (struct wcnss_vreg_info[]) {
		{ "vddmx",  1050000, 1150000, 0 },
		{ "vddcx",  1050000, 1150000, 0 },
		{ "vddpx",  1800000, 1800000, 0 },
	},
	.num_vregs = 3,
};

static const struct wcnss_data pronto_v1_data = {
	.pmu_offset = 0x1004,
	.spare_offset = 0x1088,

	.vregs = (struct wcnss_vreg_info[]) {
		{ "vddmx", 950000, 1150000, 0 },
		{ "vddcx", .super_turbo = true},
		{ "vddpx", 1800000, 1800000, 0 },
	},
	.num_vregs = 3,
};

static const struct wcnss_data pronto_v2_data = {
	.pmu_offset = 0x1004,
	.spare_offset = 0x1088,

	.vregs = (struct wcnss_vreg_info[]) {
		{ "vddmx", 1287500, 1287500, 0 },
		{ "vddcx", .super_turbo = true },
		{ "vddpx", 1800000, 1800000, 0 },
	},
	.num_vregs = 3,
};

void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
			    struct qcom_iris *iris,
			    bool use_48mhz_xo)
{
	mutex_lock(&wcnss->iris_lock);

	wcnss->iris = iris;
	wcnss->use_48mhz_xo = use_48mhz_xo;

	mutex_unlock(&wcnss->iris_lock);
}

static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;

	return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
			     wcnss->mem_region, wcnss->mem_phys,
			     wcnss->mem_size, &wcnss->mem_reloc);
}

static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
{
	u32 val;

	/* Indicate NV download capability */
	val = readl(wcnss->spare_out);
	val |= WCNSS_SPARE_NVBIN_DLND;
	writel(val, wcnss->spare_out);
}

static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
{
	u32 val;

	/* Clear PMU cfg register */
	writel(0, wcnss->pmu_cfg);

	val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
	writel(val, wcnss->pmu_cfg);

	/* Clear XO_MODE */
	val &= ~WCNSS_PMU_XO_MODE_MASK;
	if (wcnss->use_48mhz_xo)
		val |= WCNSS_PMU_XO_MODE_48 << 1;
	else
		val |= WCNSS_PMU_XO_MODE_19p2 << 1;
	writel(val, wcnss->pmu_cfg);

	/* Reset IRIS */
	val |= WCNSS_PMU_IRIS_RESET;
	writel(val, wcnss->pmu_cfg);

	/* Wait for PMU.iris_reg_reset_sts */
	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
		cpu_relax();

	/* Clear IRIS reset */
	val &= ~WCNSS_PMU_IRIS_RESET;
	writel(val, wcnss->pmu_cfg);

	/* Start IRIS XO configuration */
	val |= WCNSS_PMU_IRIS_XO_CFG;
	writel(val, wcnss->pmu_cfg);

	/* Wait for XO configuration to finish */
	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
		cpu_relax();

	/* Stop IRIS XO configuration */
	val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
	val &= ~WCNSS_PMU_IRIS_XO_CFG;
	writel(val, wcnss->pmu_cfg);

	/* Add some delay for XO to settle */
	msleep(20);
}

static int wcnss_start(struct rproc *rproc)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
	int ret;

	mutex_lock(&wcnss->iris_lock);
	if (!wcnss->iris) {
		dev_err(wcnss->dev, "no iris registered\n");
		ret = -EINVAL;
		goto release_iris_lock;
	}

	ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
	if (ret)
		goto release_iris_lock;

	ret = qcom_iris_enable(wcnss->iris);
	if (ret)
		goto disable_regulators;

	wcnss_indicate_nv_download(wcnss);
	wcnss_configure_iris(wcnss);

	ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
	if (ret) {
		dev_err(wcnss->dev,
			"failed to authenticate image and release reset\n");
		goto disable_iris;
	}

	ret = wait_for_completion_timeout(&wcnss->start_done,
					  msecs_to_jiffies(5000));
	if (wcnss->ready_irq > 0 && ret == 0) {
		/* We have a ready_irq, but it didn't fire in time. */
		dev_err(wcnss->dev, "start timed out\n");
		qcom_scm_pas_shutdown(WCNSS_PAS_ID);
		ret = -ETIMEDOUT;
		goto disable_iris;
	}

	ret = 0;

disable_iris:
	qcom_iris_disable(wcnss->iris);
disable_regulators:
	regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
release_iris_lock:
	mutex_unlock(&wcnss->iris_lock);

	return ret;
}

static int wcnss_stop(struct rproc *rproc)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
	int ret;

	if (wcnss->state) {
		qcom_smem_state_update_bits(wcnss->state,
					    BIT(wcnss->stop_bit),
					    BIT(wcnss->stop_bit));

		ret = wait_for_completion_timeout(&wcnss->stop_done,
						  msecs_to_jiffies(5000));
		if (ret == 0)
			dev_err(wcnss->dev, "timed out on wait\n");

		qcom_smem_state_update_bits(wcnss->state,
					    BIT(wcnss->stop_bit),
					    0);
	}

	ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
	if (ret)
		dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);

	return ret;
}

static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len)
{
	struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
	int offset;

	offset = da - wcnss->mem_reloc;
	if (offset < 0 || offset + len > wcnss->mem_size)
		return NULL;

	return wcnss->mem_region + offset;
}

static const struct rproc_ops wcnss_ops = {
	.start = wcnss_start,
	.stop = wcnss_stop,
	.da_to_va = wcnss_da_to_va,
	.parse_fw = qcom_register_dump_segments,
	.load = wcnss_load,
};

static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;

	rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;
	size_t len;
	char *msg;

	msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
	if (!IS_ERR(msg) && len > 0 && msg[0])
		dev_err(wcnss->dev, "fatal error received: %s\n", msg);

	rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;

	complete(&wcnss->start_done);

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
{
	/*
	 * XXX: At this point we're supposed to release the resources that we
	 * have been holding on behalf of the WCNSS. Unfortunately this
	 * interrupt comes way before the other side seems to be done.
	 *
	 * So we're currently relying on the ready interrupt firing later then
	 * this and we just disable the resources at the end of wcnss_start().
	 */

	return IRQ_HANDLED;
}

static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
{
	struct qcom_wcnss *wcnss = dev;

	complete(&wcnss->stop_done);

	return IRQ_HANDLED;
}

static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
				 const struct wcnss_vreg_info *info,
				 int num_vregs)
{
	struct regulator_bulk_data *bulk;
	int ret;
	int i;

	bulk = devm_kcalloc(wcnss->dev,
			    num_vregs, sizeof(struct regulator_bulk_data),
			    GFP_KERNEL);
	if (!bulk)
		return -ENOMEM;

	for (i = 0; i < num_vregs; i++)
		bulk[i].supply = info[i].name;

	ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
	if (ret)
		return ret;

	for (i = 0; i < num_vregs; i++) {
		if (info[i].max_voltage)
			regulator_set_voltage(bulk[i].consumer,
					      info[i].min_voltage,
					      info[i].max_voltage);

		if (info[i].load_uA)
			regulator_set_load(bulk[i].consumer, info[i].load_uA);
	}

	wcnss->vregs = bulk;
	wcnss->num_vregs = num_vregs;

	return 0;
}

static int wcnss_request_irq(struct qcom_wcnss *wcnss,
			     struct platform_device *pdev,
			     const char *name,
			     bool optional,
			     irq_handler_t thread_fn)
{
	int ret;

	ret = platform_get_irq_byname(pdev, name);
	if (ret < 0 && optional) {
		dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
		return 0;
	} else if (ret < 0) {
		dev_err(&pdev->dev, "no %s IRQ defined\n", name);
		return ret;
	}

	ret = devm_request_threaded_irq(&pdev->dev, ret,
					NULL, thread_fn,
					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
					"wcnss", wcnss);
	if (ret)
		dev_err(&pdev->dev, "request %s IRQ failed\n", name);

	return ret;
}

static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
{
	struct device_node *node;
	struct resource r;
	int ret;

	node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
	if (!node) {
		dev_err(wcnss->dev, "no memory-region specified\n");
		return -EINVAL;
	}

	ret = of_address_to_resource(node, 0, &r);
	if (ret)
		return ret;

	wcnss->mem_phys = wcnss->mem_reloc = r.start;
	wcnss->mem_size = resource_size(&r);
	wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
	if (!wcnss->mem_region) {
		dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
			&r.start, wcnss->mem_size);
		return -EBUSY;
	}

	return 0;
}

static int wcnss_probe(struct platform_device *pdev)
{
	const struct wcnss_data *data;
	struct qcom_wcnss *wcnss;
	struct resource *res;
	struct rproc *rproc;
	void __iomem *mmio;
	int ret;

	data = of_device_get_match_data(&pdev->dev);

	if (!qcom_scm_is_available())
		return -EPROBE_DEFER;

	if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
		dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
		return -ENXIO;
	}

	rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
			    WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
	if (!rproc) {
		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
		return -ENOMEM;
	}

	wcnss = (struct qcom_wcnss *)rproc->priv;
	wcnss->dev = &pdev->dev;
	wcnss->rproc = rproc;
	platform_set_drvdata(pdev, wcnss);

	init_completion(&wcnss->start_done);
	init_completion(&wcnss->stop_done);

	mutex_init(&wcnss->iris_lock);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
	mmio = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mmio)) {
		ret = PTR_ERR(mmio);
		goto free_rproc;
	};

	ret = wcnss_alloc_memory_region(wcnss);
	if (ret)
		goto free_rproc;

	wcnss->pmu_cfg = mmio + data->pmu_offset;
	wcnss->spare_out = mmio + data->spare_offset;

	ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
	if (ret)
		goto free_rproc;

	ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
	if (ret < 0)
		goto free_rproc;
	wcnss->wdog_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
	if (ret < 0)
		goto free_rproc;
	wcnss->fatal_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
	if (ret < 0)
		goto free_rproc;
	wcnss->ready_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
	if (ret < 0)
		goto free_rproc;
	wcnss->handover_irq = ret;

	ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
	if (ret < 0)
		goto free_rproc;
	wcnss->stop_ack_irq = ret;

	if (wcnss->stop_ack_irq) {
		wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
						   &wcnss->stop_bit);
		if (IS_ERR(wcnss->state)) {
			ret = PTR_ERR(wcnss->state);
			goto free_rproc;
		}
	}

	qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
	wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
	if (IS_ERR(wcnss->sysmon)) {
		ret = PTR_ERR(wcnss->sysmon);
		goto free_rproc;
	}

	ret = rproc_add(rproc);
	if (ret)
		goto free_rproc;

	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);

free_rproc:
	rproc_free(rproc);

	return ret;
}

static int wcnss_remove(struct platform_device *pdev)
{
	struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);

	of_platform_depopulate(&pdev->dev);

	qcom_smem_state_put(wcnss->state);
	rproc_del(wcnss->rproc);

	qcom_remove_sysmon_subdev(wcnss->sysmon);
	qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
	rproc_free(wcnss->rproc);

	return 0;
}

static const struct of_device_id wcnss_of_match[] = {
	{ .compatible = "qcom,riva-pil", &riva_data },
	{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
	{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
	{ },
};
MODULE_DEVICE_TABLE(of, wcnss_of_match);

static struct platform_driver wcnss_driver = {
	.probe = wcnss_probe,
	.remove = wcnss_remove,
	.driver = {
		.name = "qcom-wcnss-pil",
		.of_match_table = wcnss_of_match,
	},
};

static int __init wcnss_init(void)
{
	int ret;

	ret = platform_driver_register(&wcnss_driver);
	if (ret)
		return ret;

	ret = platform_driver_register(&qcom_iris_driver);
	if (ret)
		platform_driver_unregister(&wcnss_driver);

	return ret;
}
module_init(wcnss_init);

static void __exit wcnss_exit(void)
{
	platform_driver_unregister(&qcom_iris_driver);
	platform_driver_unregister(&wcnss_driver);
}
module_exit(wcnss_exit);

MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
aed361ad BA	2	/*
	3	* Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
	4	*
	5	* Copyright (C) 2016 Linaro Ltd
	6	* Copyright (C) 2014 Sony Mobile Communications AB
	7	* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
aed361ad BA	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/delay.h>
	12	#include <linux/firmware.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/io.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_device.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/qcom_scm.h>
	21	#include <linux/regulator/consumer.h>
	22	#include <linux/remoteproc.h>
2aad40d9	23	#include <linux/soc/qcom/mdt_loader.h>
aed361ad BA	24	#include <linux/soc/qcom/smem.h>
aed361ad BA	25	#include <linux/soc/qcom/smem_state.h>
5a856bc6	26	#include <linux/rpmsg/qcom_smd.h>
aed361ad	27
bde440ee	28	#include "qcom_common.h"
aed361ad BA	29	#include "remoteproc_internal.h"
	30	#include "qcom_wcnss.h"
	31
	32	#define WCNSS_CRASH_REASON_SMEM 422
	33	#define WCNSS_FIRMWARE_NAME "wcnss.mdt"
	34	#define WCNSS_PAS_ID 6
1fb82ee8	35	#define WCNSS_SSCTL_ID 0x13
aed361ad BA	36
	37	#define WCNSS_SPARE_NVBIN_DLND BIT(25)
	38
	39	#define WCNSS_PMU_IRIS_XO_CFG BIT(3)
	40	#define WCNSS_PMU_IRIS_XO_EN BIT(4)
	41	#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
	42	#define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
	43
	44	#define WCNSS_PMU_IRIS_RESET BIT(7)
	45	#define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
	46	#define WCNSS_PMU_IRIS_XO_READ BIT(9)
	47	#define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
	48
	49	#define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
	50	#define WCNSS_PMU_XO_MODE_19p2 0
	51	#define WCNSS_PMU_XO_MODE_48 3
	52
	53	struct wcnss_data {
	54	size_t pmu_offset;
	55	size_t spare_offset;
	56
	57	const struct wcnss_vreg_info *vregs;
	58	size_t num_vregs;
	59	};
	60
	61	struct qcom_wcnss {
	62	struct device *dev;
	63	struct rproc *rproc;
	64
	65	void __iomem *pmu_cfg;
	66	void __iomem *spare_out;
	67
	68	bool use_48mhz_xo;
	69
	70	int wdog_irq;
	71	int fatal_irq;
	72	int ready_irq;
	73	int handover_irq;
	74	int stop_ack_irq;
	75
	76	struct qcom_smem_state *state;
	77	unsigned stop_bit;
	78
	79	struct mutex iris_lock;
	80	struct qcom_iris *iris;
	81
	82	struct regulator_bulk_data *vregs;
	83	size_t num_vregs;
	84
	85	struct completion start_done;
	86	struct completion stop_done;
	87
	88	phys_addr_t mem_phys;
	89	phys_addr_t mem_reloc;
	90	void *mem_region;
	91	size_t mem_size;
5a856bc6	92
b90fcfcb	93	struct qcom_rproc_subdev smd_subdev;
1fb82ee8	94	struct qcom_sysmon *sysmon;
aed361ad BA	95	};
	96
	97	static const struct wcnss_data riva_data = {
	98	.pmu_offset = 0x28,
	99	.spare_offset = 0xb4,
	100
	101	.vregs = (struct wcnss_vreg_info[]) {
	102	{ "vddmx", 1050000, 1150000, 0 },
	103	{ "vddcx", 1050000, 1150000, 0 },
	104	{ "vddpx", 1800000, 1800000, 0 },
	105	},
	106	.num_vregs = 3,
	107	};
	108
	109	static const struct wcnss_data pronto_v1_data = {
	110	.pmu_offset = 0x1004,
	111	.spare_offset = 0x1088,
	112
	113	.vregs = (struct wcnss_vreg_info[]) {
	114	{ "vddmx", 950000, 1150000, 0 },
	115	{ "vddcx", .super_turbo = true},
	116	{ "vddpx", 1800000, 1800000, 0 },
	117	},
	118	.num_vregs = 3,
	119	};
	120
	121	static const struct wcnss_data pronto_v2_data = {
	122	.pmu_offset = 0x1004,
	123	.spare_offset = 0x1088,
	124
	125	.vregs = (struct wcnss_vreg_info[]) {
	126	{ "vddmx", 1287500, 1287500, 0 },
	127	{ "vddcx", .super_turbo = true },
	128	{ "vddpx", 1800000, 1800000, 0 },
	129	},
	130	.num_vregs = 3,
	131	};
	132
	133	void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
	134	struct qcom_iris *iris,
	135	bool use_48mhz_xo)
	136	{
	137	mutex_lock(&wcnss->iris_lock);
	138
	139	wcnss->iris = iris;
	140	wcnss->use_48mhz_xo = use_48mhz_xo;
	141
	142	mutex_unlock(&wcnss->iris_lock);
	143	}
aed361ad BA	144
	145	static int wcnss_load(struct rproc rproc, const struct firmware fw)
	146	{
	147	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
7f0dd07a BA	148
7f0dd07a BA	149	return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
4dd27f54 BA	150	wcnss->mem_region, wcnss->mem_phys,
4dd27f54 BA	151	wcnss->mem_size, &wcnss->mem_reloc);
aed361ad BA	152	}
aed361ad BA	153
aed361ad BA	154	static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
	155	{
	156	u32 val;
	157
	158	/* Indicate NV download capability */
	159	val = readl(wcnss->spare_out);
	160	val \|= WCNSS_SPARE_NVBIN_DLND;
	161	writel(val, wcnss->spare_out);
	162	}
	163
	164	static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
	165	{
	166	u32 val;
	167
	168	/* Clear PMU cfg register */
	169	writel(0, wcnss->pmu_cfg);
	170
	171	val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP \| WCNSS_PMU_IRIS_XO_EN;
	172	writel(val, wcnss->pmu_cfg);
	173
	174	/* Clear XO_MODE */
	175	val &= ~WCNSS_PMU_XO_MODE_MASK;
	176	if (wcnss->use_48mhz_xo)
	177	val \|= WCNSS_PMU_XO_MODE_48 << 1;
	178	else
	179	val \|= WCNSS_PMU_XO_MODE_19p2 << 1;
	180	writel(val, wcnss->pmu_cfg);
	181
	182	/* Reset IRIS */
	183	val \|= WCNSS_PMU_IRIS_RESET;
	184	writel(val, wcnss->pmu_cfg);
	185
	186	/* Wait for PMU.iris_reg_reset_sts */
	187	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
	188	cpu_relax();
	189
	190	/* Clear IRIS reset */
	191	val &= ~WCNSS_PMU_IRIS_RESET;
	192	writel(val, wcnss->pmu_cfg);
	193
	194	/* Start IRIS XO configuration */
	195	val \|= WCNSS_PMU_IRIS_XO_CFG;
	196	writel(val, wcnss->pmu_cfg);
	197
	198	/* Wait for XO configuration to finish */
	199	while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
	200	cpu_relax();
	201
	202	/* Stop IRIS XO configuration */
	203	val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
	204	val &= ~WCNSS_PMU_IRIS_XO_CFG;
	205	writel(val, wcnss->pmu_cfg);
	206
	207	/* Add some delay for XO to settle */
	208	msleep(20);
	209	}
	210
	211	static int wcnss_start(struct rproc *rproc)
	212	{
	213	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
	214	int ret;
	215
	216	mutex_lock(&wcnss->iris_lock);
	217	if (!wcnss->iris) {
218	dev_err(wcnss->dev, "no iris registered\n");
219	ret = -EINVAL;
220	goto release_iris_lock;
221	}
222
223	ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
224	if (ret)
225	goto release_iris_lock;
226
227	ret = qcom_iris_enable(wcnss->iris);
228	if (ret)
229	goto disable_regulators;
230
231	wcnss_indicate_nv_download(wcnss);
232	wcnss_configure_iris(wcnss);
233
234	ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
235	if (ret) {
236	dev_err(wcnss->dev,
237	"failed to authenticate image and release reset\n");
238	goto disable_iris;
239	}
240
241	ret = wait_for_completion_timeout(&wcnss->start_done,
242	msecs_to_jiffies(5000));
243	if (wcnss->ready_irq > 0 && ret == 0) {
244	/* We have a ready_irq, but it didn't fire in time. */
245	dev_err(wcnss->dev, "start timed out\n");
246	qcom_scm_pas_shutdown(WCNSS_PAS_ID);
247	ret = -ETIMEDOUT;
248	goto disable_iris;
249	}
250
251	ret = 0;
252
253	disable_iris:
254	qcom_iris_disable(wcnss->iris);
255	disable_regulators:
256	regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
257	release_iris_lock:
258	mutex_unlock(&wcnss->iris_lock);
259
260	return ret;
261	}
262
263	static int wcnss_stop(struct rproc *rproc)
264	{
265	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
266	int ret;
267
268	if (wcnss->state) {
269	qcom_smem_state_update_bits(wcnss->state,
270	BIT(wcnss->stop_bit),
271	BIT(wcnss->stop_bit));
272
273	ret = wait_for_completion_timeout(&wcnss->stop_done,
274	msecs_to_jiffies(5000));
275	if (ret == 0)
276	dev_err(wcnss->dev, "timed out on wait\n");
277
278	qcom_smem_state_update_bits(wcnss->state,
279	BIT(wcnss->stop_bit),
280	0);
281	}
282
283	ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
284	if (ret)
285	dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
286
287	return ret;
288	}
289
290	static void wcnss_da_to_va(struct rproc rproc, u64 da, int len)
291	{
292	struct qcom_wcnss wcnss = (struct qcom_wcnss )rproc->priv;
293	int offset;
294
295	offset = da - wcnss->mem_reloc;
296	if (offset < 0 \|\| offset + len > wcnss->mem_size)
297	return NULL;
298
299	return wcnss->mem_region + offset;
300	}
301
302	static const struct rproc_ops wcnss_ops = {
303	.start = wcnss_start,
304	.stop = wcnss_stop,
305	.da_to_va = wcnss_da_to_va,
dcb57ed4	306	.parse_fw = qcom_register_dump_segments,
0f21f9cc	307	.load = wcnss_load,
aed361ad BA	308	};
	309
	310	static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
	311	{
	312	struct qcom_wcnss *wcnss = dev;
	313
	314	rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
	315
	316	return IRQ_HANDLED;
	317	}
	318
	319	static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
	320	{
	321	struct qcom_wcnss *wcnss = dev;
	322	size_t len;
	323	char *msg;
	324
	325	msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
	326	if (!IS_ERR(msg) && len > 0 && msg[0])
	327	dev_err(wcnss->dev, "fatal error received: %s\n", msg);
	328
	329	rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
	330
aed361ad BA	331	return IRQ_HANDLED;
	332	}
	333
	334	static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
	335	{
	336	struct qcom_wcnss *wcnss = dev;
	337
	338	complete(&wcnss->start_done);
	339
	340	return IRQ_HANDLED;
	341	}
	342
	343	static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
	344	{
	345	/*
	346	* XXX: At this point we're supposed to release the resources that we
	347	* have been holding on behalf of the WCNSS. Unfortunately this
	348	* interrupt comes way before the other side seems to be done.
	349	*
	350	* So we're currently relying on the ready interrupt firing later then
	351	* this and we just disable the resources at the end of wcnss_start().
	352	*/
	353
	354	return IRQ_HANDLED;
	355	}
	356
	357	static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
	358	{
	359	struct qcom_wcnss *wcnss = dev;
	360
	361	complete(&wcnss->stop_done);
	362
	363	return IRQ_HANDLED;
	364	}
	365
	366	static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
	367	const struct wcnss_vreg_info *info,
	368	int num_vregs)
	369	{
	370	struct regulator_bulk_data *bulk;
	371	int ret;
	372	int i;
	373
	374	bulk = devm_kcalloc(wcnss->dev,
	375	num_vregs, sizeof(struct regulator_bulk_data),
	376	GFP_KERNEL);
	377	if (!bulk)
	378	return -ENOMEM;
	379
	380	for (i = 0; i < num_vregs; i++)
	381	bulk[i].supply = info[i].name;
	382
	383	ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
	384	if (ret)
	385	return ret;
	386
	387	for (i = 0; i < num_vregs; i++) {
	388	if (info[i].max_voltage)
	389	regulator_set_voltage(bulk[i].consumer,
	390	info[i].min_voltage,
	391	info[i].max_voltage);
	392
	393	if (info[i].load_uA)
	394	regulator_set_load(bulk[i].consumer, info[i].load_uA);
395	}
396
397	wcnss->vregs = bulk;
398	wcnss->num_vregs = num_vregs;
399
400	return 0;
401	}
402
403	static int wcnss_request_irq(struct qcom_wcnss *wcnss,
404	struct platform_device *pdev,
405	const char *name,
406	bool optional,
407	irq_handler_t thread_fn)
408	{
409	int ret;
410
411	ret = platform_get_irq_byname(pdev, name);
412	if (ret < 0 && optional) {
413	dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
414	return 0;
415	} else if (ret < 0) {
416	dev_err(&pdev->dev, "no %s IRQ defined\n", name);
417	return ret;
418	}
419
420	ret = devm_request_threaded_irq(&pdev->dev, ret,
421	NULL, thread_fn,
422	IRQF_TRIGGER_RISING \| IRQF_ONESHOT,
423	"wcnss", wcnss);
424	if (ret)
425	dev_err(&pdev->dev, "request %s IRQ failed\n", name);
426
427	return ret;
428	}
429
430	static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
431	{
432	struct device_node *node;
433	struct resource r;
434	int ret;
435
436	node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
437	if (!node) {
438	dev_err(wcnss->dev, "no memory-region specified\n");
439	return -EINVAL;
440	}
441
442	ret = of_address_to_resource(node, 0, &r);
443	if (ret)
444	return ret;
445
446	wcnss->mem_phys = wcnss->mem_reloc = r.start;
447	wcnss->mem_size = resource_size(&r);
448	wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
449	if (!wcnss->mem_region) {
450	dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
451	&r.start, wcnss->mem_size);
452	return -EBUSY;
453	}
454
455	return 0;
456	}
457
458	static int wcnss_probe(struct platform_device *pdev)
459	{
460	const struct wcnss_data *data;
461	struct qcom_wcnss *wcnss;
462	struct resource *res;
463	struct rproc *rproc;
464	void __iomem *mmio;
465	int ret;
466
467	data = of_device_get_match_data(&pdev->dev);
468
469	if (!qcom_scm_is_available())
470	return -EPROBE_DEFER;
471
472	if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
473	dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
474	return -ENXIO;
475	}
476
477	rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
478	WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
479	if (!rproc) {
480	dev_err(&pdev->dev, "unable to allocate remoteproc\n");
481	return -ENOMEM;
482	}
483
aed361ad BA	484	wcnss = (struct qcom_wcnss *)rproc->priv;
	485	wcnss->dev = &pdev->dev;
	486	wcnss->rproc = rproc;
	487	platform_set_drvdata(pdev, wcnss);
	488
	489	init_completion(&wcnss->start_done);
	490	init_completion(&wcnss->stop_done);
	491
	492	mutex_init(&wcnss->iris_lock);
	493
	494	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
	495	mmio = devm_ioremap_resource(&pdev->dev, res);
f4e1f9bb WY	496	if (IS_ERR(mmio)) {
f4e1f9bb WY	497	ret = PTR_ERR(mmio);
aed361ad BA	498	goto free_rproc;
	499	};
	500
	501	ret = wcnss_alloc_memory_region(wcnss);
	502	if (ret)
	503	goto free_rproc;
	504
	505	wcnss->pmu_cfg = mmio + data->pmu_offset;
	506	wcnss->spare_out = mmio + data->spare_offset;
	507
	508	ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
	509	if (ret)
	510	goto free_rproc;
	511
	512	ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
	513	if (ret < 0)
	514	goto free_rproc;
	515	wcnss->wdog_irq = ret;
	516
	517	ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
	518	if (ret < 0)
	519	goto free_rproc;
	520	wcnss->fatal_irq = ret;
	521
	522	ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
	523	if (ret < 0)
	524	goto free_rproc;
	525	wcnss->ready_irq = ret;
	526
	527	ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
	528	if (ret < 0)
	529	goto free_rproc;
	530	wcnss->handover_irq = ret;
	531
	532	ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
	533	if (ret < 0)
	534	goto free_rproc;
	535	wcnss->stop_ack_irq = ret;
	536
	537	if (wcnss->stop_ack_irq) {
	538	wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
	539	&wcnss->stop_bit);
	540	if (IS_ERR(wcnss->state)) {
	541	ret = PTR_ERR(wcnss->state);
	542	goto free_rproc;
	543	}
	544	}
	545
b90fcfcb	546	qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
1fb82ee8	547	wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
027045a6 SS	548	if (IS_ERR(wcnss->sysmon)) {
	549	ret = PTR_ERR(wcnss->sysmon);
	550	goto free_rproc;
	551	}
5a856bc6	552
aed361ad BA	553	ret = rproc_add(rproc);
	554	if (ret)
	555	goto free_rproc;
	556
	557	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	558
	559	free_rproc:
433c0e04	560	rproc_free(rproc);
aed361ad BA	561
	562	return ret;
	563	}
	564
	565	static int wcnss_remove(struct platform_device *pdev)
	566	{
	567	struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
	568
	569	of_platform_depopulate(&pdev->dev);
	570
	571	qcom_smem_state_put(wcnss->state);
	572	rproc_del(wcnss->rproc);
b90fcfcb	573
1fb82ee8	574	qcom_remove_sysmon_subdev(wcnss->sysmon);
b90fcfcb	575	qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
433c0e04	576	rproc_free(wcnss->rproc);
aed361ad BA	577
	578	return 0;
	579	}
	580
	581	static const struct of_device_id wcnss_of_match[] = {
	582	{ .compatible = "qcom,riva-pil", &riva_data },
	583	{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
	584	{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
	585	{ },
	586	};
4958aabb	587	MODULE_DEVICE_TABLE(of, wcnss_of_match);
aed361ad BA	588
	589	static struct platform_driver wcnss_driver = {
	590	.probe = wcnss_probe,
	591	.remove = wcnss_remove,
	592	.driver = {
	593	.name = "qcom-wcnss-pil",
	594	.of_match_table = wcnss_of_match,
	595	},
	596	};
	597
6de1a507 BA	598	static int __init wcnss_init(void)
	599	{
	600	int ret;
	601
	602	ret = platform_driver_register(&wcnss_driver);
	603	if (ret)
	604	return ret;
	605
	606	ret = platform_driver_register(&qcom_iris_driver);
	607	if (ret)
	608	platform_driver_unregister(&wcnss_driver);
	609
	610	return ret;
	611	}
	612	module_init(wcnss_init);
	613
	614	static void __exit wcnss_exit(void)
	615	{
	616	platform_driver_unregister(&qcom_iris_driver);
	617	platform_driver_unregister(&wcnss_driver);
	618	}
	619	module_exit(wcnss_exit);
	620
fff7fca5	621	MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
aed361ad	622	MODULE_LICENSE("GPL v2");