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remoteproc: q6v5: Return irq from q6v5_request_irq()
[linux-2.6-block.git] / drivers / remoteproc / qcom_q6v5_pil.c
CommitLineData
051fb70f
BA		 1/*
2 * Qualcomm Peripheral Image Loader
3 *
4 * Copyright (C) 2016 Linaro Ltd.
5 * Copyright (C) 2014 Sony Mobile Communications AB
6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/dma-mapping.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/mfd/syscon.h>
24#include <linux/module.h>
25#include <linux/of_address.h>
7a8ffe1f 26#include <linux/of_device.h>
051fb70f
BA		 27#include <linux/platform_device.h>
28#include <linux/regmap.h>
29#include <linux/regulator/consumer.h>
30#include <linux/remoteproc.h>
31#include <linux/reset.h>
2aad40d9 32#include <linux/soc/qcom/mdt_loader.h>
051fb70f
BA		 33#include <linux/soc/qcom/smem.h>
34#include <linux/soc/qcom/smem_state.h>
9f058fa2 35#include <linux/iopoll.h>
051fb70f
BA		 36
37#include "remoteproc_internal.h"
bde440ee 38#include "qcom_common.h"
051fb70f
BA		 39
40#include <linux/qcom_scm.h>
41
051fb70f
BA		 42#define MPSS_CRASH_REASON_SMEM 421
43
44/* RMB Status Register Values */
45#define RMB_PBL_SUCCESS 0x1
46
47#define RMB_MBA_XPU_UNLOCKED 0x1
48#define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
49#define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
50#define RMB_MBA_AUTH_COMPLETE 0x4
51
52/* PBL/MBA interface registers */
53#define RMB_MBA_IMAGE_REG 0x00
54#define RMB_PBL_STATUS_REG 0x04
55#define RMB_MBA_COMMAND_REG 0x08
56#define RMB_MBA_STATUS_REG 0x0C
57#define RMB_PMI_META_DATA_REG 0x10
58#define RMB_PMI_CODE_START_REG 0x14
59#define RMB_PMI_CODE_LENGTH_REG 0x18
60
61#define RMB_CMD_META_DATA_READY 0x1
62#define RMB_CMD_LOAD_READY 0x2
63
64/* QDSP6SS Register Offsets */
65#define QDSP6SS_RESET_REG 0x014
66#define QDSP6SS_GFMUX_CTL_REG 0x020
67#define QDSP6SS_PWR_CTL_REG 0x030
9f058fa2
AKD		 68#define QDSP6SS_MEM_PWR_CTL 0x0B0
69#define QDSP6SS_STRAP_ACC 0x110
051fb70f
BA		 70
71/* AXI Halt Register Offsets */
72#define AXI_HALTREQ_REG 0x0
73#define AXI_HALTACK_REG 0x4
74#define AXI_IDLE_REG 0x8
75
76#define HALT_ACK_TIMEOUT_MS 100
77
78/* QDSP6SS_RESET */
79#define Q6SS_STOP_CORE BIT(0)
80#define Q6SS_CORE_ARES BIT(1)
81#define Q6SS_BUS_ARES_ENABLE BIT(2)
82
83/* QDSP6SS_GFMUX_CTL */
84#define Q6SS_CLK_ENABLE BIT(1)
85
86/* QDSP6SS_PWR_CTL */
87#define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
88#define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
89#define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
90#define Q6SS_L2TAG_SLP_NRET_N BIT(16)
91#define Q6SS_ETB_SLP_NRET_N BIT(17)
92#define Q6SS_L2DATA_STBY_N BIT(18)
93#define Q6SS_SLP_RET_N BIT(19)
94#define Q6SS_CLAMP_IO BIT(20)
95#define QDSS_BHS_ON BIT(21)
96#define QDSS_LDO_BYP BIT(22)
97
9f058fa2
AKD		 98/* QDSP6v56 parameters */
99#define QDSP6v56_LDO_BYP BIT(25)
100#define QDSP6v56_BHS_ON BIT(24)
101#define QDSP6v56_CLAMP_WL BIT(21)
102#define QDSP6v56_CLAMP_QMC_MEM BIT(22)
103#define HALT_CHECK_MAX_LOOPS 200
104#define QDSP6SS_XO_CBCR 0x0038
105#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
106
19f902b5
AKD		 107struct reg_info {
108 struct regulator *reg;
109 int uV;
110 int uA;
111};
112
113struct qcom_mss_reg_res {
114 const char *supply;
115 int uV;
116 int uA;
117};
118
7a8ffe1f
AKD		 119struct rproc_hexagon_res {
120 const char *hexagon_mba_image;
ec671b53
AB		 121 struct qcom_mss_reg_res *proxy_supply;
122 struct qcom_mss_reg_res *active_supply;
39b2410b
AKD		 123 char **proxy_clk_names;
124 char **active_clk_names;
9f058fa2 125 int version;
6c5a9dc2 126 bool need_mem_protection;
7a8ffe1f
AKD		 127};
128
051fb70f
BA		 129struct q6v5 {
130 struct device *dev;
131 struct rproc *rproc;
132
133 void __iomem *reg_base;
134 void __iomem *rmb_base;
135
136 struct regmap *halt_map;
137 u32 halt_q6;
138 u32 halt_modem;
139 u32 halt_nc;
140
141 struct reset_control *mss_restart;
142
143 struct qcom_smem_state *state;
144 unsigned stop_bit;
145
39b2410b
AKD		 146 struct clk *active_clks[8];
147 struct clk *proxy_clks[4];
148 int active_clk_count;
149 int proxy_clk_count;
150
19f902b5
AKD		 151 struct reg_info active_regs[1];
152 struct reg_info proxy_regs[3];
153 int active_reg_count;
154 int proxy_reg_count;
051fb70f
BA		 155
156 struct completion start_done;
157 struct completion stop_done;
158 bool running;
159
160 phys_addr_t mba_phys;
161 void *mba_region;
162 size_t mba_size;
163
164 phys_addr_t mpss_phys;
165 phys_addr_t mpss_reloc;
166 void *mpss_region;
167 size_t mpss_size;
4b48921a
BA		 168
169 struct qcom_rproc_subdev smd_subdev;
1e140df0 170 struct qcom_rproc_ssr ssr_subdev;
1fb82ee8 171 struct qcom_sysmon *sysmon;
6c5a9dc2
AKD		 172 bool need_mem_protection;
173 int mpss_perm;
174 int mba_perm;
9f058fa2
AKD		 175 int version;
176};
6c5a9dc2 177
9f058fa2
AKD		 178enum {
179 MSS_MSM8916,
180 MSS_MSM8974,
181 MSS_MSM8996,
051fb70f
BA		 182};
183
19f902b5
AKD		 184static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
185 const struct qcom_mss_reg_res *reg_res)
051fb70f 186{
19f902b5
AKD		 187 int rc;
188 int i;
051fb70f 189
2bb5d906
BA		 190 if (!reg_res)
191 return 0;
192
19f902b5
AKD		 193 for (i = 0; reg_res[i].supply; i++) {
194 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
195 if (IS_ERR(regs[i].reg)) {
196 rc = PTR_ERR(regs[i].reg);
197 if (rc != -EPROBE_DEFER)
198 dev_err(dev, "Failed to get %s\n regulator",
199 reg_res[i].supply);
200 return rc;
201 }
051fb70f 202
19f902b5
AKD		 203 regs[i].uV = reg_res[i].uV;
204 regs[i].uA = reg_res[i].uA;
051fb70f
BA		 205 }
206
19f902b5 207 return i;
051fb70f
BA		 208}
209
19f902b5
AKD		 210static int q6v5_regulator_enable(struct q6v5 *qproc,
211 struct reg_info *regs, int count)
051fb70f 212{
051fb70f 213 int ret;
19f902b5 214 int i;
051fb70f 215
19f902b5
AKD		 216 for (i = 0; i < count; i++) {
217 if (regs[i].uV > 0) {
218 ret = regulator_set_voltage(regs[i].reg,
219 regs[i].uV, INT_MAX);
220 if (ret) {
221 dev_err(qproc->dev,
222 "Failed to request voltage for %d.\n",
223 i);
224 goto err;
225 }
226 }
051fb70f 227
19f902b5
AKD		 228 if (regs[i].uA > 0) {
229 ret = regulator_set_load(regs[i].reg,
230 regs[i].uA);
231 if (ret < 0) {
232 dev_err(qproc->dev,
233 "Failed to set regulator mode\n");
234 goto err;
235 }
236 }
237
238 ret = regulator_enable(regs[i].reg);
239 if (ret) {
240 dev_err(qproc->dev, "Regulator enable failed\n");
241 goto err;
242 }
243 }
244
245 return 0;
246err:
247 for (; i >= 0; i--) {
248 if (regs[i].uV > 0)
249 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
250
251 if (regs[i].uA > 0)
252 regulator_set_load(regs[i].reg, 0);
051fb70f 253
19f902b5
AKD		 254 regulator_disable(regs[i].reg);
255 }
051fb70f 256
19f902b5 257 return ret;
051fb70f
BA		 258}
259
19f902b5
AKD		 260static void q6v5_regulator_disable(struct q6v5 *qproc,
261 struct reg_info *regs, int count)
051fb70f 262{
19f902b5
AKD		 263 int i;
264
265 for (i = 0; i < count; i++) {
266 if (regs[i].uV > 0)
267 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
051fb70f 268
19f902b5
AKD		 269 if (regs[i].uA > 0)
270 regulator_set_load(regs[i].reg, 0);
051fb70f 271
19f902b5
AKD		 272 regulator_disable(regs[i].reg);
273 }
051fb70f
BA		 274}
275
39b2410b
AKD		 276static int q6v5_clk_enable(struct device *dev,
277 struct clk **clks, int count)
278{
279 int rc;
280 int i;
281
282 for (i = 0; i < count; i++) {
283 rc = clk_prepare_enable(clks[i]);
284 if (rc) {
285 dev_err(dev, "Clock enable failed\n");
286 goto err;
287 }
288 }
289
290 return 0;
291err:
292 for (i--; i >= 0; i--)
293 clk_disable_unprepare(clks[i]);
294
295 return rc;
296}
297
298static void q6v5_clk_disable(struct device *dev,
299 struct clk **clks, int count)
300{
301 int i;
302
303 for (i = 0; i < count; i++)
304 clk_disable_unprepare(clks[i]);
305}
306
6c5a9dc2
AKD		 307static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
308 bool remote_owner, phys_addr_t addr,
309 size_t size)
310{
311 struct qcom_scm_vmperm next;
6c5a9dc2
AKD		 312
313 if (!qproc->need_mem_protection)
314 return 0;
315 if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA))
316 return 0;
317 if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS))
318 return 0;
319
320 next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS;
321 next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX;
322
9f2a4342
BA		 323 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
324 current_perm, &next, 1);
6c5a9dc2
AKD		 325}
326
051fb70f
BA		 327static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
328{
329 struct q6v5 *qproc = rproc->priv;
330
331 memcpy(qproc->mba_region, fw->data, fw->size);
332
333 return 0;
334}
335
051fb70f
BA		 336static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
337{
338 unsigned long timeout;
339 s32 val;
340
341 timeout = jiffies + msecs_to_jiffies(ms);
342 for (;;) {
343 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
344 if (val)
345 break;
346
347 if (time_after(jiffies, timeout))
348 return -ETIMEDOUT;
349
350 msleep(1);
351 }
352
353 return val;
354}
355
356static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
357{
358
359 unsigned long timeout;
360 s32 val;
361
362 timeout = jiffies + msecs_to_jiffies(ms);
363 for (;;) {
364 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
365 if (val < 0)
366 break;
367
368 if (!status && val)
369 break;
370 else if (status && val == status)
371 break;
372
373 if (time_after(jiffies, timeout))
374 return -ETIMEDOUT;
375
376 msleep(1);
377 }
378
379 return val;
380}
381
382static int q6v5proc_reset(struct q6v5 *qproc)
383{
384 u32 val;
385 int ret;
9f058fa2 386 int i;
051fb70f 387
051fb70f 388
9f058fa2
AKD		 389 if (qproc->version == MSS_MSM8996) {
390 /* Override the ACC value if required */
391 writel(QDSP6SS_ACC_OVERRIDE_VAL,
392 qproc->reg_base + QDSP6SS_STRAP_ACC);
051fb70f 393
9f058fa2
AKD		 394 /* Assert resets, stop core */
395 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
396 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
397 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
398
399 /* BHS require xo cbcr to be enabled */
400 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
401 val |= 0x1;
402 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
403
404 /* Read CLKOFF bit to go low indicating CLK is enabled */
405 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
406 val, !(val & BIT(31)), 1,
407 HALT_CHECK_MAX_LOOPS);
408 if (ret) {
409 dev_err(qproc->dev,
410 "xo cbcr enabling timed out (rc:%d)\n", ret);
411 return ret;
412 }
413 /* Enable power block headswitch and wait for it to stabilize */
414 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
415 val |= QDSP6v56_BHS_ON;
416 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
417 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
418 udelay(1);
419
420 /* Put LDO in bypass mode */
421 val |= QDSP6v56_LDO_BYP;
422 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
423
424 /* Deassert QDSP6 compiler memory clamp */
425 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
426 val &= ~QDSP6v56_CLAMP_QMC_MEM;
427 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
428
429 /* Deassert memory peripheral sleep and L2 memory standby */
430 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
431 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
432
433 /* Turn on L1, L2, ETB and JU memories 1 at a time */
434 val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
435 for (i = 19; i >= 0; i--) {
436 val |= BIT(i);
437 writel(val, qproc->reg_base +
438 QDSP6SS_MEM_PWR_CTL);
439 /*
440 * Read back value to ensure the write is done then
441 * wait for 1us for both memory peripheral and data
442 * array to turn on.
443 */
444 val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
445 udelay(1);
446 }
447 /* Remove word line clamp */
448 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
449 val &= ~QDSP6v56_CLAMP_WL;
450 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
451 } else {
452 /* Assert resets, stop core */
453 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
454 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
455 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
456
457 /* Enable power block headswitch and wait for it to stabilize */
458 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
459 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
460 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
461 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
462 udelay(1);
463 /*
464 * Turn on memories. L2 banks should be done individually
465 * to minimize inrush current.
466 */
467 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
468 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
469 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
470 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
471 val |= Q6SS_L2DATA_SLP_NRET_N_2;
472 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
473 val |= Q6SS_L2DATA_SLP_NRET_N_1;
474 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
475 val |= Q6SS_L2DATA_SLP_NRET_N_0;
476 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
477 }
051fb70f
BA		 478 /* Remove IO clamp */
479 val &= ~Q6SS_CLAMP_IO;
480 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
481
482 /* Bring core out of reset */
483 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
484 val &= ~Q6SS_CORE_ARES;
485 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
486
487 /* Turn on core clock */
488 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
489 val |= Q6SS_CLK_ENABLE;
490 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
491
492 /* Start core execution */
493 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
494 val &= ~Q6SS_STOP_CORE;
495 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
496
497 /* Wait for PBL status */
498 ret = q6v5_rmb_pbl_wait(qproc, 1000);
499 if (ret == -ETIMEDOUT) {
500 dev_err(qproc->dev, "PBL boot timed out\n");
501 } else if (ret != RMB_PBL_SUCCESS) {
502 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
503 ret = -EINVAL;
504 } else {
505 ret = 0;
506 }
507
508 return ret;
509}
510
511static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
512 struct regmap *halt_map,
513 u32 offset)
514{
515 unsigned long timeout;
516 unsigned int val;
517 int ret;
518
519 /* Check if we're already idle */
520 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
521 if (!ret && val)
522 return;
523
524 /* Assert halt request */
525 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
526
527 /* Wait for halt */
528 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
529 for (;;) {
530 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
531 if (ret || val || time_after(jiffies, timeout))
532 break;
533
534 msleep(1);
535 }
536
537 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
538 if (ret || !val)
539 dev_err(qproc->dev, "port failed halt\n");
540
541 /* Clear halt request (port will remain halted until reset) */
542 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
543}
544
545static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
546{
00085f1e 547 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
051fb70f 548 dma_addr_t phys;
6c5a9dc2
AKD		 549 int mdata_perm;
550 int xferop_ret;
051fb70f
BA		 551 void *ptr;
552 int ret;
553
00085f1e 554 ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, dma_attrs);
051fb70f
BA		 555 if (!ptr) {
556 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
557 return -ENOMEM;
558 }
559
560 memcpy(ptr, fw->data, fw->size);
561
6c5a9dc2
AKD		 562 /* Hypervisor mapping to access metadata by modem */
563 mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
564 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm,
565 true, phys, fw->size);
9f2a4342
BA		 566 if (ret) {
567 dev_err(qproc->dev,
568 "assigning Q6 access to metadata failed: %d\n", ret);
1a5d5c59
CJ		 569 ret = -EAGAIN;
570 goto free_dma_attrs;
9f2a4342 571 }
6c5a9dc2 572
051fb70f
BA		 573 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
574 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
575
576 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
577 if (ret == -ETIMEDOUT)
578 dev_err(qproc->dev, "MPSS header authentication timed out\n");
579 else if (ret < 0)
580 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
581
6c5a9dc2
AKD		 582 /* Metadata authentication done, remove modem access */
583 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm,
584 false, phys, fw->size);
585 if (xferop_ret)
586 dev_warn(qproc->dev,
587 "mdt buffer not reclaimed system may become unstable\n");
588
1a5d5c59 589free_dma_attrs:
00085f1e 590 dma_free_attrs(qproc->dev, fw->size, ptr, phys, dma_attrs);
051fb70f
BA		 591
592 return ret < 0 ? ret : 0;
593}
594
e7fd2522
BA		 595static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
596{
597 if (phdr->p_type != PT_LOAD)
598 return false;
599
600 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
601 return false;
602
603 if (!phdr->p_memsz)
604 return false;
605
606 return true;
607}
608
609static int q6v5_mpss_load(struct q6v5 *qproc)
051fb70f
BA		 610{
611 const struct elf32_phdr *phdrs;
612 const struct elf32_phdr *phdr;
e7fd2522
BA		 613 const struct firmware *seg_fw;
614 const struct firmware *fw;
051fb70f 615 struct elf32_hdr *ehdr;
e7fd2522 616 phys_addr_t mpss_reloc;
051fb70f 617 phys_addr_t boot_addr;
e7fd2522
BA		 618 phys_addr_t min_addr = (phys_addr_t)ULLONG_MAX;
619 phys_addr_t max_addr = 0;
620 bool relocate = false;
621 char seg_name[10];
01625cc5 622 ssize_t offset;
94c90785 623 size_t size = 0;
e7fd2522 624 void *ptr;
051fb70f
BA		 625 int ret;
626 int i;
627
e7fd2522
BA		 628 ret = request_firmware(&fw, "modem.mdt", qproc->dev);
629 if (ret < 0) {
630 dev_err(qproc->dev, "unable to load modem.mdt\n");
051fb70f
BA		 631 return ret;
632 }
633
e7fd2522
BA		 634 /* Initialize the RMB validator */
635 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
636
637 ret = q6v5_mpss_init_image(qproc, fw);
638 if (ret)
639 goto release_firmware;
051fb70f
BA		 640
641 ehdr = (struct elf32_hdr *)fw->data;
642 phdrs = (struct elf32_phdr *)(ehdr + 1);
e7fd2522
BA		 643
644 for (i = 0; i < ehdr->e_phnum; i++) {
051fb70f
BA		 645 phdr = &phdrs[i];
646
e7fd2522 647 if (!q6v5_phdr_valid(phdr))
051fb70f
BA		 648 continue;
649
e7fd2522
BA		 650 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
651 relocate = true;
051fb70f 652
e7fd2522
BA		 653 if (phdr->p_paddr < min_addr)
654 min_addr = phdr->p_paddr;
655
656 if (phdr->p_paddr + phdr->p_memsz > max_addr)
657 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
658 }
659
660 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
94c90785 661 /* Load firmware segments */
e7fd2522
BA		 662 for (i = 0; i < ehdr->e_phnum; i++) {
663 phdr = &phdrs[i];
664
665 if (!q6v5_phdr_valid(phdr))
051fb70f
BA		 666 continue;
667
e7fd2522
BA		 668 offset = phdr->p_paddr - mpss_reloc;
669 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
670 dev_err(qproc->dev, "segment outside memory range\n");
671 ret = -EINVAL;
672 goto release_firmware;
673 }
674
675 ptr = qproc->mpss_region + offset;
676
677 if (phdr->p_filesz) {
678 snprintf(seg_name, sizeof(seg_name), "modem.b%02d", i);
679 ret = request_firmware(&seg_fw, seg_name, qproc->dev);
680 if (ret) {
681 dev_err(qproc->dev, "failed to load %s\n", seg_name);
682 goto release_firmware;
683 }
684
685 memcpy(ptr, seg_fw->data, seg_fw->size);
686
687 release_firmware(seg_fw);
688 }
689
690 if (phdr->p_memsz > phdr->p_filesz) {
691 memset(ptr + phdr->p_filesz, 0,
692 phdr->p_memsz - phdr->p_filesz);
693 }
051fb70f 694 size += phdr->p_memsz;
051fb70f
BA		 695 }
696
6c5a9dc2
AKD		 697 /* Transfer ownership of modem ddr region to q6 */
698 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true,
699 qproc->mpss_phys, qproc->mpss_size);
9f2a4342
BA		 700 if (ret) {
701 dev_err(qproc->dev,
702 "assigning Q6 access to mpss memory failed: %d\n", ret);
1a5d5c59
CJ		 703 ret = -EAGAIN;
704 goto release_firmware;
9f2a4342 705 }
6c5a9dc2 706
94c90785
AKD		 707 boot_addr = relocate ? qproc->mpss_phys : min_addr;
708 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
709 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
710 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
711
72beb490
BA		 712 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
713 if (ret == -ETIMEDOUT)
714 dev_err(qproc->dev, "MPSS authentication timed out\n");
715 else if (ret < 0)
716 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
717
051fb70f
BA		 718release_firmware:
719 release_firmware(fw);
720
721 return ret < 0 ? ret : 0;
722}
723
724static int q6v5_start(struct rproc *rproc)
725{
726 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
6c5a9dc2 727 int xfermemop_ret;
051fb70f
BA		 728 int ret;
729
19f902b5
AKD		 730 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
731 qproc->proxy_reg_count);
051fb70f 732 if (ret) {
19f902b5 733 dev_err(qproc->dev, "failed to enable proxy supplies\n");
051fb70f
BA		 734 return ret;
735 }
736
39b2410b
AKD		 737 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
738 qproc->proxy_clk_count);
739 if (ret) {
740 dev_err(qproc->dev, "failed to enable proxy clocks\n");
19f902b5
AKD		 741 goto disable_proxy_reg;
742 }
743
744 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
745 qproc->active_reg_count);
746 if (ret) {
747 dev_err(qproc->dev, "failed to enable supplies\n");
748 goto disable_proxy_clk;
39b2410b 749 }
051fb70f
BA		 750 ret = reset_control_deassert(qproc->mss_restart);
751 if (ret) {
752 dev_err(qproc->dev, "failed to deassert mss restart\n");
19f902b5 753 goto disable_vdd;
051fb70f
BA		 754 }
755
39b2410b
AKD		 756 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
757 qproc->active_clk_count);
758 if (ret) {
759 dev_err(qproc->dev, "failed to enable clocks\n");
051fb70f 760 goto assert_reset;
39b2410b 761 }
051fb70f 762
6c5a9dc2 763 /* Assign MBA image access in DDR to q6 */
2724807f
SS		 764 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
765 qproc->mba_phys, qproc->mba_size);
766 if (ret) {
9f2a4342 767 dev_err(qproc->dev,
2724807f 768 "assigning Q6 access to mba memory failed: %d\n", ret);
6c5a9dc2 769 goto disable_active_clks;
9f2a4342 770 }
6c5a9dc2 771
051fb70f
BA		 772 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
773
774 ret = q6v5proc_reset(qproc);
775 if (ret)
6c5a9dc2 776 goto reclaim_mba;
051fb70f
BA		 777
778 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
779 if (ret == -ETIMEDOUT) {
780 dev_err(qproc->dev, "MBA boot timed out\n");
781 goto halt_axi_ports;
782 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
783 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
784 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
785 ret = -EINVAL;
786 goto halt_axi_ports;
787 }
788
789 dev_info(qproc->dev, "MBA booted, loading mpss\n");
790
791 ret = q6v5_mpss_load(qproc);
792 if (ret)
6c5a9dc2 793 goto reclaim_mpss;
051fb70f
BA		 794
795 ret = wait_for_completion_timeout(&qproc->start_done,
796 msecs_to_jiffies(5000));
797 if (ret == 0) {
798 dev_err(qproc->dev, "start timed out\n");
799 ret = -ETIMEDOUT;
6c5a9dc2 800 goto reclaim_mpss;
051fb70f
BA		 801 }
802
6c5a9dc2
AKD		 803 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
804 qproc->mba_phys,
805 qproc->mba_size);
806 if (xfermemop_ret)
807 dev_err(qproc->dev,
808 "Failed to reclaim mba buffer system may become unstable\n");
051fb70f
BA		 809 qproc->running = true;
810
39b2410b
AKD		 811 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
812 qproc->proxy_clk_count);
19f902b5
AKD		 813 q6v5_regulator_disable(qproc, qproc->proxy_regs,
814 qproc->proxy_reg_count);
051fb70f
BA		 815
816 return 0;
817
6c5a9dc2
AKD		 818reclaim_mpss:
819 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
820 false, qproc->mpss_phys,
821 qproc->mpss_size);
822 WARN_ON(xfermemop_ret);
823
051fb70f
BA		 824halt_axi_ports:
825 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
826 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
827 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
6c5a9dc2
AKD		 828
829reclaim_mba:
830 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
831 qproc->mba_phys,
832 qproc->mba_size);
833 if (xfermemop_ret) {
834 dev_err(qproc->dev,
835 "Failed to reclaim mba buffer, system may become unstable\n");
836 }
837
838disable_active_clks:
39b2410b
AKD		 839 q6v5_clk_disable(qproc->dev, qproc->active_clks,
840 qproc->active_clk_count);
6c5a9dc2 841
051fb70f
BA		 842assert_reset:
843 reset_control_assert(qproc->mss_restart);
19f902b5
AKD		 844disable_vdd:
845 q6v5_regulator_disable(qproc, qproc->active_regs,
846 qproc->active_reg_count);
39b2410b
AKD		 847disable_proxy_clk:
848 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
849 qproc->proxy_clk_count);
19f902b5
AKD		 850disable_proxy_reg:
851 q6v5_regulator_disable(qproc, qproc->proxy_regs,
852 qproc->proxy_reg_count);
051fb70f
BA		 853
854 return ret;
855}
856
857static int q6v5_stop(struct rproc *rproc)
858{
859 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
860 int ret;
6c5a9dc2 861 u32 val;
051fb70f
BA		 862
863 qproc->running = false;
864
865 qcom_smem_state_update_bits(qproc->state,
866 BIT(qproc->stop_bit), BIT(qproc->stop_bit));
867
868 ret = wait_for_completion_timeout(&qproc->stop_done,
869 msecs_to_jiffies(5000));
870 if (ret == 0)
871 dev_err(qproc->dev, "timed out on wait\n");
872
873 qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
874
875 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
876 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
877 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
9f058fa2
AKD		 878 if (qproc->version == MSS_MSM8996) {
879 /*
880 * To avoid high MX current during LPASS/MSS restart.
881 */
882 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
883 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
884 QDSP6v56_CLAMP_QMC_MEM;
885 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
886 }
887
051fb70f 888
6c5a9dc2
AKD		 889 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false,
890 qproc->mpss_phys, qproc->mpss_size);
891 WARN_ON(ret);
892
051fb70f 893 reset_control_assert(qproc->mss_restart);
39b2410b
AKD		 894 q6v5_clk_disable(qproc->dev, qproc->active_clks,
895 qproc->active_clk_count);
19f902b5
AKD		 896 q6v5_regulator_disable(qproc, qproc->active_regs,
897 qproc->active_reg_count);
051fb70f
BA		 898
899 return 0;
900}
901
902static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
903{
904 struct q6v5 *qproc = rproc->priv;
905 int offset;
906
907 offset = da - qproc->mpss_reloc;
908 if (offset < 0 || offset + len > qproc->mpss_size)
909 return NULL;
910
911 return qproc->mpss_region + offset;
912}
913
914static const struct rproc_ops q6v5_ops = {
915 .start = q6v5_start,
916 .stop = q6v5_stop,
917 .da_to_va = q6v5_da_to_va,
0f21f9cc 918 .load = q6v5_load,
051fb70f
BA		 919};
920
921static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
922{
923 struct q6v5 *qproc = dev;
924 size_t len;
925 char *msg;
926
927 /* Sometimes the stop triggers a watchdog rather than a stop-ack */
928 if (!qproc->running) {
929 complete(&qproc->stop_done);
930 return IRQ_HANDLED;
931 }
932
933 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
934 if (!IS_ERR(msg) && len > 0 && msg[0])
935 dev_err(qproc->dev, "watchdog received: %s\n", msg);
936 else
937 dev_err(qproc->dev, "watchdog without message\n");
938
939 rproc_report_crash(qproc->rproc, RPROC_WATCHDOG);
940
051fb70f
BA		 941 return IRQ_HANDLED;
942}
943
944static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
945{
946 struct q6v5 *qproc = dev;
947 size_t len;
948 char *msg;
949
950 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
951 if (!IS_ERR(msg) && len > 0 && msg[0])
952 dev_err(qproc->dev, "fatal error received: %s\n", msg);
953 else
954 dev_err(qproc->dev, "fatal error without message\n");
955
956 rproc_report_crash(qproc->rproc, RPROC_FATAL_ERROR);
957
051fb70f
BA		 958 return IRQ_HANDLED;
959}
960
961static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
962{
963 struct q6v5 *qproc = dev;
964
965 complete(&qproc->start_done);
966 return IRQ_HANDLED;
967}
968
969static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
970{
971 struct q6v5 *qproc = dev;
972
973 complete(&qproc->stop_done);
974 return IRQ_HANDLED;
975}
976
977static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
978{
979 struct of_phandle_args args;
980 struct resource *res;
981 int ret;
982
983 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
984 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
b1653f23 985 if (IS_ERR(qproc->reg_base))
051fb70f 986 return PTR_ERR(qproc->reg_base);
051fb70f
BA		 987
988 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
989 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
b1653f23 990 if (IS_ERR(qproc->rmb_base))
051fb70f 991 return PTR_ERR(qproc->rmb_base);
051fb70f
BA		 992
993 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
994 "qcom,halt-regs", 3, 0, &args);
995 if (ret < 0) {
996 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
997 return -EINVAL;
998 }
999
1000 qproc->halt_map = syscon_node_to_regmap(args.np);
1001 of_node_put(args.np);
1002 if (IS_ERR(qproc->halt_map))
1003 return PTR_ERR(qproc->halt_map);
1004
1005 qproc->halt_q6 = args.args[0];
1006 qproc->halt_modem = args.args[1];
1007 qproc->halt_nc = args.args[2];
1008
1009 return 0;
1010}
1011
39b2410b
AKD		 1012static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1013 char **clk_names)
051fb70f 1014{
39b2410b 1015 int i;
051fb70f 1016
39b2410b
AKD		 1017 if (!clk_names)
1018 return 0;
1019
1020 for (i = 0; clk_names[i]; i++) {
1021 clks[i] = devm_clk_get(dev, clk_names[i]);
1022 if (IS_ERR(clks[i])) {
1023 int rc = PTR_ERR(clks[i]);
051fb70f 1024
39b2410b
AKD		 1025 if (rc != -EPROBE_DEFER)
1026 dev_err(dev, "Failed to get %s clock\n",
1027 clk_names[i]);
1028 return rc;
1029 }
051fb70f
BA		 1030 }
1031
39b2410b 1032 return i;
051fb70f
BA		 1033}
1034
1035static int q6v5_init_reset(struct q6v5 *qproc)
1036{
5acbf7e5
PZ		 1037 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1038 NULL);
051fb70f
BA		 1039 if (IS_ERR(qproc->mss_restart)) {
1040 dev_err(qproc->dev, "failed to acquire mss restart\n");
1041 return PTR_ERR(qproc->mss_restart);
1042 }
1043
1044 return 0;
1045}
1046
1047static int q6v5_request_irq(struct q6v5 *qproc,
1048 struct platform_device *pdev,
1049 const char *name,
1050 irq_handler_t thread_fn)
1051{
f4c428cf 1052 int irq;
051fb70f
BA		 1053 int ret;
1054
f4c428cf
BA		 1055 irq = platform_get_irq_byname(pdev, name);
1056 if (irq < 0) {
051fb70f 1057 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
f4c428cf 1058 return irq;
051fb70f
BA		 1059 }
1060
f4c428cf 1061 ret = devm_request_threaded_irq(&pdev->dev, irq,
051fb70f
BA		 1062 NULL, thread_fn,
1063 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1064 "q6v5", qproc);
1065 if (ret)
1066 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
1067
f4c428cf 1068 return ret ? : irq;
051fb70f
BA		 1069}
1070
1071static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1072{
1073 struct device_node *child;
1074 struct device_node *node;
1075 struct resource r;
1076 int ret;
1077
1078 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1079 node = of_parse_phandle(child, "memory-region", 0);
1080 ret = of_address_to_resource(node, 0, &r);
1081 if (ret) {
1082 dev_err(qproc->dev, "unable to resolve mba region\n");
1083 return ret;
1084 }
278d744c 1085 of_node_put(node);
051fb70f
BA		 1086
1087 qproc->mba_phys = r.start;
1088 qproc->mba_size = resource_size(&r);
1089 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
1090 if (!qproc->mba_region) {
1091 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1092 &r.start, qproc->mba_size);
1093 return -EBUSY;
1094 }
1095
1096 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1097 node = of_parse_phandle(child, "memory-region", 0);
1098 ret = of_address_to_resource(node, 0, &r);
1099 if (ret) {
1100 dev_err(qproc->dev, "unable to resolve mpss region\n");
1101 return ret;
1102 }
278d744c 1103 of_node_put(node);
051fb70f
BA		 1104
1105 qproc->mpss_phys = qproc->mpss_reloc = r.start;
1106 qproc->mpss_size = resource_size(&r);
1107 qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
1108 if (!qproc->mpss_region) {
1109 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1110 &r.start, qproc->mpss_size);
1111 return -EBUSY;
1112 }
1113
1114 return 0;
1115}
1116
1117static int q6v5_probe(struct platform_device *pdev)
1118{
7a8ffe1f 1119 const struct rproc_hexagon_res *desc;
051fb70f
BA		 1120 struct q6v5 *qproc;
1121 struct rproc *rproc;
1122 int ret;
1123
7a8ffe1f
AKD		 1124 desc = of_device_get_match_data(&pdev->dev);
1125 if (!desc)
1126 return -EINVAL;
1127
051fb70f 1128 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
7a8ffe1f 1129 desc->hexagon_mba_image, sizeof(*qproc));
051fb70f
BA		 1130 if (!rproc) {
1131 dev_err(&pdev->dev, "failed to allocate rproc\n");
1132 return -ENOMEM;
1133 }
1134
051fb70f
BA		 1135 qproc = (struct q6v5 *)rproc->priv;
1136 qproc->dev = &pdev->dev;
1137 qproc->rproc = rproc;
1138 platform_set_drvdata(pdev, qproc);
1139
1140 init_completion(&qproc->start_done);
1141 init_completion(&qproc->stop_done);
1142
1143 ret = q6v5_init_mem(qproc, pdev);
1144 if (ret)
1145 goto free_rproc;
1146
1147 ret = q6v5_alloc_memory_region(qproc);
1148 if (ret)
1149 goto free_rproc;
1150
39b2410b
AKD		 1151 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1152 desc->proxy_clk_names);
1153 if (ret < 0) {
1154 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
051fb70f 1155 goto free_rproc;
39b2410b
AKD		 1156 }
1157 qproc->proxy_clk_count = ret;
1158
1159 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1160 desc->active_clk_names);
1161 if (ret < 0) {
1162 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1163 goto free_rproc;
1164 }
1165 qproc->active_clk_count = ret;
051fb70f 1166
19f902b5
AKD		 1167 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1168 desc->proxy_supply);
1169 if (ret < 0) {
1170 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
051fb70f 1171 goto free_rproc;
19f902b5
AKD		 1172 }
1173 qproc->proxy_reg_count = ret;
1174
1175 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1176 desc->active_supply);
1177 if (ret < 0) {
1178 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1179 goto free_rproc;
1180 }
1181 qproc->active_reg_count = ret;
051fb70f
BA		 1182
1183 ret = q6v5_init_reset(qproc);
1184 if (ret)
1185 goto free_rproc;
1186
9f058fa2 1187 qproc->version = desc->version;
6c5a9dc2 1188 qproc->need_mem_protection = desc->need_mem_protection;
051fb70f
BA		 1189 ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
1190 if (ret < 0)
1191 goto free_rproc;
1192
1193 ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt);
1194 if (ret < 0)
1195 goto free_rproc;
1196
1197 ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
1198 if (ret < 0)
1199 goto free_rproc;
1200
1201 ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
1202 if (ret < 0)
1203 goto free_rproc;
1204
1205 qproc->state = qcom_smem_state_get(&pdev->dev, "stop", &qproc->stop_bit);
4e968d9e
WY		 1206 if (IS_ERR(qproc->state)) {
1207 ret = PTR_ERR(qproc->state);
051fb70f 1208 goto free_rproc;
4e968d9e 1209 }
6c5a9dc2
AKD		 1210 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1211 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
4b48921a 1212 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1e140df0 1213 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1fb82ee8 1214 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
4b48921a 1215
051fb70f
BA		 1216 ret = rproc_add(rproc);
1217 if (ret)
1218 goto free_rproc;
1219
1220 return 0;
1221
1222free_rproc:
433c0e04 1223 rproc_free(rproc);
051fb70f
BA		 1224
1225 return ret;
1226}
1227
1228static int q6v5_remove(struct platform_device *pdev)
1229{
1230 struct q6v5 *qproc = platform_get_drvdata(pdev);
1231
1232 rproc_del(qproc->rproc);
4b48921a 1233
1fb82ee8 1234 qcom_remove_sysmon_subdev(qproc->sysmon);
4b48921a 1235 qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
1e140df0 1236 qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
433c0e04 1237 rproc_free(qproc->rproc);
051fb70f
BA		 1238
1239 return 0;
1240}
1241
9f058fa2
AKD		 1242static const struct rproc_hexagon_res msm8996_mss = {
1243 .hexagon_mba_image = "mba.mbn",
1244 .proxy_clk_names = (char*[]){
1245 "xo",
1246 "pnoc",
1247 NULL
1248 },
1249 .active_clk_names = (char*[]){
1250 "iface",
1251 "bus",
1252 "mem",
1253 "gpll0_mss_clk",
1254 NULL
1255 },
1256 .need_mem_protection = true,
1257 .version = MSS_MSM8996,
1258};
1259
7a8ffe1f
AKD		 1260static const struct rproc_hexagon_res msm8916_mss = {
1261 .hexagon_mba_image = "mba.mbn",
19f902b5
AKD		 1262 .proxy_supply = (struct qcom_mss_reg_res[]) {
1263 {
1264 .supply = "mx",
1265 .uV = 1050000,
1266 },
1267 {
1268 .supply = "cx",
1269 .uA = 100000,
1270 },
1271 {
1272 .supply = "pll",
1273 .uA = 100000,
1274 },
1275 {}
1276 },
39b2410b
AKD		 1277 .proxy_clk_names = (char*[]){
1278 "xo",
1279 NULL
1280 },
1281 .active_clk_names = (char*[]){
1282 "iface",
1283 "bus",
1284 "mem",
1285 NULL
1286 },
6c5a9dc2 1287 .need_mem_protection = false,
9f058fa2 1288 .version = MSS_MSM8916,
7a8ffe1f
AKD		 1289};
1290
1291static const struct rproc_hexagon_res msm8974_mss = {
1292 .hexagon_mba_image = "mba.b00",
19f902b5
AKD		 1293 .proxy_supply = (struct qcom_mss_reg_res[]) {
1294 {
1295 .supply = "mx",
1296 .uV = 1050000,
1297 },
1298 {
1299 .supply = "cx",
1300 .uA = 100000,
1301 },
1302 {
1303 .supply = "pll",
1304 .uA = 100000,
1305 },
1306 {}
1307 },
1308 .active_supply = (struct qcom_mss_reg_res[]) {
1309 {
1310 .supply = "mss",
1311 .uV = 1050000,
1312 .uA = 100000,
1313 },
1314 {}
1315 },
39b2410b
AKD		 1316 .proxy_clk_names = (char*[]){
1317 "xo",
1318 NULL
1319 },
1320 .active_clk_names = (char*[]){
1321 "iface",
1322 "bus",
1323 "mem",
1324 NULL
1325 },
6c5a9dc2 1326 .need_mem_protection = false,
9f058fa2 1327 .version = MSS_MSM8974,
7a8ffe1f
AKD		 1328};
1329
051fb70f 1330static const struct of_device_id q6v5_of_match[] = {
7a8ffe1f
AKD		 1331 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
1332 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
1333 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
9f058fa2 1334 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
051fb70f
BA		 1335 { },
1336};
3227c876 1337MODULE_DEVICE_TABLE(of, q6v5_of_match);
051fb70f
BA		 1338
1339static struct platform_driver q6v5_driver = {
1340 .probe = q6v5_probe,
1341 .remove = q6v5_remove,
1342 .driver = {
1343 .name = "qcom-q6v5-pil",
1344 .of_match_table = q6v5_of_match,
1345 },
1346};
1347module_platform_driver(q6v5_driver);
1348
1349MODULE_DESCRIPTION("Peripheral Image Loader for Hexagon");
1350MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)