[linux-2.6-block.git] / drivers / remoteproc / qcom_q6v5_pas.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
 *
 * Copyright (C) 2016 Linaro Ltd
 * Copyright (C) 2014 Sony Mobile Communications AB
 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
 */

#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/qcom_scm.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>

#include "qcom_common.h"
#include "qcom_q6v5.h"
#include "remoteproc_internal.h"

struct adsp_data {
	int crash_reason_smem;
	const char *firmware_name;
	int pas_id;
	bool has_aggre2_clk;

	const char *ssr_name;
	const char *sysmon_name;
	int ssctl_id;
};

struct qcom_adsp {
	struct device *dev;
	struct rproc *rproc;

	struct qcom_q6v5 q6v5;

	struct clk *xo;
	struct clk *aggre2_clk;

	struct regulator *cx_supply;
	struct regulator *px_supply;

	int pas_id;
	int crash_reason_smem;
	bool has_aggre2_clk;

	struct completion start_done;
	struct completion stop_done;

	phys_addr_t mem_phys;
	phys_addr_t mem_reloc;
	void *mem_region;
	size_t mem_size;

	struct qcom_rproc_glink glink_subdev;
	struct qcom_rproc_subdev smd_subdev;
	struct qcom_rproc_ssr ssr_subdev;
	struct qcom_sysmon *sysmon;
};

static int adsp_load(struct rproc *rproc, const struct firmware *fw)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;

	return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
			     adsp->mem_region, adsp->mem_phys, adsp->mem_size,
			     &adsp->mem_reloc);

}

static int adsp_start(struct rproc *rproc)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int ret;

	qcom_q6v5_prepare(&adsp->q6v5);

	ret = clk_prepare_enable(adsp->xo);
	if (ret)
		return ret;

	ret = clk_prepare_enable(adsp->aggre2_clk);
	if (ret)
		goto disable_xo_clk;

	ret = regulator_enable(adsp->cx_supply);
	if (ret)
		goto disable_aggre2_clk;

	ret = regulator_enable(adsp->px_supply);
	if (ret)
		goto disable_cx_supply;

	ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
	if (ret) {
		dev_err(adsp->dev,
			"failed to authenticate image and release reset\n");
		goto disable_px_supply;
	}

	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
	if (ret == -ETIMEDOUT) {
		dev_err(adsp->dev, "start timed out\n");
		qcom_scm_pas_shutdown(adsp->pas_id);
		goto disable_px_supply;
	}

	return 0;

disable_px_supply:
	regulator_disable(adsp->px_supply);
disable_cx_supply:
	regulator_disable(adsp->cx_supply);
disable_aggre2_clk:
	clk_disable_unprepare(adsp->aggre2_clk);
disable_xo_clk:
	clk_disable_unprepare(adsp->xo);

	return ret;
}

static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
{
	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);

	regulator_disable(adsp->px_supply);
	regulator_disable(adsp->cx_supply);
	clk_disable_unprepare(adsp->aggre2_clk);
	clk_disable_unprepare(adsp->xo);
}

static int adsp_stop(struct rproc *rproc)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int handover;
	int ret;

	ret = qcom_q6v5_request_stop(&adsp->q6v5);
	if (ret == -ETIMEDOUT)
		dev_err(adsp->dev, "timed out on wait\n");

	ret = qcom_scm_pas_shutdown(adsp->pas_id);
	if (ret)
		dev_err(adsp->dev, "failed to shutdown: %d\n", ret);

	handover = qcom_q6v5_unprepare(&adsp->q6v5);
	if (handover)
		qcom_pas_handover(&adsp->q6v5);

	return ret;
}

static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int offset;

	offset = da - adsp->mem_reloc;
	if (offset < 0 || offset + len > adsp->mem_size)
		return NULL;

	return adsp->mem_region + offset;
}

static const struct rproc_ops adsp_ops = {
	.start = adsp_start,
	.stop = adsp_stop,
	.da_to_va = adsp_da_to_va,
	.parse_fw = qcom_register_dump_segments,
	.load = adsp_load,
};

static int adsp_init_clock(struct qcom_adsp *adsp)
{
	int ret;

	adsp->xo = devm_clk_get(adsp->dev, "xo");
	if (IS_ERR(adsp->xo)) {
		ret = PTR_ERR(adsp->xo);
		if (ret != -EPROBE_DEFER)
			dev_err(adsp->dev, "failed to get xo clock");
		return ret;
	}

	if (adsp->has_aggre2_clk) {
		adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
		if (IS_ERR(adsp->aggre2_clk)) {
			ret = PTR_ERR(adsp->aggre2_clk);
			if (ret != -EPROBE_DEFER)
				dev_err(adsp->dev,
					"failed to get aggre2 clock");
			return ret;
		}
	}

	return 0;
}

static int adsp_init_regulator(struct qcom_adsp *adsp)
{
	adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
	if (IS_ERR(adsp->cx_supply))
		return PTR_ERR(adsp->cx_supply);

	regulator_set_load(adsp->cx_supply, 100000);

	adsp->px_supply = devm_regulator_get(adsp->dev, "px");
	return PTR_ERR_OR_ZERO(adsp->px_supply);
}

static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
{
	struct device_node *node;
	struct resource r;
	int ret;

	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
	if (!node) {
		dev_err(adsp->dev, "no memory-region specified\n");
		return -EINVAL;
	}

	ret = of_address_to_resource(node, 0, &r);
	if (ret)
		return ret;

	adsp->mem_phys = adsp->mem_reloc = r.start;
	adsp->mem_size = resource_size(&r);
	adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
	if (!adsp->mem_region) {
		dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
			&r.start, adsp->mem_size);
		return -EBUSY;
	}

	return 0;
}

static int adsp_probe(struct platform_device *pdev)
{
	const struct adsp_data *desc;
	struct qcom_adsp *adsp;
	struct rproc *rproc;
	const char *fw_name;
	int ret;

	desc = of_device_get_match_data(&pdev->dev);
	if (!desc)
		return -EINVAL;

	if (!qcom_scm_is_available())
		return -EPROBE_DEFER;

	fw_name = desc->firmware_name;
	ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
				      &fw_name);
	if (ret < 0 && ret != -EINVAL)
		return ret;

	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
			    fw_name, sizeof(*adsp));
	if (!rproc) {
		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
		return -ENOMEM;
	}

	adsp = (struct qcom_adsp *)rproc->priv;
	adsp->dev = &pdev->dev;
	adsp->rproc = rproc;
	adsp->pas_id = desc->pas_id;
	adsp->has_aggre2_clk = desc->has_aggre2_clk;
	platform_set_drvdata(pdev, adsp);

	ret = adsp_alloc_memory_region(adsp);
	if (ret)
		goto free_rproc;

	ret = adsp_init_clock(adsp);
	if (ret)
		goto free_rproc;

	ret = adsp_init_regulator(adsp);
	if (ret)
		goto free_rproc;

	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
			     qcom_pas_handover);
	if (ret)
		goto free_rproc;

	qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
	qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
					      desc->sysmon_name,
					      desc->ssctl_id);
	if (IS_ERR(adsp->sysmon)) {
		ret = PTR_ERR(adsp->sysmon);
		goto free_rproc;
	}

	ret = rproc_add(rproc);
	if (ret)
		goto free_rproc;

	return 0;

free_rproc:
	rproc_free(rproc);

	return ret;
}

static int adsp_remove(struct platform_device *pdev)
{
	struct qcom_adsp *adsp = platform_get_drvdata(pdev);

	rproc_del(adsp->rproc);

	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
	qcom_remove_sysmon_subdev(adsp->sysmon);
	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
	rproc_free(adsp->rproc);

	return 0;
}

static const struct adsp_data adsp_resource_init = {
		.crash_reason_smem = 423,
		.firmware_name = "adsp.mdt",
		.pas_id = 1,
		.has_aggre2_clk = false,
		.ssr_name = "lpass",
		.sysmon_name = "adsp",
		.ssctl_id = 0x14,
};

static const struct adsp_data cdsp_resource_init = {
	.crash_reason_smem = 601,
	.firmware_name = "cdsp.mdt",
	.pas_id = 18,
	.has_aggre2_clk = false,
	.ssr_name = "cdsp",
	.sysmon_name = "cdsp",
	.ssctl_id = 0x17,
};

static const struct adsp_data slpi_resource_init = {
		.crash_reason_smem = 424,
		.firmware_name = "slpi.mdt",
		.pas_id = 12,
		.has_aggre2_clk = true,
		.ssr_name = "dsps",
		.sysmon_name = "slpi",
		.ssctl_id = 0x16,
};

static const struct adsp_data wcss_resource_init = {
	.crash_reason_smem = 421,
	.firmware_name = "wcnss.mdt",
	.pas_id = 6,
	.ssr_name = "mpss",
	.sysmon_name = "wcnss",
	.ssctl_id = 0x12,
};

static const struct of_device_id adsp_of_match[] = {
	{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
	{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
	{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
	{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
	{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
	{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
	{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);

static struct platform_driver adsp_driver = {
	.probe = adsp_probe,
	.remove = adsp_remove,
	.driver = {
		.name = "qcom_q6v5_pas",
		.of_match_table = adsp_of_match,
	},
};

module_platform_driver(adsp_driver);
MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
b9e718e9	2	/*
90a068ed	3	* Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
b9e718e9 BA	4	*
	5	* Copyright (C) 2016 Linaro Ltd
	6	* Copyright (C) 2014 Sony Mobile Communications AB
	7	* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
b9e718e9 BA	8	*/
b9e718e9 BA	9
f33a7358	10	#include <linux/clk.h>
b9e718e9 BA	11	#include <linux/firmware.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/qcom_scm.h>
	19	#include <linux/regulator/consumer.h>
	20	#include <linux/remoteproc.h>
2aad40d9	21	#include <linux/soc/qcom/mdt_loader.h>
b9e718e9 BA	22	#include <linux/soc/qcom/smem.h>
	23	#include <linux/soc/qcom/smem_state.h>
	24
bde440ee	25	#include "qcom_common.h"
6103b1a6	26	#include "qcom_q6v5.h"
b9e718e9 BA	27	#include "remoteproc_internal.h"
b9e718e9 BA	28
c7715e47 AKD	29	struct adsp_data {
	30	int crash_reason_smem;
	31	const char *firmware_name;
	32	int pas_id;
e323fc03	33	bool has_aggre2_clk;
1fb82ee8	34
1e140df0	35	const char *ssr_name;
1fb82ee8 BA	36	const char *sysmon_name;
1fb82ee8 BA	37	int ssctl_id;
c7715e47	38	};
b9e718e9 BA	39
	40	struct qcom_adsp {
	41	struct device *dev;
	42	struct rproc *rproc;
	43
6103b1a6	44	struct qcom_q6v5 q6v5;
b9e718e9	45
f33a7358	46	struct clk *xo;
e323fc03	47	struct clk *aggre2_clk;
f33a7358	48
b9e718e9	49	struct regulator *cx_supply;
e323fc03	50	struct regulator *px_supply;
b9e718e9	51
c7715e47 AKD	52	int pas_id;
c7715e47 AKD	53	int crash_reason_smem;
e323fc03	54	bool has_aggre2_clk;
c7715e47	55
b9e718e9 BA	56	struct completion start_done;
	57	struct completion stop_done;
	58
	59	phys_addr_t mem_phys;
	60	phys_addr_t mem_reloc;
	61	void *mem_region;
	62	size_t mem_size;
4b48921a	63
eea07023	64	struct qcom_rproc_glink glink_subdev;
4b48921a	65	struct qcom_rproc_subdev smd_subdev;
1e140df0	66	struct qcom_rproc_ssr ssr_subdev;
1fb82ee8	67	struct qcom_sysmon *sysmon;
b9e718e9 BA	68	};
	69
	70	static int adsp_load(struct rproc rproc, const struct firmware fw)
	71	{
	72	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
b9e718e9	73
7f0dd07a	74	return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
4dd27f54 BA	75	adsp->mem_region, adsp->mem_phys, adsp->mem_size,
	76	&adsp->mem_reloc);
	77
b9e718e9 BA	78	}
b9e718e9 BA	79
b9e718e9 BA	80	static int adsp_start(struct rproc *rproc)
	81	{
	82	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
	83	int ret;
	84
6103b1a6 BA	85	qcom_q6v5_prepare(&adsp->q6v5);
6103b1a6 BA	86
f33a7358	87	ret = clk_prepare_enable(adsp->xo);
b9e718e9 BA	88	if (ret)
	89	return ret;
	90
e323fc03 AKD	91	ret = clk_prepare_enable(adsp->aggre2_clk);
	92	if (ret)
	93	goto disable_xo_clk;
	94
f33a7358 SJ	95	ret = regulator_enable(adsp->cx_supply);
f33a7358 SJ	96	if (ret)
e323fc03 AKD	97	goto disable_aggre2_clk;
	98
	99	ret = regulator_enable(adsp->px_supply);
	100	if (ret)
	101	goto disable_cx_supply;
f33a7358	102
c7715e47	103	ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
b9e718e9 BA	104	if (ret) {
	105	dev_err(adsp->dev,
	106	"failed to authenticate image and release reset\n");
e323fc03	107	goto disable_px_supply;
b9e718e9 BA	108	}
b9e718e9 BA	109
6103b1a6 BA	110	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
6103b1a6 BA	111	if (ret == -ETIMEDOUT) {
b9e718e9	112	dev_err(adsp->dev, "start timed out\n");
c7715e47	113	qcom_scm_pas_shutdown(adsp->pas_id);
e323fc03	114	goto disable_px_supply;
b9e718e9 BA	115	}
b9e718e9 BA	116
6103b1a6	117	return 0;
b9e718e9	118
e323fc03 AKD	119	disable_px_supply:
	120	regulator_disable(adsp->px_supply);
	121	disable_cx_supply:
b9e718e9	122	regulator_disable(adsp->cx_supply);
e323fc03 AKD	123	disable_aggre2_clk:
	124	clk_disable_unprepare(adsp->aggre2_clk);
	125	disable_xo_clk:
f33a7358	126	clk_disable_unprepare(adsp->xo);
b9e718e9 BA	127
	128	return ret;
	129	}
	130
6103b1a6 BA	131	static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
	132	{
	133	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
	134
	135	regulator_disable(adsp->px_supply);
	136	regulator_disable(adsp->cx_supply);
	137	clk_disable_unprepare(adsp->aggre2_clk);
	138	clk_disable_unprepare(adsp->xo);
	139	}
	140
b9e718e9 BA	141	static int adsp_stop(struct rproc *rproc)
	142	{
	143	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
6103b1a6	144	int handover;
b9e718e9 BA	145	int ret;
b9e718e9 BA	146
6103b1a6 BA	147	ret = qcom_q6v5_request_stop(&adsp->q6v5);
6103b1a6 BA	148	if (ret == -ETIMEDOUT)
b9e718e9 BA	149	dev_err(adsp->dev, "timed out on wait\n");
b9e718e9 BA	150
c7715e47	151	ret = qcom_scm_pas_shutdown(adsp->pas_id);
b9e718e9 BA	152	if (ret)
	153	dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
	154
6103b1a6 BA	155	handover = qcom_q6v5_unprepare(&adsp->q6v5);
	156	if (handover)
	157	qcom_pas_handover(&adsp->q6v5);
	158
b9e718e9 BA	159	return ret;
	160	}
	161
	162	static void adsp_da_to_va(struct rproc rproc, u64 da, int len)
	163	{
	164	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
	165	int offset;
	166
	167	offset = da - adsp->mem_reloc;
	168	if (offset < 0 \|\| offset + len > adsp->mem_size)
	169	return NULL;
	170
	171	return adsp->mem_region + offset;
	172	}
	173
	174	static const struct rproc_ops adsp_ops = {
	175	.start = adsp_start,
	176	.stop = adsp_stop,
	177	.da_to_va = adsp_da_to_va,
dcb57ed4	178	.parse_fw = qcom_register_dump_segments,
0f21f9cc	179	.load = adsp_load,
b9e718e9 BA	180	};
b9e718e9 BA	181
f33a7358 SJ	182	static int adsp_init_clock(struct qcom_adsp *adsp)
	183	{
	184	int ret;
	185
	186	adsp->xo = devm_clk_get(adsp->dev, "xo");
	187	if (IS_ERR(adsp->xo)) {
	188	ret = PTR_ERR(adsp->xo);
	189	if (ret != -EPROBE_DEFER)
	190	dev_err(adsp->dev, "failed to get xo clock");
	191	return ret;
	192	}
	193
e323fc03 AKD	194	if (adsp->has_aggre2_clk) {
	195	adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
	196	if (IS_ERR(adsp->aggre2_clk)) {
	197	ret = PTR_ERR(adsp->aggre2_clk);
	198	if (ret != -EPROBE_DEFER)
	199	dev_err(adsp->dev,
	200	"failed to get aggre2 clock");
	201	return ret;
	202	}
	203	}
	204
f33a7358 SJ	205	return 0;
	206	}
	207
b9e718e9 BA	208	static int adsp_init_regulator(struct qcom_adsp *adsp)
	209	{
	210	adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
	211	if (IS_ERR(adsp->cx_supply))
	212	return PTR_ERR(adsp->cx_supply);
	213
	214	regulator_set_load(adsp->cx_supply, 100000);
	215
e323fc03	216	adsp->px_supply = devm_regulator_get(adsp->dev, "px");
c76929b3	217	return PTR_ERR_OR_ZERO(adsp->px_supply);
b9e718e9 BA	218	}
b9e718e9 BA	219
b9e718e9 BA	220	static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
	221	{
	222	struct device_node *node;
	223	struct resource r;
	224	int ret;
	225
	226	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
	227	if (!node) {
	228	dev_err(adsp->dev, "no memory-region specified\n");
	229	return -EINVAL;
	230	}
	231
	232	ret = of_address_to_resource(node, 0, &r);
	233	if (ret)
	234	return ret;
	235
	236	adsp->mem_phys = adsp->mem_reloc = r.start;
	237	adsp->mem_size = resource_size(&r);
	238	adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
	239	if (!adsp->mem_region) {
	240	dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
	241	&r.start, adsp->mem_size);
	242	return -EBUSY;
	243	}
	244
	245	return 0;
	246	}
	247
	248	static int adsp_probe(struct platform_device *pdev)
	249	{
c7715e47	250	const struct adsp_data *desc;
b9e718e9 BA	251	struct qcom_adsp *adsp;
b9e718e9 BA	252	struct rproc *rproc;
a5a4e02d	253	const char *fw_name;
b9e718e9 BA	254	int ret;
b9e718e9 BA	255
c7715e47 AKD	256	desc = of_device_get_match_data(&pdev->dev);
	257	if (!desc)
	258	return -EINVAL;
	259
b9e718e9 BA	260	if (!qcom_scm_is_available())
	261	return -EPROBE_DEFER;
	262
a5a4e02d SS	263	fw_name = desc->firmware_name;
	264	ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
	265	&fw_name);
	266	if (ret < 0 && ret != -EINVAL)
	267	return ret;
	268
b9e718e9	269	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
a5a4e02d	270	fw_name, sizeof(*adsp));
b9e718e9 BA	271	if (!rproc) {
	272	dev_err(&pdev->dev, "unable to allocate remoteproc\n");
	273	return -ENOMEM;
	274	}
	275
b9e718e9 BA	276	adsp = (struct qcom_adsp *)rproc->priv;
	277	adsp->dev = &pdev->dev;
	278	adsp->rproc = rproc;
c7715e47	279	adsp->pas_id = desc->pas_id;
e323fc03	280	adsp->has_aggre2_clk = desc->has_aggre2_clk;
b9e718e9 BA	281	platform_set_drvdata(pdev, adsp);
b9e718e9 BA	282
b9e718e9 BA	283	ret = adsp_alloc_memory_region(adsp);
	284	if (ret)
	285	goto free_rproc;
	286
f33a7358 SJ	287	ret = adsp_init_clock(adsp);
	288	if (ret)
	289	goto free_rproc;
	290
b9e718e9 BA	291	ret = adsp_init_regulator(adsp);
	292	if (ret)
	293	goto free_rproc;
	294
6103b1a6 BA	295	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
	296	qcom_pas_handover);
	297	if (ret)
b9e718e9	298	goto free_rproc;
b9e718e9	299
eea07023	300	qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
4b48921a	301	qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
1e140df0	302	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
1fb82ee8 BA	303	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
	304	desc->sysmon_name,
	305	desc->ssctl_id);
027045a6 SS	306	if (IS_ERR(adsp->sysmon)) {
	307	ret = PTR_ERR(adsp->sysmon);
	308	goto free_rproc;
	309	}
4b48921a	310
b9e718e9 BA	311	ret = rproc_add(rproc);
	312	if (ret)
	313	goto free_rproc;
	314
	315	return 0;
	316
	317	free_rproc:
90a80d88	318	rproc_free(rproc);
b9e718e9 BA	319
	320	return ret;
	321	}
	322
	323	static int adsp_remove(struct platform_device *pdev)
	324	{
	325	struct qcom_adsp *adsp = platform_get_drvdata(pdev);
	326
b9e718e9	327	rproc_del(adsp->rproc);
4b48921a	328
eea07023	329	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
1fb82ee8	330	qcom_remove_sysmon_subdev(adsp->sysmon);
4b48921a	331	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
1e140df0	332	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
90a80d88	333	rproc_free(adsp->rproc);
b9e718e9 BA	334
	335	return 0;
	336	}
	337
c7715e47 AKD	338	static const struct adsp_data adsp_resource_init = {
	339	.crash_reason_smem = 423,
	340	.firmware_name = "adsp.mdt",
	341	.pas_id = 1,
e323fc03	342	.has_aggre2_clk = false,
1e140df0	343	.ssr_name = "lpass",
1fb82ee8 BA	344	.sysmon_name = "adsp",
1fb82ee8 BA	345	.ssctl_id = 0x14,
c7715e47 AKD	346	};
c7715e47 AKD	347
3b0d1b65 BA	348	static const struct adsp_data cdsp_resource_init = {
	349	.crash_reason_smem = 601,
	350	.firmware_name = "cdsp.mdt",
	351	.pas_id = 18,
	352	.has_aggre2_clk = false,
	353	.ssr_name = "cdsp",
	354	.sysmon_name = "cdsp",
	355	.ssctl_id = 0x17,
	356	};
	357
90a068ed AKD	358	static const struct adsp_data slpi_resource_init = {
	359	.crash_reason_smem = 424,
	360	.firmware_name = "slpi.mdt",
	361	.pas_id = 12,
	362	.has_aggre2_clk = true,
1e140df0	363	.ssr_name = "dsps",
1fb82ee8 BA	364	.sysmon_name = "slpi",
1fb82ee8 BA	365	.ssctl_id = 0x16,
90a068ed AKD	366	};
90a068ed AKD	367
0af93682 BA	368	static const struct adsp_data wcss_resource_init = {
	369	.crash_reason_smem = 421,
	370	.firmware_name = "wcnss.mdt",
	371	.pas_id = 6,
	372	.ssr_name = "mpss",
	373	.sysmon_name = "wcnss",
	374	.ssctl_id = 0x12,
	375	};
	376
b9e718e9	377	static const struct of_device_id adsp_of_match[] = {
c7715e47 AKD	378	{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
c7715e47 AKD	379	{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
90a068ed	380	{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
0af93682 BA	381	{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
	382	{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
	383	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
3b0d1b65 BA	384	{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
3b0d1b65 BA	385	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
b9e718e9 BA	386	{ },
b9e718e9 BA	387	};
62423472	388	MODULE_DEVICE_TABLE(of, adsp_of_match);
b9e718e9 BA	389
	390	static struct platform_driver adsp_driver = {
	391	.probe = adsp_probe,
	392	.remove = adsp_remove,
	393	.driver = {
9e004f97	394	.name = "qcom_q6v5_pas",
b9e718e9 BA	395	.of_match_table = adsp_of_match,
	396	},
	397	};
	398
	399	module_platform_driver(adsp_driver);
9e004f97	400	MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
b9e718e9	401	MODULE_LICENSE("GPL v2");