[linux-2.6-block.git] / drivers / remoteproc / qcom_q6v5_pas.c

/*
 * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
 *
 * Copyright (C) 2016 Linaro Ltd
 * Copyright (C) 2014 Sony Mobile Communications AB
 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/qcom_scm.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>

#include "qcom_common.h"
#include "qcom_q6v5.h"
#include "remoteproc_internal.h"

struct adsp_data {
	int crash_reason_smem;
	const char *firmware_name;
	int pas_id;
	bool has_aggre2_clk;

	const char *ssr_name;
	const char *sysmon_name;
	int ssctl_id;
};

struct qcom_adsp {
	struct device *dev;
	struct rproc *rproc;

	struct qcom_q6v5 q6v5;

	struct clk *xo;
	struct clk *aggre2_clk;

	struct regulator *cx_supply;
	struct regulator *px_supply;

	int pas_id;
	int crash_reason_smem;
	bool has_aggre2_clk;

	struct completion start_done;
	struct completion stop_done;

	phys_addr_t mem_phys;
	phys_addr_t mem_reloc;
	void *mem_region;
	size_t mem_size;

	struct qcom_rproc_glink glink_subdev;
	struct qcom_rproc_subdev smd_subdev;
	struct qcom_rproc_ssr ssr_subdev;
	struct qcom_sysmon *sysmon;
};

static int adsp_load(struct rproc *rproc, const struct firmware *fw)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;

	return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
			     adsp->mem_region, adsp->mem_phys, adsp->mem_size,
			     &adsp->mem_reloc);

}

static int adsp_start(struct rproc *rproc)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int ret;

	qcom_q6v5_prepare(&adsp->q6v5);

	ret = clk_prepare_enable(adsp->xo);
	if (ret)
		return ret;

	ret = clk_prepare_enable(adsp->aggre2_clk);
	if (ret)
		goto disable_xo_clk;

	ret = regulator_enable(adsp->cx_supply);
	if (ret)
		goto disable_aggre2_clk;

	ret = regulator_enable(adsp->px_supply);
	if (ret)
		goto disable_cx_supply;

	ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
	if (ret) {
		dev_err(adsp->dev,
			"failed to authenticate image and release reset\n");
		goto disable_px_supply;
	}

	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
	if (ret == -ETIMEDOUT) {
		dev_err(adsp->dev, "start timed out\n");
		qcom_scm_pas_shutdown(adsp->pas_id);
		goto disable_px_supply;
	}

	return 0;

disable_px_supply:
	regulator_disable(adsp->px_supply);
disable_cx_supply:
	regulator_disable(adsp->cx_supply);
disable_aggre2_clk:
	clk_disable_unprepare(adsp->aggre2_clk);
disable_xo_clk:
	clk_disable_unprepare(adsp->xo);

	return ret;
}

static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
{
	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);

	regulator_disable(adsp->px_supply);
	regulator_disable(adsp->cx_supply);
	clk_disable_unprepare(adsp->aggre2_clk);
	clk_disable_unprepare(adsp->xo);
}

static int adsp_stop(struct rproc *rproc)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int handover;
	int ret;

	ret = qcom_q6v5_request_stop(&adsp->q6v5);
	if (ret == -ETIMEDOUT)
		dev_err(adsp->dev, "timed out on wait\n");

	ret = qcom_scm_pas_shutdown(adsp->pas_id);
	if (ret)
		dev_err(adsp->dev, "failed to shutdown: %d\n", ret);

	handover = qcom_q6v5_unprepare(&adsp->q6v5);
	if (handover)
		qcom_pas_handover(&adsp->q6v5);

	return ret;
}

static void *adsp_da_to_va(struct rproc *rproc, u64 da, int len)
{
	struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
	int offset;

	offset = da - adsp->mem_reloc;
	if (offset < 0 || offset + len > adsp->mem_size)
		return NULL;

	return adsp->mem_region + offset;
}

static const struct rproc_ops adsp_ops = {
	.start = adsp_start,
	.stop = adsp_stop,
	.da_to_va = adsp_da_to_va,
	.parse_fw = qcom_register_dump_segments,
	.load = adsp_load,
};

static int adsp_init_clock(struct qcom_adsp *adsp)
{
	int ret;

	adsp->xo = devm_clk_get(adsp->dev, "xo");
	if (IS_ERR(adsp->xo)) {
		ret = PTR_ERR(adsp->xo);
		if (ret != -EPROBE_DEFER)
			dev_err(adsp->dev, "failed to get xo clock");
		return ret;
	}

	if (adsp->has_aggre2_clk) {
		adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
		if (IS_ERR(adsp->aggre2_clk)) {
			ret = PTR_ERR(adsp->aggre2_clk);
			if (ret != -EPROBE_DEFER)
				dev_err(adsp->dev,
					"failed to get aggre2 clock");
			return ret;
		}
	}

	return 0;
}

static int adsp_init_regulator(struct qcom_adsp *adsp)
{
	adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
	if (IS_ERR(adsp->cx_supply))
		return PTR_ERR(adsp->cx_supply);

	regulator_set_load(adsp->cx_supply, 100000);

	adsp->px_supply = devm_regulator_get(adsp->dev, "px");
	return PTR_ERR_OR_ZERO(adsp->px_supply);
}

static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
{
	struct device_node *node;
	struct resource r;
	int ret;

	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
	if (!node) {
		dev_err(adsp->dev, "no memory-region specified\n");
		return -EINVAL;
	}

	ret = of_address_to_resource(node, 0, &r);
	if (ret)
		return ret;

	adsp->mem_phys = adsp->mem_reloc = r.start;
	adsp->mem_size = resource_size(&r);
	adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
	if (!adsp->mem_region) {
		dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
			&r.start, adsp->mem_size);
		return -EBUSY;
	}

	return 0;
}

static int adsp_probe(struct platform_device *pdev)
{
	const struct adsp_data *desc;
	struct qcom_adsp *adsp;
	struct rproc *rproc;
	int ret;

	desc = of_device_get_match_data(&pdev->dev);
	if (!desc)
		return -EINVAL;

	if (!qcom_scm_is_available())
		return -EPROBE_DEFER;

	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
			    desc->firmware_name, sizeof(*adsp));
	if (!rproc) {
		dev_err(&pdev->dev, "unable to allocate remoteproc\n");
		return -ENOMEM;
	}

	adsp = (struct qcom_adsp *)rproc->priv;
	adsp->dev = &pdev->dev;
	adsp->rproc = rproc;
	adsp->pas_id = desc->pas_id;
	adsp->has_aggre2_clk = desc->has_aggre2_clk;
	platform_set_drvdata(pdev, adsp);

	ret = adsp_alloc_memory_region(adsp);
	if (ret)
		goto free_rproc;

	ret = adsp_init_clock(adsp);
	if (ret)
		goto free_rproc;

	ret = adsp_init_regulator(adsp);
	if (ret)
		goto free_rproc;

	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
			     qcom_pas_handover);
	if (ret)
		goto free_rproc;

	qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
	qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
					      desc->sysmon_name,
					      desc->ssctl_id);

	ret = rproc_add(rproc);
	if (ret)
		goto free_rproc;

	return 0;

free_rproc:
	rproc_free(rproc);

	return ret;
}

static int adsp_remove(struct platform_device *pdev)
{
	struct qcom_adsp *adsp = platform_get_drvdata(pdev);

	rproc_del(adsp->rproc);

	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
	qcom_remove_sysmon_subdev(adsp->sysmon);
	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
	rproc_free(adsp->rproc);

	return 0;
}

static const struct adsp_data adsp_resource_init = {
		.crash_reason_smem = 423,
		.firmware_name = "adsp.mdt",
		.pas_id = 1,
		.has_aggre2_clk = false,
		.ssr_name = "lpass",
		.sysmon_name = "adsp",
		.ssctl_id = 0x14,
};

static const struct adsp_data cdsp_resource_init = {
	.crash_reason_smem = 601,
	.firmware_name = "cdsp.mdt",
	.pas_id = 18,
	.has_aggre2_clk = false,
	.ssr_name = "cdsp",
	.sysmon_name = "cdsp",
	.ssctl_id = 0x17,
};

static const struct adsp_data slpi_resource_init = {
		.crash_reason_smem = 424,
		.firmware_name = "slpi.mdt",
		.pas_id = 12,
		.has_aggre2_clk = true,
		.ssr_name = "dsps",
		.sysmon_name = "slpi",
		.ssctl_id = 0x16,
};

static const struct adsp_data wcss_resource_init = {
	.crash_reason_smem = 421,
	.firmware_name = "wcnss.mdt",
	.pas_id = 6,
	.ssr_name = "mpss",
	.sysmon_name = "wcnss",
	.ssctl_id = 0x12,
};

static const struct of_device_id adsp_of_match[] = {
	{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
	{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
	{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
	{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
	{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
	{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
	{ },
};
MODULE_DEVICE_TABLE(of, adsp_of_match);

static struct platform_driver adsp_driver = {
	.probe = adsp_probe,
	.remove = adsp_remove,
	.driver = {
		.name = "qcom_q6v5_pas",
		.of_match_table = adsp_of_match,
	},
};

module_platform_driver(adsp_driver);
MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
b9e718e9	1	/*
90a068ed	2	* Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
b9e718e9 BA	3	*
	4	* Copyright (C) 2016 Linaro Ltd
	5	* Copyright (C) 2014 Sony Mobile Communications AB
	6	* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
f33a7358	18	#include <linux/clk.h>
b9e718e9 BA	19	#include <linux/firmware.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/of_address.h>
	24	#include <linux/of_device.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/qcom_scm.h>
	27	#include <linux/regulator/consumer.h>
	28	#include <linux/remoteproc.h>
2aad40d9	29	#include <linux/soc/qcom/mdt_loader.h>
b9e718e9 BA	30	#include <linux/soc/qcom/smem.h>
	31	#include <linux/soc/qcom/smem_state.h>
	32
bde440ee	33	#include "qcom_common.h"
6103b1a6	34	#include "qcom_q6v5.h"
b9e718e9 BA	35	#include "remoteproc_internal.h"
b9e718e9 BA	36
c7715e47 AKD	37	struct adsp_data {
	38	int crash_reason_smem;
	39	const char *firmware_name;
	40	int pas_id;
e323fc03	41	bool has_aggre2_clk;
1fb82ee8	42
1e140df0	43	const char *ssr_name;
1fb82ee8 BA	44	const char *sysmon_name;
1fb82ee8 BA	45	int ssctl_id;
c7715e47	46	};
b9e718e9 BA	47
	48	struct qcom_adsp {
	49	struct device *dev;
	50	struct rproc *rproc;
	51
6103b1a6	52	struct qcom_q6v5 q6v5;
b9e718e9	53
f33a7358	54	struct clk *xo;
e323fc03	55	struct clk *aggre2_clk;
f33a7358	56
b9e718e9	57	struct regulator *cx_supply;
e323fc03	58	struct regulator *px_supply;
b9e718e9	59
c7715e47 AKD	60	int pas_id;
c7715e47 AKD	61	int crash_reason_smem;
e323fc03	62	bool has_aggre2_clk;
c7715e47	63
b9e718e9 BA	64	struct completion start_done;
	65	struct completion stop_done;
	66
	67	phys_addr_t mem_phys;
	68	phys_addr_t mem_reloc;
	69	void *mem_region;
	70	size_t mem_size;
4b48921a	71
eea07023	72	struct qcom_rproc_glink glink_subdev;
4b48921a	73	struct qcom_rproc_subdev smd_subdev;
1e140df0	74	struct qcom_rproc_ssr ssr_subdev;
1fb82ee8	75	struct qcom_sysmon *sysmon;
b9e718e9 BA	76	};
	77
	78	static int adsp_load(struct rproc rproc, const struct firmware fw)
	79	{
	80	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
b9e718e9	81
7f0dd07a	82	return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
4dd27f54 BA	83	adsp->mem_region, adsp->mem_phys, adsp->mem_size,
	84	&adsp->mem_reloc);
	85
b9e718e9 BA	86	}
b9e718e9 BA	87
b9e718e9 BA	88	static int adsp_start(struct rproc *rproc)
	89	{
	90	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
	91	int ret;
	92
6103b1a6 BA	93	qcom_q6v5_prepare(&adsp->q6v5);
6103b1a6 BA	94
f33a7358	95	ret = clk_prepare_enable(adsp->xo);
b9e718e9 BA	96	if (ret)
	97	return ret;
	98
e323fc03 AKD	99	ret = clk_prepare_enable(adsp->aggre2_clk);
	100	if (ret)
	101	goto disable_xo_clk;
	102
f33a7358 SJ	103	ret = regulator_enable(adsp->cx_supply);
f33a7358 SJ	104	if (ret)
e323fc03 AKD	105	goto disable_aggre2_clk;
	106
	107	ret = regulator_enable(adsp->px_supply);
	108	if (ret)
	109	goto disable_cx_supply;
f33a7358	110
c7715e47	111	ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
b9e718e9 BA	112	if (ret) {
	113	dev_err(adsp->dev,
	114	"failed to authenticate image and release reset\n");
e323fc03	115	goto disable_px_supply;
b9e718e9 BA	116	}
b9e718e9 BA	117
6103b1a6 BA	118	ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
6103b1a6 BA	119	if (ret == -ETIMEDOUT) {
b9e718e9	120	dev_err(adsp->dev, "start timed out\n");
c7715e47	121	qcom_scm_pas_shutdown(adsp->pas_id);
e323fc03	122	goto disable_px_supply;
b9e718e9 BA	123	}
b9e718e9 BA	124
6103b1a6	125	return 0;
b9e718e9	126
e323fc03 AKD	127	disable_px_supply:
	128	regulator_disable(adsp->px_supply);
	129	disable_cx_supply:
b9e718e9	130	regulator_disable(adsp->cx_supply);
e323fc03 AKD	131	disable_aggre2_clk:
	132	clk_disable_unprepare(adsp->aggre2_clk);
	133	disable_xo_clk:
f33a7358	134	clk_disable_unprepare(adsp->xo);
b9e718e9 BA	135
	136	return ret;
	137	}
	138
6103b1a6 BA	139	static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
	140	{
	141	struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
	142
	143	regulator_disable(adsp->px_supply);
	144	regulator_disable(adsp->cx_supply);
	145	clk_disable_unprepare(adsp->aggre2_clk);
	146	clk_disable_unprepare(adsp->xo);
	147	}
	148
b9e718e9 BA	149	static int adsp_stop(struct rproc *rproc)
	150	{
	151	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
6103b1a6	152	int handover;
b9e718e9 BA	153	int ret;
b9e718e9 BA	154
6103b1a6 BA	155	ret = qcom_q6v5_request_stop(&adsp->q6v5);
6103b1a6 BA	156	if (ret == -ETIMEDOUT)
b9e718e9 BA	157	dev_err(adsp->dev, "timed out on wait\n");
b9e718e9 BA	158
c7715e47	159	ret = qcom_scm_pas_shutdown(adsp->pas_id);
b9e718e9 BA	160	if (ret)
	161	dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
	162
6103b1a6 BA	163	handover = qcom_q6v5_unprepare(&adsp->q6v5);
	164	if (handover)
	165	qcom_pas_handover(&adsp->q6v5);
	166
b9e718e9 BA	167	return ret;
	168	}
	169
	170	static void adsp_da_to_va(struct rproc rproc, u64 da, int len)
	171	{
	172	struct qcom_adsp adsp = (struct qcom_adsp )rproc->priv;
	173	int offset;
	174
	175	offset = da - adsp->mem_reloc;
	176	if (offset < 0 \|\| offset + len > adsp->mem_size)
	177	return NULL;
	178
	179	return adsp->mem_region + offset;
	180	}
	181
	182	static const struct rproc_ops adsp_ops = {
	183	.start = adsp_start,
	184	.stop = adsp_stop,
	185	.da_to_va = adsp_da_to_va,
dcb57ed4	186	.parse_fw = qcom_register_dump_segments,
0f21f9cc	187	.load = adsp_load,
b9e718e9 BA	188	};
b9e718e9 BA	189
f33a7358 SJ	190	static int adsp_init_clock(struct qcom_adsp *adsp)
	191	{
	192	int ret;
	193
	194	adsp->xo = devm_clk_get(adsp->dev, "xo");
	195	if (IS_ERR(adsp->xo)) {
	196	ret = PTR_ERR(adsp->xo);
	197	if (ret != -EPROBE_DEFER)
	198	dev_err(adsp->dev, "failed to get xo clock");
	199	return ret;
	200	}
	201
e323fc03 AKD	202	if (adsp->has_aggre2_clk) {
	203	adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
	204	if (IS_ERR(adsp->aggre2_clk)) {
	205	ret = PTR_ERR(adsp->aggre2_clk);
	206	if (ret != -EPROBE_DEFER)
	207	dev_err(adsp->dev,
	208	"failed to get aggre2 clock");
	209	return ret;
	210	}
	211	}
	212
f33a7358 SJ	213	return 0;
	214	}
	215
b9e718e9 BA	216	static int adsp_init_regulator(struct qcom_adsp *adsp)
	217	{
	218	adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
	219	if (IS_ERR(adsp->cx_supply))
	220	return PTR_ERR(adsp->cx_supply);
	221
	222	regulator_set_load(adsp->cx_supply, 100000);
	223
e323fc03	224	adsp->px_supply = devm_regulator_get(adsp->dev, "px");
c76929b3	225	return PTR_ERR_OR_ZERO(adsp->px_supply);
b9e718e9 BA	226	}
b9e718e9 BA	227
b9e718e9 BA	228	static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
	229	{
	230	struct device_node *node;
	231	struct resource r;
	232	int ret;
	233
	234	node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
	235	if (!node) {
	236	dev_err(adsp->dev, "no memory-region specified\n");
	237	return -EINVAL;
	238	}
	239
	240	ret = of_address_to_resource(node, 0, &r);
	241	if (ret)
	242	return ret;
	243
	244	adsp->mem_phys = adsp->mem_reloc = r.start;
	245	adsp->mem_size = resource_size(&r);
	246	adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
	247	if (!adsp->mem_region) {
	248	dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
	249	&r.start, adsp->mem_size);
	250	return -EBUSY;
	251	}
	252
	253	return 0;
	254	}
	255
	256	static int adsp_probe(struct platform_device *pdev)
	257	{
c7715e47	258	const struct adsp_data *desc;
b9e718e9 BA	259	struct qcom_adsp *adsp;
	260	struct rproc *rproc;
	261	int ret;
	262
c7715e47 AKD	263	desc = of_device_get_match_data(&pdev->dev);
	264	if (!desc)
	265	return -EINVAL;
	266
b9e718e9 BA	267	if (!qcom_scm_is_available())
	268	return -EPROBE_DEFER;
	269
b9e718e9	270	rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
c7715e47	271	desc->firmware_name, sizeof(*adsp));
b9e718e9 BA	272	if (!rproc) {
	273	dev_err(&pdev->dev, "unable to allocate remoteproc\n");
	274	return -ENOMEM;
	275	}
	276
b9e718e9 BA	277	adsp = (struct qcom_adsp *)rproc->priv;
	278	adsp->dev = &pdev->dev;
	279	adsp->rproc = rproc;
c7715e47	280	adsp->pas_id = desc->pas_id;
e323fc03	281	adsp->has_aggre2_clk = desc->has_aggre2_clk;
b9e718e9 BA	282	platform_set_drvdata(pdev, adsp);
b9e718e9 BA	283
b9e718e9 BA	284	ret = adsp_alloc_memory_region(adsp);
	285	if (ret)
	286	goto free_rproc;
	287
f33a7358 SJ	288	ret = adsp_init_clock(adsp);
	289	if (ret)
	290	goto free_rproc;
	291
b9e718e9 BA	292	ret = adsp_init_regulator(adsp);
	293	if (ret)
	294	goto free_rproc;
	295
6103b1a6 BA	296	ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
	297	qcom_pas_handover);
	298	if (ret)
b9e718e9	299	goto free_rproc;
b9e718e9	300
eea07023	301	qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
4b48921a	302	qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
1e140df0	303	qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
1fb82ee8 BA	304	adsp->sysmon = qcom_add_sysmon_subdev(rproc,
	305	desc->sysmon_name,
	306	desc->ssctl_id);
4b48921a	307
b9e718e9 BA	308	ret = rproc_add(rproc);
	309	if (ret)
	310	goto free_rproc;
	311
	312	return 0;
	313
	314	free_rproc:
90a80d88	315	rproc_free(rproc);
b9e718e9 BA	316
	317	return ret;
	318	}
	319
	320	static int adsp_remove(struct platform_device *pdev)
	321	{
	322	struct qcom_adsp *adsp = platform_get_drvdata(pdev);
	323
b9e718e9	324	rproc_del(adsp->rproc);
4b48921a	325
eea07023	326	qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
1fb82ee8	327	qcom_remove_sysmon_subdev(adsp->sysmon);
4b48921a	328	qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
1e140df0	329	qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
90a80d88	330	rproc_free(adsp->rproc);
b9e718e9 BA	331
	332	return 0;
	333	}
	334
c7715e47 AKD	335	static const struct adsp_data adsp_resource_init = {
	336	.crash_reason_smem = 423,
	337	.firmware_name = "adsp.mdt",
	338	.pas_id = 1,
e323fc03	339	.has_aggre2_clk = false,
1e140df0	340	.ssr_name = "lpass",
1fb82ee8 BA	341	.sysmon_name = "adsp",
1fb82ee8 BA	342	.ssctl_id = 0x14,
c7715e47 AKD	343	};
c7715e47 AKD	344
3b0d1b65 BA	345	static const struct adsp_data cdsp_resource_init = {
	346	.crash_reason_smem = 601,
	347	.firmware_name = "cdsp.mdt",
	348	.pas_id = 18,
	349	.has_aggre2_clk = false,
	350	.ssr_name = "cdsp",
	351	.sysmon_name = "cdsp",
	352	.ssctl_id = 0x17,
	353	};
	354
90a068ed AKD	355	static const struct adsp_data slpi_resource_init = {
	356	.crash_reason_smem = 424,
	357	.firmware_name = "slpi.mdt",
	358	.pas_id = 12,
	359	.has_aggre2_clk = true,
1e140df0	360	.ssr_name = "dsps",
1fb82ee8 BA	361	.sysmon_name = "slpi",
1fb82ee8 BA	362	.ssctl_id = 0x16,
90a068ed AKD	363	};
90a068ed AKD	364
0af93682 BA	365	static const struct adsp_data wcss_resource_init = {
	366	.crash_reason_smem = 421,
	367	.firmware_name = "wcnss.mdt",
	368	.pas_id = 6,
	369	.ssr_name = "mpss",
	370	.sysmon_name = "wcnss",
	371	.ssctl_id = 0x12,
	372	};
	373
b9e718e9	374	static const struct of_device_id adsp_of_match[] = {
c7715e47 AKD	375	{ .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
c7715e47 AKD	376	{ .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
90a068ed	377	{ .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
0af93682 BA	378	{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
	379	{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
	380	{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
3b0d1b65 BA	381	{ .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
3b0d1b65 BA	382	{ .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
b9e718e9 BA	383	{ },
b9e718e9 BA	384	};
62423472	385	MODULE_DEVICE_TABLE(of, adsp_of_match);
b9e718e9 BA	386
	387	static struct platform_driver adsp_driver = {
	388	.probe = adsp_probe,
	389	.remove = adsp_remove,
	390	.driver = {
9e004f97	391	.name = "qcom_q6v5_pas",
b9e718e9 BA	392	.of_match_table = adsp_of_match,
	393	},
	394	};
	395
	396	module_platform_driver(adsp_driver);
9e004f97	397	MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
b9e718e9	398	MODULE_LICENSE("GPL v2");