Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
051fb70f | 2 | /* |
ef73c22f | 3 | * Qualcomm self-authenticating modem subsystem remoteproc driver |
051fb70f BA |
4 | * |
5 | * Copyright (C) 2016 Linaro Ltd. | |
6 | * Copyright (C) 2014 Sony Mobile Communications AB | |
7 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. | |
051fb70f BA |
8 | */ |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/dma-mapping.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/mfd/syscon.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_address.h> | |
7a8ffe1f | 18 | #include <linux/of_device.h> |
051fb70f | 19 | #include <linux/platform_device.h> |
4760a896 RN |
20 | #include <linux/pm_domain.h> |
21 | #include <linux/pm_runtime.h> | |
051fb70f BA |
22 | #include <linux/regmap.h> |
23 | #include <linux/regulator/consumer.h> | |
24 | #include <linux/remoteproc.h> | |
25 | #include <linux/reset.h> | |
2aad40d9 | 26 | #include <linux/soc/qcom/mdt_loader.h> |
9f058fa2 | 27 | #include <linux/iopoll.h> |
051fb70f BA |
28 | |
29 | #include "remoteproc_internal.h" | |
bde440ee | 30 | #include "qcom_common.h" |
7d674731 | 31 | #include "qcom_q6v5.h" |
051fb70f BA |
32 | |
33 | #include <linux/qcom_scm.h> | |
34 | ||
051fb70f BA |
35 | #define MPSS_CRASH_REASON_SMEM 421 |
36 | ||
37 | /* RMB Status Register Values */ | |
38 | #define RMB_PBL_SUCCESS 0x1 | |
39 | ||
40 | #define RMB_MBA_XPU_UNLOCKED 0x1 | |
41 | #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2 | |
42 | #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3 | |
43 | #define RMB_MBA_AUTH_COMPLETE 0x4 | |
44 | ||
45 | /* PBL/MBA interface registers */ | |
46 | #define RMB_MBA_IMAGE_REG 0x00 | |
47 | #define RMB_PBL_STATUS_REG 0x04 | |
48 | #define RMB_MBA_COMMAND_REG 0x08 | |
49 | #define RMB_MBA_STATUS_REG 0x0C | |
50 | #define RMB_PMI_META_DATA_REG 0x10 | |
51 | #define RMB_PMI_CODE_START_REG 0x14 | |
52 | #define RMB_PMI_CODE_LENGTH_REG 0x18 | |
231f67d1 SS |
53 | #define RMB_MBA_MSS_STATUS 0x40 |
54 | #define RMB_MBA_ALT_RESET 0x44 | |
051fb70f BA |
55 | |
56 | #define RMB_CMD_META_DATA_READY 0x1 | |
57 | #define RMB_CMD_LOAD_READY 0x2 | |
58 | ||
59 | /* QDSP6SS Register Offsets */ | |
60 | #define QDSP6SS_RESET_REG 0x014 | |
61 | #define QDSP6SS_GFMUX_CTL_REG 0x020 | |
62 | #define QDSP6SS_PWR_CTL_REG 0x030 | |
9f058fa2 | 63 | #define QDSP6SS_MEM_PWR_CTL 0x0B0 |
1665cbd5 | 64 | #define QDSP6V6SS_MEM_PWR_CTL 0x034 |
9f058fa2 | 65 | #define QDSP6SS_STRAP_ACC 0x110 |
051fb70f BA |
66 | |
67 | /* AXI Halt Register Offsets */ | |
68 | #define AXI_HALTREQ_REG 0x0 | |
69 | #define AXI_HALTACK_REG 0x4 | |
70 | #define AXI_IDLE_REG 0x8 | |
6439b527 SS |
71 | #define NAV_AXI_HALTREQ_BIT BIT(0) |
72 | #define NAV_AXI_HALTACK_BIT BIT(1) | |
73 | #define NAV_AXI_IDLE_BIT BIT(2) | |
051fb70f BA |
74 | |
75 | #define HALT_ACK_TIMEOUT_MS 100 | |
76 | ||
77 | /* QDSP6SS_RESET */ | |
78 | #define Q6SS_STOP_CORE BIT(0) | |
79 | #define Q6SS_CORE_ARES BIT(1) | |
80 | #define Q6SS_BUS_ARES_ENABLE BIT(2) | |
81 | ||
82 | /* QDSP6SS_GFMUX_CTL */ | |
83 | #define Q6SS_CLK_ENABLE BIT(1) | |
84 | ||
85 | /* QDSP6SS_PWR_CTL */ | |
86 | #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0) | |
87 | #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1) | |
88 | #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2) | |
89 | #define Q6SS_L2TAG_SLP_NRET_N BIT(16) | |
90 | #define Q6SS_ETB_SLP_NRET_N BIT(17) | |
91 | #define Q6SS_L2DATA_STBY_N BIT(18) | |
92 | #define Q6SS_SLP_RET_N BIT(19) | |
93 | #define Q6SS_CLAMP_IO BIT(20) | |
94 | #define QDSS_BHS_ON BIT(21) | |
95 | #define QDSS_LDO_BYP BIT(22) | |
96 | ||
9f058fa2 AKD |
97 | /* QDSP6v56 parameters */ |
98 | #define QDSP6v56_LDO_BYP BIT(25) | |
99 | #define QDSP6v56_BHS_ON BIT(24) | |
100 | #define QDSP6v56_CLAMP_WL BIT(21) | |
101 | #define QDSP6v56_CLAMP_QMC_MEM BIT(22) | |
102 | #define HALT_CHECK_MAX_LOOPS 200 | |
103 | #define QDSP6SS_XO_CBCR 0x0038 | |
104 | #define QDSP6SS_ACC_OVERRIDE_VAL 0x20 | |
105 | ||
231f67d1 | 106 | /* QDSP6v65 parameters */ |
6439b527 | 107 | #define QDSP6SS_CORE_CBCR 0x20 |
231f67d1 SS |
108 | #define QDSP6SS_SLEEP 0x3C |
109 | #define QDSP6SS_BOOT_CORE_START 0x400 | |
110 | #define QDSP6SS_BOOT_CMD 0x404 | |
6439b527 | 111 | #define QDSP6SS_BOOT_STATUS 0x408 |
231f67d1 SS |
112 | #define SLEEP_CHECK_MAX_LOOPS 200 |
113 | #define BOOT_FSM_TIMEOUT 10000 | |
114 | ||
19f902b5 AKD |
115 | struct reg_info { |
116 | struct regulator *reg; | |
117 | int uV; | |
118 | int uA; | |
119 | }; | |
120 | ||
121 | struct qcom_mss_reg_res { | |
122 | const char *supply; | |
123 | int uV; | |
124 | int uA; | |
125 | }; | |
126 | ||
7a8ffe1f AKD |
127 | struct rproc_hexagon_res { |
128 | const char *hexagon_mba_image; | |
ec671b53 AB |
129 | struct qcom_mss_reg_res *proxy_supply; |
130 | struct qcom_mss_reg_res *active_supply; | |
39b2410b | 131 | char **proxy_clk_names; |
231f67d1 | 132 | char **reset_clk_names; |
39b2410b | 133 | char **active_clk_names; |
deb9bb83 | 134 | char **active_pd_names; |
4760a896 | 135 | char **proxy_pd_names; |
9f058fa2 | 136 | int version; |
6c5a9dc2 | 137 | bool need_mem_protection; |
231f67d1 | 138 | bool has_alt_reset; |
6439b527 | 139 | bool has_halt_nav; |
7a8ffe1f AKD |
140 | }; |
141 | ||
051fb70f BA |
142 | struct q6v5 { |
143 | struct device *dev; | |
144 | struct rproc *rproc; | |
145 | ||
146 | void __iomem *reg_base; | |
147 | void __iomem *rmb_base; | |
148 | ||
149 | struct regmap *halt_map; | |
6439b527 SS |
150 | struct regmap *halt_nav_map; |
151 | struct regmap *conn_map; | |
152 | ||
051fb70f BA |
153 | u32 halt_q6; |
154 | u32 halt_modem; | |
155 | u32 halt_nc; | |
6439b527 SS |
156 | u32 halt_nav; |
157 | u32 conn_box; | |
051fb70f BA |
158 | |
159 | struct reset_control *mss_restart; | |
29a5f9aa | 160 | struct reset_control *pdc_reset; |
051fb70f | 161 | |
7d674731 | 162 | struct qcom_q6v5 q6v5; |
663e9845 | 163 | |
39b2410b | 164 | struct clk *active_clks[8]; |
231f67d1 | 165 | struct clk *reset_clks[4]; |
39b2410b | 166 | struct clk *proxy_clks[4]; |
deb9bb83 | 167 | struct device *active_pds[1]; |
4760a896 | 168 | struct device *proxy_pds[3]; |
39b2410b | 169 | int active_clk_count; |
231f67d1 | 170 | int reset_clk_count; |
39b2410b | 171 | int proxy_clk_count; |
deb9bb83 | 172 | int active_pd_count; |
4760a896 | 173 | int proxy_pd_count; |
39b2410b | 174 | |
19f902b5 AKD |
175 | struct reg_info active_regs[1]; |
176 | struct reg_info proxy_regs[3]; | |
177 | int active_reg_count; | |
178 | int proxy_reg_count; | |
051fb70f | 179 | |
051fb70f BA |
180 | bool running; |
181 | ||
0304530d | 182 | bool dump_mba_loaded; |
7dd8ade2 SS |
183 | unsigned long dump_segment_mask; |
184 | unsigned long dump_complete_mask; | |
185 | ||
051fb70f BA |
186 | phys_addr_t mba_phys; |
187 | void *mba_region; | |
188 | size_t mba_size; | |
189 | ||
190 | phys_addr_t mpss_phys; | |
191 | phys_addr_t mpss_reloc; | |
192 | void *mpss_region; | |
193 | size_t mpss_size; | |
4b48921a | 194 | |
4725496e | 195 | struct qcom_rproc_glink glink_subdev; |
4b48921a | 196 | struct qcom_rproc_subdev smd_subdev; |
1e140df0 | 197 | struct qcom_rproc_ssr ssr_subdev; |
1fb82ee8 | 198 | struct qcom_sysmon *sysmon; |
6c5a9dc2 | 199 | bool need_mem_protection; |
231f67d1 | 200 | bool has_alt_reset; |
6439b527 | 201 | bool has_halt_nav; |
6c5a9dc2 AKD |
202 | int mpss_perm; |
203 | int mba_perm; | |
a5a4e02d | 204 | const char *hexagon_mdt_image; |
9f058fa2 AKD |
205 | int version; |
206 | }; | |
6c5a9dc2 | 207 | |
9f058fa2 AKD |
208 | enum { |
209 | MSS_MSM8916, | |
210 | MSS_MSM8974, | |
211 | MSS_MSM8996, | |
1665cbd5 | 212 | MSS_MSM8998, |
6439b527 | 213 | MSS_SC7180, |
231f67d1 | 214 | MSS_SDM845, |
051fb70f BA |
215 | }; |
216 | ||
19f902b5 AKD |
217 | static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, |
218 | const struct qcom_mss_reg_res *reg_res) | |
051fb70f | 219 | { |
19f902b5 AKD |
220 | int rc; |
221 | int i; | |
051fb70f | 222 | |
2bb5d906 BA |
223 | if (!reg_res) |
224 | return 0; | |
225 | ||
19f902b5 AKD |
226 | for (i = 0; reg_res[i].supply; i++) { |
227 | regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); | |
228 | if (IS_ERR(regs[i].reg)) { | |
229 | rc = PTR_ERR(regs[i].reg); | |
230 | if (rc != -EPROBE_DEFER) | |
231 | dev_err(dev, "Failed to get %s\n regulator", | |
232 | reg_res[i].supply); | |
233 | return rc; | |
234 | } | |
051fb70f | 235 | |
19f902b5 AKD |
236 | regs[i].uV = reg_res[i].uV; |
237 | regs[i].uA = reg_res[i].uA; | |
051fb70f BA |
238 | } |
239 | ||
19f902b5 | 240 | return i; |
051fb70f BA |
241 | } |
242 | ||
19f902b5 AKD |
243 | static int q6v5_regulator_enable(struct q6v5 *qproc, |
244 | struct reg_info *regs, int count) | |
051fb70f | 245 | { |
051fb70f | 246 | int ret; |
19f902b5 | 247 | int i; |
051fb70f | 248 | |
19f902b5 AKD |
249 | for (i = 0; i < count; i++) { |
250 | if (regs[i].uV > 0) { | |
251 | ret = regulator_set_voltage(regs[i].reg, | |
252 | regs[i].uV, INT_MAX); | |
253 | if (ret) { | |
254 | dev_err(qproc->dev, | |
255 | "Failed to request voltage for %d.\n", | |
256 | i); | |
257 | goto err; | |
258 | } | |
259 | } | |
051fb70f | 260 | |
19f902b5 AKD |
261 | if (regs[i].uA > 0) { |
262 | ret = regulator_set_load(regs[i].reg, | |
263 | regs[i].uA); | |
264 | if (ret < 0) { | |
265 | dev_err(qproc->dev, | |
266 | "Failed to set regulator mode\n"); | |
267 | goto err; | |
268 | } | |
269 | } | |
270 | ||
271 | ret = regulator_enable(regs[i].reg); | |
272 | if (ret) { | |
273 | dev_err(qproc->dev, "Regulator enable failed\n"); | |
274 | goto err; | |
275 | } | |
276 | } | |
277 | ||
278 | return 0; | |
279 | err: | |
280 | for (; i >= 0; i--) { | |
281 | if (regs[i].uV > 0) | |
282 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
283 | ||
284 | if (regs[i].uA > 0) | |
285 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 286 | |
19f902b5 AKD |
287 | regulator_disable(regs[i].reg); |
288 | } | |
051fb70f | 289 | |
19f902b5 | 290 | return ret; |
051fb70f BA |
291 | } |
292 | ||
19f902b5 AKD |
293 | static void q6v5_regulator_disable(struct q6v5 *qproc, |
294 | struct reg_info *regs, int count) | |
051fb70f | 295 | { |
19f902b5 AKD |
296 | int i; |
297 | ||
298 | for (i = 0; i < count; i++) { | |
299 | if (regs[i].uV > 0) | |
300 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
051fb70f | 301 | |
19f902b5 AKD |
302 | if (regs[i].uA > 0) |
303 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 304 | |
19f902b5 AKD |
305 | regulator_disable(regs[i].reg); |
306 | } | |
051fb70f BA |
307 | } |
308 | ||
39b2410b AKD |
309 | static int q6v5_clk_enable(struct device *dev, |
310 | struct clk **clks, int count) | |
311 | { | |
312 | int rc; | |
313 | int i; | |
314 | ||
315 | for (i = 0; i < count; i++) { | |
316 | rc = clk_prepare_enable(clks[i]); | |
317 | if (rc) { | |
318 | dev_err(dev, "Clock enable failed\n"); | |
319 | goto err; | |
320 | } | |
321 | } | |
322 | ||
323 | return 0; | |
324 | err: | |
325 | for (i--; i >= 0; i--) | |
326 | clk_disable_unprepare(clks[i]); | |
327 | ||
328 | return rc; | |
329 | } | |
330 | ||
331 | static void q6v5_clk_disable(struct device *dev, | |
332 | struct clk **clks, int count) | |
333 | { | |
334 | int i; | |
335 | ||
336 | for (i = 0; i < count; i++) | |
337 | clk_disable_unprepare(clks[i]); | |
338 | } | |
339 | ||
4760a896 RN |
340 | static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds, |
341 | size_t pd_count) | |
342 | { | |
343 | int ret; | |
344 | int i; | |
345 | ||
346 | for (i = 0; i < pd_count; i++) { | |
347 | dev_pm_genpd_set_performance_state(pds[i], INT_MAX); | |
348 | ret = pm_runtime_get_sync(pds[i]); | |
349 | if (ret < 0) | |
350 | goto unroll_pd_votes; | |
351 | } | |
352 | ||
353 | return 0; | |
354 | ||
355 | unroll_pd_votes: | |
356 | for (i--; i >= 0; i--) { | |
357 | dev_pm_genpd_set_performance_state(pds[i], 0); | |
358 | pm_runtime_put(pds[i]); | |
359 | } | |
360 | ||
361 | return ret; | |
362 | }; | |
363 | ||
364 | static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds, | |
365 | size_t pd_count) | |
366 | { | |
367 | int i; | |
368 | ||
369 | for (i = 0; i < pd_count; i++) { | |
370 | dev_pm_genpd_set_performance_state(pds[i], 0); | |
371 | pm_runtime_put(pds[i]); | |
372 | } | |
373 | } | |
374 | ||
6c5a9dc2 AKD |
375 | static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, |
376 | bool remote_owner, phys_addr_t addr, | |
377 | size_t size) | |
378 | { | |
379 | struct qcom_scm_vmperm next; | |
6c5a9dc2 AKD |
380 | |
381 | if (!qproc->need_mem_protection) | |
382 | return 0; | |
383 | if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA)) | |
384 | return 0; | |
385 | if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS)) | |
386 | return 0; | |
387 | ||
388 | next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS; | |
389 | next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX; | |
390 | ||
9f2a4342 BA |
391 | return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K), |
392 | current_perm, &next, 1); | |
6c5a9dc2 AKD |
393 | } |
394 | ||
051fb70f BA |
395 | static int q6v5_load(struct rproc *rproc, const struct firmware *fw) |
396 | { | |
397 | struct q6v5 *qproc = rproc->priv; | |
398 | ||
399 | memcpy(qproc->mba_region, fw->data, fw->size); | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
9f135fa1 SS |
404 | static int q6v5_reset_assert(struct q6v5 *qproc) |
405 | { | |
29a5f9aa SS |
406 | int ret; |
407 | ||
408 | if (qproc->has_alt_reset) { | |
409 | reset_control_assert(qproc->pdc_reset); | |
410 | ret = reset_control_reset(qproc->mss_restart); | |
411 | reset_control_deassert(qproc->pdc_reset); | |
6439b527 SS |
412 | } else if (qproc->has_halt_nav) { |
413 | /* SWAR using CONN_BOX_SPARE_0 for pipeline glitch issue */ | |
414 | reset_control_assert(qproc->pdc_reset); | |
415 | regmap_update_bits(qproc->conn_map, qproc->conn_box, | |
416 | BIT(0), BIT(0)); | |
417 | regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav, | |
418 | NAV_AXI_HALTREQ_BIT, 0); | |
419 | reset_control_assert(qproc->mss_restart); | |
420 | reset_control_deassert(qproc->pdc_reset); | |
421 | regmap_update_bits(qproc->conn_map, qproc->conn_box, | |
422 | BIT(0), 0); | |
423 | ret = reset_control_deassert(qproc->mss_restart); | |
29a5f9aa SS |
424 | } else { |
425 | ret = reset_control_assert(qproc->mss_restart); | |
426 | } | |
427 | ||
428 | return ret; | |
9f135fa1 SS |
429 | } |
430 | ||
431 | static int q6v5_reset_deassert(struct q6v5 *qproc) | |
432 | { | |
231f67d1 SS |
433 | int ret; |
434 | ||
435 | if (qproc->has_alt_reset) { | |
29a5f9aa | 436 | reset_control_assert(qproc->pdc_reset); |
231f67d1 SS |
437 | writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET); |
438 | ret = reset_control_reset(qproc->mss_restart); | |
439 | writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); | |
29a5f9aa | 440 | reset_control_deassert(qproc->pdc_reset); |
6439b527 SS |
441 | } else if (qproc->has_halt_nav) { |
442 | ret = reset_control_reset(qproc->mss_restart); | |
231f67d1 SS |
443 | } else { |
444 | ret = reset_control_deassert(qproc->mss_restart); | |
445 | } | |
446 | ||
447 | return ret; | |
9f135fa1 SS |
448 | } |
449 | ||
051fb70f BA |
450 | static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms) |
451 | { | |
452 | unsigned long timeout; | |
453 | s32 val; | |
454 | ||
455 | timeout = jiffies + msecs_to_jiffies(ms); | |
456 | for (;;) { | |
457 | val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG); | |
458 | if (val) | |
459 | break; | |
460 | ||
461 | if (time_after(jiffies, timeout)) | |
462 | return -ETIMEDOUT; | |
463 | ||
464 | msleep(1); | |
465 | } | |
466 | ||
467 | return val; | |
468 | } | |
469 | ||
470 | static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms) | |
471 | { | |
472 | ||
473 | unsigned long timeout; | |
474 | s32 val; | |
475 | ||
476 | timeout = jiffies + msecs_to_jiffies(ms); | |
477 | for (;;) { | |
478 | val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); | |
479 | if (val < 0) | |
480 | break; | |
481 | ||
482 | if (!status && val) | |
483 | break; | |
484 | else if (status && val == status) | |
485 | break; | |
486 | ||
487 | if (time_after(jiffies, timeout)) | |
488 | return -ETIMEDOUT; | |
489 | ||
490 | msleep(1); | |
491 | } | |
492 | ||
493 | return val; | |
494 | } | |
495 | ||
496 | static int q6v5proc_reset(struct q6v5 *qproc) | |
497 | { | |
498 | u32 val; | |
499 | int ret; | |
9f058fa2 | 500 | int i; |
051fb70f | 501 | |
231f67d1 SS |
502 | if (qproc->version == MSS_SDM845) { |
503 | val = readl(qproc->reg_base + QDSP6SS_SLEEP); | |
504 | val |= 0x1; | |
505 | writel(val, qproc->reg_base + QDSP6SS_SLEEP); | |
051fb70f | 506 | |
231f67d1 SS |
507 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, |
508 | val, !(val & BIT(31)), 1, | |
509 | SLEEP_CHECK_MAX_LOOPS); | |
510 | if (ret) { | |
511 | dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); | |
512 | return -ETIMEDOUT; | |
513 | } | |
514 | ||
515 | /* De-assert QDSP6 stop core */ | |
516 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); | |
517 | /* Trigger boot FSM */ | |
518 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); | |
519 | ||
520 | ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, | |
521 | val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); | |
522 | if (ret) { | |
523 | dev_err(qproc->dev, "Boot FSM failed to complete.\n"); | |
524 | /* Reset the modem so that boot FSM is in reset state */ | |
525 | q6v5_reset_deassert(qproc); | |
526 | return ret; | |
527 | } | |
528 | ||
6439b527 SS |
529 | goto pbl_wait; |
530 | } else if (qproc->version == MSS_SC7180) { | |
531 | val = readl(qproc->reg_base + QDSP6SS_SLEEP); | |
532 | val |= 0x1; | |
533 | writel(val, qproc->reg_base + QDSP6SS_SLEEP); | |
534 | ||
535 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, | |
536 | val, !(val & BIT(31)), 1, | |
537 | SLEEP_CHECK_MAX_LOOPS); | |
538 | if (ret) { | |
539 | dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); | |
540 | return -ETIMEDOUT; | |
541 | } | |
542 | ||
543 | /* Turn on the XO clock needed for PLL setup */ | |
544 | val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); | |
545 | val |= 0x1; | |
546 | writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); | |
547 | ||
548 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, | |
549 | val, !(val & BIT(31)), 1, | |
550 | SLEEP_CHECK_MAX_LOOPS); | |
551 | if (ret) { | |
552 | dev_err(qproc->dev, "QDSP6SS XO clock timed out\n"); | |
553 | return -ETIMEDOUT; | |
554 | } | |
555 | ||
556 | /* Configure Q6 core CBCR to auto-enable after reset sequence */ | |
557 | val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR); | |
558 | val |= 0x1; | |
559 | writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR); | |
560 | ||
561 | /* De-assert the Q6 stop core signal */ | |
562 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); | |
563 | ||
564 | /* Trigger the boot FSM to start the Q6 out-of-reset sequence */ | |
565 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); | |
566 | ||
567 | /* Poll the QDSP6SS_BOOT_STATUS for FSM completion */ | |
568 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BOOT_STATUS, | |
569 | val, (val & BIT(0)) != 0, 1, | |
570 | SLEEP_CHECK_MAX_LOOPS); | |
571 | if (ret) { | |
572 | dev_err(qproc->dev, "Boot FSM failed to complete.\n"); | |
573 | /* Reset the modem so that boot FSM is in reset state */ | |
574 | q6v5_reset_deassert(qproc); | |
575 | return ret; | |
576 | } | |
231f67d1 | 577 | goto pbl_wait; |
1665cbd5 JH |
578 | } else if (qproc->version == MSS_MSM8996 || |
579 | qproc->version == MSS_MSM8998) { | |
580 | int mem_pwr_ctl; | |
581 | ||
9f058fa2 AKD |
582 | /* Override the ACC value if required */ |
583 | writel(QDSP6SS_ACC_OVERRIDE_VAL, | |
584 | qproc->reg_base + QDSP6SS_STRAP_ACC); | |
051fb70f | 585 | |
9f058fa2 AKD |
586 | /* Assert resets, stop core */ |
587 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
588 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
589 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
590 | ||
591 | /* BHS require xo cbcr to be enabled */ | |
592 | val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); | |
593 | val |= 0x1; | |
594 | writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); | |
595 | ||
596 | /* Read CLKOFF bit to go low indicating CLK is enabled */ | |
597 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, | |
598 | val, !(val & BIT(31)), 1, | |
599 | HALT_CHECK_MAX_LOOPS); | |
600 | if (ret) { | |
601 | dev_err(qproc->dev, | |
602 | "xo cbcr enabling timed out (rc:%d)\n", ret); | |
603 | return ret; | |
604 | } | |
605 | /* Enable power block headswitch and wait for it to stabilize */ | |
606 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
607 | val |= QDSP6v56_BHS_ON; | |
608 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
609 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
610 | udelay(1); | |
611 | ||
612 | /* Put LDO in bypass mode */ | |
613 | val |= QDSP6v56_LDO_BYP; | |
614 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
615 | ||
616 | /* Deassert QDSP6 compiler memory clamp */ | |
617 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
618 | val &= ~QDSP6v56_CLAMP_QMC_MEM; | |
619 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
620 | ||
621 | /* Deassert memory peripheral sleep and L2 memory standby */ | |
622 | val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; | |
623 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
624 | ||
625 | /* Turn on L1, L2, ETB and JU memories 1 at a time */ | |
1665cbd5 JH |
626 | if (qproc->version == MSS_MSM8996) { |
627 | mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL; | |
628 | i = 19; | |
629 | } else { | |
630 | /* MSS_MSM8998 */ | |
631 | mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL; | |
632 | i = 28; | |
633 | } | |
634 | val = readl(qproc->reg_base + mem_pwr_ctl); | |
635 | for (; i >= 0; i--) { | |
9f058fa2 | 636 | val |= BIT(i); |
1665cbd5 | 637 | writel(val, qproc->reg_base + mem_pwr_ctl); |
9f058fa2 AKD |
638 | /* |
639 | * Read back value to ensure the write is done then | |
640 | * wait for 1us for both memory peripheral and data | |
641 | * array to turn on. | |
642 | */ | |
1665cbd5 | 643 | val |= readl(qproc->reg_base + mem_pwr_ctl); |
9f058fa2 AKD |
644 | udelay(1); |
645 | } | |
646 | /* Remove word line clamp */ | |
647 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
648 | val &= ~QDSP6v56_CLAMP_WL; | |
649 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
650 | } else { | |
651 | /* Assert resets, stop core */ | |
652 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
653 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
654 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
655 | ||
656 | /* Enable power block headswitch and wait for it to stabilize */ | |
657 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
658 | val |= QDSS_BHS_ON | QDSS_LDO_BYP; | |
659 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
660 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
661 | udelay(1); | |
662 | /* | |
663 | * Turn on memories. L2 banks should be done individually | |
664 | * to minimize inrush current. | |
665 | */ | |
666 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
667 | val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | | |
668 | Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; | |
669 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
670 | val |= Q6SS_L2DATA_SLP_NRET_N_2; | |
671 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
672 | val |= Q6SS_L2DATA_SLP_NRET_N_1; | |
673 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
674 | val |= Q6SS_L2DATA_SLP_NRET_N_0; | |
675 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
676 | } | |
051fb70f BA |
677 | /* Remove IO clamp */ |
678 | val &= ~Q6SS_CLAMP_IO; | |
679 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
680 | ||
681 | /* Bring core out of reset */ | |
682 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
683 | val &= ~Q6SS_CORE_ARES; | |
684 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
685 | ||
686 | /* Turn on core clock */ | |
687 | val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
688 | val |= Q6SS_CLK_ENABLE; | |
689 | writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
690 | ||
691 | /* Start core execution */ | |
692 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
693 | val &= ~Q6SS_STOP_CORE; | |
694 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
695 | ||
231f67d1 | 696 | pbl_wait: |
051fb70f BA |
697 | /* Wait for PBL status */ |
698 | ret = q6v5_rmb_pbl_wait(qproc, 1000); | |
699 | if (ret == -ETIMEDOUT) { | |
700 | dev_err(qproc->dev, "PBL boot timed out\n"); | |
701 | } else if (ret != RMB_PBL_SUCCESS) { | |
702 | dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret); | |
703 | ret = -EINVAL; | |
704 | } else { | |
705 | ret = 0; | |
706 | } | |
707 | ||
708 | return ret; | |
709 | } | |
710 | ||
711 | static void q6v5proc_halt_axi_port(struct q6v5 *qproc, | |
712 | struct regmap *halt_map, | |
713 | u32 offset) | |
714 | { | |
715 | unsigned long timeout; | |
716 | unsigned int val; | |
717 | int ret; | |
718 | ||
719 | /* Check if we're already idle */ | |
720 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
721 | if (!ret && val) | |
722 | return; | |
723 | ||
724 | /* Assert halt request */ | |
725 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); | |
726 | ||
727 | /* Wait for halt */ | |
728 | timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS); | |
729 | for (;;) { | |
730 | ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val); | |
731 | if (ret || val || time_after(jiffies, timeout)) | |
732 | break; | |
733 | ||
734 | msleep(1); | |
735 | } | |
736 | ||
737 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
738 | if (ret || !val) | |
739 | dev_err(qproc->dev, "port failed halt\n"); | |
740 | ||
741 | /* Clear halt request (port will remain halted until reset) */ | |
742 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); | |
743 | } | |
744 | ||
6439b527 SS |
745 | static void q6v5proc_halt_nav_axi_port(struct q6v5 *qproc, |
746 | struct regmap *halt_map, | |
747 | u32 offset) | |
748 | { | |
749 | unsigned long timeout; | |
750 | unsigned int val; | |
751 | int ret; | |
752 | ||
753 | /* Check if we're already idle */ | |
754 | ret = regmap_read(halt_map, offset, &val); | |
755 | if (!ret && (val & NAV_AXI_IDLE_BIT)) | |
756 | return; | |
757 | ||
758 | /* Assert halt request */ | |
759 | regmap_update_bits(halt_map, offset, NAV_AXI_HALTREQ_BIT, | |
760 | NAV_AXI_HALTREQ_BIT); | |
761 | ||
762 | /* Wait for halt ack*/ | |
763 | timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS); | |
764 | for (;;) { | |
765 | ret = regmap_read(halt_map, offset, &val); | |
766 | if (ret || (val & NAV_AXI_HALTACK_BIT) || | |
767 | time_after(jiffies, timeout)) | |
768 | break; | |
769 | ||
770 | udelay(5); | |
771 | } | |
772 | ||
773 | ret = regmap_read(halt_map, offset, &val); | |
774 | if (ret || !(val & NAV_AXI_IDLE_BIT)) | |
775 | dev_err(qproc->dev, "port failed halt\n"); | |
776 | } | |
777 | ||
051fb70f BA |
778 | static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) |
779 | { | |
00085f1e | 780 | unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; |
051fb70f | 781 | dma_addr_t phys; |
f04b9138 | 782 | void *metadata; |
6c5a9dc2 AKD |
783 | int mdata_perm; |
784 | int xferop_ret; | |
f04b9138 | 785 | size_t size; |
051fb70f BA |
786 | void *ptr; |
787 | int ret; | |
788 | ||
f04b9138 BA |
789 | metadata = qcom_mdt_read_metadata(fw, &size); |
790 | if (IS_ERR(metadata)) | |
791 | return PTR_ERR(metadata); | |
792 | ||
793 | ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs); | |
051fb70f | 794 | if (!ptr) { |
f04b9138 | 795 | kfree(metadata); |
051fb70f BA |
796 | dev_err(qproc->dev, "failed to allocate mdt buffer\n"); |
797 | return -ENOMEM; | |
798 | } | |
799 | ||
f04b9138 | 800 | memcpy(ptr, metadata, size); |
051fb70f | 801 | |
6c5a9dc2 AKD |
802 | /* Hypervisor mapping to access metadata by modem */ |
803 | mdata_perm = BIT(QCOM_SCM_VMID_HLOS); | |
f04b9138 | 804 | ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, phys, size); |
9f2a4342 BA |
805 | if (ret) { |
806 | dev_err(qproc->dev, | |
807 | "assigning Q6 access to metadata failed: %d\n", ret); | |
1a5d5c59 CJ |
808 | ret = -EAGAIN; |
809 | goto free_dma_attrs; | |
9f2a4342 | 810 | } |
6c5a9dc2 | 811 | |
051fb70f BA |
812 | writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG); |
813 | writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
814 | ||
815 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000); | |
816 | if (ret == -ETIMEDOUT) | |
817 | dev_err(qproc->dev, "MPSS header authentication timed out\n"); | |
818 | else if (ret < 0) | |
819 | dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret); | |
820 | ||
6c5a9dc2 | 821 | /* Metadata authentication done, remove modem access */ |
f04b9138 | 822 | xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, phys, size); |
6c5a9dc2 AKD |
823 | if (xferop_ret) |
824 | dev_warn(qproc->dev, | |
825 | "mdt buffer not reclaimed system may become unstable\n"); | |
826 | ||
1a5d5c59 | 827 | free_dma_attrs: |
f04b9138 BA |
828 | dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs); |
829 | kfree(metadata); | |
051fb70f BA |
830 | |
831 | return ret < 0 ? ret : 0; | |
832 | } | |
833 | ||
e7fd2522 BA |
834 | static bool q6v5_phdr_valid(const struct elf32_phdr *phdr) |
835 | { | |
836 | if (phdr->p_type != PT_LOAD) | |
837 | return false; | |
838 | ||
839 | if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH) | |
840 | return false; | |
841 | ||
842 | if (!phdr->p_memsz) | |
843 | return false; | |
844 | ||
845 | return true; | |
846 | } | |
847 | ||
0304530d SS |
848 | static int q6v5_mba_load(struct q6v5 *qproc) |
849 | { | |
850 | int ret; | |
851 | int xfermemop_ret; | |
852 | ||
853 | qcom_q6v5_prepare(&qproc->q6v5); | |
854 | ||
deb9bb83 BA |
855 | ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count); |
856 | if (ret < 0) { | |
857 | dev_err(qproc->dev, "failed to enable active power domains\n"); | |
858 | goto disable_irqs; | |
859 | } | |
860 | ||
4760a896 RN |
861 | ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
862 | if (ret < 0) { | |
863 | dev_err(qproc->dev, "failed to enable proxy power domains\n"); | |
deb9bb83 | 864 | goto disable_active_pds; |
4760a896 RN |
865 | } |
866 | ||
0304530d SS |
867 | ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, |
868 | qproc->proxy_reg_count); | |
869 | if (ret) { | |
870 | dev_err(qproc->dev, "failed to enable proxy supplies\n"); | |
4760a896 | 871 | goto disable_proxy_pds; |
0304530d SS |
872 | } |
873 | ||
874 | ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, | |
875 | qproc->proxy_clk_count); | |
876 | if (ret) { | |
877 | dev_err(qproc->dev, "failed to enable proxy clocks\n"); | |
878 | goto disable_proxy_reg; | |
879 | } | |
880 | ||
881 | ret = q6v5_regulator_enable(qproc, qproc->active_regs, | |
882 | qproc->active_reg_count); | |
883 | if (ret) { | |
884 | dev_err(qproc->dev, "failed to enable supplies\n"); | |
885 | goto disable_proxy_clk; | |
886 | } | |
887 | ||
888 | ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks, | |
889 | qproc->reset_clk_count); | |
890 | if (ret) { | |
891 | dev_err(qproc->dev, "failed to enable reset clocks\n"); | |
892 | goto disable_vdd; | |
893 | } | |
894 | ||
895 | ret = q6v5_reset_deassert(qproc); | |
896 | if (ret) { | |
897 | dev_err(qproc->dev, "failed to deassert mss restart\n"); | |
898 | goto disable_reset_clks; | |
899 | } | |
900 | ||
901 | ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, | |
902 | qproc->active_clk_count); | |
903 | if (ret) { | |
904 | dev_err(qproc->dev, "failed to enable clocks\n"); | |
905 | goto assert_reset; | |
906 | } | |
907 | ||
908 | /* Assign MBA image access in DDR to q6 */ | |
909 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, | |
910 | qproc->mba_phys, qproc->mba_size); | |
911 | if (ret) { | |
912 | dev_err(qproc->dev, | |
913 | "assigning Q6 access to mba memory failed: %d\n", ret); | |
914 | goto disable_active_clks; | |
915 | } | |
916 | ||
917 | writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); | |
918 | ||
919 | ret = q6v5proc_reset(qproc); | |
920 | if (ret) | |
921 | goto reclaim_mba; | |
922 | ||
923 | ret = q6v5_rmb_mba_wait(qproc, 0, 5000); | |
924 | if (ret == -ETIMEDOUT) { | |
925 | dev_err(qproc->dev, "MBA boot timed out\n"); | |
926 | goto halt_axi_ports; | |
927 | } else if (ret != RMB_MBA_XPU_UNLOCKED && | |
928 | ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) { | |
929 | dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret); | |
930 | ret = -EINVAL; | |
931 | goto halt_axi_ports; | |
932 | } | |
933 | ||
934 | qproc->dump_mba_loaded = true; | |
935 | return 0; | |
936 | ||
937 | halt_axi_ports: | |
938 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
939 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); | |
6439b527 SS |
940 | if (qproc->has_halt_nav) |
941 | q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, | |
942 | qproc->halt_nav); | |
0304530d SS |
943 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); |
944 | ||
945 | reclaim_mba: | |
946 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, | |
947 | qproc->mba_phys, | |
948 | qproc->mba_size); | |
949 | if (xfermemop_ret) { | |
950 | dev_err(qproc->dev, | |
951 | "Failed to reclaim mba buffer, system may become unstable\n"); | |
952 | } | |
953 | ||
954 | disable_active_clks: | |
955 | q6v5_clk_disable(qproc->dev, qproc->active_clks, | |
956 | qproc->active_clk_count); | |
957 | assert_reset: | |
958 | q6v5_reset_assert(qproc); | |
959 | disable_reset_clks: | |
960 | q6v5_clk_disable(qproc->dev, qproc->reset_clks, | |
961 | qproc->reset_clk_count); | |
962 | disable_vdd: | |
963 | q6v5_regulator_disable(qproc, qproc->active_regs, | |
964 | qproc->active_reg_count); | |
965 | disable_proxy_clk: | |
966 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, | |
967 | qproc->proxy_clk_count); | |
968 | disable_proxy_reg: | |
969 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
970 | qproc->proxy_reg_count); | |
4760a896 RN |
971 | disable_proxy_pds: |
972 | q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); | |
deb9bb83 BA |
973 | disable_active_pds: |
974 | q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); | |
0304530d SS |
975 | disable_irqs: |
976 | qcom_q6v5_unprepare(&qproc->q6v5); | |
977 | ||
978 | return ret; | |
979 | } | |
980 | ||
981 | static void q6v5_mba_reclaim(struct q6v5 *qproc) | |
982 | { | |
983 | int ret; | |
984 | u32 val; | |
985 | ||
986 | qproc->dump_mba_loaded = false; | |
987 | ||
988 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
989 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); | |
6439b527 SS |
990 | if (qproc->has_halt_nav) |
991 | q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, | |
992 | qproc->halt_nav); | |
0304530d SS |
993 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); |
994 | if (qproc->version == MSS_MSM8996) { | |
995 | /* | |
996 | * To avoid high MX current during LPASS/MSS restart. | |
997 | */ | |
998 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
999 | val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | | |
1000 | QDSP6v56_CLAMP_QMC_MEM; | |
1001 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
1002 | } | |
1003 | ||
1004 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, | |
1005 | false, qproc->mpss_phys, | |
1006 | qproc->mpss_size); | |
1007 | WARN_ON(ret); | |
1008 | ||
1009 | q6v5_reset_assert(qproc); | |
1010 | ||
1011 | q6v5_clk_disable(qproc->dev, qproc->reset_clks, | |
1012 | qproc->reset_clk_count); | |
1013 | q6v5_clk_disable(qproc->dev, qproc->active_clks, | |
1014 | qproc->active_clk_count); | |
1015 | q6v5_regulator_disable(qproc, qproc->active_regs, | |
1016 | qproc->active_reg_count); | |
deb9bb83 | 1017 | q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); |
0304530d SS |
1018 | |
1019 | /* In case of failure or coredump scenario where reclaiming MBA memory | |
1020 | * could not happen reclaim it here. | |
1021 | */ | |
1022 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, | |
1023 | qproc->mba_phys, | |
1024 | qproc->mba_size); | |
1025 | WARN_ON(ret); | |
1026 | ||
1027 | ret = qcom_q6v5_unprepare(&qproc->q6v5); | |
1028 | if (ret) { | |
4760a896 RN |
1029 | q6v5_pds_disable(qproc, qproc->proxy_pds, |
1030 | qproc->proxy_pd_count); | |
0304530d SS |
1031 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, |
1032 | qproc->proxy_clk_count); | |
1033 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
1034 | qproc->proxy_reg_count); | |
1035 | } | |
1036 | } | |
1037 | ||
e7fd2522 | 1038 | static int q6v5_mpss_load(struct q6v5 *qproc) |
051fb70f BA |
1039 | { |
1040 | const struct elf32_phdr *phdrs; | |
1041 | const struct elf32_phdr *phdr; | |
e7fd2522 BA |
1042 | const struct firmware *seg_fw; |
1043 | const struct firmware *fw; | |
051fb70f | 1044 | struct elf32_hdr *ehdr; |
e7fd2522 | 1045 | phys_addr_t mpss_reloc; |
051fb70f | 1046 | phys_addr_t boot_addr; |
d7dc899a | 1047 | phys_addr_t min_addr = PHYS_ADDR_MAX; |
e7fd2522 BA |
1048 | phys_addr_t max_addr = 0; |
1049 | bool relocate = false; | |
a5a4e02d SS |
1050 | char *fw_name; |
1051 | size_t fw_name_len; | |
01625cc5 | 1052 | ssize_t offset; |
94c90785 | 1053 | size_t size = 0; |
e7fd2522 | 1054 | void *ptr; |
051fb70f BA |
1055 | int ret; |
1056 | int i; | |
1057 | ||
a5a4e02d SS |
1058 | fw_name_len = strlen(qproc->hexagon_mdt_image); |
1059 | if (fw_name_len <= 4) | |
1060 | return -EINVAL; | |
1061 | ||
1062 | fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL); | |
1063 | if (!fw_name) | |
1064 | return -ENOMEM; | |
1065 | ||
1066 | ret = request_firmware(&fw, fw_name, qproc->dev); | |
e7fd2522 | 1067 | if (ret < 0) { |
a5a4e02d SS |
1068 | dev_err(qproc->dev, "unable to load %s\n", fw_name); |
1069 | goto out; | |
051fb70f BA |
1070 | } |
1071 | ||
e7fd2522 BA |
1072 | /* Initialize the RMB validator */ |
1073 | writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1074 | ||
1075 | ret = q6v5_mpss_init_image(qproc, fw); | |
1076 | if (ret) | |
1077 | goto release_firmware; | |
051fb70f BA |
1078 | |
1079 | ehdr = (struct elf32_hdr *)fw->data; | |
1080 | phdrs = (struct elf32_phdr *)(ehdr + 1); | |
e7fd2522 BA |
1081 | |
1082 | for (i = 0; i < ehdr->e_phnum; i++) { | |
051fb70f BA |
1083 | phdr = &phdrs[i]; |
1084 | ||
e7fd2522 | 1085 | if (!q6v5_phdr_valid(phdr)) |
051fb70f BA |
1086 | continue; |
1087 | ||
e7fd2522 BA |
1088 | if (phdr->p_flags & QCOM_MDT_RELOCATABLE) |
1089 | relocate = true; | |
051fb70f | 1090 | |
e7fd2522 BA |
1091 | if (phdr->p_paddr < min_addr) |
1092 | min_addr = phdr->p_paddr; | |
1093 | ||
1094 | if (phdr->p_paddr + phdr->p_memsz > max_addr) | |
1095 | max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); | |
1096 | } | |
1097 | ||
1098 | mpss_reloc = relocate ? min_addr : qproc->mpss_phys; | |
3bf62eb7 | 1099 | qproc->mpss_reloc = mpss_reloc; |
94c90785 | 1100 | /* Load firmware segments */ |
e7fd2522 BA |
1101 | for (i = 0; i < ehdr->e_phnum; i++) { |
1102 | phdr = &phdrs[i]; | |
1103 | ||
1104 | if (!q6v5_phdr_valid(phdr)) | |
051fb70f BA |
1105 | continue; |
1106 | ||
e7fd2522 BA |
1107 | offset = phdr->p_paddr - mpss_reloc; |
1108 | if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) { | |
1109 | dev_err(qproc->dev, "segment outside memory range\n"); | |
1110 | ret = -EINVAL; | |
1111 | goto release_firmware; | |
1112 | } | |
1113 | ||
1114 | ptr = qproc->mpss_region + offset; | |
1115 | ||
f04b9138 BA |
1116 | if (phdr->p_filesz && phdr->p_offset < fw->size) { |
1117 | /* Firmware is large enough to be non-split */ | |
1118 | if (phdr->p_offset + phdr->p_filesz > fw->size) { | |
1119 | dev_err(qproc->dev, | |
1120 | "failed to load segment %d from truncated file %s\n", | |
1121 | i, fw_name); | |
1122 | ret = -EINVAL; | |
1123 | goto release_firmware; | |
1124 | } | |
1125 | ||
1126 | memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz); | |
1127 | } else if (phdr->p_filesz) { | |
a5a4e02d SS |
1128 | /* Replace "xxx.xxx" with "xxx.bxx" */ |
1129 | sprintf(fw_name + fw_name_len - 3, "b%02d", i); | |
1130 | ret = request_firmware(&seg_fw, fw_name, qproc->dev); | |
e7fd2522 | 1131 | if (ret) { |
a5a4e02d | 1132 | dev_err(qproc->dev, "failed to load %s\n", fw_name); |
e7fd2522 BA |
1133 | goto release_firmware; |
1134 | } | |
1135 | ||
1136 | memcpy(ptr, seg_fw->data, seg_fw->size); | |
1137 | ||
1138 | release_firmware(seg_fw); | |
1139 | } | |
1140 | ||
1141 | if (phdr->p_memsz > phdr->p_filesz) { | |
1142 | memset(ptr + phdr->p_filesz, 0, | |
1143 | phdr->p_memsz - phdr->p_filesz); | |
1144 | } | |
051fb70f | 1145 | size += phdr->p_memsz; |
051fb70f BA |
1146 | } |
1147 | ||
6c5a9dc2 AKD |
1148 | /* Transfer ownership of modem ddr region to q6 */ |
1149 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, | |
1150 | qproc->mpss_phys, qproc->mpss_size); | |
9f2a4342 BA |
1151 | if (ret) { |
1152 | dev_err(qproc->dev, | |
1153 | "assigning Q6 access to mpss memory failed: %d\n", ret); | |
1a5d5c59 CJ |
1154 | ret = -EAGAIN; |
1155 | goto release_firmware; | |
9f2a4342 | 1156 | } |
6c5a9dc2 | 1157 | |
94c90785 AKD |
1158 | boot_addr = relocate ? qproc->mpss_phys : min_addr; |
1159 | writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG); | |
1160 | writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
1161 | writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1162 | ||
72beb490 BA |
1163 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000); |
1164 | if (ret == -ETIMEDOUT) | |
1165 | dev_err(qproc->dev, "MPSS authentication timed out\n"); | |
1166 | else if (ret < 0) | |
1167 | dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret); | |
1168 | ||
051fb70f BA |
1169 | release_firmware: |
1170 | release_firmware(fw); | |
a5a4e02d SS |
1171 | out: |
1172 | kfree(fw_name); | |
051fb70f BA |
1173 | |
1174 | return ret < 0 ? ret : 0; | |
1175 | } | |
1176 | ||
7dd8ade2 SS |
1177 | static void qcom_q6v5_dump_segment(struct rproc *rproc, |
1178 | struct rproc_dump_segment *segment, | |
1179 | void *dest) | |
1180 | { | |
1181 | int ret = 0; | |
1182 | struct q6v5 *qproc = rproc->priv; | |
1183 | unsigned long mask = BIT((unsigned long)segment->priv); | |
1184 | void *ptr = rproc_da_to_va(rproc, segment->da, segment->size); | |
1185 | ||
1186 | /* Unlock mba before copying segments */ | |
1187 | if (!qproc->dump_mba_loaded) | |
1188 | ret = q6v5_mba_load(qproc); | |
1189 | ||
1190 | if (!ptr || ret) | |
1191 | memset(dest, 0xff, segment->size); | |
1192 | else | |
1193 | memcpy(dest, ptr, segment->size); | |
1194 | ||
1195 | qproc->dump_segment_mask |= mask; | |
1196 | ||
1197 | /* Reclaim mba after copying segments */ | |
1198 | if (qproc->dump_segment_mask == qproc->dump_complete_mask) { | |
1199 | if (qproc->dump_mba_loaded) | |
1200 | q6v5_mba_reclaim(qproc); | |
1201 | } | |
1202 | } | |
1203 | ||
051fb70f BA |
1204 | static int q6v5_start(struct rproc *rproc) |
1205 | { | |
1206 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
6c5a9dc2 | 1207 | int xfermemop_ret; |
051fb70f BA |
1208 | int ret; |
1209 | ||
0304530d | 1210 | ret = q6v5_mba_load(qproc); |
051fb70f | 1211 | if (ret) |
0304530d | 1212 | return ret; |
051fb70f BA |
1213 | |
1214 | dev_info(qproc->dev, "MBA booted, loading mpss\n"); | |
1215 | ||
1216 | ret = q6v5_mpss_load(qproc); | |
1217 | if (ret) | |
6c5a9dc2 | 1218 | goto reclaim_mpss; |
051fb70f | 1219 | |
7d674731 BA |
1220 | ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000)); |
1221 | if (ret == -ETIMEDOUT) { | |
051fb70f | 1222 | dev_err(qproc->dev, "start timed out\n"); |
6c5a9dc2 | 1223 | goto reclaim_mpss; |
051fb70f BA |
1224 | } |
1225 | ||
6c5a9dc2 AKD |
1226 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, |
1227 | qproc->mba_phys, | |
1228 | qproc->mba_size); | |
1229 | if (xfermemop_ret) | |
1230 | dev_err(qproc->dev, | |
1231 | "Failed to reclaim mba buffer system may become unstable\n"); | |
7dd8ade2 SS |
1232 | |
1233 | /* Reset Dump Segment Mask */ | |
1234 | qproc->dump_segment_mask = 0; | |
051fb70f BA |
1235 | qproc->running = true; |
1236 | ||
051fb70f BA |
1237 | return 0; |
1238 | ||
6c5a9dc2 AKD |
1239 | reclaim_mpss: |
1240 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, | |
1241 | false, qproc->mpss_phys, | |
1242 | qproc->mpss_size); | |
1243 | WARN_ON(xfermemop_ret); | |
0304530d | 1244 | q6v5_mba_reclaim(qproc); |
663e9845 | 1245 | |
051fb70f BA |
1246 | return ret; |
1247 | } | |
1248 | ||
1249 | static int q6v5_stop(struct rproc *rproc) | |
1250 | { | |
1251 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
1252 | int ret; | |
1253 | ||
1254 | qproc->running = false; | |
1255 | ||
7d674731 BA |
1256 | ret = qcom_q6v5_request_stop(&qproc->q6v5); |
1257 | if (ret == -ETIMEDOUT) | |
051fb70f BA |
1258 | dev_err(qproc->dev, "timed out on wait\n"); |
1259 | ||
0304530d | 1260 | q6v5_mba_reclaim(qproc); |
051fb70f BA |
1261 | |
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len) | |
1266 | { | |
1267 | struct q6v5 *qproc = rproc->priv; | |
1268 | int offset; | |
1269 | ||
1270 | offset = da - qproc->mpss_reloc; | |
1271 | if (offset < 0 || offset + len > qproc->mpss_size) | |
1272 | return NULL; | |
1273 | ||
1274 | return qproc->mpss_region + offset; | |
1275 | } | |
1276 | ||
f18b7e91 SS |
1277 | static int qcom_q6v5_register_dump_segments(struct rproc *rproc, |
1278 | const struct firmware *mba_fw) | |
1279 | { | |
1280 | const struct firmware *fw; | |
1281 | const struct elf32_phdr *phdrs; | |
1282 | const struct elf32_phdr *phdr; | |
1283 | const struct elf32_hdr *ehdr; | |
1284 | struct q6v5 *qproc = rproc->priv; | |
1285 | unsigned long i; | |
1286 | int ret; | |
1287 | ||
a5a4e02d | 1288 | ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev); |
f18b7e91 | 1289 | if (ret < 0) { |
a5a4e02d SS |
1290 | dev_err(qproc->dev, "unable to load %s\n", |
1291 | qproc->hexagon_mdt_image); | |
f18b7e91 SS |
1292 | return ret; |
1293 | } | |
1294 | ||
1295 | ehdr = (struct elf32_hdr *)fw->data; | |
1296 | phdrs = (struct elf32_phdr *)(ehdr + 1); | |
1297 | qproc->dump_complete_mask = 0; | |
1298 | ||
1299 | for (i = 0; i < ehdr->e_phnum; i++) { | |
1300 | phdr = &phdrs[i]; | |
1301 | ||
1302 | if (!q6v5_phdr_valid(phdr)) | |
1303 | continue; | |
1304 | ||
1305 | ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr, | |
1306 | phdr->p_memsz, | |
1307 | qcom_q6v5_dump_segment, | |
1308 | (void *)i); | |
1309 | if (ret) | |
1310 | break; | |
1311 | ||
1312 | qproc->dump_complete_mask |= BIT(i); | |
1313 | } | |
1314 | ||
1315 | release_firmware(fw); | |
1316 | return ret; | |
1317 | } | |
1318 | ||
051fb70f BA |
1319 | static const struct rproc_ops q6v5_ops = { |
1320 | .start = q6v5_start, | |
1321 | .stop = q6v5_stop, | |
1322 | .da_to_va = q6v5_da_to_va, | |
f18b7e91 | 1323 | .parse_fw = qcom_q6v5_register_dump_segments, |
0f21f9cc | 1324 | .load = q6v5_load, |
051fb70f BA |
1325 | }; |
1326 | ||
7d674731 | 1327 | static void qcom_msa_handover(struct qcom_q6v5 *q6v5) |
663e9845 | 1328 | { |
7d674731 | 1329 | struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5); |
663e9845 SS |
1330 | |
1331 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, | |
1332 | qproc->proxy_clk_count); | |
1333 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
1334 | qproc->proxy_reg_count); | |
4760a896 | 1335 | q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
051fb70f BA |
1336 | } |
1337 | ||
1338 | static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) | |
1339 | { | |
1340 | struct of_phandle_args args; | |
1341 | struct resource *res; | |
1342 | int ret; | |
1343 | ||
1344 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); | |
1345 | qproc->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
b1653f23 | 1346 | if (IS_ERR(qproc->reg_base)) |
051fb70f | 1347 | return PTR_ERR(qproc->reg_base); |
051fb70f BA |
1348 | |
1349 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); | |
1350 | qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res); | |
b1653f23 | 1351 | if (IS_ERR(qproc->rmb_base)) |
051fb70f | 1352 | return PTR_ERR(qproc->rmb_base); |
051fb70f BA |
1353 | |
1354 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
1355 | "qcom,halt-regs", 3, 0, &args); | |
1356 | if (ret < 0) { | |
1357 | dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); | |
1358 | return -EINVAL; | |
1359 | } | |
1360 | ||
1361 | qproc->halt_map = syscon_node_to_regmap(args.np); | |
1362 | of_node_put(args.np); | |
1363 | if (IS_ERR(qproc->halt_map)) | |
1364 | return PTR_ERR(qproc->halt_map); | |
1365 | ||
1366 | qproc->halt_q6 = args.args[0]; | |
1367 | qproc->halt_modem = args.args[1]; | |
1368 | qproc->halt_nc = args.args[2]; | |
1369 | ||
6439b527 SS |
1370 | if (qproc->has_halt_nav) { |
1371 | struct platform_device *nav_pdev; | |
1372 | ||
1373 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
1374 | "qcom,halt-nav-regs", | |
1375 | 1, 0, &args); | |
1376 | if (ret < 0) { | |
1377 | dev_err(&pdev->dev, "failed to parse halt-nav-regs\n"); | |
1378 | return -EINVAL; | |
1379 | } | |
1380 | ||
1381 | nav_pdev = of_find_device_by_node(args.np); | |
1382 | of_node_put(args.np); | |
1383 | if (!nav_pdev) { | |
1384 | dev_err(&pdev->dev, "failed to get mss clock device\n"); | |
1385 | return -EPROBE_DEFER; | |
1386 | } | |
1387 | ||
1388 | qproc->halt_nav_map = dev_get_regmap(&nav_pdev->dev, NULL); | |
1389 | if (!qproc->halt_nav_map) { | |
1390 | dev_err(&pdev->dev, "failed to get map from device\n"); | |
1391 | return -EINVAL; | |
1392 | } | |
1393 | qproc->halt_nav = args.args[0]; | |
1394 | ||
1395 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
1396 | "qcom,halt-nav-regs", | |
1397 | 1, 1, &args); | |
1398 | if (ret < 0) { | |
1399 | dev_err(&pdev->dev, "failed to parse halt-nav-regs\n"); | |
1400 | return -EINVAL; | |
1401 | } | |
1402 | ||
1403 | qproc->conn_map = syscon_node_to_regmap(args.np); | |
1404 | of_node_put(args.np); | |
1405 | if (IS_ERR(qproc->conn_map)) | |
1406 | return PTR_ERR(qproc->conn_map); | |
1407 | ||
1408 | qproc->conn_box = args.args[0]; | |
1409 | } | |
1410 | ||
051fb70f BA |
1411 | return 0; |
1412 | } | |
1413 | ||
39b2410b AKD |
1414 | static int q6v5_init_clocks(struct device *dev, struct clk **clks, |
1415 | char **clk_names) | |
051fb70f | 1416 | { |
39b2410b | 1417 | int i; |
051fb70f | 1418 | |
39b2410b AKD |
1419 | if (!clk_names) |
1420 | return 0; | |
1421 | ||
1422 | for (i = 0; clk_names[i]; i++) { | |
1423 | clks[i] = devm_clk_get(dev, clk_names[i]); | |
1424 | if (IS_ERR(clks[i])) { | |
1425 | int rc = PTR_ERR(clks[i]); | |
051fb70f | 1426 | |
39b2410b AKD |
1427 | if (rc != -EPROBE_DEFER) |
1428 | dev_err(dev, "Failed to get %s clock\n", | |
1429 | clk_names[i]); | |
1430 | return rc; | |
1431 | } | |
051fb70f BA |
1432 | } |
1433 | ||
39b2410b | 1434 | return i; |
051fb70f BA |
1435 | } |
1436 | ||
4760a896 RN |
1437 | static int q6v5_pds_attach(struct device *dev, struct device **devs, |
1438 | char **pd_names) | |
1439 | { | |
1440 | size_t num_pds = 0; | |
1441 | int ret; | |
1442 | int i; | |
1443 | ||
1444 | if (!pd_names) | |
1445 | return 0; | |
1446 | ||
1447 | while (pd_names[num_pds]) | |
1448 | num_pds++; | |
1449 | ||
1450 | for (i = 0; i < num_pds; i++) { | |
1451 | devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); | |
f2583fde SS |
1452 | if (IS_ERR_OR_NULL(devs[i])) { |
1453 | ret = PTR_ERR(devs[i]) ? : -ENODATA; | |
4760a896 RN |
1454 | goto unroll_attach; |
1455 | } | |
1456 | } | |
1457 | ||
1458 | return num_pds; | |
1459 | ||
1460 | unroll_attach: | |
1461 | for (i--; i >= 0; i--) | |
1462 | dev_pm_domain_detach(devs[i], false); | |
1463 | ||
1464 | return ret; | |
1465 | }; | |
1466 | ||
1467 | static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds, | |
1468 | size_t pd_count) | |
1469 | { | |
1470 | int i; | |
1471 | ||
1472 | for (i = 0; i < pd_count; i++) | |
1473 | dev_pm_domain_detach(pds[i], false); | |
1474 | } | |
1475 | ||
051fb70f BA |
1476 | static int q6v5_init_reset(struct q6v5 *qproc) |
1477 | { | |
5acbf7e5 | 1478 | qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev, |
9e483efd | 1479 | "mss_restart"); |
051fb70f BA |
1480 | if (IS_ERR(qproc->mss_restart)) { |
1481 | dev_err(qproc->dev, "failed to acquire mss restart\n"); | |
1482 | return PTR_ERR(qproc->mss_restart); | |
1483 | } | |
1484 | ||
6439b527 | 1485 | if (qproc->has_alt_reset || qproc->has_halt_nav) { |
29a5f9aa SS |
1486 | qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev, |
1487 | "pdc_reset"); | |
1488 | if (IS_ERR(qproc->pdc_reset)) { | |
1489 | dev_err(qproc->dev, "failed to acquire pdc reset\n"); | |
1490 | return PTR_ERR(qproc->pdc_reset); | |
1491 | } | |
1492 | } | |
1493 | ||
051fb70f BA |
1494 | return 0; |
1495 | } | |
1496 | ||
051fb70f BA |
1497 | static int q6v5_alloc_memory_region(struct q6v5 *qproc) |
1498 | { | |
1499 | struct device_node *child; | |
1500 | struct device_node *node; | |
1501 | struct resource r; | |
1502 | int ret; | |
1503 | ||
1504 | child = of_get_child_by_name(qproc->dev->of_node, "mba"); | |
1505 | node = of_parse_phandle(child, "memory-region", 0); | |
1506 | ret = of_address_to_resource(node, 0, &r); | |
1507 | if (ret) { | |
1508 | dev_err(qproc->dev, "unable to resolve mba region\n"); | |
1509 | return ret; | |
1510 | } | |
278d744c | 1511 | of_node_put(node); |
051fb70f BA |
1512 | |
1513 | qproc->mba_phys = r.start; | |
1514 | qproc->mba_size = resource_size(&r); | |
1515 | qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size); | |
1516 | if (!qproc->mba_region) { | |
1517 | dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", | |
1518 | &r.start, qproc->mba_size); | |
1519 | return -EBUSY; | |
1520 | } | |
1521 | ||
1522 | child = of_get_child_by_name(qproc->dev->of_node, "mpss"); | |
1523 | node = of_parse_phandle(child, "memory-region", 0); | |
1524 | ret = of_address_to_resource(node, 0, &r); | |
1525 | if (ret) { | |
1526 | dev_err(qproc->dev, "unable to resolve mpss region\n"); | |
1527 | return ret; | |
1528 | } | |
278d744c | 1529 | of_node_put(node); |
051fb70f BA |
1530 | |
1531 | qproc->mpss_phys = qproc->mpss_reloc = r.start; | |
1532 | qproc->mpss_size = resource_size(&r); | |
1533 | qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size); | |
1534 | if (!qproc->mpss_region) { | |
1535 | dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", | |
1536 | &r.start, qproc->mpss_size); | |
1537 | return -EBUSY; | |
1538 | } | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static int q6v5_probe(struct platform_device *pdev) | |
1544 | { | |
7a8ffe1f | 1545 | const struct rproc_hexagon_res *desc; |
051fb70f BA |
1546 | struct q6v5 *qproc; |
1547 | struct rproc *rproc; | |
a5a4e02d | 1548 | const char *mba_image; |
051fb70f BA |
1549 | int ret; |
1550 | ||
7a8ffe1f AKD |
1551 | desc = of_device_get_match_data(&pdev->dev); |
1552 | if (!desc) | |
1553 | return -EINVAL; | |
1554 | ||
bbcda302 BN |
1555 | if (desc->need_mem_protection && !qcom_scm_is_available()) |
1556 | return -EPROBE_DEFER; | |
1557 | ||
a5a4e02d SS |
1558 | mba_image = desc->hexagon_mba_image; |
1559 | ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", | |
1560 | 0, &mba_image); | |
1561 | if (ret < 0 && ret != -EINVAL) | |
1562 | return ret; | |
1563 | ||
051fb70f | 1564 | rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops, |
a5a4e02d | 1565 | mba_image, sizeof(*qproc)); |
051fb70f BA |
1566 | if (!rproc) { |
1567 | dev_err(&pdev->dev, "failed to allocate rproc\n"); | |
1568 | return -ENOMEM; | |
1569 | } | |
1570 | ||
4107102d RF |
1571 | rproc->auto_boot = false; |
1572 | ||
051fb70f BA |
1573 | qproc = (struct q6v5 *)rproc->priv; |
1574 | qproc->dev = &pdev->dev; | |
1575 | qproc->rproc = rproc; | |
a5a4e02d SS |
1576 | qproc->hexagon_mdt_image = "modem.mdt"; |
1577 | ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", | |
1578 | 1, &qproc->hexagon_mdt_image); | |
1579 | if (ret < 0 && ret != -EINVAL) | |
1580 | return ret; | |
1581 | ||
051fb70f BA |
1582 | platform_set_drvdata(pdev, qproc); |
1583 | ||
6439b527 | 1584 | qproc->has_halt_nav = desc->has_halt_nav; |
051fb70f BA |
1585 | ret = q6v5_init_mem(qproc, pdev); |
1586 | if (ret) | |
1587 | goto free_rproc; | |
1588 | ||
1589 | ret = q6v5_alloc_memory_region(qproc); | |
1590 | if (ret) | |
1591 | goto free_rproc; | |
1592 | ||
39b2410b AKD |
1593 | ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks, |
1594 | desc->proxy_clk_names); | |
1595 | if (ret < 0) { | |
1596 | dev_err(&pdev->dev, "Failed to get proxy clocks.\n"); | |
051fb70f | 1597 | goto free_rproc; |
39b2410b AKD |
1598 | } |
1599 | qproc->proxy_clk_count = ret; | |
1600 | ||
231f67d1 SS |
1601 | ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks, |
1602 | desc->reset_clk_names); | |
1603 | if (ret < 0) { | |
1604 | dev_err(&pdev->dev, "Failed to get reset clocks.\n"); | |
1605 | goto free_rproc; | |
1606 | } | |
1607 | qproc->reset_clk_count = ret; | |
1608 | ||
39b2410b AKD |
1609 | ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks, |
1610 | desc->active_clk_names); | |
1611 | if (ret < 0) { | |
1612 | dev_err(&pdev->dev, "Failed to get active clocks.\n"); | |
1613 | goto free_rproc; | |
1614 | } | |
1615 | qproc->active_clk_count = ret; | |
051fb70f | 1616 | |
19f902b5 AKD |
1617 | ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs, |
1618 | desc->proxy_supply); | |
1619 | if (ret < 0) { | |
1620 | dev_err(&pdev->dev, "Failed to get proxy regulators.\n"); | |
051fb70f | 1621 | goto free_rproc; |
19f902b5 AKD |
1622 | } |
1623 | qproc->proxy_reg_count = ret; | |
1624 | ||
1625 | ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs, | |
1626 | desc->active_supply); | |
1627 | if (ret < 0) { | |
1628 | dev_err(&pdev->dev, "Failed to get active regulators.\n"); | |
1629 | goto free_rproc; | |
1630 | } | |
1631 | qproc->active_reg_count = ret; | |
051fb70f | 1632 | |
deb9bb83 BA |
1633 | ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds, |
1634 | desc->active_pd_names); | |
1635 | if (ret < 0) { | |
1636 | dev_err(&pdev->dev, "Failed to attach active power domains\n"); | |
1637 | goto free_rproc; | |
1638 | } | |
1639 | qproc->active_pd_count = ret; | |
1640 | ||
4760a896 RN |
1641 | ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds, |
1642 | desc->proxy_pd_names); | |
1643 | if (ret < 0) { | |
1644 | dev_err(&pdev->dev, "Failed to init power domains\n"); | |
deb9bb83 | 1645 | goto detach_active_pds; |
4760a896 RN |
1646 | } |
1647 | qproc->proxy_pd_count = ret; | |
1648 | ||
29a5f9aa | 1649 | qproc->has_alt_reset = desc->has_alt_reset; |
051fb70f BA |
1650 | ret = q6v5_init_reset(qproc); |
1651 | if (ret) | |
4760a896 | 1652 | goto detach_proxy_pds; |
051fb70f | 1653 | |
9f058fa2 | 1654 | qproc->version = desc->version; |
6c5a9dc2 | 1655 | qproc->need_mem_protection = desc->need_mem_protection; |
051fb70f | 1656 | |
7d674731 BA |
1657 | ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, |
1658 | qcom_msa_handover); | |
1659 | if (ret) | |
4760a896 | 1660 | goto detach_proxy_pds; |
051fb70f | 1661 | |
6c5a9dc2 AKD |
1662 | qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); |
1663 | qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); | |
4725496e | 1664 | qcom_add_glink_subdev(rproc, &qproc->glink_subdev); |
4b48921a | 1665 | qcom_add_smd_subdev(rproc, &qproc->smd_subdev); |
1e140df0 | 1666 | qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss"); |
1fb82ee8 | 1667 | qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12); |
027045a6 SS |
1668 | if (IS_ERR(qproc->sysmon)) { |
1669 | ret = PTR_ERR(qproc->sysmon); | |
4760a896 | 1670 | goto detach_proxy_pds; |
027045a6 | 1671 | } |
4b48921a | 1672 | |
051fb70f BA |
1673 | ret = rproc_add(rproc); |
1674 | if (ret) | |
4760a896 | 1675 | goto detach_proxy_pds; |
051fb70f BA |
1676 | |
1677 | return 0; | |
1678 | ||
4760a896 RN |
1679 | detach_proxy_pds: |
1680 | q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); | |
deb9bb83 BA |
1681 | detach_active_pds: |
1682 | q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); | |
051fb70f | 1683 | free_rproc: |
433c0e04 | 1684 | rproc_free(rproc); |
051fb70f BA |
1685 | |
1686 | return ret; | |
1687 | } | |
1688 | ||
1689 | static int q6v5_remove(struct platform_device *pdev) | |
1690 | { | |
1691 | struct q6v5 *qproc = platform_get_drvdata(pdev); | |
1692 | ||
1693 | rproc_del(qproc->rproc); | |
4b48921a | 1694 | |
1fb82ee8 | 1695 | qcom_remove_sysmon_subdev(qproc->sysmon); |
4725496e | 1696 | qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev); |
4b48921a | 1697 | qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev); |
1e140df0 | 1698 | qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev); |
4760a896 | 1699 | |
deb9bb83 | 1700 | q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); |
4760a896 RN |
1701 | q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
1702 | ||
433c0e04 | 1703 | rproc_free(qproc->rproc); |
051fb70f BA |
1704 | |
1705 | return 0; | |
1706 | } | |
1707 | ||
6439b527 SS |
1708 | static const struct rproc_hexagon_res sc7180_mss = { |
1709 | .hexagon_mba_image = "mba.mbn", | |
1710 | .proxy_clk_names = (char*[]){ | |
1711 | "xo", | |
1712 | NULL | |
1713 | }, | |
1714 | .reset_clk_names = (char*[]){ | |
1715 | "iface", | |
1716 | "bus", | |
1717 | "snoc_axi", | |
1718 | NULL | |
1719 | }, | |
1720 | .active_clk_names = (char*[]){ | |
1721 | "mnoc_axi", | |
1722 | "nav", | |
1723 | "mss_nav", | |
1724 | "mss_crypto", | |
1725 | NULL | |
1726 | }, | |
1727 | .active_pd_names = (char*[]){ | |
1728 | "load_state", | |
1729 | NULL | |
1730 | }, | |
1731 | .proxy_pd_names = (char*[]){ | |
1732 | "cx", | |
1733 | "mx", | |
1734 | "mss", | |
1735 | NULL | |
1736 | }, | |
1737 | .need_mem_protection = true, | |
1738 | .has_alt_reset = false, | |
1739 | .has_halt_nav = true, | |
1740 | .version = MSS_SC7180, | |
1741 | }; | |
1742 | ||
231f67d1 SS |
1743 | static const struct rproc_hexagon_res sdm845_mss = { |
1744 | .hexagon_mba_image = "mba.mbn", | |
1745 | .proxy_clk_names = (char*[]){ | |
1746 | "xo", | |
231f67d1 SS |
1747 | "prng", |
1748 | NULL | |
1749 | }, | |
1750 | .reset_clk_names = (char*[]){ | |
1751 | "iface", | |
1752 | "snoc_axi", | |
1753 | NULL | |
1754 | }, | |
1755 | .active_clk_names = (char*[]){ | |
1756 | "bus", | |
1757 | "mem", | |
1758 | "gpll0_mss", | |
1759 | "mnoc_axi", | |
1760 | NULL | |
1761 | }, | |
deb9bb83 BA |
1762 | .active_pd_names = (char*[]){ |
1763 | "load_state", | |
1764 | NULL | |
1765 | }, | |
4760a896 RN |
1766 | .proxy_pd_names = (char*[]){ |
1767 | "cx", | |
1768 | "mx", | |
1769 | "mss", | |
1770 | NULL | |
1771 | }, | |
231f67d1 SS |
1772 | .need_mem_protection = true, |
1773 | .has_alt_reset = true, | |
6439b527 | 1774 | .has_halt_nav = false, |
231f67d1 SS |
1775 | .version = MSS_SDM845, |
1776 | }; | |
1777 | ||
1665cbd5 JH |
1778 | static const struct rproc_hexagon_res msm8998_mss = { |
1779 | .hexagon_mba_image = "mba.mbn", | |
1780 | .proxy_clk_names = (char*[]){ | |
1781 | "xo", | |
1782 | "qdss", | |
1783 | "mem", | |
1784 | NULL | |
1785 | }, | |
1786 | .active_clk_names = (char*[]){ | |
1787 | "iface", | |
1788 | "bus", | |
1665cbd5 JH |
1789 | "gpll0_mss", |
1790 | "mnoc_axi", | |
1791 | "snoc_axi", | |
1792 | NULL | |
1793 | }, | |
1794 | .proxy_pd_names = (char*[]){ | |
1795 | "cx", | |
1796 | "mx", | |
1797 | NULL | |
1798 | }, | |
1799 | .need_mem_protection = true, | |
1800 | .has_alt_reset = false, | |
6439b527 | 1801 | .has_halt_nav = false, |
1665cbd5 JH |
1802 | .version = MSS_MSM8998, |
1803 | }; | |
1804 | ||
9f058fa2 AKD |
1805 | static const struct rproc_hexagon_res msm8996_mss = { |
1806 | .hexagon_mba_image = "mba.mbn", | |
47b87474 SS |
1807 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
1808 | { | |
1809 | .supply = "pll", | |
1810 | .uA = 100000, | |
1811 | }, | |
1812 | {} | |
1813 | }, | |
9f058fa2 AKD |
1814 | .proxy_clk_names = (char*[]){ |
1815 | "xo", | |
1816 | "pnoc", | |
80ec419c | 1817 | "qdss", |
9f058fa2 AKD |
1818 | NULL |
1819 | }, | |
1820 | .active_clk_names = (char*[]){ | |
1821 | "iface", | |
1822 | "bus", | |
1823 | "mem", | |
80ec419c SS |
1824 | "gpll0_mss", |
1825 | "snoc_axi", | |
1826 | "mnoc_axi", | |
9f058fa2 AKD |
1827 | NULL |
1828 | }, | |
1829 | .need_mem_protection = true, | |
231f67d1 | 1830 | .has_alt_reset = false, |
6439b527 | 1831 | .has_halt_nav = false, |
9f058fa2 AKD |
1832 | .version = MSS_MSM8996, |
1833 | }; | |
1834 | ||
7a8ffe1f AKD |
1835 | static const struct rproc_hexagon_res msm8916_mss = { |
1836 | .hexagon_mba_image = "mba.mbn", | |
19f902b5 AKD |
1837 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
1838 | { | |
1839 | .supply = "mx", | |
1840 | .uV = 1050000, | |
1841 | }, | |
1842 | { | |
1843 | .supply = "cx", | |
1844 | .uA = 100000, | |
1845 | }, | |
1846 | { | |
1847 | .supply = "pll", | |
1848 | .uA = 100000, | |
1849 | }, | |
1850 | {} | |
1851 | }, | |
39b2410b AKD |
1852 | .proxy_clk_names = (char*[]){ |
1853 | "xo", | |
1854 | NULL | |
1855 | }, | |
1856 | .active_clk_names = (char*[]){ | |
1857 | "iface", | |
1858 | "bus", | |
1859 | "mem", | |
1860 | NULL | |
1861 | }, | |
6c5a9dc2 | 1862 | .need_mem_protection = false, |
231f67d1 | 1863 | .has_alt_reset = false, |
6439b527 | 1864 | .has_halt_nav = false, |
9f058fa2 | 1865 | .version = MSS_MSM8916, |
7a8ffe1f AKD |
1866 | }; |
1867 | ||
1868 | static const struct rproc_hexagon_res msm8974_mss = { | |
1869 | .hexagon_mba_image = "mba.b00", | |
19f902b5 AKD |
1870 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
1871 | { | |
1872 | .supply = "mx", | |
1873 | .uV = 1050000, | |
1874 | }, | |
1875 | { | |
1876 | .supply = "cx", | |
1877 | .uA = 100000, | |
1878 | }, | |
1879 | { | |
1880 | .supply = "pll", | |
1881 | .uA = 100000, | |
1882 | }, | |
1883 | {} | |
1884 | }, | |
1885 | .active_supply = (struct qcom_mss_reg_res[]) { | |
1886 | { | |
1887 | .supply = "mss", | |
1888 | .uV = 1050000, | |
1889 | .uA = 100000, | |
1890 | }, | |
1891 | {} | |
1892 | }, | |
39b2410b AKD |
1893 | .proxy_clk_names = (char*[]){ |
1894 | "xo", | |
1895 | NULL | |
1896 | }, | |
1897 | .active_clk_names = (char*[]){ | |
1898 | "iface", | |
1899 | "bus", | |
1900 | "mem", | |
1901 | NULL | |
1902 | }, | |
6c5a9dc2 | 1903 | .need_mem_protection = false, |
231f67d1 | 1904 | .has_alt_reset = false, |
6439b527 | 1905 | .has_halt_nav = false, |
9f058fa2 | 1906 | .version = MSS_MSM8974, |
7a8ffe1f AKD |
1907 | }; |
1908 | ||
051fb70f | 1909 | static const struct of_device_id q6v5_of_match[] = { |
7a8ffe1f AKD |
1910 | { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, |
1911 | { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, | |
1912 | { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, | |
9f058fa2 | 1913 | { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, |
1665cbd5 | 1914 | { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss}, |
6439b527 | 1915 | { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss}, |
231f67d1 | 1916 | { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss}, |
051fb70f BA |
1917 | { }, |
1918 | }; | |
3227c876 | 1919 | MODULE_DEVICE_TABLE(of, q6v5_of_match); |
051fb70f BA |
1920 | |
1921 | static struct platform_driver q6v5_driver = { | |
1922 | .probe = q6v5_probe, | |
1923 | .remove = q6v5_remove, | |
1924 | .driver = { | |
ef73c22f | 1925 | .name = "qcom-q6v5-mss", |
051fb70f BA |
1926 | .of_match_table = q6v5_of_match, |
1927 | }, | |
1928 | }; | |
1929 | module_platform_driver(q6v5_driver); | |
1930 | ||
ef73c22f | 1931 | MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver"); |
051fb70f | 1932 | MODULE_LICENSE("GPL v2"); |