Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
051fb70f | 2 | /* |
ef73c22f | 3 | * Qualcomm self-authenticating modem subsystem remoteproc driver |
051fb70f BA |
4 | * |
5 | * Copyright (C) 2016 Linaro Ltd. | |
6 | * Copyright (C) 2014 Sony Mobile Communications AB | |
7 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. | |
051fb70f BA |
8 | */ |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
318130cc | 12 | #include <linux/devcoredump.h> |
051fb70f BA |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/mfd/syscon.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of_address.h> | |
7a8ffe1f | 19 | #include <linux/of_device.h> |
051fb70f | 20 | #include <linux/platform_device.h> |
4760a896 RN |
21 | #include <linux/pm_domain.h> |
22 | #include <linux/pm_runtime.h> | |
051fb70f BA |
23 | #include <linux/regmap.h> |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/remoteproc.h> | |
26 | #include <linux/reset.h> | |
2aad40d9 | 27 | #include <linux/soc/qcom/mdt_loader.h> |
9f058fa2 | 28 | #include <linux/iopoll.h> |
7999096f | 29 | #include <linux/slab.h> |
051fb70f BA |
30 | |
31 | #include "remoteproc_internal.h" | |
bde440ee | 32 | #include "qcom_common.h" |
d4c78d21 | 33 | #include "qcom_pil_info.h" |
7d674731 | 34 | #include "qcom_q6v5.h" |
051fb70f BA |
35 | |
36 | #include <linux/qcom_scm.h> | |
37 | ||
051fb70f BA |
38 | #define MPSS_CRASH_REASON_SMEM 421 |
39 | ||
318130cc SS |
40 | #define MBA_LOG_SIZE SZ_4K |
41 | ||
051fb70f BA |
42 | /* RMB Status Register Values */ |
43 | #define RMB_PBL_SUCCESS 0x1 | |
44 | ||
45 | #define RMB_MBA_XPU_UNLOCKED 0x1 | |
46 | #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2 | |
47 | #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3 | |
48 | #define RMB_MBA_AUTH_COMPLETE 0x4 | |
49 | ||
50 | /* PBL/MBA interface registers */ | |
51 | #define RMB_MBA_IMAGE_REG 0x00 | |
52 | #define RMB_PBL_STATUS_REG 0x04 | |
53 | #define RMB_MBA_COMMAND_REG 0x08 | |
54 | #define RMB_MBA_STATUS_REG 0x0C | |
55 | #define RMB_PMI_META_DATA_REG 0x10 | |
56 | #define RMB_PMI_CODE_START_REG 0x14 | |
57 | #define RMB_PMI_CODE_LENGTH_REG 0x18 | |
231f67d1 SS |
58 | #define RMB_MBA_MSS_STATUS 0x40 |
59 | #define RMB_MBA_ALT_RESET 0x44 | |
051fb70f BA |
60 | |
61 | #define RMB_CMD_META_DATA_READY 0x1 | |
62 | #define RMB_CMD_LOAD_READY 0x2 | |
63 | ||
64 | /* QDSP6SS Register Offsets */ | |
65 | #define QDSP6SS_RESET_REG 0x014 | |
66 | #define QDSP6SS_GFMUX_CTL_REG 0x020 | |
67 | #define QDSP6SS_PWR_CTL_REG 0x030 | |
9f058fa2 | 68 | #define QDSP6SS_MEM_PWR_CTL 0x0B0 |
1665cbd5 | 69 | #define QDSP6V6SS_MEM_PWR_CTL 0x034 |
9f058fa2 | 70 | #define QDSP6SS_STRAP_ACC 0x110 |
051fb70f BA |
71 | |
72 | /* AXI Halt Register Offsets */ | |
73 | #define AXI_HALTREQ_REG 0x0 | |
74 | #define AXI_HALTACK_REG 0x4 | |
75 | #define AXI_IDLE_REG 0x8 | |
600c39b3 | 76 | #define AXI_GATING_VALID_OVERRIDE BIT(0) |
051fb70f | 77 | |
01bf3fec | 78 | #define HALT_ACK_TIMEOUT_US 100000 |
051fb70f | 79 | |
c842379d SS |
80 | /* QACCEPT Register Offsets */ |
81 | #define QACCEPT_ACCEPT_REG 0x0 | |
82 | #define QACCEPT_ACTIVE_REG 0x4 | |
83 | #define QACCEPT_DENY_REG 0x8 | |
84 | #define QACCEPT_REQ_REG 0xC | |
85 | ||
86 | #define QACCEPT_TIMEOUT_US 50 | |
87 | ||
051fb70f BA |
88 | /* QDSP6SS_RESET */ |
89 | #define Q6SS_STOP_CORE BIT(0) | |
90 | #define Q6SS_CORE_ARES BIT(1) | |
91 | #define Q6SS_BUS_ARES_ENABLE BIT(2) | |
92 | ||
7e0f8688 SS |
93 | /* QDSP6SS CBCR */ |
94 | #define Q6SS_CBCR_CLKEN BIT(0) | |
95 | #define Q6SS_CBCR_CLKOFF BIT(31) | |
96 | #define Q6SS_CBCR_TIMEOUT_US 200 | |
97 | ||
051fb70f BA |
98 | /* QDSP6SS_GFMUX_CTL */ |
99 | #define Q6SS_CLK_ENABLE BIT(1) | |
100 | ||
101 | /* QDSP6SS_PWR_CTL */ | |
102 | #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0) | |
103 | #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1) | |
104 | #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2) | |
105 | #define Q6SS_L2TAG_SLP_NRET_N BIT(16) | |
106 | #define Q6SS_ETB_SLP_NRET_N BIT(17) | |
107 | #define Q6SS_L2DATA_STBY_N BIT(18) | |
108 | #define Q6SS_SLP_RET_N BIT(19) | |
109 | #define Q6SS_CLAMP_IO BIT(20) | |
110 | #define QDSS_BHS_ON BIT(21) | |
111 | #define QDSS_LDO_BYP BIT(22) | |
112 | ||
9f058fa2 AKD |
113 | /* QDSP6v56 parameters */ |
114 | #define QDSP6v56_LDO_BYP BIT(25) | |
115 | #define QDSP6v56_BHS_ON BIT(24) | |
116 | #define QDSP6v56_CLAMP_WL BIT(21) | |
117 | #define QDSP6v56_CLAMP_QMC_MEM BIT(22) | |
9f058fa2 AKD |
118 | #define QDSP6SS_XO_CBCR 0x0038 |
119 | #define QDSP6SS_ACC_OVERRIDE_VAL 0x20 | |
120 | ||
231f67d1 | 121 | /* QDSP6v65 parameters */ |
6439b527 | 122 | #define QDSP6SS_CORE_CBCR 0x20 |
231f67d1 SS |
123 | #define QDSP6SS_SLEEP 0x3C |
124 | #define QDSP6SS_BOOT_CORE_START 0x400 | |
125 | #define QDSP6SS_BOOT_CMD 0x404 | |
231f67d1 SS |
126 | #define BOOT_FSM_TIMEOUT 10000 |
127 | ||
19f902b5 AKD |
128 | struct reg_info { |
129 | struct regulator *reg; | |
130 | int uV; | |
131 | int uA; | |
132 | }; | |
133 | ||
134 | struct qcom_mss_reg_res { | |
135 | const char *supply; | |
136 | int uV; | |
137 | int uA; | |
138 | }; | |
139 | ||
7a8ffe1f AKD |
140 | struct rproc_hexagon_res { |
141 | const char *hexagon_mba_image; | |
ec671b53 | 142 | struct qcom_mss_reg_res *proxy_supply; |
8750cf39 | 143 | struct qcom_mss_reg_res *fallback_proxy_supply; |
ec671b53 | 144 | struct qcom_mss_reg_res *active_supply; |
39b2410b | 145 | char **proxy_clk_names; |
231f67d1 | 146 | char **reset_clk_names; |
39b2410b | 147 | char **active_clk_names; |
4760a896 | 148 | char **proxy_pd_names; |
9f058fa2 | 149 | int version; |
6c5a9dc2 | 150 | bool need_mem_protection; |
231f67d1 | 151 | bool has_alt_reset; |
318130cc | 152 | bool has_mba_logs; |
a9fdc79d | 153 | bool has_spare_reg; |
c842379d SS |
154 | bool has_qaccept_regs; |
155 | bool has_ext_cntl_regs; | |
156 | bool has_vq6; | |
7a8ffe1f AKD |
157 | }; |
158 | ||
051fb70f BA |
159 | struct q6v5 { |
160 | struct device *dev; | |
161 | struct rproc *rproc; | |
162 | ||
163 | void __iomem *reg_base; | |
164 | void __iomem *rmb_base; | |
165 | ||
166 | struct regmap *halt_map; | |
6439b527 SS |
167 | struct regmap *conn_map; |
168 | ||
051fb70f BA |
169 | u32 halt_q6; |
170 | u32 halt_modem; | |
171 | u32 halt_nc; | |
c842379d | 172 | u32 halt_vq6; |
6439b527 | 173 | u32 conn_box; |
051fb70f | 174 | |
c842379d SS |
175 | u32 qaccept_mdm; |
176 | u32 qaccept_cx; | |
177 | u32 qaccept_axi; | |
178 | ||
179 | u32 axim1_clk_off; | |
180 | u32 crypto_clk_off; | |
181 | u32 force_clk_on; | |
182 | u32 rscc_disable; | |
183 | ||
051fb70f | 184 | struct reset_control *mss_restart; |
29a5f9aa | 185 | struct reset_control *pdc_reset; |
051fb70f | 186 | |
7d674731 | 187 | struct qcom_q6v5 q6v5; |
663e9845 | 188 | |
39b2410b | 189 | struct clk *active_clks[8]; |
231f67d1 | 190 | struct clk *reset_clks[4]; |
39b2410b | 191 | struct clk *proxy_clks[4]; |
4760a896 | 192 | struct device *proxy_pds[3]; |
39b2410b | 193 | int active_clk_count; |
231f67d1 | 194 | int reset_clk_count; |
39b2410b | 195 | int proxy_clk_count; |
4760a896 | 196 | int proxy_pd_count; |
39b2410b | 197 | |
19f902b5 | 198 | struct reg_info active_regs[1]; |
8750cf39 SG |
199 | struct reg_info proxy_regs[1]; |
200 | struct reg_info fallback_proxy_regs[2]; | |
19f902b5 AKD |
201 | int active_reg_count; |
202 | int proxy_reg_count; | |
8750cf39 | 203 | int fallback_proxy_reg_count; |
051fb70f | 204 | |
0304530d | 205 | bool dump_mba_loaded; |
7ac516d3 SS |
206 | size_t current_dump_size; |
207 | size_t total_dump_size; | |
7dd8ade2 | 208 | |
051fb70f | 209 | phys_addr_t mba_phys; |
051fb70f | 210 | size_t mba_size; |
fe6a5dc4 | 211 | size_t dp_size; |
051fb70f BA |
212 | |
213 | phys_addr_t mpss_phys; | |
214 | phys_addr_t mpss_reloc; | |
051fb70f | 215 | size_t mpss_size; |
4b48921a | 216 | |
4725496e | 217 | struct qcom_rproc_glink glink_subdev; |
4b48921a | 218 | struct qcom_rproc_subdev smd_subdev; |
1e140df0 | 219 | struct qcom_rproc_ssr ssr_subdev; |
1fb82ee8 | 220 | struct qcom_sysmon *sysmon; |
6c5a9dc2 | 221 | bool need_mem_protection; |
231f67d1 | 222 | bool has_alt_reset; |
318130cc | 223 | bool has_mba_logs; |
a9fdc79d | 224 | bool has_spare_reg; |
c842379d SS |
225 | bool has_qaccept_regs; |
226 | bool has_ext_cntl_regs; | |
227 | bool has_vq6; | |
6c5a9dc2 AKD |
228 | int mpss_perm; |
229 | int mba_perm; | |
a5a4e02d | 230 | const char *hexagon_mdt_image; |
9f058fa2 AKD |
231 | int version; |
232 | }; | |
6c5a9dc2 | 233 | |
9f058fa2 AKD |
234 | enum { |
235 | MSS_MSM8916, | |
236 | MSS_MSM8974, | |
237 | MSS_MSM8996, | |
1665cbd5 | 238 | MSS_MSM8998, |
6439b527 | 239 | MSS_SC7180, |
c842379d | 240 | MSS_SC7280, |
231f67d1 | 241 | MSS_SDM845, |
051fb70f BA |
242 | }; |
243 | ||
19f902b5 AKD |
244 | static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, |
245 | const struct qcom_mss_reg_res *reg_res) | |
051fb70f | 246 | { |
19f902b5 AKD |
247 | int rc; |
248 | int i; | |
051fb70f | 249 | |
2bb5d906 BA |
250 | if (!reg_res) |
251 | return 0; | |
252 | ||
19f902b5 AKD |
253 | for (i = 0; reg_res[i].supply; i++) { |
254 | regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); | |
255 | if (IS_ERR(regs[i].reg)) { | |
256 | rc = PTR_ERR(regs[i].reg); | |
257 | if (rc != -EPROBE_DEFER) | |
258 | dev_err(dev, "Failed to get %s\n regulator", | |
259 | reg_res[i].supply); | |
260 | return rc; | |
261 | } | |
051fb70f | 262 | |
19f902b5 AKD |
263 | regs[i].uV = reg_res[i].uV; |
264 | regs[i].uA = reg_res[i].uA; | |
051fb70f BA |
265 | } |
266 | ||
19f902b5 | 267 | return i; |
051fb70f BA |
268 | } |
269 | ||
19f902b5 AKD |
270 | static int q6v5_regulator_enable(struct q6v5 *qproc, |
271 | struct reg_info *regs, int count) | |
051fb70f | 272 | { |
051fb70f | 273 | int ret; |
19f902b5 | 274 | int i; |
051fb70f | 275 | |
19f902b5 AKD |
276 | for (i = 0; i < count; i++) { |
277 | if (regs[i].uV > 0) { | |
278 | ret = regulator_set_voltage(regs[i].reg, | |
279 | regs[i].uV, INT_MAX); | |
280 | if (ret) { | |
281 | dev_err(qproc->dev, | |
282 | "Failed to request voltage for %d.\n", | |
283 | i); | |
284 | goto err; | |
285 | } | |
286 | } | |
051fb70f | 287 | |
19f902b5 AKD |
288 | if (regs[i].uA > 0) { |
289 | ret = regulator_set_load(regs[i].reg, | |
290 | regs[i].uA); | |
291 | if (ret < 0) { | |
292 | dev_err(qproc->dev, | |
293 | "Failed to set regulator mode\n"); | |
294 | goto err; | |
295 | } | |
296 | } | |
297 | ||
298 | ret = regulator_enable(regs[i].reg); | |
299 | if (ret) { | |
300 | dev_err(qproc->dev, "Regulator enable failed\n"); | |
301 | goto err; | |
302 | } | |
303 | } | |
304 | ||
305 | return 0; | |
306 | err: | |
307 | for (; i >= 0; i--) { | |
308 | if (regs[i].uV > 0) | |
309 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
310 | ||
311 | if (regs[i].uA > 0) | |
312 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 313 | |
19f902b5 AKD |
314 | regulator_disable(regs[i].reg); |
315 | } | |
051fb70f | 316 | |
19f902b5 | 317 | return ret; |
051fb70f BA |
318 | } |
319 | ||
19f902b5 AKD |
320 | static void q6v5_regulator_disable(struct q6v5 *qproc, |
321 | struct reg_info *regs, int count) | |
051fb70f | 322 | { |
19f902b5 AKD |
323 | int i; |
324 | ||
325 | for (i = 0; i < count; i++) { | |
326 | if (regs[i].uV > 0) | |
327 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
051fb70f | 328 | |
19f902b5 AKD |
329 | if (regs[i].uA > 0) |
330 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 331 | |
19f902b5 AKD |
332 | regulator_disable(regs[i].reg); |
333 | } | |
051fb70f BA |
334 | } |
335 | ||
39b2410b AKD |
336 | static int q6v5_clk_enable(struct device *dev, |
337 | struct clk **clks, int count) | |
338 | { | |
339 | int rc; | |
340 | int i; | |
341 | ||
342 | for (i = 0; i < count; i++) { | |
343 | rc = clk_prepare_enable(clks[i]); | |
344 | if (rc) { | |
345 | dev_err(dev, "Clock enable failed\n"); | |
346 | goto err; | |
347 | } | |
348 | } | |
349 | ||
350 | return 0; | |
351 | err: | |
352 | for (i--; i >= 0; i--) | |
353 | clk_disable_unprepare(clks[i]); | |
354 | ||
355 | return rc; | |
356 | } | |
357 | ||
358 | static void q6v5_clk_disable(struct device *dev, | |
359 | struct clk **clks, int count) | |
360 | { | |
361 | int i; | |
362 | ||
363 | for (i = 0; i < count; i++) | |
364 | clk_disable_unprepare(clks[i]); | |
365 | } | |
366 | ||
4760a896 RN |
367 | static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds, |
368 | size_t pd_count) | |
369 | { | |
370 | int ret; | |
371 | int i; | |
372 | ||
373 | for (i = 0; i < pd_count; i++) { | |
374 | dev_pm_genpd_set_performance_state(pds[i], INT_MAX); | |
375 | ret = pm_runtime_get_sync(pds[i]); | |
a2472305 ZQ |
376 | if (ret < 0) { |
377 | pm_runtime_put_noidle(pds[i]); | |
378 | dev_pm_genpd_set_performance_state(pds[i], 0); | |
4760a896 | 379 | goto unroll_pd_votes; |
a2472305 | 380 | } |
4760a896 RN |
381 | } |
382 | ||
383 | return 0; | |
384 | ||
385 | unroll_pd_votes: | |
386 | for (i--; i >= 0; i--) { | |
387 | dev_pm_genpd_set_performance_state(pds[i], 0); | |
388 | pm_runtime_put(pds[i]); | |
389 | } | |
390 | ||
391 | return ret; | |
58396810 | 392 | } |
4760a896 RN |
393 | |
394 | static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds, | |
395 | size_t pd_count) | |
396 | { | |
397 | int i; | |
398 | ||
399 | for (i = 0; i < pd_count; i++) { | |
400 | dev_pm_genpd_set_performance_state(pds[i], 0); | |
401 | pm_runtime_put(pds[i]); | |
402 | } | |
403 | } | |
404 | ||
6c5a9dc2 | 405 | static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, |
715d8525 | 406 | bool local, bool remote, phys_addr_t addr, |
6c5a9dc2 AKD |
407 | size_t size) |
408 | { | |
715d8525 BA |
409 | struct qcom_scm_vmperm next[2]; |
410 | int perms = 0; | |
6c5a9dc2 AKD |
411 | |
412 | if (!qproc->need_mem_protection) | |
413 | return 0; | |
715d8525 BA |
414 | |
415 | if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) && | |
416 | remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA))) | |
6c5a9dc2 AKD |
417 | return 0; |
418 | ||
715d8525 BA |
419 | if (local) { |
420 | next[perms].vmid = QCOM_SCM_VMID_HLOS; | |
421 | next[perms].perm = QCOM_SCM_PERM_RWX; | |
422 | perms++; | |
423 | } | |
424 | ||
425 | if (remote) { | |
426 | next[perms].vmid = QCOM_SCM_VMID_MSS_MSA; | |
427 | next[perms].perm = QCOM_SCM_PERM_RW; | |
428 | perms++; | |
429 | } | |
6c5a9dc2 | 430 | |
9f2a4342 | 431 | return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K), |
715d8525 | 432 | current_perm, next, perms); |
6c5a9dc2 AKD |
433 | } |
434 | ||
a7ed5e57 | 435 | static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region) |
fe6a5dc4 SS |
436 | { |
437 | const struct firmware *dp_fw; | |
438 | ||
439 | if (request_firmware_direct(&dp_fw, "msadp", qproc->dev)) | |
440 | return; | |
441 | ||
442 | if (SZ_1M + dp_fw->size <= qproc->mba_size) { | |
a7ed5e57 | 443 | memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size); |
fe6a5dc4 SS |
444 | qproc->dp_size = dp_fw->size; |
445 | } | |
446 | ||
447 | release_firmware(dp_fw); | |
448 | } | |
449 | ||
051fb70f BA |
450 | static int q6v5_load(struct rproc *rproc, const struct firmware *fw) |
451 | { | |
452 | struct q6v5 *qproc = rproc->priv; | |
a7ed5e57 | 453 | void *mba_region; |
051fb70f | 454 | |
e013f455 SS |
455 | /* MBA is restricted to a maximum size of 1M */ |
456 | if (fw->size > qproc->mba_size || fw->size > SZ_1M) { | |
457 | dev_err(qproc->dev, "MBA firmware load failed\n"); | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
a7ed5e57 SS |
461 | mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC); |
462 | if (!mba_region) { | |
463 | dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", | |
464 | &qproc->mba_phys, qproc->mba_size); | |
465 | return -EBUSY; | |
466 | } | |
467 | ||
468 | memcpy(mba_region, fw->data, fw->size); | |
469 | q6v5_debug_policy_load(qproc, mba_region); | |
470 | memunmap(mba_region); | |
051fb70f BA |
471 | |
472 | return 0; | |
473 | } | |
474 | ||
9f135fa1 SS |
475 | static int q6v5_reset_assert(struct q6v5 *qproc) |
476 | { | |
29a5f9aa SS |
477 | int ret; |
478 | ||
479 | if (qproc->has_alt_reset) { | |
480 | reset_control_assert(qproc->pdc_reset); | |
481 | ret = reset_control_reset(qproc->mss_restart); | |
482 | reset_control_deassert(qproc->pdc_reset); | |
a9fdc79d | 483 | } else if (qproc->has_spare_reg) { |
600c39b3 SS |
484 | /* |
485 | * When the AXI pipeline is being reset with the Q6 modem partly | |
486 | * operational there is possibility of AXI valid signal to | |
487 | * glitch, leading to spurious transactions and Q6 hangs. A work | |
488 | * around is employed by asserting the AXI_GATING_VALID_OVERRIDE | |
a9fdc79d SS |
489 | * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE |
490 | * is withdrawn post MSS assert followed by a MSS deassert, | |
491 | * while holding the PDC reset. | |
600c39b3 | 492 | */ |
6439b527 SS |
493 | reset_control_assert(qproc->pdc_reset); |
494 | regmap_update_bits(qproc->conn_map, qproc->conn_box, | |
600c39b3 | 495 | AXI_GATING_VALID_OVERRIDE, 1); |
6439b527 SS |
496 | reset_control_assert(qproc->mss_restart); |
497 | reset_control_deassert(qproc->pdc_reset); | |
498 | regmap_update_bits(qproc->conn_map, qproc->conn_box, | |
600c39b3 | 499 | AXI_GATING_VALID_OVERRIDE, 0); |
6439b527 | 500 | ret = reset_control_deassert(qproc->mss_restart); |
c842379d SS |
501 | } else if (qproc->has_ext_cntl_regs) { |
502 | regmap_write(qproc->conn_map, qproc->rscc_disable, 0); | |
503 | reset_control_assert(qproc->pdc_reset); | |
504 | reset_control_assert(qproc->mss_restart); | |
505 | reset_control_deassert(qproc->pdc_reset); | |
506 | ret = reset_control_deassert(qproc->mss_restart); | |
29a5f9aa SS |
507 | } else { |
508 | ret = reset_control_assert(qproc->mss_restart); | |
509 | } | |
510 | ||
511 | return ret; | |
9f135fa1 SS |
512 | } |
513 | ||
514 | static int q6v5_reset_deassert(struct q6v5 *qproc) | |
515 | { | |
231f67d1 SS |
516 | int ret; |
517 | ||
518 | if (qproc->has_alt_reset) { | |
29a5f9aa | 519 | reset_control_assert(qproc->pdc_reset); |
231f67d1 SS |
520 | writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET); |
521 | ret = reset_control_reset(qproc->mss_restart); | |
522 | writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); | |
29a5f9aa | 523 | reset_control_deassert(qproc->pdc_reset); |
c842379d | 524 | } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) { |
6439b527 | 525 | ret = reset_control_reset(qproc->mss_restart); |
231f67d1 SS |
526 | } else { |
527 | ret = reset_control_deassert(qproc->mss_restart); | |
528 | } | |
529 | ||
530 | return ret; | |
9f135fa1 SS |
531 | } |
532 | ||
051fb70f BA |
533 | static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms) |
534 | { | |
535 | unsigned long timeout; | |
536 | s32 val; | |
537 | ||
538 | timeout = jiffies + msecs_to_jiffies(ms); | |
539 | for (;;) { | |
540 | val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG); | |
541 | if (val) | |
542 | break; | |
543 | ||
544 | if (time_after(jiffies, timeout)) | |
545 | return -ETIMEDOUT; | |
546 | ||
547 | msleep(1); | |
548 | } | |
549 | ||
550 | return val; | |
551 | } | |
552 | ||
553 | static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms) | |
554 | { | |
555 | ||
556 | unsigned long timeout; | |
557 | s32 val; | |
558 | ||
559 | timeout = jiffies + msecs_to_jiffies(ms); | |
560 | for (;;) { | |
561 | val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); | |
562 | if (val < 0) | |
563 | break; | |
564 | ||
565 | if (!status && val) | |
566 | break; | |
567 | else if (status && val == status) | |
568 | break; | |
569 | ||
570 | if (time_after(jiffies, timeout)) | |
571 | return -ETIMEDOUT; | |
572 | ||
573 | msleep(1); | |
574 | } | |
575 | ||
576 | return val; | |
577 | } | |
578 | ||
318130cc SS |
579 | static void q6v5_dump_mba_logs(struct q6v5 *qproc) |
580 | { | |
581 | struct rproc *rproc = qproc->rproc; | |
582 | void *data; | |
a7ed5e57 | 583 | void *mba_region; |
318130cc SS |
584 | |
585 | if (!qproc->has_mba_logs) | |
586 | return; | |
587 | ||
588 | if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys, | |
589 | qproc->mba_size)) | |
590 | return; | |
591 | ||
a7ed5e57 SS |
592 | mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC); |
593 | if (!mba_region) | |
318130cc SS |
594 | return; |
595 | ||
a7ed5e57 SS |
596 | data = vmalloc(MBA_LOG_SIZE); |
597 | if (data) { | |
598 | memcpy(data, mba_region, MBA_LOG_SIZE); | |
599 | dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL); | |
600 | } | |
601 | memunmap(mba_region); | |
318130cc SS |
602 | } |
603 | ||
051fb70f BA |
604 | static int q6v5proc_reset(struct q6v5 *qproc) |
605 | { | |
606 | u32 val; | |
607 | int ret; | |
9f058fa2 | 608 | int i; |
051fb70f | 609 | |
231f67d1 SS |
610 | if (qproc->version == MSS_SDM845) { |
611 | val = readl(qproc->reg_base + QDSP6SS_SLEEP); | |
7e0f8688 | 612 | val |= Q6SS_CBCR_CLKEN; |
231f67d1 | 613 | writel(val, qproc->reg_base + QDSP6SS_SLEEP); |
051fb70f | 614 | |
231f67d1 | 615 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, |
7e0f8688 SS |
616 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
617 | Q6SS_CBCR_TIMEOUT_US); | |
231f67d1 SS |
618 | if (ret) { |
619 | dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); | |
620 | return -ETIMEDOUT; | |
621 | } | |
622 | ||
623 | /* De-assert QDSP6 stop core */ | |
624 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); | |
625 | /* Trigger boot FSM */ | |
626 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); | |
627 | ||
628 | ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, | |
629 | val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); | |
630 | if (ret) { | |
631 | dev_err(qproc->dev, "Boot FSM failed to complete.\n"); | |
632 | /* Reset the modem so that boot FSM is in reset state */ | |
633 | q6v5_reset_deassert(qproc); | |
634 | return ret; | |
635 | } | |
636 | ||
6439b527 | 637 | goto pbl_wait; |
c842379d | 638 | } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) { |
6439b527 | 639 | val = readl(qproc->reg_base + QDSP6SS_SLEEP); |
7e0f8688 | 640 | val |= Q6SS_CBCR_CLKEN; |
6439b527 SS |
641 | writel(val, qproc->reg_base + QDSP6SS_SLEEP); |
642 | ||
643 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, | |
7e0f8688 SS |
644 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
645 | Q6SS_CBCR_TIMEOUT_US); | |
6439b527 SS |
646 | if (ret) { |
647 | dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); | |
648 | return -ETIMEDOUT; | |
649 | } | |
650 | ||
651 | /* Turn on the XO clock needed for PLL setup */ | |
652 | val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); | |
7e0f8688 | 653 | val |= Q6SS_CBCR_CLKEN; |
6439b527 SS |
654 | writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); |
655 | ||
656 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, | |
7e0f8688 SS |
657 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
658 | Q6SS_CBCR_TIMEOUT_US); | |
6439b527 SS |
659 | if (ret) { |
660 | dev_err(qproc->dev, "QDSP6SS XO clock timed out\n"); | |
661 | return -ETIMEDOUT; | |
662 | } | |
663 | ||
664 | /* Configure Q6 core CBCR to auto-enable after reset sequence */ | |
665 | val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR); | |
7e0f8688 | 666 | val |= Q6SS_CBCR_CLKEN; |
6439b527 SS |
667 | writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR); |
668 | ||
669 | /* De-assert the Q6 stop core signal */ | |
670 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); | |
671 | ||
4e6751a1 SS |
672 | /* Wait for 10 us for any staggering logic to settle */ |
673 | usleep_range(10, 20); | |
674 | ||
6439b527 SS |
675 | /* Trigger the boot FSM to start the Q6 out-of-reset sequence */ |
676 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); | |
677 | ||
4e6751a1 SS |
678 | /* Poll the MSS_STATUS for FSM completion */ |
679 | ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, | |
680 | val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); | |
6439b527 SS |
681 | if (ret) { |
682 | dev_err(qproc->dev, "Boot FSM failed to complete.\n"); | |
683 | /* Reset the modem so that boot FSM is in reset state */ | |
684 | q6v5_reset_deassert(qproc); | |
685 | return ret; | |
686 | } | |
231f67d1 | 687 | goto pbl_wait; |
1665cbd5 JH |
688 | } else if (qproc->version == MSS_MSM8996 || |
689 | qproc->version == MSS_MSM8998) { | |
690 | int mem_pwr_ctl; | |
691 | ||
9f058fa2 AKD |
692 | /* Override the ACC value if required */ |
693 | writel(QDSP6SS_ACC_OVERRIDE_VAL, | |
694 | qproc->reg_base + QDSP6SS_STRAP_ACC); | |
051fb70f | 695 | |
9f058fa2 AKD |
696 | /* Assert resets, stop core */ |
697 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
698 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
699 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
700 | ||
701 | /* BHS require xo cbcr to be enabled */ | |
702 | val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); | |
7e0f8688 | 703 | val |= Q6SS_CBCR_CLKEN; |
9f058fa2 AKD |
704 | writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); |
705 | ||
706 | /* Read CLKOFF bit to go low indicating CLK is enabled */ | |
707 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, | |
7e0f8688 SS |
708 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
709 | Q6SS_CBCR_TIMEOUT_US); | |
9f058fa2 AKD |
710 | if (ret) { |
711 | dev_err(qproc->dev, | |
712 | "xo cbcr enabling timed out (rc:%d)\n", ret); | |
713 | return ret; | |
714 | } | |
715 | /* Enable power block headswitch and wait for it to stabilize */ | |
716 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
717 | val |= QDSP6v56_BHS_ON; | |
718 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
719 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
720 | udelay(1); | |
721 | ||
722 | /* Put LDO in bypass mode */ | |
723 | val |= QDSP6v56_LDO_BYP; | |
724 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
725 | ||
726 | /* Deassert QDSP6 compiler memory clamp */ | |
727 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
728 | val &= ~QDSP6v56_CLAMP_QMC_MEM; | |
729 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
730 | ||
731 | /* Deassert memory peripheral sleep and L2 memory standby */ | |
732 | val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; | |
733 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
734 | ||
735 | /* Turn on L1, L2, ETB and JU memories 1 at a time */ | |
1665cbd5 JH |
736 | if (qproc->version == MSS_MSM8996) { |
737 | mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL; | |
738 | i = 19; | |
739 | } else { | |
740 | /* MSS_MSM8998 */ | |
741 | mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL; | |
742 | i = 28; | |
743 | } | |
744 | val = readl(qproc->reg_base + mem_pwr_ctl); | |
745 | for (; i >= 0; i--) { | |
9f058fa2 | 746 | val |= BIT(i); |
1665cbd5 | 747 | writel(val, qproc->reg_base + mem_pwr_ctl); |
9f058fa2 AKD |
748 | /* |
749 | * Read back value to ensure the write is done then | |
750 | * wait for 1us for both memory peripheral and data | |
751 | * array to turn on. | |
752 | */ | |
1665cbd5 | 753 | val |= readl(qproc->reg_base + mem_pwr_ctl); |
9f058fa2 AKD |
754 | udelay(1); |
755 | } | |
756 | /* Remove word line clamp */ | |
757 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
758 | val &= ~QDSP6v56_CLAMP_WL; | |
759 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
760 | } else { | |
761 | /* Assert resets, stop core */ | |
762 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
763 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
764 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
765 | ||
766 | /* Enable power block headswitch and wait for it to stabilize */ | |
767 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
768 | val |= QDSS_BHS_ON | QDSS_LDO_BYP; | |
769 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
770 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
771 | udelay(1); | |
772 | /* | |
773 | * Turn on memories. L2 banks should be done individually | |
774 | * to minimize inrush current. | |
775 | */ | |
776 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
777 | val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | | |
778 | Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; | |
779 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
780 | val |= Q6SS_L2DATA_SLP_NRET_N_2; | |
781 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
782 | val |= Q6SS_L2DATA_SLP_NRET_N_1; | |
783 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
784 | val |= Q6SS_L2DATA_SLP_NRET_N_0; | |
785 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
786 | } | |
051fb70f BA |
787 | /* Remove IO clamp */ |
788 | val &= ~Q6SS_CLAMP_IO; | |
789 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
790 | ||
791 | /* Bring core out of reset */ | |
792 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
793 | val &= ~Q6SS_CORE_ARES; | |
794 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
795 | ||
796 | /* Turn on core clock */ | |
797 | val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
798 | val |= Q6SS_CLK_ENABLE; | |
799 | writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
800 | ||
801 | /* Start core execution */ | |
802 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
803 | val &= ~Q6SS_STOP_CORE; | |
804 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
805 | ||
231f67d1 | 806 | pbl_wait: |
051fb70f BA |
807 | /* Wait for PBL status */ |
808 | ret = q6v5_rmb_pbl_wait(qproc, 1000); | |
809 | if (ret == -ETIMEDOUT) { | |
810 | dev_err(qproc->dev, "PBL boot timed out\n"); | |
811 | } else if (ret != RMB_PBL_SUCCESS) { | |
812 | dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret); | |
813 | ret = -EINVAL; | |
814 | } else { | |
815 | ret = 0; | |
816 | } | |
817 | ||
818 | return ret; | |
819 | } | |
820 | ||
c842379d SS |
821 | static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) |
822 | { | |
823 | unsigned int val; | |
824 | int ret; | |
825 | ||
826 | if (!qproc->has_qaccept_regs) | |
827 | return 0; | |
828 | ||
829 | if (qproc->has_ext_cntl_regs) { | |
830 | regmap_write(qproc->conn_map, qproc->rscc_disable, 0); | |
831 | regmap_write(qproc->conn_map, qproc->force_clk_on, 1); | |
832 | ||
833 | ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val, | |
834 | !val, 1, Q6SS_CBCR_TIMEOUT_US); | |
835 | if (ret) { | |
836 | dev_err(qproc->dev, "failed to enable axim1 clock\n"); | |
837 | return -ETIMEDOUT; | |
838 | } | |
839 | } | |
840 | ||
841 | regmap_write(map, offset + QACCEPT_REQ_REG, 1); | |
842 | ||
843 | /* Wait for accept */ | |
844 | ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5, | |
845 | QACCEPT_TIMEOUT_US); | |
846 | if (ret) { | |
847 | dev_err(qproc->dev, "qchannel enable failed\n"); | |
848 | return -ETIMEDOUT; | |
849 | } | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
854 | static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) | |
855 | { | |
856 | int ret; | |
857 | unsigned int val, retry; | |
858 | unsigned int nretry = 10; | |
859 | bool takedown_complete = false; | |
860 | ||
861 | if (!qproc->has_qaccept_regs) | |
862 | return; | |
863 | ||
864 | while (!takedown_complete && nretry) { | |
865 | nretry--; | |
866 | ||
867 | /* Wait for active transactions to complete */ | |
868 | regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5, | |
869 | QACCEPT_TIMEOUT_US); | |
870 | ||
871 | /* Request Q-channel transaction takedown */ | |
872 | regmap_write(map, offset + QACCEPT_REQ_REG, 0); | |
873 | ||
874 | /* | |
875 | * If the request is denied, reset the Q-channel takedown request, | |
876 | * wait for active transactions to complete and retry takedown. | |
877 | */ | |
878 | retry = 10; | |
879 | while (retry) { | |
880 | usleep_range(5, 10); | |
881 | retry--; | |
882 | ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val); | |
883 | if (!ret && val) { | |
884 | regmap_write(map, offset + QACCEPT_REQ_REG, 1); | |
885 | break; | |
886 | } | |
887 | ||
888 | ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val); | |
889 | if (!ret && !val) { | |
890 | takedown_complete = true; | |
891 | break; | |
892 | } | |
893 | } | |
894 | ||
895 | if (!retry) | |
896 | break; | |
897 | } | |
898 | ||
899 | /* Rely on mss_restart to clear out pending transactions on takedown failure */ | |
900 | if (!takedown_complete) | |
901 | dev_err(qproc->dev, "qchannel takedown failed\n"); | |
902 | } | |
903 | ||
051fb70f BA |
904 | static void q6v5proc_halt_axi_port(struct q6v5 *qproc, |
905 | struct regmap *halt_map, | |
906 | u32 offset) | |
907 | { | |
051fb70f BA |
908 | unsigned int val; |
909 | int ret; | |
910 | ||
911 | /* Check if we're already idle */ | |
912 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
913 | if (!ret && val) | |
914 | return; | |
915 | ||
916 | /* Assert halt request */ | |
917 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); | |
918 | ||
919 | /* Wait for halt */ | |
01bf3fec SS |
920 | regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val, |
921 | val, 1000, HALT_ACK_TIMEOUT_US); | |
051fb70f BA |
922 | |
923 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
924 | if (ret || !val) | |
925 | dev_err(qproc->dev, "port failed halt\n"); | |
926 | ||
927 | /* Clear halt request (port will remain halted until reset) */ | |
928 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); | |
929 | } | |
930 | ||
931 | static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) | |
932 | { | |
00085f1e | 933 | unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; |
051fb70f | 934 | dma_addr_t phys; |
f04b9138 | 935 | void *metadata; |
6c5a9dc2 AKD |
936 | int mdata_perm; |
937 | int xferop_ret; | |
f04b9138 | 938 | size_t size; |
051fb70f BA |
939 | void *ptr; |
940 | int ret; | |
941 | ||
f04b9138 BA |
942 | metadata = qcom_mdt_read_metadata(fw, &size); |
943 | if (IS_ERR(metadata)) | |
944 | return PTR_ERR(metadata); | |
945 | ||
946 | ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs); | |
051fb70f | 947 | if (!ptr) { |
f04b9138 | 948 | kfree(metadata); |
051fb70f BA |
949 | dev_err(qproc->dev, "failed to allocate mdt buffer\n"); |
950 | return -ENOMEM; | |
951 | } | |
952 | ||
f04b9138 | 953 | memcpy(ptr, metadata, size); |
051fb70f | 954 | |
6c5a9dc2 AKD |
955 | /* Hypervisor mapping to access metadata by modem */ |
956 | mdata_perm = BIT(QCOM_SCM_VMID_HLOS); | |
715d8525 BA |
957 | ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true, |
958 | phys, size); | |
9f2a4342 BA |
959 | if (ret) { |
960 | dev_err(qproc->dev, | |
961 | "assigning Q6 access to metadata failed: %d\n", ret); | |
1a5d5c59 CJ |
962 | ret = -EAGAIN; |
963 | goto free_dma_attrs; | |
9f2a4342 | 964 | } |
6c5a9dc2 | 965 | |
051fb70f BA |
966 | writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG); |
967 | writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
968 | ||
969 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000); | |
970 | if (ret == -ETIMEDOUT) | |
971 | dev_err(qproc->dev, "MPSS header authentication timed out\n"); | |
972 | else if (ret < 0) | |
973 | dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret); | |
974 | ||
6c5a9dc2 | 975 | /* Metadata authentication done, remove modem access */ |
715d8525 BA |
976 | xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false, |
977 | phys, size); | |
6c5a9dc2 AKD |
978 | if (xferop_ret) |
979 | dev_warn(qproc->dev, | |
980 | "mdt buffer not reclaimed system may become unstable\n"); | |
981 | ||
1a5d5c59 | 982 | free_dma_attrs: |
f04b9138 BA |
983 | dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs); |
984 | kfree(metadata); | |
051fb70f BA |
985 | |
986 | return ret < 0 ? ret : 0; | |
987 | } | |
988 | ||
e7fd2522 BA |
989 | static bool q6v5_phdr_valid(const struct elf32_phdr *phdr) |
990 | { | |
991 | if (phdr->p_type != PT_LOAD) | |
992 | return false; | |
993 | ||
994 | if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH) | |
995 | return false; | |
996 | ||
997 | if (!phdr->p_memsz) | |
998 | return false; | |
999 | ||
1000 | return true; | |
1001 | } | |
1002 | ||
0304530d SS |
1003 | static int q6v5_mba_load(struct q6v5 *qproc) |
1004 | { | |
1005 | int ret; | |
1006 | int xfermemop_ret; | |
318130cc | 1007 | bool mba_load_err = false; |
0304530d | 1008 | |
c1fe10d2 SS |
1009 | ret = qcom_q6v5_prepare(&qproc->q6v5); |
1010 | if (ret) | |
1011 | return ret; | |
deb9bb83 | 1012 | |
4760a896 RN |
1013 | ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
1014 | if (ret < 0) { | |
1015 | dev_err(qproc->dev, "failed to enable proxy power domains\n"); | |
c1fe10d2 | 1016 | goto disable_irqs; |
4760a896 RN |
1017 | } |
1018 | ||
8750cf39 SG |
1019 | ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs, |
1020 | qproc->fallback_proxy_reg_count); | |
1021 | if (ret) { | |
1022 | dev_err(qproc->dev, "failed to enable fallback proxy supplies\n"); | |
1023 | goto disable_proxy_pds; | |
1024 | } | |
1025 | ||
0304530d SS |
1026 | ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, |
1027 | qproc->proxy_reg_count); | |
1028 | if (ret) { | |
1029 | dev_err(qproc->dev, "failed to enable proxy supplies\n"); | |
8750cf39 | 1030 | goto disable_fallback_proxy_reg; |
0304530d SS |
1031 | } |
1032 | ||
1033 | ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, | |
1034 | qproc->proxy_clk_count); | |
1035 | if (ret) { | |
1036 | dev_err(qproc->dev, "failed to enable proxy clocks\n"); | |
1037 | goto disable_proxy_reg; | |
1038 | } | |
1039 | ||
1040 | ret = q6v5_regulator_enable(qproc, qproc->active_regs, | |
1041 | qproc->active_reg_count); | |
1042 | if (ret) { | |
1043 | dev_err(qproc->dev, "failed to enable supplies\n"); | |
1044 | goto disable_proxy_clk; | |
1045 | } | |
1046 | ||
1047 | ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks, | |
1048 | qproc->reset_clk_count); | |
1049 | if (ret) { | |
1050 | dev_err(qproc->dev, "failed to enable reset clocks\n"); | |
1051 | goto disable_vdd; | |
1052 | } | |
1053 | ||
1054 | ret = q6v5_reset_deassert(qproc); | |
1055 | if (ret) { | |
1056 | dev_err(qproc->dev, "failed to deassert mss restart\n"); | |
1057 | goto disable_reset_clks; | |
1058 | } | |
1059 | ||
1060 | ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, | |
1061 | qproc->active_clk_count); | |
1062 | if (ret) { | |
1063 | dev_err(qproc->dev, "failed to enable clocks\n"); | |
1064 | goto assert_reset; | |
1065 | } | |
1066 | ||
c842379d SS |
1067 | ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); |
1068 | if (ret) { | |
1069 | dev_err(qproc->dev, "failed to enable axi bridge\n"); | |
1070 | goto disable_active_clks; | |
1071 | } | |
1072 | ||
4360f93a SS |
1073 | /* |
1074 | * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide | |
1075 | * the Q6 access to this region. | |
1076 | */ | |
1077 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true, | |
1078 | qproc->mpss_phys, qproc->mpss_size); | |
1079 | if (ret) { | |
1080 | dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret); | |
1081 | goto disable_active_clks; | |
1082 | } | |
1083 | ||
0304530d | 1084 | /* Assign MBA image access in DDR to q6 */ |
715d8525 | 1085 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true, |
0304530d SS |
1086 | qproc->mba_phys, qproc->mba_size); |
1087 | if (ret) { | |
1088 | dev_err(qproc->dev, | |
1089 | "assigning Q6 access to mba memory failed: %d\n", ret); | |
1090 | goto disable_active_clks; | |
1091 | } | |
1092 | ||
1093 | writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); | |
fe6a5dc4 SS |
1094 | if (qproc->dp_size) { |
1095 | writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG); | |
1096 | writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1097 | } | |
0304530d SS |
1098 | |
1099 | ret = q6v5proc_reset(qproc); | |
1100 | if (ret) | |
1101 | goto reclaim_mba; | |
1102 | ||
1103 | ret = q6v5_rmb_mba_wait(qproc, 0, 5000); | |
1104 | if (ret == -ETIMEDOUT) { | |
1105 | dev_err(qproc->dev, "MBA boot timed out\n"); | |
1106 | goto halt_axi_ports; | |
1107 | } else if (ret != RMB_MBA_XPU_UNLOCKED && | |
1108 | ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) { | |
1109 | dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret); | |
1110 | ret = -EINVAL; | |
1111 | goto halt_axi_ports; | |
1112 | } | |
1113 | ||
1114 | qproc->dump_mba_loaded = true; | |
1115 | return 0; | |
1116 | ||
1117 | halt_axi_ports: | |
1118 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
c842379d SS |
1119 | if (qproc->has_vq6) |
1120 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6); | |
0304530d SS |
1121 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); |
1122 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); | |
c842379d SS |
1123 | q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm); |
1124 | q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx); | |
1125 | q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); | |
318130cc | 1126 | mba_load_err = true; |
0304530d | 1127 | reclaim_mba: |
715d8525 BA |
1128 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, |
1129 | false, qproc->mba_phys, | |
0304530d SS |
1130 | qproc->mba_size); |
1131 | if (xfermemop_ret) { | |
1132 | dev_err(qproc->dev, | |
1133 | "Failed to reclaim mba buffer, system may become unstable\n"); | |
318130cc SS |
1134 | } else if (mba_load_err) { |
1135 | q6v5_dump_mba_logs(qproc); | |
0304530d SS |
1136 | } |
1137 | ||
1138 | disable_active_clks: | |
1139 | q6v5_clk_disable(qproc->dev, qproc->active_clks, | |
1140 | qproc->active_clk_count); | |
1141 | assert_reset: | |
1142 | q6v5_reset_assert(qproc); | |
1143 | disable_reset_clks: | |
1144 | q6v5_clk_disable(qproc->dev, qproc->reset_clks, | |
1145 | qproc->reset_clk_count); | |
1146 | disable_vdd: | |
1147 | q6v5_regulator_disable(qproc, qproc->active_regs, | |
1148 | qproc->active_reg_count); | |
1149 | disable_proxy_clk: | |
1150 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, | |
1151 | qproc->proxy_clk_count); | |
1152 | disable_proxy_reg: | |
1153 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
1154 | qproc->proxy_reg_count); | |
8750cf39 SG |
1155 | disable_fallback_proxy_reg: |
1156 | q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, | |
1157 | qproc->fallback_proxy_reg_count); | |
4760a896 RN |
1158 | disable_proxy_pds: |
1159 | q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); | |
0304530d SS |
1160 | disable_irqs: |
1161 | qcom_q6v5_unprepare(&qproc->q6v5); | |
1162 | ||
1163 | return ret; | |
1164 | } | |
1165 | ||
1166 | static void q6v5_mba_reclaim(struct q6v5 *qproc) | |
1167 | { | |
1168 | int ret; | |
1169 | u32 val; | |
1170 | ||
1171 | qproc->dump_mba_loaded = false; | |
fe6a5dc4 | 1172 | qproc->dp_size = 0; |
0304530d SS |
1173 | |
1174 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
c842379d SS |
1175 | if (qproc->has_vq6) |
1176 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6); | |
0304530d SS |
1177 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); |
1178 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); | |
1179 | if (qproc->version == MSS_MSM8996) { | |
1180 | /* | |
1181 | * To avoid high MX current during LPASS/MSS restart. | |
1182 | */ | |
1183 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
1184 | val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | | |
1185 | QDSP6v56_CLAMP_QMC_MEM; | |
1186 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
1187 | } | |
1188 | ||
c842379d SS |
1189 | if (qproc->has_ext_cntl_regs) { |
1190 | regmap_write(qproc->conn_map, qproc->rscc_disable, 1); | |
1191 | ||
1192 | ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val, | |
1193 | !val, 1, Q6SS_CBCR_TIMEOUT_US); | |
1194 | if (ret) | |
1195 | dev_err(qproc->dev, "failed to enable axim1 clock\n"); | |
1196 | ||
1197 | ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val, | |
1198 | !val, 1, Q6SS_CBCR_TIMEOUT_US); | |
1199 | if (ret) | |
1200 | dev_err(qproc->dev, "failed to enable crypto clock\n"); | |
1201 | } | |
1202 | ||
1203 | q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm); | |
1204 | q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx); | |
1205 | q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi); | |
1206 | ||
0304530d SS |
1207 | q6v5_reset_assert(qproc); |
1208 | ||
1209 | q6v5_clk_disable(qproc->dev, qproc->reset_clks, | |
1210 | qproc->reset_clk_count); | |
1211 | q6v5_clk_disable(qproc->dev, qproc->active_clks, | |
1212 | qproc->active_clk_count); | |
1213 | q6v5_regulator_disable(qproc, qproc->active_regs, | |
1214 | qproc->active_reg_count); | |
1215 | ||
1216 | /* In case of failure or coredump scenario where reclaiming MBA memory | |
1217 | * could not happen reclaim it here. | |
1218 | */ | |
715d8525 | 1219 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, |
0304530d SS |
1220 | qproc->mba_phys, |
1221 | qproc->mba_size); | |
1222 | WARN_ON(ret); | |
1223 | ||
1224 | ret = qcom_q6v5_unprepare(&qproc->q6v5); | |
1225 | if (ret) { | |
4760a896 RN |
1226 | q6v5_pds_disable(qproc, qproc->proxy_pds, |
1227 | qproc->proxy_pd_count); | |
0304530d SS |
1228 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, |
1229 | qproc->proxy_clk_count); | |
8750cf39 SG |
1230 | q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, |
1231 | qproc->fallback_proxy_reg_count); | |
0304530d SS |
1232 | q6v5_regulator_disable(qproc, qproc->proxy_regs, |
1233 | qproc->proxy_reg_count); | |
1234 | } | |
1235 | } | |
1236 | ||
d96f2571 SS |
1237 | static int q6v5_reload_mba(struct rproc *rproc) |
1238 | { | |
1239 | struct q6v5 *qproc = rproc->priv; | |
1240 | const struct firmware *fw; | |
1241 | int ret; | |
1242 | ||
1243 | ret = request_firmware(&fw, rproc->firmware, qproc->dev); | |
1244 | if (ret < 0) | |
1245 | return ret; | |
1246 | ||
1247 | q6v5_load(rproc, fw); | |
1248 | ret = q6v5_mba_load(qproc); | |
1249 | release_firmware(fw); | |
1250 | ||
1251 | return ret; | |
1252 | } | |
1253 | ||
e7fd2522 | 1254 | static int q6v5_mpss_load(struct q6v5 *qproc) |
051fb70f BA |
1255 | { |
1256 | const struct elf32_phdr *phdrs; | |
1257 | const struct elf32_phdr *phdr; | |
e7fd2522 BA |
1258 | const struct firmware *seg_fw; |
1259 | const struct firmware *fw; | |
051fb70f | 1260 | struct elf32_hdr *ehdr; |
e7fd2522 | 1261 | phys_addr_t mpss_reloc; |
051fb70f | 1262 | phys_addr_t boot_addr; |
d7dc899a | 1263 | phys_addr_t min_addr = PHYS_ADDR_MAX; |
e7fd2522 | 1264 | phys_addr_t max_addr = 0; |
715d8525 | 1265 | u32 code_length; |
e7fd2522 | 1266 | bool relocate = false; |
a5a4e02d SS |
1267 | char *fw_name; |
1268 | size_t fw_name_len; | |
01625cc5 | 1269 | ssize_t offset; |
94c90785 | 1270 | size_t size = 0; |
e7fd2522 | 1271 | void *ptr; |
051fb70f BA |
1272 | int ret; |
1273 | int i; | |
1274 | ||
a5a4e02d SS |
1275 | fw_name_len = strlen(qproc->hexagon_mdt_image); |
1276 | if (fw_name_len <= 4) | |
1277 | return -EINVAL; | |
1278 | ||
1279 | fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL); | |
1280 | if (!fw_name) | |
1281 | return -ENOMEM; | |
1282 | ||
1283 | ret = request_firmware(&fw, fw_name, qproc->dev); | |
e7fd2522 | 1284 | if (ret < 0) { |
a5a4e02d SS |
1285 | dev_err(qproc->dev, "unable to load %s\n", fw_name); |
1286 | goto out; | |
051fb70f BA |
1287 | } |
1288 | ||
e7fd2522 BA |
1289 | /* Initialize the RMB validator */ |
1290 | writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1291 | ||
1292 | ret = q6v5_mpss_init_image(qproc, fw); | |
1293 | if (ret) | |
1294 | goto release_firmware; | |
051fb70f BA |
1295 | |
1296 | ehdr = (struct elf32_hdr *)fw->data; | |
1297 | phdrs = (struct elf32_phdr *)(ehdr + 1); | |
e7fd2522 BA |
1298 | |
1299 | for (i = 0; i < ehdr->e_phnum; i++) { | |
051fb70f BA |
1300 | phdr = &phdrs[i]; |
1301 | ||
e7fd2522 | 1302 | if (!q6v5_phdr_valid(phdr)) |
051fb70f BA |
1303 | continue; |
1304 | ||
e7fd2522 BA |
1305 | if (phdr->p_flags & QCOM_MDT_RELOCATABLE) |
1306 | relocate = true; | |
051fb70f | 1307 | |
e7fd2522 BA |
1308 | if (phdr->p_paddr < min_addr) |
1309 | min_addr = phdr->p_paddr; | |
1310 | ||
1311 | if (phdr->p_paddr + phdr->p_memsz > max_addr) | |
1312 | max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); | |
1313 | } | |
1314 | ||
4360f93a | 1315 | /* |
900fc60d | 1316 | * In case of a modem subsystem restart on secure devices, the modem |
4360f93a | 1317 | * memory can be reclaimed only after MBA is loaded. |
900fc60d | 1318 | */ |
715d8525 | 1319 | q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false, |
900fc60d BA |
1320 | qproc->mpss_phys, qproc->mpss_size); |
1321 | ||
715d8525 BA |
1322 | /* Share ownership between Linux and MSS, during segment loading */ |
1323 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true, | |
1324 | qproc->mpss_phys, qproc->mpss_size); | |
1325 | if (ret) { | |
1326 | dev_err(qproc->dev, | |
1327 | "assigning Q6 access to mpss memory failed: %d\n", ret); | |
1328 | ret = -EAGAIN; | |
1329 | goto release_firmware; | |
1330 | } | |
1331 | ||
e7fd2522 | 1332 | mpss_reloc = relocate ? min_addr : qproc->mpss_phys; |
3bf62eb7 | 1333 | qproc->mpss_reloc = mpss_reloc; |
94c90785 | 1334 | /* Load firmware segments */ |
e7fd2522 BA |
1335 | for (i = 0; i < ehdr->e_phnum; i++) { |
1336 | phdr = &phdrs[i]; | |
1337 | ||
1338 | if (!q6v5_phdr_valid(phdr)) | |
051fb70f BA |
1339 | continue; |
1340 | ||
e7fd2522 BA |
1341 | offset = phdr->p_paddr - mpss_reloc; |
1342 | if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) { | |
1343 | dev_err(qproc->dev, "segment outside memory range\n"); | |
1344 | ret = -EINVAL; | |
1345 | goto release_firmware; | |
1346 | } | |
1347 | ||
3d2ee789 BA |
1348 | if (phdr->p_filesz > phdr->p_memsz) { |
1349 | dev_err(qproc->dev, | |
1350 | "refusing to load segment %d with p_filesz > p_memsz\n", | |
1351 | i); | |
1352 | ret = -EINVAL; | |
1353 | goto release_firmware; | |
1354 | } | |
1355 | ||
04ff5d19 | 1356 | ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC); |
be050a34 SS |
1357 | if (!ptr) { |
1358 | dev_err(qproc->dev, | |
1359 | "unable to map memory region: %pa+%zx-%x\n", | |
1360 | &qproc->mpss_phys, offset, phdr->p_memsz); | |
1361 | goto release_firmware; | |
1362 | } | |
e7fd2522 | 1363 | |
f04b9138 BA |
1364 | if (phdr->p_filesz && phdr->p_offset < fw->size) { |
1365 | /* Firmware is large enough to be non-split */ | |
1366 | if (phdr->p_offset + phdr->p_filesz > fw->size) { | |
1367 | dev_err(qproc->dev, | |
1368 | "failed to load segment %d from truncated file %s\n", | |
1369 | i, fw_name); | |
1370 | ret = -EINVAL; | |
04ff5d19 | 1371 | memunmap(ptr); |
f04b9138 BA |
1372 | goto release_firmware; |
1373 | } | |
1374 | ||
1375 | memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz); | |
1376 | } else if (phdr->p_filesz) { | |
a5a4e02d SS |
1377 | /* Replace "xxx.xxx" with "xxx.bxx" */ |
1378 | sprintf(fw_name + fw_name_len - 3, "b%02d", i); | |
135b9e8d SS |
1379 | ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev, |
1380 | ptr, phdr->p_filesz); | |
e7fd2522 | 1381 | if (ret) { |
a5a4e02d | 1382 | dev_err(qproc->dev, "failed to load %s\n", fw_name); |
04ff5d19 | 1383 | memunmap(ptr); |
e7fd2522 BA |
1384 | goto release_firmware; |
1385 | } | |
1386 | ||
3d2ee789 BA |
1387 | if (seg_fw->size != phdr->p_filesz) { |
1388 | dev_err(qproc->dev, | |
1389 | "failed to load segment %d from truncated file %s\n", | |
1390 | i, fw_name); | |
1391 | ret = -EINVAL; | |
1392 | release_firmware(seg_fw); | |
1393 | memunmap(ptr); | |
1394 | goto release_firmware; | |
1395 | } | |
1396 | ||
e7fd2522 BA |
1397 | release_firmware(seg_fw); |
1398 | } | |
1399 | ||
1400 | if (phdr->p_memsz > phdr->p_filesz) { | |
1401 | memset(ptr + phdr->p_filesz, 0, | |
1402 | phdr->p_memsz - phdr->p_filesz); | |
1403 | } | |
04ff5d19 | 1404 | memunmap(ptr); |
051fb70f | 1405 | size += phdr->p_memsz; |
715d8525 BA |
1406 | |
1407 | code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1408 | if (!code_length) { | |
1409 | boot_addr = relocate ? qproc->mpss_phys : min_addr; | |
1410 | writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG); | |
1411 | writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
1412 | } | |
1413 | writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1414 | ||
1415 | ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); | |
1416 | if (ret < 0) { | |
1417 | dev_err(qproc->dev, "MPSS authentication failed: %d\n", | |
1418 | ret); | |
1419 | goto release_firmware; | |
1420 | } | |
051fb70f BA |
1421 | } |
1422 | ||
6c5a9dc2 | 1423 | /* Transfer ownership of modem ddr region to q6 */ |
715d8525 | 1424 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true, |
6c5a9dc2 | 1425 | qproc->mpss_phys, qproc->mpss_size); |
9f2a4342 BA |
1426 | if (ret) { |
1427 | dev_err(qproc->dev, | |
1428 | "assigning Q6 access to mpss memory failed: %d\n", ret); | |
1a5d5c59 CJ |
1429 | ret = -EAGAIN; |
1430 | goto release_firmware; | |
9f2a4342 | 1431 | } |
6c5a9dc2 | 1432 | |
72beb490 BA |
1433 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000); |
1434 | if (ret == -ETIMEDOUT) | |
1435 | dev_err(qproc->dev, "MPSS authentication timed out\n"); | |
1436 | else if (ret < 0) | |
1437 | dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret); | |
1438 | ||
d4c78d21 BA |
1439 | qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size); |
1440 | ||
051fb70f BA |
1441 | release_firmware: |
1442 | release_firmware(fw); | |
a5a4e02d SS |
1443 | out: |
1444 | kfree(fw_name); | |
051fb70f BA |
1445 | |
1446 | return ret < 0 ? ret : 0; | |
1447 | } | |
1448 | ||
7dd8ade2 SS |
1449 | static void qcom_q6v5_dump_segment(struct rproc *rproc, |
1450 | struct rproc_dump_segment *segment, | |
76abf9ce | 1451 | void *dest, size_t cp_offset, size_t size) |
7dd8ade2 SS |
1452 | { |
1453 | int ret = 0; | |
1454 | struct q6v5 *qproc = rproc->priv; | |
be050a34 SS |
1455 | int offset = segment->da - qproc->mpss_reloc; |
1456 | void *ptr = NULL; | |
7dd8ade2 SS |
1457 | |
1458 | /* Unlock mba before copying segments */ | |
900fc60d | 1459 | if (!qproc->dump_mba_loaded) { |
d96f2571 | 1460 | ret = q6v5_reload_mba(rproc); |
900fc60d BA |
1461 | if (!ret) { |
1462 | /* Reset ownership back to Linux to copy segments */ | |
1463 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, | |
715d8525 | 1464 | true, false, |
900fc60d BA |
1465 | qproc->mpss_phys, |
1466 | qproc->mpss_size); | |
1467 | } | |
1468 | } | |
7dd8ade2 | 1469 | |
be050a34 | 1470 | if (!ret) |
04ff5d19 | 1471 | ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC); |
be050a34 SS |
1472 | |
1473 | if (ptr) { | |
76abf9ce | 1474 | memcpy(dest, ptr, size); |
04ff5d19 | 1475 | memunmap(ptr); |
be050a34 | 1476 | } else { |
76abf9ce | 1477 | memset(dest, 0xff, size); |
be050a34 | 1478 | } |
7dd8ade2 | 1479 | |
76abf9ce | 1480 | qproc->current_dump_size += size; |
7dd8ade2 SS |
1481 | |
1482 | /* Reclaim mba after copying segments */ | |
7ac516d3 | 1483 | if (qproc->current_dump_size == qproc->total_dump_size) { |
900fc60d BA |
1484 | if (qproc->dump_mba_loaded) { |
1485 | /* Try to reset ownership back to Q6 */ | |
1486 | q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, | |
715d8525 | 1487 | false, true, |
900fc60d BA |
1488 | qproc->mpss_phys, |
1489 | qproc->mpss_size); | |
7dd8ade2 | 1490 | q6v5_mba_reclaim(qproc); |
900fc60d | 1491 | } |
7dd8ade2 SS |
1492 | } |
1493 | } | |
1494 | ||
051fb70f BA |
1495 | static int q6v5_start(struct rproc *rproc) |
1496 | { | |
1497 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
6c5a9dc2 | 1498 | int xfermemop_ret; |
051fb70f BA |
1499 | int ret; |
1500 | ||
0304530d | 1501 | ret = q6v5_mba_load(qproc); |
051fb70f | 1502 | if (ret) |
0304530d | 1503 | return ret; |
051fb70f | 1504 | |
fe6a5dc4 SS |
1505 | dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n", |
1506 | qproc->dp_size ? "" : "out"); | |
051fb70f BA |
1507 | |
1508 | ret = q6v5_mpss_load(qproc); | |
1509 | if (ret) | |
6c5a9dc2 | 1510 | goto reclaim_mpss; |
051fb70f | 1511 | |
7d674731 BA |
1512 | ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000)); |
1513 | if (ret == -ETIMEDOUT) { | |
051fb70f | 1514 | dev_err(qproc->dev, "start timed out\n"); |
6c5a9dc2 | 1515 | goto reclaim_mpss; |
051fb70f BA |
1516 | } |
1517 | ||
715d8525 BA |
1518 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, |
1519 | false, qproc->mba_phys, | |
6c5a9dc2 AKD |
1520 | qproc->mba_size); |
1521 | if (xfermemop_ret) | |
1522 | dev_err(qproc->dev, | |
1523 | "Failed to reclaim mba buffer system may become unstable\n"); | |
7dd8ade2 SS |
1524 | |
1525 | /* Reset Dump Segment Mask */ | |
7ac516d3 | 1526 | qproc->current_dump_size = 0; |
051fb70f | 1527 | |
051fb70f BA |
1528 | return 0; |
1529 | ||
6c5a9dc2 | 1530 | reclaim_mpss: |
0304530d | 1531 | q6v5_mba_reclaim(qproc); |
318130cc | 1532 | q6v5_dump_mba_logs(qproc); |
663e9845 | 1533 | |
051fb70f BA |
1534 | return ret; |
1535 | } | |
1536 | ||
1537 | static int q6v5_stop(struct rproc *rproc) | |
1538 | { | |
1539 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
1540 | int ret; | |
1541 | ||
ed5da808 | 1542 | ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon); |
7d674731 | 1543 | if (ret == -ETIMEDOUT) |
051fb70f BA |
1544 | dev_err(qproc->dev, "timed out on wait\n"); |
1545 | ||
0304530d | 1546 | q6v5_mba_reclaim(qproc); |
051fb70f BA |
1547 | |
1548 | return 0; | |
1549 | } | |
1550 | ||
f18b7e91 SS |
1551 | static int qcom_q6v5_register_dump_segments(struct rproc *rproc, |
1552 | const struct firmware *mba_fw) | |
1553 | { | |
1554 | const struct firmware *fw; | |
1555 | const struct elf32_phdr *phdrs; | |
1556 | const struct elf32_phdr *phdr; | |
1557 | const struct elf32_hdr *ehdr; | |
1558 | struct q6v5 *qproc = rproc->priv; | |
1559 | unsigned long i; | |
1560 | int ret; | |
1561 | ||
a5a4e02d | 1562 | ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev); |
f18b7e91 | 1563 | if (ret < 0) { |
a5a4e02d SS |
1564 | dev_err(qproc->dev, "unable to load %s\n", |
1565 | qproc->hexagon_mdt_image); | |
f18b7e91 SS |
1566 | return ret; |
1567 | } | |
1568 | ||
3898fc99 CL |
1569 | rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); |
1570 | ||
f18b7e91 SS |
1571 | ehdr = (struct elf32_hdr *)fw->data; |
1572 | phdrs = (struct elf32_phdr *)(ehdr + 1); | |
7ac516d3 | 1573 | qproc->total_dump_size = 0; |
f18b7e91 SS |
1574 | |
1575 | for (i = 0; i < ehdr->e_phnum; i++) { | |
1576 | phdr = &phdrs[i]; | |
1577 | ||
1578 | if (!q6v5_phdr_valid(phdr)) | |
1579 | continue; | |
1580 | ||
1581 | ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr, | |
1582 | phdr->p_memsz, | |
1583 | qcom_q6v5_dump_segment, | |
7ac516d3 | 1584 | NULL); |
f18b7e91 SS |
1585 | if (ret) |
1586 | break; | |
1587 | ||
7ac516d3 | 1588 | qproc->total_dump_size += phdr->p_memsz; |
f18b7e91 SS |
1589 | } |
1590 | ||
1591 | release_firmware(fw); | |
1592 | return ret; | |
1593 | } | |
1594 | ||
051fb70f BA |
1595 | static const struct rproc_ops q6v5_ops = { |
1596 | .start = q6v5_start, | |
1597 | .stop = q6v5_stop, | |
f18b7e91 | 1598 | .parse_fw = qcom_q6v5_register_dump_segments, |
0f21f9cc | 1599 | .load = q6v5_load, |
051fb70f BA |
1600 | }; |
1601 | ||
7d674731 | 1602 | static void qcom_msa_handover(struct qcom_q6v5 *q6v5) |
663e9845 | 1603 | { |
7d674731 | 1604 | struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5); |
663e9845 SS |
1605 | |
1606 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, | |
1607 | qproc->proxy_clk_count); | |
1608 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
1609 | qproc->proxy_reg_count); | |
8750cf39 SG |
1610 | q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, |
1611 | qproc->fallback_proxy_reg_count); | |
4760a896 | 1612 | q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
051fb70f BA |
1613 | } |
1614 | ||
1615 | static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) | |
1616 | { | |
1617 | struct of_phandle_args args; | |
c842379d | 1618 | int halt_cell_cnt = 3; |
051fb70f BA |
1619 | int ret; |
1620 | ||
9db9c738 | 1621 | qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6"); |
b1653f23 | 1622 | if (IS_ERR(qproc->reg_base)) |
051fb70f | 1623 | return PTR_ERR(qproc->reg_base); |
051fb70f | 1624 | |
9db9c738 | 1625 | qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb"); |
b1653f23 | 1626 | if (IS_ERR(qproc->rmb_base)) |
051fb70f | 1627 | return PTR_ERR(qproc->rmb_base); |
051fb70f | 1628 | |
c842379d SS |
1629 | if (qproc->has_vq6) |
1630 | halt_cell_cnt++; | |
1631 | ||
051fb70f | 1632 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, |
c842379d | 1633 | "qcom,halt-regs", halt_cell_cnt, 0, &args); |
051fb70f BA |
1634 | if (ret < 0) { |
1635 | dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); | |
1636 | return -EINVAL; | |
1637 | } | |
1638 | ||
1639 | qproc->halt_map = syscon_node_to_regmap(args.np); | |
1640 | of_node_put(args.np); | |
1641 | if (IS_ERR(qproc->halt_map)) | |
1642 | return PTR_ERR(qproc->halt_map); | |
1643 | ||
1644 | qproc->halt_q6 = args.args[0]; | |
1645 | qproc->halt_modem = args.args[1]; | |
1646 | qproc->halt_nc = args.args[2]; | |
1647 | ||
c842379d SS |
1648 | if (qproc->has_vq6) |
1649 | qproc->halt_vq6 = args.args[3]; | |
1650 | ||
1651 | if (qproc->has_qaccept_regs) { | |
1652 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
1653 | "qcom,qaccept-regs", | |
1654 | 3, 0, &args); | |
1655 | if (ret < 0) { | |
1656 | dev_err(&pdev->dev, "failed to parse qaccept-regs\n"); | |
1657 | return -EINVAL; | |
1658 | } | |
1659 | ||
1660 | qproc->qaccept_mdm = args.args[0]; | |
1661 | qproc->qaccept_cx = args.args[1]; | |
1662 | qproc->qaccept_axi = args.args[2]; | |
1663 | } | |
1664 | ||
1665 | if (qproc->has_ext_cntl_regs) { | |
1666 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
1667 | "qcom,ext-regs", | |
1668 | 2, 0, &args); | |
1669 | if (ret < 0) { | |
1670 | dev_err(&pdev->dev, "failed to parse ext-regs index 0\n"); | |
1671 | return -EINVAL; | |
1672 | } | |
1673 | ||
1674 | qproc->conn_map = syscon_node_to_regmap(args.np); | |
1675 | of_node_put(args.np); | |
1676 | if (IS_ERR(qproc->conn_map)) | |
1677 | return PTR_ERR(qproc->conn_map); | |
1678 | ||
1679 | qproc->force_clk_on = args.args[0]; | |
1680 | qproc->rscc_disable = args.args[1]; | |
1681 | ||
1682 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
1683 | "qcom,ext-regs", | |
1684 | 2, 1, &args); | |
1685 | if (ret < 0) { | |
1686 | dev_err(&pdev->dev, "failed to parse ext-regs index 1\n"); | |
1687 | return -EINVAL; | |
1688 | } | |
1689 | ||
1690 | qproc->axim1_clk_off = args.args[0]; | |
1691 | qproc->crypto_clk_off = args.args[1]; | |
1692 | } | |
1693 | ||
a9fdc79d | 1694 | if (qproc->has_spare_reg) { |
6439b527 | 1695 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, |
a9fdc79d | 1696 | "qcom,spare-regs", |
6439b527 SS |
1697 | 1, 0, &args); |
1698 | if (ret < 0) { | |
a9fdc79d | 1699 | dev_err(&pdev->dev, "failed to parse spare-regs\n"); |
6439b527 SS |
1700 | return -EINVAL; |
1701 | } | |
1702 | ||
1703 | qproc->conn_map = syscon_node_to_regmap(args.np); | |
1704 | of_node_put(args.np); | |
1705 | if (IS_ERR(qproc->conn_map)) | |
1706 | return PTR_ERR(qproc->conn_map); | |
1707 | ||
1708 | qproc->conn_box = args.args[0]; | |
1709 | } | |
1710 | ||
051fb70f BA |
1711 | return 0; |
1712 | } | |
1713 | ||
39b2410b AKD |
1714 | static int q6v5_init_clocks(struct device *dev, struct clk **clks, |
1715 | char **clk_names) | |
051fb70f | 1716 | { |
39b2410b | 1717 | int i; |
051fb70f | 1718 | |
39b2410b AKD |
1719 | if (!clk_names) |
1720 | return 0; | |
1721 | ||
1722 | for (i = 0; clk_names[i]; i++) { | |
1723 | clks[i] = devm_clk_get(dev, clk_names[i]); | |
1724 | if (IS_ERR(clks[i])) { | |
1725 | int rc = PTR_ERR(clks[i]); | |
051fb70f | 1726 | |
39b2410b AKD |
1727 | if (rc != -EPROBE_DEFER) |
1728 | dev_err(dev, "Failed to get %s clock\n", | |
1729 | clk_names[i]); | |
1730 | return rc; | |
1731 | } | |
051fb70f BA |
1732 | } |
1733 | ||
39b2410b | 1734 | return i; |
051fb70f BA |
1735 | } |
1736 | ||
4760a896 RN |
1737 | static int q6v5_pds_attach(struct device *dev, struct device **devs, |
1738 | char **pd_names) | |
1739 | { | |
1740 | size_t num_pds = 0; | |
1741 | int ret; | |
1742 | int i; | |
1743 | ||
1744 | if (!pd_names) | |
1745 | return 0; | |
1746 | ||
1747 | while (pd_names[num_pds]) | |
1748 | num_pds++; | |
1749 | ||
1750 | for (i = 0; i < num_pds; i++) { | |
1751 | devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); | |
f2583fde SS |
1752 | if (IS_ERR_OR_NULL(devs[i])) { |
1753 | ret = PTR_ERR(devs[i]) ? : -ENODATA; | |
4760a896 RN |
1754 | goto unroll_attach; |
1755 | } | |
1756 | } | |
1757 | ||
1758 | return num_pds; | |
1759 | ||
1760 | unroll_attach: | |
1761 | for (i--; i >= 0; i--) | |
1762 | dev_pm_domain_detach(devs[i], false); | |
1763 | ||
1764 | return ret; | |
58396810 | 1765 | } |
4760a896 RN |
1766 | |
1767 | static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds, | |
1768 | size_t pd_count) | |
1769 | { | |
1770 | int i; | |
1771 | ||
1772 | for (i = 0; i < pd_count; i++) | |
1773 | dev_pm_domain_detach(pds[i], false); | |
1774 | } | |
1775 | ||
051fb70f BA |
1776 | static int q6v5_init_reset(struct q6v5 *qproc) |
1777 | { | |
5acbf7e5 | 1778 | qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev, |
9e483efd | 1779 | "mss_restart"); |
051fb70f BA |
1780 | if (IS_ERR(qproc->mss_restart)) { |
1781 | dev_err(qproc->dev, "failed to acquire mss restart\n"); | |
1782 | return PTR_ERR(qproc->mss_restart); | |
1783 | } | |
1784 | ||
c842379d | 1785 | if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) { |
29a5f9aa SS |
1786 | qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev, |
1787 | "pdc_reset"); | |
1788 | if (IS_ERR(qproc->pdc_reset)) { | |
1789 | dev_err(qproc->dev, "failed to acquire pdc reset\n"); | |
1790 | return PTR_ERR(qproc->pdc_reset); | |
1791 | } | |
1792 | } | |
1793 | ||
051fb70f BA |
1794 | return 0; |
1795 | } | |
1796 | ||
051fb70f BA |
1797 | static int q6v5_alloc_memory_region(struct q6v5 *qproc) |
1798 | { | |
1799 | struct device_node *child; | |
1800 | struct device_node *node; | |
1801 | struct resource r; | |
1802 | int ret; | |
1803 | ||
6663ce6f SS |
1804 | /* |
1805 | * In the absence of mba/mpss sub-child, extract the mba and mpss | |
1806 | * reserved memory regions from device's memory-region property. | |
1807 | */ | |
051fb70f | 1808 | child = of_get_child_by_name(qproc->dev->of_node, "mba"); |
07a5dcc4 | 1809 | if (!child) { |
6663ce6f SS |
1810 | node = of_parse_phandle(qproc->dev->of_node, |
1811 | "memory-region", 0); | |
07a5dcc4 | 1812 | } else { |
6663ce6f | 1813 | node = of_parse_phandle(child, "memory-region", 0); |
07a5dcc4 ML |
1814 | of_node_put(child); |
1815 | } | |
6663ce6f | 1816 | |
051fb70f | 1817 | ret = of_address_to_resource(node, 0, &r); |
07a5dcc4 | 1818 | of_node_put(node); |
051fb70f BA |
1819 | if (ret) { |
1820 | dev_err(qproc->dev, "unable to resolve mba region\n"); | |
1821 | return ret; | |
1822 | } | |
1823 | ||
1824 | qproc->mba_phys = r.start; | |
1825 | qproc->mba_size = resource_size(&r); | |
051fb70f | 1826 | |
6663ce6f SS |
1827 | if (!child) { |
1828 | node = of_parse_phandle(qproc->dev->of_node, | |
1829 | "memory-region", 1); | |
1830 | } else { | |
1831 | child = of_get_child_by_name(qproc->dev->of_node, "mpss"); | |
1832 | node = of_parse_phandle(child, "memory-region", 0); | |
07a5dcc4 | 1833 | of_node_put(child); |
6663ce6f SS |
1834 | } |
1835 | ||
051fb70f | 1836 | ret = of_address_to_resource(node, 0, &r); |
07a5dcc4 | 1837 | of_node_put(node); |
051fb70f BA |
1838 | if (ret) { |
1839 | dev_err(qproc->dev, "unable to resolve mpss region\n"); | |
1840 | return ret; | |
1841 | } | |
1842 | ||
1843 | qproc->mpss_phys = qproc->mpss_reloc = r.start; | |
1844 | qproc->mpss_size = resource_size(&r); | |
051fb70f BA |
1845 | |
1846 | return 0; | |
1847 | } | |
1848 | ||
1849 | static int q6v5_probe(struct platform_device *pdev) | |
1850 | { | |
7a8ffe1f | 1851 | const struct rproc_hexagon_res *desc; |
051fb70f BA |
1852 | struct q6v5 *qproc; |
1853 | struct rproc *rproc; | |
a5a4e02d | 1854 | const char *mba_image; |
051fb70f BA |
1855 | int ret; |
1856 | ||
7a8ffe1f AKD |
1857 | desc = of_device_get_match_data(&pdev->dev); |
1858 | if (!desc) | |
1859 | return -EINVAL; | |
1860 | ||
bbcda302 BN |
1861 | if (desc->need_mem_protection && !qcom_scm_is_available()) |
1862 | return -EPROBE_DEFER; | |
1863 | ||
a5a4e02d SS |
1864 | mba_image = desc->hexagon_mba_image; |
1865 | ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", | |
1866 | 0, &mba_image); | |
9af2a2a9 BA |
1867 | if (ret < 0 && ret != -EINVAL) { |
1868 | dev_err(&pdev->dev, "unable to read mba firmware-name\n"); | |
a5a4e02d | 1869 | return ret; |
9af2a2a9 | 1870 | } |
a5a4e02d | 1871 | |
051fb70f | 1872 | rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops, |
a5a4e02d | 1873 | mba_image, sizeof(*qproc)); |
051fb70f BA |
1874 | if (!rproc) { |
1875 | dev_err(&pdev->dev, "failed to allocate rproc\n"); | |
1876 | return -ENOMEM; | |
1877 | } | |
1878 | ||
4107102d | 1879 | rproc->auto_boot = false; |
3898fc99 | 1880 | rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); |
4107102d | 1881 | |
051fb70f BA |
1882 | qproc = (struct q6v5 *)rproc->priv; |
1883 | qproc->dev = &pdev->dev; | |
1884 | qproc->rproc = rproc; | |
a5a4e02d SS |
1885 | qproc->hexagon_mdt_image = "modem.mdt"; |
1886 | ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", | |
1887 | 1, &qproc->hexagon_mdt_image); | |
9af2a2a9 BA |
1888 | if (ret < 0 && ret != -EINVAL) { |
1889 | dev_err(&pdev->dev, "unable to read mpss firmware-name\n"); | |
13c060b5 | 1890 | goto free_rproc; |
9af2a2a9 | 1891 | } |
a5a4e02d | 1892 | |
051fb70f BA |
1893 | platform_set_drvdata(pdev, qproc); |
1894 | ||
c842379d SS |
1895 | qproc->has_qaccept_regs = desc->has_qaccept_regs; |
1896 | qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs; | |
1897 | qproc->has_vq6 = desc->has_vq6; | |
a9fdc79d | 1898 | qproc->has_spare_reg = desc->has_spare_reg; |
051fb70f BA |
1899 | ret = q6v5_init_mem(qproc, pdev); |
1900 | if (ret) | |
1901 | goto free_rproc; | |
1902 | ||
1903 | ret = q6v5_alloc_memory_region(qproc); | |
1904 | if (ret) | |
1905 | goto free_rproc; | |
1906 | ||
39b2410b AKD |
1907 | ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks, |
1908 | desc->proxy_clk_names); | |
1909 | if (ret < 0) { | |
1910 | dev_err(&pdev->dev, "Failed to get proxy clocks.\n"); | |
051fb70f | 1911 | goto free_rproc; |
39b2410b AKD |
1912 | } |
1913 | qproc->proxy_clk_count = ret; | |
1914 | ||
231f67d1 SS |
1915 | ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks, |
1916 | desc->reset_clk_names); | |
1917 | if (ret < 0) { | |
1918 | dev_err(&pdev->dev, "Failed to get reset clocks.\n"); | |
1919 | goto free_rproc; | |
1920 | } | |
1921 | qproc->reset_clk_count = ret; | |
1922 | ||
39b2410b AKD |
1923 | ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks, |
1924 | desc->active_clk_names); | |
1925 | if (ret < 0) { | |
1926 | dev_err(&pdev->dev, "Failed to get active clocks.\n"); | |
1927 | goto free_rproc; | |
1928 | } | |
1929 | qproc->active_clk_count = ret; | |
051fb70f | 1930 | |
19f902b5 AKD |
1931 | ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs, |
1932 | desc->proxy_supply); | |
1933 | if (ret < 0) { | |
1934 | dev_err(&pdev->dev, "Failed to get proxy regulators.\n"); | |
051fb70f | 1935 | goto free_rproc; |
19f902b5 AKD |
1936 | } |
1937 | qproc->proxy_reg_count = ret; | |
1938 | ||
1939 | ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs, | |
1940 | desc->active_supply); | |
1941 | if (ret < 0) { | |
1942 | dev_err(&pdev->dev, "Failed to get active regulators.\n"); | |
1943 | goto free_rproc; | |
1944 | } | |
1945 | qproc->active_reg_count = ret; | |
051fb70f | 1946 | |
4760a896 RN |
1947 | ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds, |
1948 | desc->proxy_pd_names); | |
8750cf39 SG |
1949 | /* Fallback to regulators for old device trees */ |
1950 | if (ret == -ENODATA && desc->fallback_proxy_supply) { | |
1951 | ret = q6v5_regulator_init(&pdev->dev, | |
1952 | qproc->fallback_proxy_regs, | |
1953 | desc->fallback_proxy_supply); | |
1954 | if (ret < 0) { | |
1955 | dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n"); | |
c1fe10d2 | 1956 | goto free_rproc; |
8750cf39 SG |
1957 | } |
1958 | qproc->fallback_proxy_reg_count = ret; | |
1959 | } else if (ret < 0) { | |
4760a896 | 1960 | dev_err(&pdev->dev, "Failed to init power domains\n"); |
c1fe10d2 | 1961 | goto free_rproc; |
8750cf39 SG |
1962 | } else { |
1963 | qproc->proxy_pd_count = ret; | |
4760a896 | 1964 | } |
4760a896 | 1965 | |
29a5f9aa | 1966 | qproc->has_alt_reset = desc->has_alt_reset; |
051fb70f BA |
1967 | ret = q6v5_init_reset(qproc); |
1968 | if (ret) | |
4760a896 | 1969 | goto detach_proxy_pds; |
051fb70f | 1970 | |
9f058fa2 | 1971 | qproc->version = desc->version; |
6c5a9dc2 | 1972 | qproc->need_mem_protection = desc->need_mem_protection; |
318130cc | 1973 | qproc->has_mba_logs = desc->has_mba_logs; |
051fb70f | 1974 | |
c1fe10d2 | 1975 | ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem", |
7d674731 BA |
1976 | qcom_msa_handover); |
1977 | if (ret) | |
4760a896 | 1978 | goto detach_proxy_pds; |
051fb70f | 1979 | |
6c5a9dc2 AKD |
1980 | qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); |
1981 | qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); | |
cd9fc8f1 | 1982 | qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss"); |
4b48921a | 1983 | qcom_add_smd_subdev(rproc, &qproc->smd_subdev); |
1e140df0 | 1984 | qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss"); |
1fb82ee8 | 1985 | qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12); |
027045a6 SS |
1986 | if (IS_ERR(qproc->sysmon)) { |
1987 | ret = PTR_ERR(qproc->sysmon); | |
58396810 | 1988 | goto remove_subdevs; |
027045a6 | 1989 | } |
4b48921a | 1990 | |
051fb70f BA |
1991 | ret = rproc_add(rproc); |
1992 | if (ret) | |
58396810 | 1993 | goto remove_sysmon_subdev; |
051fb70f BA |
1994 | |
1995 | return 0; | |
1996 | ||
58396810 AE |
1997 | remove_sysmon_subdev: |
1998 | qcom_remove_sysmon_subdev(qproc->sysmon); | |
1999 | remove_subdevs: | |
58396810 AE |
2000 | qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev); |
2001 | qcom_remove_smd_subdev(rproc, &qproc->smd_subdev); | |
2002 | qcom_remove_glink_subdev(rproc, &qproc->glink_subdev); | |
2003 | detach_proxy_pds: | |
4760a896 | 2004 | q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
051fb70f | 2005 | free_rproc: |
433c0e04 | 2006 | rproc_free(rproc); |
051fb70f BA |
2007 | |
2008 | return ret; | |
2009 | } | |
2010 | ||
2011 | static int q6v5_remove(struct platform_device *pdev) | |
2012 | { | |
2013 | struct q6v5 *qproc = platform_get_drvdata(pdev); | |
58396810 | 2014 | struct rproc *rproc = qproc->rproc; |
051fb70f | 2015 | |
58396810 | 2016 | rproc_del(rproc); |
4b48921a | 2017 | |
c1fe10d2 | 2018 | qcom_q6v5_deinit(&qproc->q6v5); |
1fb82ee8 | 2019 | qcom_remove_sysmon_subdev(qproc->sysmon); |
58396810 AE |
2020 | qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev); |
2021 | qcom_remove_smd_subdev(rproc, &qproc->smd_subdev); | |
2022 | qcom_remove_glink_subdev(rproc, &qproc->glink_subdev); | |
4760a896 RN |
2023 | |
2024 | q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); | |
2025 | ||
58396810 | 2026 | rproc_free(rproc); |
051fb70f BA |
2027 | |
2028 | return 0; | |
2029 | } | |
2030 | ||
6439b527 SS |
2031 | static const struct rproc_hexagon_res sc7180_mss = { |
2032 | .hexagon_mba_image = "mba.mbn", | |
2033 | .proxy_clk_names = (char*[]){ | |
2034 | "xo", | |
2035 | NULL | |
2036 | }, | |
2037 | .reset_clk_names = (char*[]){ | |
2038 | "iface", | |
2039 | "bus", | |
2040 | "snoc_axi", | |
2041 | NULL | |
2042 | }, | |
2043 | .active_clk_names = (char*[]){ | |
2044 | "mnoc_axi", | |
2045 | "nav", | |
6439b527 SS |
2046 | NULL |
2047 | }, | |
6439b527 SS |
2048 | .proxy_pd_names = (char*[]){ |
2049 | "cx", | |
2050 | "mx", | |
2051 | "mss", | |
2052 | NULL | |
2053 | }, | |
2054 | .need_mem_protection = true, | |
2055 | .has_alt_reset = false, | |
318130cc | 2056 | .has_mba_logs = true, |
a9fdc79d | 2057 | .has_spare_reg = true, |
c842379d SS |
2058 | .has_qaccept_regs = false, |
2059 | .has_ext_cntl_regs = false, | |
2060 | .has_vq6 = false, | |
6439b527 SS |
2061 | .version = MSS_SC7180, |
2062 | }; | |
2063 | ||
c842379d SS |
2064 | static const struct rproc_hexagon_res sc7280_mss = { |
2065 | .hexagon_mba_image = "mba.mbn", | |
2066 | .proxy_clk_names = (char*[]){ | |
2067 | "xo", | |
2068 | "pka", | |
2069 | NULL | |
2070 | }, | |
2071 | .active_clk_names = (char*[]){ | |
2072 | "iface", | |
2073 | "offline", | |
2074 | "snoc_axi", | |
2075 | NULL | |
2076 | }, | |
2077 | .proxy_pd_names = (char*[]){ | |
2078 | "cx", | |
2079 | "mss", | |
2080 | NULL | |
2081 | }, | |
2082 | .need_mem_protection = true, | |
2083 | .has_alt_reset = false, | |
2084 | .has_mba_logs = true, | |
2085 | .has_spare_reg = false, | |
2086 | .has_qaccept_regs = true, | |
2087 | .has_ext_cntl_regs = true, | |
2088 | .has_vq6 = true, | |
2089 | .version = MSS_SC7280, | |
2090 | }; | |
2091 | ||
231f67d1 SS |
2092 | static const struct rproc_hexagon_res sdm845_mss = { |
2093 | .hexagon_mba_image = "mba.mbn", | |
2094 | .proxy_clk_names = (char*[]){ | |
2095 | "xo", | |
231f67d1 SS |
2096 | "prng", |
2097 | NULL | |
2098 | }, | |
2099 | .reset_clk_names = (char*[]){ | |
2100 | "iface", | |
2101 | "snoc_axi", | |
2102 | NULL | |
2103 | }, | |
2104 | .active_clk_names = (char*[]){ | |
2105 | "bus", | |
2106 | "mem", | |
2107 | "gpll0_mss", | |
2108 | "mnoc_axi", | |
2109 | NULL | |
2110 | }, | |
4760a896 RN |
2111 | .proxy_pd_names = (char*[]){ |
2112 | "cx", | |
2113 | "mx", | |
2114 | "mss", | |
2115 | NULL | |
2116 | }, | |
231f67d1 SS |
2117 | .need_mem_protection = true, |
2118 | .has_alt_reset = true, | |
318130cc | 2119 | .has_mba_logs = false, |
a9fdc79d | 2120 | .has_spare_reg = false, |
c842379d SS |
2121 | .has_qaccept_regs = false, |
2122 | .has_ext_cntl_regs = false, | |
2123 | .has_vq6 = false, | |
231f67d1 SS |
2124 | .version = MSS_SDM845, |
2125 | }; | |
2126 | ||
1665cbd5 JH |
2127 | static const struct rproc_hexagon_res msm8998_mss = { |
2128 | .hexagon_mba_image = "mba.mbn", | |
2129 | .proxy_clk_names = (char*[]){ | |
2130 | "xo", | |
2131 | "qdss", | |
2132 | "mem", | |
2133 | NULL | |
2134 | }, | |
2135 | .active_clk_names = (char*[]){ | |
2136 | "iface", | |
2137 | "bus", | |
1665cbd5 JH |
2138 | "gpll0_mss", |
2139 | "mnoc_axi", | |
2140 | "snoc_axi", | |
2141 | NULL | |
2142 | }, | |
2143 | .proxy_pd_names = (char*[]){ | |
2144 | "cx", | |
2145 | "mx", | |
2146 | NULL | |
2147 | }, | |
2148 | .need_mem_protection = true, | |
2149 | .has_alt_reset = false, | |
318130cc | 2150 | .has_mba_logs = false, |
a9fdc79d | 2151 | .has_spare_reg = false, |
c842379d SS |
2152 | .has_qaccept_regs = false, |
2153 | .has_ext_cntl_regs = false, | |
2154 | .has_vq6 = false, | |
1665cbd5 JH |
2155 | .version = MSS_MSM8998, |
2156 | }; | |
2157 | ||
9f058fa2 AKD |
2158 | static const struct rproc_hexagon_res msm8996_mss = { |
2159 | .hexagon_mba_image = "mba.mbn", | |
47b87474 SS |
2160 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
2161 | { | |
2162 | .supply = "pll", | |
2163 | .uA = 100000, | |
2164 | }, | |
2165 | {} | |
2166 | }, | |
9f058fa2 AKD |
2167 | .proxy_clk_names = (char*[]){ |
2168 | "xo", | |
2169 | "pnoc", | |
80ec419c | 2170 | "qdss", |
9f058fa2 AKD |
2171 | NULL |
2172 | }, | |
2173 | .active_clk_names = (char*[]){ | |
2174 | "iface", | |
2175 | "bus", | |
2176 | "mem", | |
80ec419c SS |
2177 | "gpll0_mss", |
2178 | "snoc_axi", | |
2179 | "mnoc_axi", | |
9f058fa2 AKD |
2180 | NULL |
2181 | }, | |
2182 | .need_mem_protection = true, | |
231f67d1 | 2183 | .has_alt_reset = false, |
318130cc | 2184 | .has_mba_logs = false, |
a9fdc79d | 2185 | .has_spare_reg = false, |
c842379d SS |
2186 | .has_qaccept_regs = false, |
2187 | .has_ext_cntl_regs = false, | |
2188 | .has_vq6 = false, | |
9f058fa2 AKD |
2189 | .version = MSS_MSM8996, |
2190 | }; | |
2191 | ||
7a8ffe1f AKD |
2192 | static const struct rproc_hexagon_res msm8916_mss = { |
2193 | .hexagon_mba_image = "mba.mbn", | |
19f902b5 | 2194 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
8750cf39 SG |
2195 | { |
2196 | .supply = "pll", | |
2197 | .uA = 100000, | |
2198 | }, | |
2199 | {} | |
2200 | }, | |
2201 | .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { | |
19f902b5 AKD |
2202 | { |
2203 | .supply = "mx", | |
2204 | .uV = 1050000, | |
2205 | }, | |
2206 | { | |
2207 | .supply = "cx", | |
2208 | .uA = 100000, | |
2209 | }, | |
19f902b5 AKD |
2210 | {} |
2211 | }, | |
39b2410b AKD |
2212 | .proxy_clk_names = (char*[]){ |
2213 | "xo", | |
2214 | NULL | |
2215 | }, | |
2216 | .active_clk_names = (char*[]){ | |
2217 | "iface", | |
2218 | "bus", | |
2219 | "mem", | |
2220 | NULL | |
2221 | }, | |
8750cf39 SG |
2222 | .proxy_pd_names = (char*[]){ |
2223 | "mx", | |
2224 | "cx", | |
2225 | NULL | |
2226 | }, | |
6c5a9dc2 | 2227 | .need_mem_protection = false, |
231f67d1 | 2228 | .has_alt_reset = false, |
318130cc | 2229 | .has_mba_logs = false, |
a9fdc79d | 2230 | .has_spare_reg = false, |
c842379d SS |
2231 | .has_qaccept_regs = false, |
2232 | .has_ext_cntl_regs = false, | |
2233 | .has_vq6 = false, | |
9f058fa2 | 2234 | .version = MSS_MSM8916, |
7a8ffe1f AKD |
2235 | }; |
2236 | ||
2237 | static const struct rproc_hexagon_res msm8974_mss = { | |
2238 | .hexagon_mba_image = "mba.b00", | |
19f902b5 | 2239 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
8750cf39 SG |
2240 | { |
2241 | .supply = "pll", | |
2242 | .uA = 100000, | |
2243 | }, | |
2244 | {} | |
2245 | }, | |
2246 | .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { | |
19f902b5 AKD |
2247 | { |
2248 | .supply = "mx", | |
2249 | .uV = 1050000, | |
2250 | }, | |
2251 | { | |
2252 | .supply = "cx", | |
2253 | .uA = 100000, | |
2254 | }, | |
19f902b5 AKD |
2255 | {} |
2256 | }, | |
2257 | .active_supply = (struct qcom_mss_reg_res[]) { | |
2258 | { | |
2259 | .supply = "mss", | |
2260 | .uV = 1050000, | |
2261 | .uA = 100000, | |
2262 | }, | |
2263 | {} | |
2264 | }, | |
39b2410b AKD |
2265 | .proxy_clk_names = (char*[]){ |
2266 | "xo", | |
2267 | NULL | |
2268 | }, | |
2269 | .active_clk_names = (char*[]){ | |
2270 | "iface", | |
2271 | "bus", | |
2272 | "mem", | |
2273 | NULL | |
2274 | }, | |
8750cf39 SG |
2275 | .proxy_pd_names = (char*[]){ |
2276 | "mx", | |
2277 | "cx", | |
2278 | NULL | |
2279 | }, | |
6c5a9dc2 | 2280 | .need_mem_protection = false, |
231f67d1 | 2281 | .has_alt_reset = false, |
318130cc | 2282 | .has_mba_logs = false, |
a9fdc79d | 2283 | .has_spare_reg = false, |
c842379d SS |
2284 | .has_qaccept_regs = false, |
2285 | .has_ext_cntl_regs = false, | |
2286 | .has_vq6 = false, | |
9f058fa2 | 2287 | .version = MSS_MSM8974, |
7a8ffe1f AKD |
2288 | }; |
2289 | ||
051fb70f | 2290 | static const struct of_device_id q6v5_of_match[] = { |
7a8ffe1f AKD |
2291 | { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, |
2292 | { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, | |
2293 | { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, | |
9f058fa2 | 2294 | { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, |
1665cbd5 | 2295 | { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss}, |
6439b527 | 2296 | { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss}, |
c842379d | 2297 | { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss}, |
231f67d1 | 2298 | { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss}, |
051fb70f BA |
2299 | { }, |
2300 | }; | |
3227c876 | 2301 | MODULE_DEVICE_TABLE(of, q6v5_of_match); |
051fb70f BA |
2302 | |
2303 | static struct platform_driver q6v5_driver = { | |
2304 | .probe = q6v5_probe, | |
2305 | .remove = q6v5_remove, | |
2306 | .driver = { | |
ef73c22f | 2307 | .name = "qcom-q6v5-mss", |
051fb70f BA |
2308 | .of_match_table = q6v5_of_match, |
2309 | }, | |
2310 | }; | |
2311 | module_platform_driver(q6v5_driver); | |
2312 | ||
ef73c22f | 2313 | MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver"); |
051fb70f | 2314 | MODULE_LICENSE("GPL v2"); |