Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
051fb70f | 2 | /* |
ef73c22f | 3 | * Qualcomm self-authenticating modem subsystem remoteproc driver |
051fb70f BA |
4 | * |
5 | * Copyright (C) 2016 Linaro Ltd. | |
6 | * Copyright (C) 2014 Sony Mobile Communications AB | |
7 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. | |
051fb70f BA |
8 | */ |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
318130cc | 12 | #include <linux/devcoredump.h> |
051fb70f BA |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/mfd/syscon.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of_address.h> | |
7a8ffe1f | 19 | #include <linux/of_device.h> |
051fb70f | 20 | #include <linux/platform_device.h> |
4760a896 RN |
21 | #include <linux/pm_domain.h> |
22 | #include <linux/pm_runtime.h> | |
051fb70f BA |
23 | #include <linux/regmap.h> |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/remoteproc.h> | |
26 | #include <linux/reset.h> | |
2aad40d9 | 27 | #include <linux/soc/qcom/mdt_loader.h> |
9f058fa2 | 28 | #include <linux/iopoll.h> |
7999096f | 29 | #include <linux/slab.h> |
051fb70f BA |
30 | |
31 | #include "remoteproc_internal.h" | |
bde440ee | 32 | #include "qcom_common.h" |
d4c78d21 | 33 | #include "qcom_pil_info.h" |
7d674731 | 34 | #include "qcom_q6v5.h" |
051fb70f BA |
35 | |
36 | #include <linux/qcom_scm.h> | |
37 | ||
051fb70f BA |
38 | #define MPSS_CRASH_REASON_SMEM 421 |
39 | ||
318130cc SS |
40 | #define MBA_LOG_SIZE SZ_4K |
41 | ||
051fb70f BA |
42 | /* RMB Status Register Values */ |
43 | #define RMB_PBL_SUCCESS 0x1 | |
44 | ||
45 | #define RMB_MBA_XPU_UNLOCKED 0x1 | |
46 | #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2 | |
47 | #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3 | |
48 | #define RMB_MBA_AUTH_COMPLETE 0x4 | |
49 | ||
50 | /* PBL/MBA interface registers */ | |
51 | #define RMB_MBA_IMAGE_REG 0x00 | |
52 | #define RMB_PBL_STATUS_REG 0x04 | |
53 | #define RMB_MBA_COMMAND_REG 0x08 | |
54 | #define RMB_MBA_STATUS_REG 0x0C | |
55 | #define RMB_PMI_META_DATA_REG 0x10 | |
56 | #define RMB_PMI_CODE_START_REG 0x14 | |
57 | #define RMB_PMI_CODE_LENGTH_REG 0x18 | |
231f67d1 SS |
58 | #define RMB_MBA_MSS_STATUS 0x40 |
59 | #define RMB_MBA_ALT_RESET 0x44 | |
051fb70f BA |
60 | |
61 | #define RMB_CMD_META_DATA_READY 0x1 | |
62 | #define RMB_CMD_LOAD_READY 0x2 | |
63 | ||
64 | /* QDSP6SS Register Offsets */ | |
65 | #define QDSP6SS_RESET_REG 0x014 | |
66 | #define QDSP6SS_GFMUX_CTL_REG 0x020 | |
67 | #define QDSP6SS_PWR_CTL_REG 0x030 | |
9f058fa2 | 68 | #define QDSP6SS_MEM_PWR_CTL 0x0B0 |
1665cbd5 | 69 | #define QDSP6V6SS_MEM_PWR_CTL 0x034 |
9f058fa2 | 70 | #define QDSP6SS_STRAP_ACC 0x110 |
051fb70f BA |
71 | |
72 | /* AXI Halt Register Offsets */ | |
73 | #define AXI_HALTREQ_REG 0x0 | |
74 | #define AXI_HALTACK_REG 0x4 | |
75 | #define AXI_IDLE_REG 0x8 | |
600c39b3 | 76 | #define AXI_GATING_VALID_OVERRIDE BIT(0) |
051fb70f | 77 | |
01bf3fec | 78 | #define HALT_ACK_TIMEOUT_US 100000 |
051fb70f BA |
79 | |
80 | /* QDSP6SS_RESET */ | |
81 | #define Q6SS_STOP_CORE BIT(0) | |
82 | #define Q6SS_CORE_ARES BIT(1) | |
83 | #define Q6SS_BUS_ARES_ENABLE BIT(2) | |
84 | ||
7e0f8688 SS |
85 | /* QDSP6SS CBCR */ |
86 | #define Q6SS_CBCR_CLKEN BIT(0) | |
87 | #define Q6SS_CBCR_CLKOFF BIT(31) | |
88 | #define Q6SS_CBCR_TIMEOUT_US 200 | |
89 | ||
051fb70f BA |
90 | /* QDSP6SS_GFMUX_CTL */ |
91 | #define Q6SS_CLK_ENABLE BIT(1) | |
92 | ||
93 | /* QDSP6SS_PWR_CTL */ | |
94 | #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0) | |
95 | #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1) | |
96 | #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2) | |
97 | #define Q6SS_L2TAG_SLP_NRET_N BIT(16) | |
98 | #define Q6SS_ETB_SLP_NRET_N BIT(17) | |
99 | #define Q6SS_L2DATA_STBY_N BIT(18) | |
100 | #define Q6SS_SLP_RET_N BIT(19) | |
101 | #define Q6SS_CLAMP_IO BIT(20) | |
102 | #define QDSS_BHS_ON BIT(21) | |
103 | #define QDSS_LDO_BYP BIT(22) | |
104 | ||
9f058fa2 AKD |
105 | /* QDSP6v56 parameters */ |
106 | #define QDSP6v56_LDO_BYP BIT(25) | |
107 | #define QDSP6v56_BHS_ON BIT(24) | |
108 | #define QDSP6v56_CLAMP_WL BIT(21) | |
109 | #define QDSP6v56_CLAMP_QMC_MEM BIT(22) | |
9f058fa2 AKD |
110 | #define QDSP6SS_XO_CBCR 0x0038 |
111 | #define QDSP6SS_ACC_OVERRIDE_VAL 0x20 | |
112 | ||
231f67d1 | 113 | /* QDSP6v65 parameters */ |
6439b527 | 114 | #define QDSP6SS_CORE_CBCR 0x20 |
231f67d1 SS |
115 | #define QDSP6SS_SLEEP 0x3C |
116 | #define QDSP6SS_BOOT_CORE_START 0x400 | |
117 | #define QDSP6SS_BOOT_CMD 0x404 | |
231f67d1 SS |
118 | #define BOOT_FSM_TIMEOUT 10000 |
119 | ||
19f902b5 AKD |
120 | struct reg_info { |
121 | struct regulator *reg; | |
122 | int uV; | |
123 | int uA; | |
124 | }; | |
125 | ||
126 | struct qcom_mss_reg_res { | |
127 | const char *supply; | |
128 | int uV; | |
129 | int uA; | |
130 | }; | |
131 | ||
7a8ffe1f AKD |
132 | struct rproc_hexagon_res { |
133 | const char *hexagon_mba_image; | |
ec671b53 | 134 | struct qcom_mss_reg_res *proxy_supply; |
8750cf39 | 135 | struct qcom_mss_reg_res *fallback_proxy_supply; |
ec671b53 | 136 | struct qcom_mss_reg_res *active_supply; |
39b2410b | 137 | char **proxy_clk_names; |
231f67d1 | 138 | char **reset_clk_names; |
39b2410b | 139 | char **active_clk_names; |
deb9bb83 | 140 | char **active_pd_names; |
4760a896 | 141 | char **proxy_pd_names; |
9f058fa2 | 142 | int version; |
6c5a9dc2 | 143 | bool need_mem_protection; |
231f67d1 | 144 | bool has_alt_reset; |
318130cc | 145 | bool has_mba_logs; |
a9fdc79d | 146 | bool has_spare_reg; |
7a8ffe1f AKD |
147 | }; |
148 | ||
051fb70f BA |
149 | struct q6v5 { |
150 | struct device *dev; | |
151 | struct rproc *rproc; | |
152 | ||
153 | void __iomem *reg_base; | |
154 | void __iomem *rmb_base; | |
155 | ||
156 | struct regmap *halt_map; | |
6439b527 SS |
157 | struct regmap *conn_map; |
158 | ||
051fb70f BA |
159 | u32 halt_q6; |
160 | u32 halt_modem; | |
161 | u32 halt_nc; | |
6439b527 | 162 | u32 conn_box; |
051fb70f BA |
163 | |
164 | struct reset_control *mss_restart; | |
29a5f9aa | 165 | struct reset_control *pdc_reset; |
051fb70f | 166 | |
7d674731 | 167 | struct qcom_q6v5 q6v5; |
663e9845 | 168 | |
39b2410b | 169 | struct clk *active_clks[8]; |
231f67d1 | 170 | struct clk *reset_clks[4]; |
39b2410b | 171 | struct clk *proxy_clks[4]; |
deb9bb83 | 172 | struct device *active_pds[1]; |
4760a896 | 173 | struct device *proxy_pds[3]; |
39b2410b | 174 | int active_clk_count; |
231f67d1 | 175 | int reset_clk_count; |
39b2410b | 176 | int proxy_clk_count; |
deb9bb83 | 177 | int active_pd_count; |
4760a896 | 178 | int proxy_pd_count; |
39b2410b | 179 | |
19f902b5 | 180 | struct reg_info active_regs[1]; |
8750cf39 SG |
181 | struct reg_info proxy_regs[1]; |
182 | struct reg_info fallback_proxy_regs[2]; | |
19f902b5 AKD |
183 | int active_reg_count; |
184 | int proxy_reg_count; | |
8750cf39 | 185 | int fallback_proxy_reg_count; |
051fb70f | 186 | |
0304530d | 187 | bool dump_mba_loaded; |
7ac516d3 SS |
188 | size_t current_dump_size; |
189 | size_t total_dump_size; | |
7dd8ade2 | 190 | |
051fb70f BA |
191 | phys_addr_t mba_phys; |
192 | void *mba_region; | |
193 | size_t mba_size; | |
fe6a5dc4 | 194 | size_t dp_size; |
051fb70f BA |
195 | |
196 | phys_addr_t mpss_phys; | |
197 | phys_addr_t mpss_reloc; | |
051fb70f | 198 | size_t mpss_size; |
4b48921a | 199 | |
4725496e | 200 | struct qcom_rproc_glink glink_subdev; |
4b48921a | 201 | struct qcom_rproc_subdev smd_subdev; |
1e140df0 | 202 | struct qcom_rproc_ssr ssr_subdev; |
1fb82ee8 | 203 | struct qcom_sysmon *sysmon; |
6c5a9dc2 | 204 | bool need_mem_protection; |
231f67d1 | 205 | bool has_alt_reset; |
318130cc | 206 | bool has_mba_logs; |
a9fdc79d | 207 | bool has_spare_reg; |
6c5a9dc2 AKD |
208 | int mpss_perm; |
209 | int mba_perm; | |
a5a4e02d | 210 | const char *hexagon_mdt_image; |
9f058fa2 AKD |
211 | int version; |
212 | }; | |
6c5a9dc2 | 213 | |
9f058fa2 AKD |
214 | enum { |
215 | MSS_MSM8916, | |
216 | MSS_MSM8974, | |
217 | MSS_MSM8996, | |
1665cbd5 | 218 | MSS_MSM8998, |
6439b527 | 219 | MSS_SC7180, |
231f67d1 | 220 | MSS_SDM845, |
051fb70f BA |
221 | }; |
222 | ||
19f902b5 AKD |
223 | static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, |
224 | const struct qcom_mss_reg_res *reg_res) | |
051fb70f | 225 | { |
19f902b5 AKD |
226 | int rc; |
227 | int i; | |
051fb70f | 228 | |
2bb5d906 BA |
229 | if (!reg_res) |
230 | return 0; | |
231 | ||
19f902b5 AKD |
232 | for (i = 0; reg_res[i].supply; i++) { |
233 | regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); | |
234 | if (IS_ERR(regs[i].reg)) { | |
235 | rc = PTR_ERR(regs[i].reg); | |
236 | if (rc != -EPROBE_DEFER) | |
237 | dev_err(dev, "Failed to get %s\n regulator", | |
238 | reg_res[i].supply); | |
239 | return rc; | |
240 | } | |
051fb70f | 241 | |
19f902b5 AKD |
242 | regs[i].uV = reg_res[i].uV; |
243 | regs[i].uA = reg_res[i].uA; | |
051fb70f BA |
244 | } |
245 | ||
19f902b5 | 246 | return i; |
051fb70f BA |
247 | } |
248 | ||
19f902b5 AKD |
249 | static int q6v5_regulator_enable(struct q6v5 *qproc, |
250 | struct reg_info *regs, int count) | |
051fb70f | 251 | { |
051fb70f | 252 | int ret; |
19f902b5 | 253 | int i; |
051fb70f | 254 | |
19f902b5 AKD |
255 | for (i = 0; i < count; i++) { |
256 | if (regs[i].uV > 0) { | |
257 | ret = regulator_set_voltage(regs[i].reg, | |
258 | regs[i].uV, INT_MAX); | |
259 | if (ret) { | |
260 | dev_err(qproc->dev, | |
261 | "Failed to request voltage for %d.\n", | |
262 | i); | |
263 | goto err; | |
264 | } | |
265 | } | |
051fb70f | 266 | |
19f902b5 AKD |
267 | if (regs[i].uA > 0) { |
268 | ret = regulator_set_load(regs[i].reg, | |
269 | regs[i].uA); | |
270 | if (ret < 0) { | |
271 | dev_err(qproc->dev, | |
272 | "Failed to set regulator mode\n"); | |
273 | goto err; | |
274 | } | |
275 | } | |
276 | ||
277 | ret = regulator_enable(regs[i].reg); | |
278 | if (ret) { | |
279 | dev_err(qproc->dev, "Regulator enable failed\n"); | |
280 | goto err; | |
281 | } | |
282 | } | |
283 | ||
284 | return 0; | |
285 | err: | |
286 | for (; i >= 0; i--) { | |
287 | if (regs[i].uV > 0) | |
288 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
289 | ||
290 | if (regs[i].uA > 0) | |
291 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 292 | |
19f902b5 AKD |
293 | regulator_disable(regs[i].reg); |
294 | } | |
051fb70f | 295 | |
19f902b5 | 296 | return ret; |
051fb70f BA |
297 | } |
298 | ||
19f902b5 AKD |
299 | static void q6v5_regulator_disable(struct q6v5 *qproc, |
300 | struct reg_info *regs, int count) | |
051fb70f | 301 | { |
19f902b5 AKD |
302 | int i; |
303 | ||
304 | for (i = 0; i < count; i++) { | |
305 | if (regs[i].uV > 0) | |
306 | regulator_set_voltage(regs[i].reg, 0, INT_MAX); | |
051fb70f | 307 | |
19f902b5 AKD |
308 | if (regs[i].uA > 0) |
309 | regulator_set_load(regs[i].reg, 0); | |
051fb70f | 310 | |
19f902b5 AKD |
311 | regulator_disable(regs[i].reg); |
312 | } | |
051fb70f BA |
313 | } |
314 | ||
39b2410b AKD |
315 | static int q6v5_clk_enable(struct device *dev, |
316 | struct clk **clks, int count) | |
317 | { | |
318 | int rc; | |
319 | int i; | |
320 | ||
321 | for (i = 0; i < count; i++) { | |
322 | rc = clk_prepare_enable(clks[i]); | |
323 | if (rc) { | |
324 | dev_err(dev, "Clock enable failed\n"); | |
325 | goto err; | |
326 | } | |
327 | } | |
328 | ||
329 | return 0; | |
330 | err: | |
331 | for (i--; i >= 0; i--) | |
332 | clk_disable_unprepare(clks[i]); | |
333 | ||
334 | return rc; | |
335 | } | |
336 | ||
337 | static void q6v5_clk_disable(struct device *dev, | |
338 | struct clk **clks, int count) | |
339 | { | |
340 | int i; | |
341 | ||
342 | for (i = 0; i < count; i++) | |
343 | clk_disable_unprepare(clks[i]); | |
344 | } | |
345 | ||
4760a896 RN |
346 | static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds, |
347 | size_t pd_count) | |
348 | { | |
349 | int ret; | |
350 | int i; | |
351 | ||
352 | for (i = 0; i < pd_count; i++) { | |
353 | dev_pm_genpd_set_performance_state(pds[i], INT_MAX); | |
354 | ret = pm_runtime_get_sync(pds[i]); | |
355 | if (ret < 0) | |
356 | goto unroll_pd_votes; | |
357 | } | |
358 | ||
359 | return 0; | |
360 | ||
361 | unroll_pd_votes: | |
362 | for (i--; i >= 0; i--) { | |
363 | dev_pm_genpd_set_performance_state(pds[i], 0); | |
364 | pm_runtime_put(pds[i]); | |
365 | } | |
366 | ||
367 | return ret; | |
58396810 | 368 | } |
4760a896 RN |
369 | |
370 | static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds, | |
371 | size_t pd_count) | |
372 | { | |
373 | int i; | |
374 | ||
375 | for (i = 0; i < pd_count; i++) { | |
376 | dev_pm_genpd_set_performance_state(pds[i], 0); | |
377 | pm_runtime_put(pds[i]); | |
378 | } | |
379 | } | |
380 | ||
6c5a9dc2 | 381 | static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, |
715d8525 | 382 | bool local, bool remote, phys_addr_t addr, |
6c5a9dc2 AKD |
383 | size_t size) |
384 | { | |
715d8525 BA |
385 | struct qcom_scm_vmperm next[2]; |
386 | int perms = 0; | |
6c5a9dc2 AKD |
387 | |
388 | if (!qproc->need_mem_protection) | |
389 | return 0; | |
715d8525 BA |
390 | |
391 | if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) && | |
392 | remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA))) | |
6c5a9dc2 AKD |
393 | return 0; |
394 | ||
715d8525 BA |
395 | if (local) { |
396 | next[perms].vmid = QCOM_SCM_VMID_HLOS; | |
397 | next[perms].perm = QCOM_SCM_PERM_RWX; | |
398 | perms++; | |
399 | } | |
400 | ||
401 | if (remote) { | |
402 | next[perms].vmid = QCOM_SCM_VMID_MSS_MSA; | |
403 | next[perms].perm = QCOM_SCM_PERM_RW; | |
404 | perms++; | |
405 | } | |
6c5a9dc2 | 406 | |
9f2a4342 | 407 | return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K), |
715d8525 | 408 | current_perm, next, perms); |
6c5a9dc2 AKD |
409 | } |
410 | ||
fe6a5dc4 SS |
411 | static void q6v5_debug_policy_load(struct q6v5 *qproc) |
412 | { | |
413 | const struct firmware *dp_fw; | |
414 | ||
415 | if (request_firmware_direct(&dp_fw, "msadp", qproc->dev)) | |
416 | return; | |
417 | ||
418 | if (SZ_1M + dp_fw->size <= qproc->mba_size) { | |
419 | memcpy(qproc->mba_region + SZ_1M, dp_fw->data, dp_fw->size); | |
420 | qproc->dp_size = dp_fw->size; | |
421 | } | |
422 | ||
423 | release_firmware(dp_fw); | |
424 | } | |
425 | ||
051fb70f BA |
426 | static int q6v5_load(struct rproc *rproc, const struct firmware *fw) |
427 | { | |
428 | struct q6v5 *qproc = rproc->priv; | |
429 | ||
e013f455 SS |
430 | /* MBA is restricted to a maximum size of 1M */ |
431 | if (fw->size > qproc->mba_size || fw->size > SZ_1M) { | |
432 | dev_err(qproc->dev, "MBA firmware load failed\n"); | |
433 | return -EINVAL; | |
434 | } | |
435 | ||
051fb70f | 436 | memcpy(qproc->mba_region, fw->data, fw->size); |
fe6a5dc4 | 437 | q6v5_debug_policy_load(qproc); |
051fb70f BA |
438 | |
439 | return 0; | |
440 | } | |
441 | ||
9f135fa1 SS |
442 | static int q6v5_reset_assert(struct q6v5 *qproc) |
443 | { | |
29a5f9aa SS |
444 | int ret; |
445 | ||
446 | if (qproc->has_alt_reset) { | |
447 | reset_control_assert(qproc->pdc_reset); | |
448 | ret = reset_control_reset(qproc->mss_restart); | |
449 | reset_control_deassert(qproc->pdc_reset); | |
a9fdc79d | 450 | } else if (qproc->has_spare_reg) { |
600c39b3 SS |
451 | /* |
452 | * When the AXI pipeline is being reset with the Q6 modem partly | |
453 | * operational there is possibility of AXI valid signal to | |
454 | * glitch, leading to spurious transactions and Q6 hangs. A work | |
455 | * around is employed by asserting the AXI_GATING_VALID_OVERRIDE | |
a9fdc79d SS |
456 | * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE |
457 | * is withdrawn post MSS assert followed by a MSS deassert, | |
458 | * while holding the PDC reset. | |
600c39b3 | 459 | */ |
6439b527 SS |
460 | reset_control_assert(qproc->pdc_reset); |
461 | regmap_update_bits(qproc->conn_map, qproc->conn_box, | |
600c39b3 | 462 | AXI_GATING_VALID_OVERRIDE, 1); |
6439b527 SS |
463 | reset_control_assert(qproc->mss_restart); |
464 | reset_control_deassert(qproc->pdc_reset); | |
465 | regmap_update_bits(qproc->conn_map, qproc->conn_box, | |
600c39b3 | 466 | AXI_GATING_VALID_OVERRIDE, 0); |
6439b527 | 467 | ret = reset_control_deassert(qproc->mss_restart); |
29a5f9aa SS |
468 | } else { |
469 | ret = reset_control_assert(qproc->mss_restart); | |
470 | } | |
471 | ||
472 | return ret; | |
9f135fa1 SS |
473 | } |
474 | ||
475 | static int q6v5_reset_deassert(struct q6v5 *qproc) | |
476 | { | |
231f67d1 SS |
477 | int ret; |
478 | ||
479 | if (qproc->has_alt_reset) { | |
29a5f9aa | 480 | reset_control_assert(qproc->pdc_reset); |
231f67d1 SS |
481 | writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET); |
482 | ret = reset_control_reset(qproc->mss_restart); | |
483 | writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); | |
29a5f9aa | 484 | reset_control_deassert(qproc->pdc_reset); |
a9fdc79d | 485 | } else if (qproc->has_spare_reg) { |
6439b527 | 486 | ret = reset_control_reset(qproc->mss_restart); |
231f67d1 SS |
487 | } else { |
488 | ret = reset_control_deassert(qproc->mss_restart); | |
489 | } | |
490 | ||
491 | return ret; | |
9f135fa1 SS |
492 | } |
493 | ||
051fb70f BA |
494 | static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms) |
495 | { | |
496 | unsigned long timeout; | |
497 | s32 val; | |
498 | ||
499 | timeout = jiffies + msecs_to_jiffies(ms); | |
500 | for (;;) { | |
501 | val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG); | |
502 | if (val) | |
503 | break; | |
504 | ||
505 | if (time_after(jiffies, timeout)) | |
506 | return -ETIMEDOUT; | |
507 | ||
508 | msleep(1); | |
509 | } | |
510 | ||
511 | return val; | |
512 | } | |
513 | ||
514 | static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms) | |
515 | { | |
516 | ||
517 | unsigned long timeout; | |
518 | s32 val; | |
519 | ||
520 | timeout = jiffies + msecs_to_jiffies(ms); | |
521 | for (;;) { | |
522 | val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); | |
523 | if (val < 0) | |
524 | break; | |
525 | ||
526 | if (!status && val) | |
527 | break; | |
528 | else if (status && val == status) | |
529 | break; | |
530 | ||
531 | if (time_after(jiffies, timeout)) | |
532 | return -ETIMEDOUT; | |
533 | ||
534 | msleep(1); | |
535 | } | |
536 | ||
537 | return val; | |
538 | } | |
539 | ||
318130cc SS |
540 | static void q6v5_dump_mba_logs(struct q6v5 *qproc) |
541 | { | |
542 | struct rproc *rproc = qproc->rproc; | |
543 | void *data; | |
544 | ||
545 | if (!qproc->has_mba_logs) | |
546 | return; | |
547 | ||
548 | if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys, | |
549 | qproc->mba_size)) | |
550 | return; | |
551 | ||
552 | data = vmalloc(MBA_LOG_SIZE); | |
553 | if (!data) | |
554 | return; | |
555 | ||
556 | memcpy(data, qproc->mba_region, MBA_LOG_SIZE); | |
557 | dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL); | |
558 | } | |
559 | ||
051fb70f BA |
560 | static int q6v5proc_reset(struct q6v5 *qproc) |
561 | { | |
562 | u32 val; | |
563 | int ret; | |
9f058fa2 | 564 | int i; |
051fb70f | 565 | |
231f67d1 SS |
566 | if (qproc->version == MSS_SDM845) { |
567 | val = readl(qproc->reg_base + QDSP6SS_SLEEP); | |
7e0f8688 | 568 | val |= Q6SS_CBCR_CLKEN; |
231f67d1 | 569 | writel(val, qproc->reg_base + QDSP6SS_SLEEP); |
051fb70f | 570 | |
231f67d1 | 571 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, |
7e0f8688 SS |
572 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
573 | Q6SS_CBCR_TIMEOUT_US); | |
231f67d1 SS |
574 | if (ret) { |
575 | dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); | |
576 | return -ETIMEDOUT; | |
577 | } | |
578 | ||
579 | /* De-assert QDSP6 stop core */ | |
580 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); | |
581 | /* Trigger boot FSM */ | |
582 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); | |
583 | ||
584 | ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, | |
585 | val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); | |
586 | if (ret) { | |
587 | dev_err(qproc->dev, "Boot FSM failed to complete.\n"); | |
588 | /* Reset the modem so that boot FSM is in reset state */ | |
589 | q6v5_reset_deassert(qproc); | |
590 | return ret; | |
591 | } | |
592 | ||
6439b527 SS |
593 | goto pbl_wait; |
594 | } else if (qproc->version == MSS_SC7180) { | |
595 | val = readl(qproc->reg_base + QDSP6SS_SLEEP); | |
7e0f8688 | 596 | val |= Q6SS_CBCR_CLKEN; |
6439b527 SS |
597 | writel(val, qproc->reg_base + QDSP6SS_SLEEP); |
598 | ||
599 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, | |
7e0f8688 SS |
600 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
601 | Q6SS_CBCR_TIMEOUT_US); | |
6439b527 SS |
602 | if (ret) { |
603 | dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); | |
604 | return -ETIMEDOUT; | |
605 | } | |
606 | ||
607 | /* Turn on the XO clock needed for PLL setup */ | |
608 | val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); | |
7e0f8688 | 609 | val |= Q6SS_CBCR_CLKEN; |
6439b527 SS |
610 | writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); |
611 | ||
612 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, | |
7e0f8688 SS |
613 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
614 | Q6SS_CBCR_TIMEOUT_US); | |
6439b527 SS |
615 | if (ret) { |
616 | dev_err(qproc->dev, "QDSP6SS XO clock timed out\n"); | |
617 | return -ETIMEDOUT; | |
618 | } | |
619 | ||
620 | /* Configure Q6 core CBCR to auto-enable after reset sequence */ | |
621 | val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR); | |
7e0f8688 | 622 | val |= Q6SS_CBCR_CLKEN; |
6439b527 SS |
623 | writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR); |
624 | ||
625 | /* De-assert the Q6 stop core signal */ | |
626 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); | |
627 | ||
4e6751a1 SS |
628 | /* Wait for 10 us for any staggering logic to settle */ |
629 | usleep_range(10, 20); | |
630 | ||
6439b527 SS |
631 | /* Trigger the boot FSM to start the Q6 out-of-reset sequence */ |
632 | writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); | |
633 | ||
4e6751a1 SS |
634 | /* Poll the MSS_STATUS for FSM completion */ |
635 | ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, | |
636 | val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); | |
6439b527 SS |
637 | if (ret) { |
638 | dev_err(qproc->dev, "Boot FSM failed to complete.\n"); | |
639 | /* Reset the modem so that boot FSM is in reset state */ | |
640 | q6v5_reset_deassert(qproc); | |
641 | return ret; | |
642 | } | |
231f67d1 | 643 | goto pbl_wait; |
1665cbd5 JH |
644 | } else if (qproc->version == MSS_MSM8996 || |
645 | qproc->version == MSS_MSM8998) { | |
646 | int mem_pwr_ctl; | |
647 | ||
9f058fa2 AKD |
648 | /* Override the ACC value if required */ |
649 | writel(QDSP6SS_ACC_OVERRIDE_VAL, | |
650 | qproc->reg_base + QDSP6SS_STRAP_ACC); | |
051fb70f | 651 | |
9f058fa2 AKD |
652 | /* Assert resets, stop core */ |
653 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
654 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
655 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
656 | ||
657 | /* BHS require xo cbcr to be enabled */ | |
658 | val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); | |
7e0f8688 | 659 | val |= Q6SS_CBCR_CLKEN; |
9f058fa2 AKD |
660 | writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); |
661 | ||
662 | /* Read CLKOFF bit to go low indicating CLK is enabled */ | |
663 | ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, | |
7e0f8688 SS |
664 | val, !(val & Q6SS_CBCR_CLKOFF), 1, |
665 | Q6SS_CBCR_TIMEOUT_US); | |
9f058fa2 AKD |
666 | if (ret) { |
667 | dev_err(qproc->dev, | |
668 | "xo cbcr enabling timed out (rc:%d)\n", ret); | |
669 | return ret; | |
670 | } | |
671 | /* Enable power block headswitch and wait for it to stabilize */ | |
672 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
673 | val |= QDSP6v56_BHS_ON; | |
674 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
675 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
676 | udelay(1); | |
677 | ||
678 | /* Put LDO in bypass mode */ | |
679 | val |= QDSP6v56_LDO_BYP; | |
680 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
681 | ||
682 | /* Deassert QDSP6 compiler memory clamp */ | |
683 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
684 | val &= ~QDSP6v56_CLAMP_QMC_MEM; | |
685 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
686 | ||
687 | /* Deassert memory peripheral sleep and L2 memory standby */ | |
688 | val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; | |
689 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
690 | ||
691 | /* Turn on L1, L2, ETB and JU memories 1 at a time */ | |
1665cbd5 JH |
692 | if (qproc->version == MSS_MSM8996) { |
693 | mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL; | |
694 | i = 19; | |
695 | } else { | |
696 | /* MSS_MSM8998 */ | |
697 | mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL; | |
698 | i = 28; | |
699 | } | |
700 | val = readl(qproc->reg_base + mem_pwr_ctl); | |
701 | for (; i >= 0; i--) { | |
9f058fa2 | 702 | val |= BIT(i); |
1665cbd5 | 703 | writel(val, qproc->reg_base + mem_pwr_ctl); |
9f058fa2 AKD |
704 | /* |
705 | * Read back value to ensure the write is done then | |
706 | * wait for 1us for both memory peripheral and data | |
707 | * array to turn on. | |
708 | */ | |
1665cbd5 | 709 | val |= readl(qproc->reg_base + mem_pwr_ctl); |
9f058fa2 AKD |
710 | udelay(1); |
711 | } | |
712 | /* Remove word line clamp */ | |
713 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
714 | val &= ~QDSP6v56_CLAMP_WL; | |
715 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
716 | } else { | |
717 | /* Assert resets, stop core */ | |
718 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
719 | val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; | |
720 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
721 | ||
722 | /* Enable power block headswitch and wait for it to stabilize */ | |
723 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
724 | val |= QDSS_BHS_ON | QDSS_LDO_BYP; | |
725 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
726 | val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
727 | udelay(1); | |
728 | /* | |
729 | * Turn on memories. L2 banks should be done individually | |
730 | * to minimize inrush current. | |
731 | */ | |
732 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
733 | val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | | |
734 | Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; | |
735 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
736 | val |= Q6SS_L2DATA_SLP_NRET_N_2; | |
737 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
738 | val |= Q6SS_L2DATA_SLP_NRET_N_1; | |
739 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
740 | val |= Q6SS_L2DATA_SLP_NRET_N_0; | |
741 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
742 | } | |
051fb70f BA |
743 | /* Remove IO clamp */ |
744 | val &= ~Q6SS_CLAMP_IO; | |
745 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
746 | ||
747 | /* Bring core out of reset */ | |
748 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
749 | val &= ~Q6SS_CORE_ARES; | |
750 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
751 | ||
752 | /* Turn on core clock */ | |
753 | val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
754 | val |= Q6SS_CLK_ENABLE; | |
755 | writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); | |
756 | ||
757 | /* Start core execution */ | |
758 | val = readl(qproc->reg_base + QDSP6SS_RESET_REG); | |
759 | val &= ~Q6SS_STOP_CORE; | |
760 | writel(val, qproc->reg_base + QDSP6SS_RESET_REG); | |
761 | ||
231f67d1 | 762 | pbl_wait: |
051fb70f BA |
763 | /* Wait for PBL status */ |
764 | ret = q6v5_rmb_pbl_wait(qproc, 1000); | |
765 | if (ret == -ETIMEDOUT) { | |
766 | dev_err(qproc->dev, "PBL boot timed out\n"); | |
767 | } else if (ret != RMB_PBL_SUCCESS) { | |
768 | dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret); | |
769 | ret = -EINVAL; | |
770 | } else { | |
771 | ret = 0; | |
772 | } | |
773 | ||
774 | return ret; | |
775 | } | |
776 | ||
777 | static void q6v5proc_halt_axi_port(struct q6v5 *qproc, | |
778 | struct regmap *halt_map, | |
779 | u32 offset) | |
780 | { | |
051fb70f BA |
781 | unsigned int val; |
782 | int ret; | |
783 | ||
784 | /* Check if we're already idle */ | |
785 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
786 | if (!ret && val) | |
787 | return; | |
788 | ||
789 | /* Assert halt request */ | |
790 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); | |
791 | ||
792 | /* Wait for halt */ | |
01bf3fec SS |
793 | regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val, |
794 | val, 1000, HALT_ACK_TIMEOUT_US); | |
051fb70f BA |
795 | |
796 | ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); | |
797 | if (ret || !val) | |
798 | dev_err(qproc->dev, "port failed halt\n"); | |
799 | ||
800 | /* Clear halt request (port will remain halted until reset) */ | |
801 | regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); | |
802 | } | |
803 | ||
804 | static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) | |
805 | { | |
00085f1e | 806 | unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; |
051fb70f | 807 | dma_addr_t phys; |
f04b9138 | 808 | void *metadata; |
6c5a9dc2 AKD |
809 | int mdata_perm; |
810 | int xferop_ret; | |
f04b9138 | 811 | size_t size; |
051fb70f BA |
812 | void *ptr; |
813 | int ret; | |
814 | ||
f04b9138 BA |
815 | metadata = qcom_mdt_read_metadata(fw, &size); |
816 | if (IS_ERR(metadata)) | |
817 | return PTR_ERR(metadata); | |
818 | ||
819 | ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs); | |
051fb70f | 820 | if (!ptr) { |
f04b9138 | 821 | kfree(metadata); |
051fb70f BA |
822 | dev_err(qproc->dev, "failed to allocate mdt buffer\n"); |
823 | return -ENOMEM; | |
824 | } | |
825 | ||
f04b9138 | 826 | memcpy(ptr, metadata, size); |
051fb70f | 827 | |
6c5a9dc2 AKD |
828 | /* Hypervisor mapping to access metadata by modem */ |
829 | mdata_perm = BIT(QCOM_SCM_VMID_HLOS); | |
715d8525 BA |
830 | ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true, |
831 | phys, size); | |
9f2a4342 BA |
832 | if (ret) { |
833 | dev_err(qproc->dev, | |
834 | "assigning Q6 access to metadata failed: %d\n", ret); | |
1a5d5c59 CJ |
835 | ret = -EAGAIN; |
836 | goto free_dma_attrs; | |
9f2a4342 | 837 | } |
6c5a9dc2 | 838 | |
051fb70f BA |
839 | writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG); |
840 | writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
841 | ||
842 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000); | |
843 | if (ret == -ETIMEDOUT) | |
844 | dev_err(qproc->dev, "MPSS header authentication timed out\n"); | |
845 | else if (ret < 0) | |
846 | dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret); | |
847 | ||
6c5a9dc2 | 848 | /* Metadata authentication done, remove modem access */ |
715d8525 BA |
849 | xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false, |
850 | phys, size); | |
6c5a9dc2 AKD |
851 | if (xferop_ret) |
852 | dev_warn(qproc->dev, | |
853 | "mdt buffer not reclaimed system may become unstable\n"); | |
854 | ||
1a5d5c59 | 855 | free_dma_attrs: |
f04b9138 BA |
856 | dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs); |
857 | kfree(metadata); | |
051fb70f BA |
858 | |
859 | return ret < 0 ? ret : 0; | |
860 | } | |
861 | ||
e7fd2522 BA |
862 | static bool q6v5_phdr_valid(const struct elf32_phdr *phdr) |
863 | { | |
864 | if (phdr->p_type != PT_LOAD) | |
865 | return false; | |
866 | ||
867 | if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH) | |
868 | return false; | |
869 | ||
870 | if (!phdr->p_memsz) | |
871 | return false; | |
872 | ||
873 | return true; | |
874 | } | |
875 | ||
0304530d SS |
876 | static int q6v5_mba_load(struct q6v5 *qproc) |
877 | { | |
878 | int ret; | |
879 | int xfermemop_ret; | |
318130cc | 880 | bool mba_load_err = false; |
0304530d SS |
881 | |
882 | qcom_q6v5_prepare(&qproc->q6v5); | |
883 | ||
deb9bb83 BA |
884 | ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count); |
885 | if (ret < 0) { | |
886 | dev_err(qproc->dev, "failed to enable active power domains\n"); | |
887 | goto disable_irqs; | |
888 | } | |
889 | ||
4760a896 RN |
890 | ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
891 | if (ret < 0) { | |
892 | dev_err(qproc->dev, "failed to enable proxy power domains\n"); | |
deb9bb83 | 893 | goto disable_active_pds; |
4760a896 RN |
894 | } |
895 | ||
8750cf39 SG |
896 | ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs, |
897 | qproc->fallback_proxy_reg_count); | |
898 | if (ret) { | |
899 | dev_err(qproc->dev, "failed to enable fallback proxy supplies\n"); | |
900 | goto disable_proxy_pds; | |
901 | } | |
902 | ||
0304530d SS |
903 | ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, |
904 | qproc->proxy_reg_count); | |
905 | if (ret) { | |
906 | dev_err(qproc->dev, "failed to enable proxy supplies\n"); | |
8750cf39 | 907 | goto disable_fallback_proxy_reg; |
0304530d SS |
908 | } |
909 | ||
910 | ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, | |
911 | qproc->proxy_clk_count); | |
912 | if (ret) { | |
913 | dev_err(qproc->dev, "failed to enable proxy clocks\n"); | |
914 | goto disable_proxy_reg; | |
915 | } | |
916 | ||
917 | ret = q6v5_regulator_enable(qproc, qproc->active_regs, | |
918 | qproc->active_reg_count); | |
919 | if (ret) { | |
920 | dev_err(qproc->dev, "failed to enable supplies\n"); | |
921 | goto disable_proxy_clk; | |
922 | } | |
923 | ||
924 | ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks, | |
925 | qproc->reset_clk_count); | |
926 | if (ret) { | |
927 | dev_err(qproc->dev, "failed to enable reset clocks\n"); | |
928 | goto disable_vdd; | |
929 | } | |
930 | ||
931 | ret = q6v5_reset_deassert(qproc); | |
932 | if (ret) { | |
933 | dev_err(qproc->dev, "failed to deassert mss restart\n"); | |
934 | goto disable_reset_clks; | |
935 | } | |
936 | ||
937 | ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, | |
938 | qproc->active_clk_count); | |
939 | if (ret) { | |
940 | dev_err(qproc->dev, "failed to enable clocks\n"); | |
941 | goto assert_reset; | |
942 | } | |
943 | ||
4360f93a SS |
944 | /* |
945 | * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide | |
946 | * the Q6 access to this region. | |
947 | */ | |
948 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true, | |
949 | qproc->mpss_phys, qproc->mpss_size); | |
950 | if (ret) { | |
951 | dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret); | |
952 | goto disable_active_clks; | |
953 | } | |
954 | ||
0304530d | 955 | /* Assign MBA image access in DDR to q6 */ |
715d8525 | 956 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true, |
0304530d SS |
957 | qproc->mba_phys, qproc->mba_size); |
958 | if (ret) { | |
959 | dev_err(qproc->dev, | |
960 | "assigning Q6 access to mba memory failed: %d\n", ret); | |
961 | goto disable_active_clks; | |
962 | } | |
963 | ||
964 | writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); | |
fe6a5dc4 SS |
965 | if (qproc->dp_size) { |
966 | writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG); | |
967 | writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
968 | } | |
0304530d SS |
969 | |
970 | ret = q6v5proc_reset(qproc); | |
971 | if (ret) | |
972 | goto reclaim_mba; | |
973 | ||
974 | ret = q6v5_rmb_mba_wait(qproc, 0, 5000); | |
975 | if (ret == -ETIMEDOUT) { | |
976 | dev_err(qproc->dev, "MBA boot timed out\n"); | |
977 | goto halt_axi_ports; | |
978 | } else if (ret != RMB_MBA_XPU_UNLOCKED && | |
979 | ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) { | |
980 | dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret); | |
981 | ret = -EINVAL; | |
982 | goto halt_axi_ports; | |
983 | } | |
984 | ||
985 | qproc->dump_mba_loaded = true; | |
986 | return 0; | |
987 | ||
988 | halt_axi_ports: | |
989 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
990 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); | |
991 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); | |
318130cc | 992 | mba_load_err = true; |
0304530d | 993 | reclaim_mba: |
715d8525 BA |
994 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, |
995 | false, qproc->mba_phys, | |
0304530d SS |
996 | qproc->mba_size); |
997 | if (xfermemop_ret) { | |
998 | dev_err(qproc->dev, | |
999 | "Failed to reclaim mba buffer, system may become unstable\n"); | |
318130cc SS |
1000 | } else if (mba_load_err) { |
1001 | q6v5_dump_mba_logs(qproc); | |
0304530d SS |
1002 | } |
1003 | ||
1004 | disable_active_clks: | |
1005 | q6v5_clk_disable(qproc->dev, qproc->active_clks, | |
1006 | qproc->active_clk_count); | |
1007 | assert_reset: | |
1008 | q6v5_reset_assert(qproc); | |
1009 | disable_reset_clks: | |
1010 | q6v5_clk_disable(qproc->dev, qproc->reset_clks, | |
1011 | qproc->reset_clk_count); | |
1012 | disable_vdd: | |
1013 | q6v5_regulator_disable(qproc, qproc->active_regs, | |
1014 | qproc->active_reg_count); | |
1015 | disable_proxy_clk: | |
1016 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, | |
1017 | qproc->proxy_clk_count); | |
1018 | disable_proxy_reg: | |
1019 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
1020 | qproc->proxy_reg_count); | |
8750cf39 SG |
1021 | disable_fallback_proxy_reg: |
1022 | q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, | |
1023 | qproc->fallback_proxy_reg_count); | |
4760a896 RN |
1024 | disable_proxy_pds: |
1025 | q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); | |
deb9bb83 BA |
1026 | disable_active_pds: |
1027 | q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); | |
0304530d SS |
1028 | disable_irqs: |
1029 | qcom_q6v5_unprepare(&qproc->q6v5); | |
1030 | ||
1031 | return ret; | |
1032 | } | |
1033 | ||
1034 | static void q6v5_mba_reclaim(struct q6v5 *qproc) | |
1035 | { | |
1036 | int ret; | |
1037 | u32 val; | |
1038 | ||
1039 | qproc->dump_mba_loaded = false; | |
fe6a5dc4 | 1040 | qproc->dp_size = 0; |
0304530d SS |
1041 | |
1042 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); | |
1043 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); | |
1044 | q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); | |
1045 | if (qproc->version == MSS_MSM8996) { | |
1046 | /* | |
1047 | * To avoid high MX current during LPASS/MSS restart. | |
1048 | */ | |
1049 | val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
1050 | val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | | |
1051 | QDSP6v56_CLAMP_QMC_MEM; | |
1052 | writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); | |
1053 | } | |
1054 | ||
0304530d SS |
1055 | q6v5_reset_assert(qproc); |
1056 | ||
1057 | q6v5_clk_disable(qproc->dev, qproc->reset_clks, | |
1058 | qproc->reset_clk_count); | |
1059 | q6v5_clk_disable(qproc->dev, qproc->active_clks, | |
1060 | qproc->active_clk_count); | |
1061 | q6v5_regulator_disable(qproc, qproc->active_regs, | |
1062 | qproc->active_reg_count); | |
deb9bb83 | 1063 | q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); |
0304530d SS |
1064 | |
1065 | /* In case of failure or coredump scenario where reclaiming MBA memory | |
1066 | * could not happen reclaim it here. | |
1067 | */ | |
715d8525 | 1068 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, |
0304530d SS |
1069 | qproc->mba_phys, |
1070 | qproc->mba_size); | |
1071 | WARN_ON(ret); | |
1072 | ||
1073 | ret = qcom_q6v5_unprepare(&qproc->q6v5); | |
1074 | if (ret) { | |
4760a896 RN |
1075 | q6v5_pds_disable(qproc, qproc->proxy_pds, |
1076 | qproc->proxy_pd_count); | |
0304530d SS |
1077 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, |
1078 | qproc->proxy_clk_count); | |
8750cf39 SG |
1079 | q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, |
1080 | qproc->fallback_proxy_reg_count); | |
0304530d SS |
1081 | q6v5_regulator_disable(qproc, qproc->proxy_regs, |
1082 | qproc->proxy_reg_count); | |
1083 | } | |
1084 | } | |
1085 | ||
d96f2571 SS |
1086 | static int q6v5_reload_mba(struct rproc *rproc) |
1087 | { | |
1088 | struct q6v5 *qproc = rproc->priv; | |
1089 | const struct firmware *fw; | |
1090 | int ret; | |
1091 | ||
1092 | ret = request_firmware(&fw, rproc->firmware, qproc->dev); | |
1093 | if (ret < 0) | |
1094 | return ret; | |
1095 | ||
1096 | q6v5_load(rproc, fw); | |
1097 | ret = q6v5_mba_load(qproc); | |
1098 | release_firmware(fw); | |
1099 | ||
1100 | return ret; | |
1101 | } | |
1102 | ||
e7fd2522 | 1103 | static int q6v5_mpss_load(struct q6v5 *qproc) |
051fb70f BA |
1104 | { |
1105 | const struct elf32_phdr *phdrs; | |
1106 | const struct elf32_phdr *phdr; | |
e7fd2522 BA |
1107 | const struct firmware *seg_fw; |
1108 | const struct firmware *fw; | |
051fb70f | 1109 | struct elf32_hdr *ehdr; |
e7fd2522 | 1110 | phys_addr_t mpss_reloc; |
051fb70f | 1111 | phys_addr_t boot_addr; |
d7dc899a | 1112 | phys_addr_t min_addr = PHYS_ADDR_MAX; |
e7fd2522 | 1113 | phys_addr_t max_addr = 0; |
715d8525 | 1114 | u32 code_length; |
e7fd2522 | 1115 | bool relocate = false; |
a5a4e02d SS |
1116 | char *fw_name; |
1117 | size_t fw_name_len; | |
01625cc5 | 1118 | ssize_t offset; |
94c90785 | 1119 | size_t size = 0; |
e7fd2522 | 1120 | void *ptr; |
051fb70f BA |
1121 | int ret; |
1122 | int i; | |
1123 | ||
a5a4e02d SS |
1124 | fw_name_len = strlen(qproc->hexagon_mdt_image); |
1125 | if (fw_name_len <= 4) | |
1126 | return -EINVAL; | |
1127 | ||
1128 | fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL); | |
1129 | if (!fw_name) | |
1130 | return -ENOMEM; | |
1131 | ||
1132 | ret = request_firmware(&fw, fw_name, qproc->dev); | |
e7fd2522 | 1133 | if (ret < 0) { |
a5a4e02d SS |
1134 | dev_err(qproc->dev, "unable to load %s\n", fw_name); |
1135 | goto out; | |
051fb70f BA |
1136 | } |
1137 | ||
e7fd2522 BA |
1138 | /* Initialize the RMB validator */ |
1139 | writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1140 | ||
1141 | ret = q6v5_mpss_init_image(qproc, fw); | |
1142 | if (ret) | |
1143 | goto release_firmware; | |
051fb70f BA |
1144 | |
1145 | ehdr = (struct elf32_hdr *)fw->data; | |
1146 | phdrs = (struct elf32_phdr *)(ehdr + 1); | |
e7fd2522 BA |
1147 | |
1148 | for (i = 0; i < ehdr->e_phnum; i++) { | |
051fb70f BA |
1149 | phdr = &phdrs[i]; |
1150 | ||
e7fd2522 | 1151 | if (!q6v5_phdr_valid(phdr)) |
051fb70f BA |
1152 | continue; |
1153 | ||
e7fd2522 BA |
1154 | if (phdr->p_flags & QCOM_MDT_RELOCATABLE) |
1155 | relocate = true; | |
051fb70f | 1156 | |
e7fd2522 BA |
1157 | if (phdr->p_paddr < min_addr) |
1158 | min_addr = phdr->p_paddr; | |
1159 | ||
1160 | if (phdr->p_paddr + phdr->p_memsz > max_addr) | |
1161 | max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); | |
1162 | } | |
1163 | ||
4360f93a | 1164 | /* |
900fc60d | 1165 | * In case of a modem subsystem restart on secure devices, the modem |
4360f93a | 1166 | * memory can be reclaimed only after MBA is loaded. |
900fc60d | 1167 | */ |
715d8525 | 1168 | q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false, |
900fc60d BA |
1169 | qproc->mpss_phys, qproc->mpss_size); |
1170 | ||
715d8525 BA |
1171 | /* Share ownership between Linux and MSS, during segment loading */ |
1172 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true, | |
1173 | qproc->mpss_phys, qproc->mpss_size); | |
1174 | if (ret) { | |
1175 | dev_err(qproc->dev, | |
1176 | "assigning Q6 access to mpss memory failed: %d\n", ret); | |
1177 | ret = -EAGAIN; | |
1178 | goto release_firmware; | |
1179 | } | |
1180 | ||
e7fd2522 | 1181 | mpss_reloc = relocate ? min_addr : qproc->mpss_phys; |
3bf62eb7 | 1182 | qproc->mpss_reloc = mpss_reloc; |
94c90785 | 1183 | /* Load firmware segments */ |
e7fd2522 BA |
1184 | for (i = 0; i < ehdr->e_phnum; i++) { |
1185 | phdr = &phdrs[i]; | |
1186 | ||
1187 | if (!q6v5_phdr_valid(phdr)) | |
051fb70f BA |
1188 | continue; |
1189 | ||
e7fd2522 BA |
1190 | offset = phdr->p_paddr - mpss_reloc; |
1191 | if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) { | |
1192 | dev_err(qproc->dev, "segment outside memory range\n"); | |
1193 | ret = -EINVAL; | |
1194 | goto release_firmware; | |
1195 | } | |
1196 | ||
04ff5d19 | 1197 | ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC); |
be050a34 SS |
1198 | if (!ptr) { |
1199 | dev_err(qproc->dev, | |
1200 | "unable to map memory region: %pa+%zx-%x\n", | |
1201 | &qproc->mpss_phys, offset, phdr->p_memsz); | |
1202 | goto release_firmware; | |
1203 | } | |
e7fd2522 | 1204 | |
f04b9138 BA |
1205 | if (phdr->p_filesz && phdr->p_offset < fw->size) { |
1206 | /* Firmware is large enough to be non-split */ | |
1207 | if (phdr->p_offset + phdr->p_filesz > fw->size) { | |
1208 | dev_err(qproc->dev, | |
1209 | "failed to load segment %d from truncated file %s\n", | |
1210 | i, fw_name); | |
1211 | ret = -EINVAL; | |
04ff5d19 | 1212 | memunmap(ptr); |
f04b9138 BA |
1213 | goto release_firmware; |
1214 | } | |
1215 | ||
1216 | memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz); | |
1217 | } else if (phdr->p_filesz) { | |
a5a4e02d SS |
1218 | /* Replace "xxx.xxx" with "xxx.bxx" */ |
1219 | sprintf(fw_name + fw_name_len - 3, "b%02d", i); | |
135b9e8d SS |
1220 | ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev, |
1221 | ptr, phdr->p_filesz); | |
e7fd2522 | 1222 | if (ret) { |
a5a4e02d | 1223 | dev_err(qproc->dev, "failed to load %s\n", fw_name); |
04ff5d19 | 1224 | memunmap(ptr); |
e7fd2522 BA |
1225 | goto release_firmware; |
1226 | } | |
1227 | ||
e7fd2522 BA |
1228 | release_firmware(seg_fw); |
1229 | } | |
1230 | ||
1231 | if (phdr->p_memsz > phdr->p_filesz) { | |
1232 | memset(ptr + phdr->p_filesz, 0, | |
1233 | phdr->p_memsz - phdr->p_filesz); | |
1234 | } | |
04ff5d19 | 1235 | memunmap(ptr); |
051fb70f | 1236 | size += phdr->p_memsz; |
715d8525 BA |
1237 | |
1238 | code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1239 | if (!code_length) { | |
1240 | boot_addr = relocate ? qproc->mpss_phys : min_addr; | |
1241 | writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG); | |
1242 | writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); | |
1243 | } | |
1244 | writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); | |
1245 | ||
1246 | ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); | |
1247 | if (ret < 0) { | |
1248 | dev_err(qproc->dev, "MPSS authentication failed: %d\n", | |
1249 | ret); | |
1250 | goto release_firmware; | |
1251 | } | |
051fb70f BA |
1252 | } |
1253 | ||
6c5a9dc2 | 1254 | /* Transfer ownership of modem ddr region to q6 */ |
715d8525 | 1255 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true, |
6c5a9dc2 | 1256 | qproc->mpss_phys, qproc->mpss_size); |
9f2a4342 BA |
1257 | if (ret) { |
1258 | dev_err(qproc->dev, | |
1259 | "assigning Q6 access to mpss memory failed: %d\n", ret); | |
1a5d5c59 CJ |
1260 | ret = -EAGAIN; |
1261 | goto release_firmware; | |
9f2a4342 | 1262 | } |
6c5a9dc2 | 1263 | |
72beb490 BA |
1264 | ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000); |
1265 | if (ret == -ETIMEDOUT) | |
1266 | dev_err(qproc->dev, "MPSS authentication timed out\n"); | |
1267 | else if (ret < 0) | |
1268 | dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret); | |
1269 | ||
d4c78d21 BA |
1270 | qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size); |
1271 | ||
051fb70f BA |
1272 | release_firmware: |
1273 | release_firmware(fw); | |
a5a4e02d SS |
1274 | out: |
1275 | kfree(fw_name); | |
051fb70f BA |
1276 | |
1277 | return ret < 0 ? ret : 0; | |
1278 | } | |
1279 | ||
7dd8ade2 SS |
1280 | static void qcom_q6v5_dump_segment(struct rproc *rproc, |
1281 | struct rproc_dump_segment *segment, | |
76abf9ce | 1282 | void *dest, size_t cp_offset, size_t size) |
7dd8ade2 SS |
1283 | { |
1284 | int ret = 0; | |
1285 | struct q6v5 *qproc = rproc->priv; | |
be050a34 SS |
1286 | int offset = segment->da - qproc->mpss_reloc; |
1287 | void *ptr = NULL; | |
7dd8ade2 SS |
1288 | |
1289 | /* Unlock mba before copying segments */ | |
900fc60d | 1290 | if (!qproc->dump_mba_loaded) { |
d96f2571 | 1291 | ret = q6v5_reload_mba(rproc); |
900fc60d BA |
1292 | if (!ret) { |
1293 | /* Reset ownership back to Linux to copy segments */ | |
1294 | ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, | |
715d8525 | 1295 | true, false, |
900fc60d BA |
1296 | qproc->mpss_phys, |
1297 | qproc->mpss_size); | |
1298 | } | |
1299 | } | |
7dd8ade2 | 1300 | |
be050a34 | 1301 | if (!ret) |
04ff5d19 | 1302 | ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC); |
be050a34 SS |
1303 | |
1304 | if (ptr) { | |
76abf9ce | 1305 | memcpy(dest, ptr, size); |
04ff5d19 | 1306 | memunmap(ptr); |
be050a34 | 1307 | } else { |
76abf9ce | 1308 | memset(dest, 0xff, size); |
be050a34 | 1309 | } |
7dd8ade2 | 1310 | |
76abf9ce | 1311 | qproc->current_dump_size += size; |
7dd8ade2 SS |
1312 | |
1313 | /* Reclaim mba after copying segments */ | |
7ac516d3 | 1314 | if (qproc->current_dump_size == qproc->total_dump_size) { |
900fc60d BA |
1315 | if (qproc->dump_mba_loaded) { |
1316 | /* Try to reset ownership back to Q6 */ | |
1317 | q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, | |
715d8525 | 1318 | false, true, |
900fc60d BA |
1319 | qproc->mpss_phys, |
1320 | qproc->mpss_size); | |
7dd8ade2 | 1321 | q6v5_mba_reclaim(qproc); |
900fc60d | 1322 | } |
7dd8ade2 SS |
1323 | } |
1324 | } | |
1325 | ||
051fb70f BA |
1326 | static int q6v5_start(struct rproc *rproc) |
1327 | { | |
1328 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
6c5a9dc2 | 1329 | int xfermemop_ret; |
051fb70f BA |
1330 | int ret; |
1331 | ||
0304530d | 1332 | ret = q6v5_mba_load(qproc); |
051fb70f | 1333 | if (ret) |
0304530d | 1334 | return ret; |
051fb70f | 1335 | |
fe6a5dc4 SS |
1336 | dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n", |
1337 | qproc->dp_size ? "" : "out"); | |
051fb70f BA |
1338 | |
1339 | ret = q6v5_mpss_load(qproc); | |
1340 | if (ret) | |
6c5a9dc2 | 1341 | goto reclaim_mpss; |
051fb70f | 1342 | |
7d674731 BA |
1343 | ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000)); |
1344 | if (ret == -ETIMEDOUT) { | |
051fb70f | 1345 | dev_err(qproc->dev, "start timed out\n"); |
6c5a9dc2 | 1346 | goto reclaim_mpss; |
051fb70f BA |
1347 | } |
1348 | ||
715d8525 BA |
1349 | xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, |
1350 | false, qproc->mba_phys, | |
6c5a9dc2 AKD |
1351 | qproc->mba_size); |
1352 | if (xfermemop_ret) | |
1353 | dev_err(qproc->dev, | |
1354 | "Failed to reclaim mba buffer system may become unstable\n"); | |
7dd8ade2 SS |
1355 | |
1356 | /* Reset Dump Segment Mask */ | |
7ac516d3 | 1357 | qproc->current_dump_size = 0; |
051fb70f | 1358 | |
051fb70f BA |
1359 | return 0; |
1360 | ||
6c5a9dc2 | 1361 | reclaim_mpss: |
0304530d | 1362 | q6v5_mba_reclaim(qproc); |
318130cc | 1363 | q6v5_dump_mba_logs(qproc); |
663e9845 | 1364 | |
051fb70f BA |
1365 | return ret; |
1366 | } | |
1367 | ||
1368 | static int q6v5_stop(struct rproc *rproc) | |
1369 | { | |
1370 | struct q6v5 *qproc = (struct q6v5 *)rproc->priv; | |
1371 | int ret; | |
1372 | ||
7d674731 BA |
1373 | ret = qcom_q6v5_request_stop(&qproc->q6v5); |
1374 | if (ret == -ETIMEDOUT) | |
051fb70f BA |
1375 | dev_err(qproc->dev, "timed out on wait\n"); |
1376 | ||
0304530d | 1377 | q6v5_mba_reclaim(qproc); |
051fb70f BA |
1378 | |
1379 | return 0; | |
1380 | } | |
1381 | ||
f18b7e91 SS |
1382 | static int qcom_q6v5_register_dump_segments(struct rproc *rproc, |
1383 | const struct firmware *mba_fw) | |
1384 | { | |
1385 | const struct firmware *fw; | |
1386 | const struct elf32_phdr *phdrs; | |
1387 | const struct elf32_phdr *phdr; | |
1388 | const struct elf32_hdr *ehdr; | |
1389 | struct q6v5 *qproc = rproc->priv; | |
1390 | unsigned long i; | |
1391 | int ret; | |
1392 | ||
a5a4e02d | 1393 | ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev); |
f18b7e91 | 1394 | if (ret < 0) { |
a5a4e02d SS |
1395 | dev_err(qproc->dev, "unable to load %s\n", |
1396 | qproc->hexagon_mdt_image); | |
f18b7e91 SS |
1397 | return ret; |
1398 | } | |
1399 | ||
3898fc99 CL |
1400 | rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); |
1401 | ||
f18b7e91 SS |
1402 | ehdr = (struct elf32_hdr *)fw->data; |
1403 | phdrs = (struct elf32_phdr *)(ehdr + 1); | |
7ac516d3 | 1404 | qproc->total_dump_size = 0; |
f18b7e91 SS |
1405 | |
1406 | for (i = 0; i < ehdr->e_phnum; i++) { | |
1407 | phdr = &phdrs[i]; | |
1408 | ||
1409 | if (!q6v5_phdr_valid(phdr)) | |
1410 | continue; | |
1411 | ||
1412 | ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr, | |
1413 | phdr->p_memsz, | |
1414 | qcom_q6v5_dump_segment, | |
7ac516d3 | 1415 | NULL); |
f18b7e91 SS |
1416 | if (ret) |
1417 | break; | |
1418 | ||
7ac516d3 | 1419 | qproc->total_dump_size += phdr->p_memsz; |
f18b7e91 SS |
1420 | } |
1421 | ||
1422 | release_firmware(fw); | |
1423 | return ret; | |
1424 | } | |
1425 | ||
051fb70f BA |
1426 | static const struct rproc_ops q6v5_ops = { |
1427 | .start = q6v5_start, | |
1428 | .stop = q6v5_stop, | |
f18b7e91 | 1429 | .parse_fw = qcom_q6v5_register_dump_segments, |
0f21f9cc | 1430 | .load = q6v5_load, |
051fb70f BA |
1431 | }; |
1432 | ||
7d674731 | 1433 | static void qcom_msa_handover(struct qcom_q6v5 *q6v5) |
663e9845 | 1434 | { |
7d674731 | 1435 | struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5); |
663e9845 SS |
1436 | |
1437 | q6v5_clk_disable(qproc->dev, qproc->proxy_clks, | |
1438 | qproc->proxy_clk_count); | |
1439 | q6v5_regulator_disable(qproc, qproc->proxy_regs, | |
1440 | qproc->proxy_reg_count); | |
8750cf39 SG |
1441 | q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs, |
1442 | qproc->fallback_proxy_reg_count); | |
4760a896 | 1443 | q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
051fb70f BA |
1444 | } |
1445 | ||
1446 | static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) | |
1447 | { | |
1448 | struct of_phandle_args args; | |
1449 | struct resource *res; | |
1450 | int ret; | |
1451 | ||
1452 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); | |
1453 | qproc->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
b1653f23 | 1454 | if (IS_ERR(qproc->reg_base)) |
051fb70f | 1455 | return PTR_ERR(qproc->reg_base); |
051fb70f BA |
1456 | |
1457 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); | |
1458 | qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res); | |
b1653f23 | 1459 | if (IS_ERR(qproc->rmb_base)) |
051fb70f | 1460 | return PTR_ERR(qproc->rmb_base); |
051fb70f BA |
1461 | |
1462 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
1463 | "qcom,halt-regs", 3, 0, &args); | |
1464 | if (ret < 0) { | |
1465 | dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); | |
1466 | return -EINVAL; | |
1467 | } | |
1468 | ||
1469 | qproc->halt_map = syscon_node_to_regmap(args.np); | |
1470 | of_node_put(args.np); | |
1471 | if (IS_ERR(qproc->halt_map)) | |
1472 | return PTR_ERR(qproc->halt_map); | |
1473 | ||
1474 | qproc->halt_q6 = args.args[0]; | |
1475 | qproc->halt_modem = args.args[1]; | |
1476 | qproc->halt_nc = args.args[2]; | |
1477 | ||
a9fdc79d | 1478 | if (qproc->has_spare_reg) { |
6439b527 | 1479 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, |
a9fdc79d | 1480 | "qcom,spare-regs", |
6439b527 SS |
1481 | 1, 0, &args); |
1482 | if (ret < 0) { | |
a9fdc79d | 1483 | dev_err(&pdev->dev, "failed to parse spare-regs\n"); |
6439b527 SS |
1484 | return -EINVAL; |
1485 | } | |
1486 | ||
1487 | qproc->conn_map = syscon_node_to_regmap(args.np); | |
1488 | of_node_put(args.np); | |
1489 | if (IS_ERR(qproc->conn_map)) | |
1490 | return PTR_ERR(qproc->conn_map); | |
1491 | ||
1492 | qproc->conn_box = args.args[0]; | |
1493 | } | |
1494 | ||
051fb70f BA |
1495 | return 0; |
1496 | } | |
1497 | ||
39b2410b AKD |
1498 | static int q6v5_init_clocks(struct device *dev, struct clk **clks, |
1499 | char **clk_names) | |
051fb70f | 1500 | { |
39b2410b | 1501 | int i; |
051fb70f | 1502 | |
39b2410b AKD |
1503 | if (!clk_names) |
1504 | return 0; | |
1505 | ||
1506 | for (i = 0; clk_names[i]; i++) { | |
1507 | clks[i] = devm_clk_get(dev, clk_names[i]); | |
1508 | if (IS_ERR(clks[i])) { | |
1509 | int rc = PTR_ERR(clks[i]); | |
051fb70f | 1510 | |
39b2410b AKD |
1511 | if (rc != -EPROBE_DEFER) |
1512 | dev_err(dev, "Failed to get %s clock\n", | |
1513 | clk_names[i]); | |
1514 | return rc; | |
1515 | } | |
051fb70f BA |
1516 | } |
1517 | ||
39b2410b | 1518 | return i; |
051fb70f BA |
1519 | } |
1520 | ||
4760a896 RN |
1521 | static int q6v5_pds_attach(struct device *dev, struct device **devs, |
1522 | char **pd_names) | |
1523 | { | |
1524 | size_t num_pds = 0; | |
1525 | int ret; | |
1526 | int i; | |
1527 | ||
1528 | if (!pd_names) | |
1529 | return 0; | |
1530 | ||
1531 | while (pd_names[num_pds]) | |
1532 | num_pds++; | |
1533 | ||
1534 | for (i = 0; i < num_pds; i++) { | |
1535 | devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); | |
f2583fde SS |
1536 | if (IS_ERR_OR_NULL(devs[i])) { |
1537 | ret = PTR_ERR(devs[i]) ? : -ENODATA; | |
4760a896 RN |
1538 | goto unroll_attach; |
1539 | } | |
1540 | } | |
1541 | ||
1542 | return num_pds; | |
1543 | ||
1544 | unroll_attach: | |
1545 | for (i--; i >= 0; i--) | |
1546 | dev_pm_domain_detach(devs[i], false); | |
1547 | ||
1548 | return ret; | |
58396810 | 1549 | } |
4760a896 RN |
1550 | |
1551 | static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds, | |
1552 | size_t pd_count) | |
1553 | { | |
1554 | int i; | |
1555 | ||
1556 | for (i = 0; i < pd_count; i++) | |
1557 | dev_pm_domain_detach(pds[i], false); | |
1558 | } | |
1559 | ||
051fb70f BA |
1560 | static int q6v5_init_reset(struct q6v5 *qproc) |
1561 | { | |
5acbf7e5 | 1562 | qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev, |
9e483efd | 1563 | "mss_restart"); |
051fb70f BA |
1564 | if (IS_ERR(qproc->mss_restart)) { |
1565 | dev_err(qproc->dev, "failed to acquire mss restart\n"); | |
1566 | return PTR_ERR(qproc->mss_restart); | |
1567 | } | |
1568 | ||
a9fdc79d | 1569 | if (qproc->has_alt_reset || qproc->has_spare_reg) { |
29a5f9aa SS |
1570 | qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev, |
1571 | "pdc_reset"); | |
1572 | if (IS_ERR(qproc->pdc_reset)) { | |
1573 | dev_err(qproc->dev, "failed to acquire pdc reset\n"); | |
1574 | return PTR_ERR(qproc->pdc_reset); | |
1575 | } | |
1576 | } | |
1577 | ||
051fb70f BA |
1578 | return 0; |
1579 | } | |
1580 | ||
051fb70f BA |
1581 | static int q6v5_alloc_memory_region(struct q6v5 *qproc) |
1582 | { | |
1583 | struct device_node *child; | |
1584 | struct device_node *node; | |
1585 | struct resource r; | |
1586 | int ret; | |
1587 | ||
6663ce6f SS |
1588 | /* |
1589 | * In the absence of mba/mpss sub-child, extract the mba and mpss | |
1590 | * reserved memory regions from device's memory-region property. | |
1591 | */ | |
051fb70f | 1592 | child = of_get_child_by_name(qproc->dev->of_node, "mba"); |
6663ce6f SS |
1593 | if (!child) |
1594 | node = of_parse_phandle(qproc->dev->of_node, | |
1595 | "memory-region", 0); | |
1596 | else | |
1597 | node = of_parse_phandle(child, "memory-region", 0); | |
1598 | ||
051fb70f BA |
1599 | ret = of_address_to_resource(node, 0, &r); |
1600 | if (ret) { | |
1601 | dev_err(qproc->dev, "unable to resolve mba region\n"); | |
1602 | return ret; | |
1603 | } | |
278d744c | 1604 | of_node_put(node); |
051fb70f BA |
1605 | |
1606 | qproc->mba_phys = r.start; | |
1607 | qproc->mba_size = resource_size(&r); | |
1608 | qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size); | |
1609 | if (!qproc->mba_region) { | |
1610 | dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", | |
1611 | &r.start, qproc->mba_size); | |
1612 | return -EBUSY; | |
1613 | } | |
1614 | ||
6663ce6f SS |
1615 | if (!child) { |
1616 | node = of_parse_phandle(qproc->dev->of_node, | |
1617 | "memory-region", 1); | |
1618 | } else { | |
1619 | child = of_get_child_by_name(qproc->dev->of_node, "mpss"); | |
1620 | node = of_parse_phandle(child, "memory-region", 0); | |
1621 | } | |
1622 | ||
051fb70f BA |
1623 | ret = of_address_to_resource(node, 0, &r); |
1624 | if (ret) { | |
1625 | dev_err(qproc->dev, "unable to resolve mpss region\n"); | |
1626 | return ret; | |
1627 | } | |
278d744c | 1628 | of_node_put(node); |
051fb70f BA |
1629 | |
1630 | qproc->mpss_phys = qproc->mpss_reloc = r.start; | |
1631 | qproc->mpss_size = resource_size(&r); | |
051fb70f BA |
1632 | |
1633 | return 0; | |
1634 | } | |
1635 | ||
1636 | static int q6v5_probe(struct platform_device *pdev) | |
1637 | { | |
7a8ffe1f | 1638 | const struct rproc_hexagon_res *desc; |
051fb70f BA |
1639 | struct q6v5 *qproc; |
1640 | struct rproc *rproc; | |
a5a4e02d | 1641 | const char *mba_image; |
051fb70f BA |
1642 | int ret; |
1643 | ||
7a8ffe1f AKD |
1644 | desc = of_device_get_match_data(&pdev->dev); |
1645 | if (!desc) | |
1646 | return -EINVAL; | |
1647 | ||
bbcda302 BN |
1648 | if (desc->need_mem_protection && !qcom_scm_is_available()) |
1649 | return -EPROBE_DEFER; | |
1650 | ||
a5a4e02d SS |
1651 | mba_image = desc->hexagon_mba_image; |
1652 | ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", | |
1653 | 0, &mba_image); | |
1654 | if (ret < 0 && ret != -EINVAL) | |
1655 | return ret; | |
1656 | ||
051fb70f | 1657 | rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops, |
a5a4e02d | 1658 | mba_image, sizeof(*qproc)); |
051fb70f BA |
1659 | if (!rproc) { |
1660 | dev_err(&pdev->dev, "failed to allocate rproc\n"); | |
1661 | return -ENOMEM; | |
1662 | } | |
1663 | ||
4107102d | 1664 | rproc->auto_boot = false; |
3898fc99 | 1665 | rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); |
4107102d | 1666 | |
051fb70f BA |
1667 | qproc = (struct q6v5 *)rproc->priv; |
1668 | qproc->dev = &pdev->dev; | |
1669 | qproc->rproc = rproc; | |
a5a4e02d SS |
1670 | qproc->hexagon_mdt_image = "modem.mdt"; |
1671 | ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", | |
1672 | 1, &qproc->hexagon_mdt_image); | |
1673 | if (ret < 0 && ret != -EINVAL) | |
13c060b5 | 1674 | goto free_rproc; |
a5a4e02d | 1675 | |
051fb70f BA |
1676 | platform_set_drvdata(pdev, qproc); |
1677 | ||
a9fdc79d | 1678 | qproc->has_spare_reg = desc->has_spare_reg; |
051fb70f BA |
1679 | ret = q6v5_init_mem(qproc, pdev); |
1680 | if (ret) | |
1681 | goto free_rproc; | |
1682 | ||
1683 | ret = q6v5_alloc_memory_region(qproc); | |
1684 | if (ret) | |
1685 | goto free_rproc; | |
1686 | ||
39b2410b AKD |
1687 | ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks, |
1688 | desc->proxy_clk_names); | |
1689 | if (ret < 0) { | |
1690 | dev_err(&pdev->dev, "Failed to get proxy clocks.\n"); | |
051fb70f | 1691 | goto free_rproc; |
39b2410b AKD |
1692 | } |
1693 | qproc->proxy_clk_count = ret; | |
1694 | ||
231f67d1 SS |
1695 | ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks, |
1696 | desc->reset_clk_names); | |
1697 | if (ret < 0) { | |
1698 | dev_err(&pdev->dev, "Failed to get reset clocks.\n"); | |
1699 | goto free_rproc; | |
1700 | } | |
1701 | qproc->reset_clk_count = ret; | |
1702 | ||
39b2410b AKD |
1703 | ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks, |
1704 | desc->active_clk_names); | |
1705 | if (ret < 0) { | |
1706 | dev_err(&pdev->dev, "Failed to get active clocks.\n"); | |
1707 | goto free_rproc; | |
1708 | } | |
1709 | qproc->active_clk_count = ret; | |
051fb70f | 1710 | |
19f902b5 AKD |
1711 | ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs, |
1712 | desc->proxy_supply); | |
1713 | if (ret < 0) { | |
1714 | dev_err(&pdev->dev, "Failed to get proxy regulators.\n"); | |
051fb70f | 1715 | goto free_rproc; |
19f902b5 AKD |
1716 | } |
1717 | qproc->proxy_reg_count = ret; | |
1718 | ||
1719 | ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs, | |
1720 | desc->active_supply); | |
1721 | if (ret < 0) { | |
1722 | dev_err(&pdev->dev, "Failed to get active regulators.\n"); | |
1723 | goto free_rproc; | |
1724 | } | |
1725 | qproc->active_reg_count = ret; | |
051fb70f | 1726 | |
deb9bb83 BA |
1727 | ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds, |
1728 | desc->active_pd_names); | |
1729 | if (ret < 0) { | |
1730 | dev_err(&pdev->dev, "Failed to attach active power domains\n"); | |
1731 | goto free_rproc; | |
1732 | } | |
1733 | qproc->active_pd_count = ret; | |
1734 | ||
4760a896 RN |
1735 | ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds, |
1736 | desc->proxy_pd_names); | |
8750cf39 SG |
1737 | /* Fallback to regulators for old device trees */ |
1738 | if (ret == -ENODATA && desc->fallback_proxy_supply) { | |
1739 | ret = q6v5_regulator_init(&pdev->dev, | |
1740 | qproc->fallback_proxy_regs, | |
1741 | desc->fallback_proxy_supply); | |
1742 | if (ret < 0) { | |
1743 | dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n"); | |
1744 | goto detach_active_pds; | |
1745 | } | |
1746 | qproc->fallback_proxy_reg_count = ret; | |
1747 | } else if (ret < 0) { | |
4760a896 | 1748 | dev_err(&pdev->dev, "Failed to init power domains\n"); |
deb9bb83 | 1749 | goto detach_active_pds; |
8750cf39 SG |
1750 | } else { |
1751 | qproc->proxy_pd_count = ret; | |
4760a896 | 1752 | } |
4760a896 | 1753 | |
29a5f9aa | 1754 | qproc->has_alt_reset = desc->has_alt_reset; |
051fb70f BA |
1755 | ret = q6v5_init_reset(qproc); |
1756 | if (ret) | |
4760a896 | 1757 | goto detach_proxy_pds; |
051fb70f | 1758 | |
9f058fa2 | 1759 | qproc->version = desc->version; |
6c5a9dc2 | 1760 | qproc->need_mem_protection = desc->need_mem_protection; |
318130cc | 1761 | qproc->has_mba_logs = desc->has_mba_logs; |
051fb70f | 1762 | |
7d674731 BA |
1763 | ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, |
1764 | qcom_msa_handover); | |
1765 | if (ret) | |
4760a896 | 1766 | goto detach_proxy_pds; |
051fb70f | 1767 | |
6c5a9dc2 AKD |
1768 | qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); |
1769 | qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); | |
cd9fc8f1 | 1770 | qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss"); |
4b48921a | 1771 | qcom_add_smd_subdev(rproc, &qproc->smd_subdev); |
1e140df0 | 1772 | qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss"); |
1fb82ee8 | 1773 | qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12); |
027045a6 SS |
1774 | if (IS_ERR(qproc->sysmon)) { |
1775 | ret = PTR_ERR(qproc->sysmon); | |
58396810 | 1776 | goto remove_subdevs; |
027045a6 | 1777 | } |
4b48921a | 1778 | |
051fb70f BA |
1779 | ret = rproc_add(rproc); |
1780 | if (ret) | |
58396810 | 1781 | goto remove_sysmon_subdev; |
051fb70f BA |
1782 | |
1783 | return 0; | |
1784 | ||
58396810 AE |
1785 | remove_sysmon_subdev: |
1786 | qcom_remove_sysmon_subdev(qproc->sysmon); | |
1787 | remove_subdevs: | |
58396810 AE |
1788 | qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev); |
1789 | qcom_remove_smd_subdev(rproc, &qproc->smd_subdev); | |
1790 | qcom_remove_glink_subdev(rproc, &qproc->glink_subdev); | |
1791 | detach_proxy_pds: | |
4760a896 | 1792 | q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); |
deb9bb83 BA |
1793 | detach_active_pds: |
1794 | q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); | |
051fb70f | 1795 | free_rproc: |
433c0e04 | 1796 | rproc_free(rproc); |
051fb70f BA |
1797 | |
1798 | return ret; | |
1799 | } | |
1800 | ||
1801 | static int q6v5_remove(struct platform_device *pdev) | |
1802 | { | |
1803 | struct q6v5 *qproc = platform_get_drvdata(pdev); | |
58396810 | 1804 | struct rproc *rproc = qproc->rproc; |
051fb70f | 1805 | |
58396810 | 1806 | rproc_del(rproc); |
4b48921a | 1807 | |
1fb82ee8 | 1808 | qcom_remove_sysmon_subdev(qproc->sysmon); |
58396810 AE |
1809 | qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev); |
1810 | qcom_remove_smd_subdev(rproc, &qproc->smd_subdev); | |
1811 | qcom_remove_glink_subdev(rproc, &qproc->glink_subdev); | |
4760a896 RN |
1812 | |
1813 | q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); | |
58396810 | 1814 | q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); |
4760a896 | 1815 | |
58396810 | 1816 | rproc_free(rproc); |
051fb70f BA |
1817 | |
1818 | return 0; | |
1819 | } | |
1820 | ||
6439b527 SS |
1821 | static const struct rproc_hexagon_res sc7180_mss = { |
1822 | .hexagon_mba_image = "mba.mbn", | |
1823 | .proxy_clk_names = (char*[]){ | |
1824 | "xo", | |
1825 | NULL | |
1826 | }, | |
1827 | .reset_clk_names = (char*[]){ | |
1828 | "iface", | |
1829 | "bus", | |
1830 | "snoc_axi", | |
1831 | NULL | |
1832 | }, | |
1833 | .active_clk_names = (char*[]){ | |
1834 | "mnoc_axi", | |
1835 | "nav", | |
6439b527 SS |
1836 | NULL |
1837 | }, | |
1838 | .active_pd_names = (char*[]){ | |
1839 | "load_state", | |
1840 | NULL | |
1841 | }, | |
1842 | .proxy_pd_names = (char*[]){ | |
1843 | "cx", | |
1844 | "mx", | |
1845 | "mss", | |
1846 | NULL | |
1847 | }, | |
1848 | .need_mem_protection = true, | |
1849 | .has_alt_reset = false, | |
318130cc | 1850 | .has_mba_logs = true, |
a9fdc79d | 1851 | .has_spare_reg = true, |
6439b527 SS |
1852 | .version = MSS_SC7180, |
1853 | }; | |
1854 | ||
231f67d1 SS |
1855 | static const struct rproc_hexagon_res sdm845_mss = { |
1856 | .hexagon_mba_image = "mba.mbn", | |
1857 | .proxy_clk_names = (char*[]){ | |
1858 | "xo", | |
231f67d1 SS |
1859 | "prng", |
1860 | NULL | |
1861 | }, | |
1862 | .reset_clk_names = (char*[]){ | |
1863 | "iface", | |
1864 | "snoc_axi", | |
1865 | NULL | |
1866 | }, | |
1867 | .active_clk_names = (char*[]){ | |
1868 | "bus", | |
1869 | "mem", | |
1870 | "gpll0_mss", | |
1871 | "mnoc_axi", | |
1872 | NULL | |
1873 | }, | |
deb9bb83 BA |
1874 | .active_pd_names = (char*[]){ |
1875 | "load_state", | |
1876 | NULL | |
1877 | }, | |
4760a896 RN |
1878 | .proxy_pd_names = (char*[]){ |
1879 | "cx", | |
1880 | "mx", | |
1881 | "mss", | |
1882 | NULL | |
1883 | }, | |
231f67d1 SS |
1884 | .need_mem_protection = true, |
1885 | .has_alt_reset = true, | |
318130cc | 1886 | .has_mba_logs = false, |
a9fdc79d | 1887 | .has_spare_reg = false, |
231f67d1 SS |
1888 | .version = MSS_SDM845, |
1889 | }; | |
1890 | ||
1665cbd5 JH |
1891 | static const struct rproc_hexagon_res msm8998_mss = { |
1892 | .hexagon_mba_image = "mba.mbn", | |
1893 | .proxy_clk_names = (char*[]){ | |
1894 | "xo", | |
1895 | "qdss", | |
1896 | "mem", | |
1897 | NULL | |
1898 | }, | |
1899 | .active_clk_names = (char*[]){ | |
1900 | "iface", | |
1901 | "bus", | |
1665cbd5 JH |
1902 | "gpll0_mss", |
1903 | "mnoc_axi", | |
1904 | "snoc_axi", | |
1905 | NULL | |
1906 | }, | |
1907 | .proxy_pd_names = (char*[]){ | |
1908 | "cx", | |
1909 | "mx", | |
1910 | NULL | |
1911 | }, | |
1912 | .need_mem_protection = true, | |
1913 | .has_alt_reset = false, | |
318130cc | 1914 | .has_mba_logs = false, |
a9fdc79d | 1915 | .has_spare_reg = false, |
1665cbd5 JH |
1916 | .version = MSS_MSM8998, |
1917 | }; | |
1918 | ||
9f058fa2 AKD |
1919 | static const struct rproc_hexagon_res msm8996_mss = { |
1920 | .hexagon_mba_image = "mba.mbn", | |
47b87474 SS |
1921 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
1922 | { | |
1923 | .supply = "pll", | |
1924 | .uA = 100000, | |
1925 | }, | |
1926 | {} | |
1927 | }, | |
9f058fa2 AKD |
1928 | .proxy_clk_names = (char*[]){ |
1929 | "xo", | |
1930 | "pnoc", | |
80ec419c | 1931 | "qdss", |
9f058fa2 AKD |
1932 | NULL |
1933 | }, | |
1934 | .active_clk_names = (char*[]){ | |
1935 | "iface", | |
1936 | "bus", | |
1937 | "mem", | |
80ec419c SS |
1938 | "gpll0_mss", |
1939 | "snoc_axi", | |
1940 | "mnoc_axi", | |
9f058fa2 AKD |
1941 | NULL |
1942 | }, | |
1943 | .need_mem_protection = true, | |
231f67d1 | 1944 | .has_alt_reset = false, |
318130cc | 1945 | .has_mba_logs = false, |
a9fdc79d | 1946 | .has_spare_reg = false, |
9f058fa2 AKD |
1947 | .version = MSS_MSM8996, |
1948 | }; | |
1949 | ||
7a8ffe1f AKD |
1950 | static const struct rproc_hexagon_res msm8916_mss = { |
1951 | .hexagon_mba_image = "mba.mbn", | |
19f902b5 | 1952 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
8750cf39 SG |
1953 | { |
1954 | .supply = "pll", | |
1955 | .uA = 100000, | |
1956 | }, | |
1957 | {} | |
1958 | }, | |
1959 | .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { | |
19f902b5 AKD |
1960 | { |
1961 | .supply = "mx", | |
1962 | .uV = 1050000, | |
1963 | }, | |
1964 | { | |
1965 | .supply = "cx", | |
1966 | .uA = 100000, | |
1967 | }, | |
19f902b5 AKD |
1968 | {} |
1969 | }, | |
39b2410b AKD |
1970 | .proxy_clk_names = (char*[]){ |
1971 | "xo", | |
1972 | NULL | |
1973 | }, | |
1974 | .active_clk_names = (char*[]){ | |
1975 | "iface", | |
1976 | "bus", | |
1977 | "mem", | |
1978 | NULL | |
1979 | }, | |
8750cf39 SG |
1980 | .proxy_pd_names = (char*[]){ |
1981 | "mx", | |
1982 | "cx", | |
1983 | NULL | |
1984 | }, | |
6c5a9dc2 | 1985 | .need_mem_protection = false, |
231f67d1 | 1986 | .has_alt_reset = false, |
318130cc | 1987 | .has_mba_logs = false, |
a9fdc79d | 1988 | .has_spare_reg = false, |
9f058fa2 | 1989 | .version = MSS_MSM8916, |
7a8ffe1f AKD |
1990 | }; |
1991 | ||
1992 | static const struct rproc_hexagon_res msm8974_mss = { | |
1993 | .hexagon_mba_image = "mba.b00", | |
19f902b5 | 1994 | .proxy_supply = (struct qcom_mss_reg_res[]) { |
8750cf39 SG |
1995 | { |
1996 | .supply = "pll", | |
1997 | .uA = 100000, | |
1998 | }, | |
1999 | {} | |
2000 | }, | |
2001 | .fallback_proxy_supply = (struct qcom_mss_reg_res[]) { | |
19f902b5 AKD |
2002 | { |
2003 | .supply = "mx", | |
2004 | .uV = 1050000, | |
2005 | }, | |
2006 | { | |
2007 | .supply = "cx", | |
2008 | .uA = 100000, | |
2009 | }, | |
19f902b5 AKD |
2010 | {} |
2011 | }, | |
2012 | .active_supply = (struct qcom_mss_reg_res[]) { | |
2013 | { | |
2014 | .supply = "mss", | |
2015 | .uV = 1050000, | |
2016 | .uA = 100000, | |
2017 | }, | |
2018 | {} | |
2019 | }, | |
39b2410b AKD |
2020 | .proxy_clk_names = (char*[]){ |
2021 | "xo", | |
2022 | NULL | |
2023 | }, | |
2024 | .active_clk_names = (char*[]){ | |
2025 | "iface", | |
2026 | "bus", | |
2027 | "mem", | |
2028 | NULL | |
2029 | }, | |
8750cf39 SG |
2030 | .proxy_pd_names = (char*[]){ |
2031 | "mx", | |
2032 | "cx", | |
2033 | NULL | |
2034 | }, | |
6c5a9dc2 | 2035 | .need_mem_protection = false, |
231f67d1 | 2036 | .has_alt_reset = false, |
318130cc | 2037 | .has_mba_logs = false, |
a9fdc79d | 2038 | .has_spare_reg = false, |
9f058fa2 | 2039 | .version = MSS_MSM8974, |
7a8ffe1f AKD |
2040 | }; |
2041 | ||
051fb70f | 2042 | static const struct of_device_id q6v5_of_match[] = { |
7a8ffe1f AKD |
2043 | { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, |
2044 | { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, | |
2045 | { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, | |
9f058fa2 | 2046 | { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, |
1665cbd5 | 2047 | { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss}, |
6439b527 | 2048 | { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss}, |
231f67d1 | 2049 | { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss}, |
051fb70f BA |
2050 | { }, |
2051 | }; | |
3227c876 | 2052 | MODULE_DEVICE_TABLE(of, q6v5_of_match); |
051fb70f BA |
2053 | |
2054 | static struct platform_driver q6v5_driver = { | |
2055 | .probe = q6v5_probe, | |
2056 | .remove = q6v5_remove, | |
2057 | .driver = { | |
ef73c22f | 2058 | .name = "qcom-q6v5-mss", |
051fb70f BA |
2059 | .of_match_table = q6v5_of_match, |
2060 | }, | |
2061 | }; | |
2062 | module_platform_driver(q6v5_driver); | |
2063 | ||
ef73c22f | 2064 | MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver"); |
051fb70f | 2065 | MODULE_LICENSE("GPL v2"); |