Commit | Line | Data |
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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
34ed5a33 OBC |
2 | /* |
3 | * OMAP Remote Processor driver | |
4 | * | |
75242927 | 5 | * Copyright (C) 2011-2020 Texas Instruments Incorporated - http://www.ti.com/ |
34ed5a33 OBC |
6 | * Copyright (C) 2011 Google, Inc. |
7 | * | |
8 | * Ohad Ben-Cohen <ohad@wizery.com> | |
9 | * Brian Swetland <swetland@google.com> | |
10 | * Fernando Guzman Lugo <fernando.lugo@ti.com> | |
11 | * Mark Grosen <mgrosen@ti.com> | |
12 | * Suman Anna <s-anna@ti.com> | |
13 | * Hari Kanigeri <h-kanigeri2@ti.com> | |
34ed5a33 OBC |
14 | */ |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
9077ac1a SA |
18 | #include <linux/clk.h> |
19 | #include <linux/clk/ti.h> | |
34ed5a33 | 20 | #include <linux/err.h> |
9077ac1a | 21 | #include <linux/io.h> |
3440d8da RH |
22 | #include <linux/of.h> |
23 | #include <linux/of_platform.h> | |
f4af5bd2 | 24 | #include <linux/of_reserved_mem.h> |
34ed5a33 | 25 | #include <linux/platform_device.h> |
5f31b232 | 26 | #include <linux/pm_runtime.h> |
34ed5a33 | 27 | #include <linux/dma-mapping.h> |
69591e4a | 28 | #include <linux/interrupt.h> |
34ed5a33 | 29 | #include <linux/remoteproc.h> |
8841a66a | 30 | #include <linux/mailbox_client.h> |
9077ac1a | 31 | #include <linux/omap-iommu.h> |
c869c75c | 32 | #include <linux/omap-mailbox.h> |
75242927 SA |
33 | #include <linux/regmap.h> |
34 | #include <linux/mfd/syscon.h> | |
35 | #include <linux/reset.h> | |
e28edc57 SA |
36 | #include <clocksource/timer-ti-dm.h> |
37 | ||
38 | #include <linux/platform_data/dmtimer-omap.h> | |
34ed5a33 OBC |
39 | |
40 | #include "omap_remoteproc.h" | |
41 | #include "remoteproc_internal.h" | |
42 | ||
5f31b232 SA |
43 | /* default auto-suspend delay (ms) */ |
44 | #define DEFAULT_AUTOSUSPEND_DELAY 10000 | |
45 | ||
75242927 SA |
46 | /** |
47 | * struct omap_rproc_boot_data - boot data structure for the DSP omap rprocs | |
48 | * @syscon: regmap handle for the system control configuration module | |
49 | * @boot_reg: boot register offset within the @syscon regmap | |
0aaf1913 SA |
50 | * @boot_reg_shift: bit-field shift required for the boot address value in |
51 | * @boot_reg | |
75242927 SA |
52 | */ |
53 | struct omap_rproc_boot_data { | |
54 | struct regmap *syscon; | |
55 | unsigned int boot_reg; | |
0aaf1913 | 56 | unsigned int boot_reg_shift; |
75242927 SA |
57 | }; |
58 | ||
4a032199 SA |
59 | /** |
60 | * struct omap_rproc_mem - internal memory structure | |
61 | * @cpu_addr: MPU virtual address of the memory region | |
62 | * @bus_addr: bus address used to access the memory region | |
63 | * @dev_addr: device address of the memory region from DSP view | |
64 | * @size: size of the memory region | |
65 | */ | |
66 | struct omap_rproc_mem { | |
67 | void __iomem *cpu_addr; | |
68 | phys_addr_t bus_addr; | |
69 | u32 dev_addr; | |
70 | size_t size; | |
71 | }; | |
72 | ||
e28edc57 SA |
73 | /** |
74 | * struct omap_rproc_timer - data structure for a timer used by a omap rproc | |
75 | * @odt: timer pointer | |
76 | * @timer_ops: OMAP dmtimer ops for @odt timer | |
69591e4a | 77 | * @irq: timer irq |
e28edc57 SA |
78 | */ |
79 | struct omap_rproc_timer { | |
80 | struct omap_dm_timer *odt; | |
81 | const struct omap_dm_timer_ops *timer_ops; | |
69591e4a | 82 | int irq; |
e28edc57 SA |
83 | }; |
84 | ||
34ed5a33 OBC |
85 | /** |
86 | * struct omap_rproc - omap remote processor state | |
8841a66a SA |
87 | * @mbox: mailbox channel handle |
88 | * @client: mailbox client to request the mailbox channel | |
75242927 | 89 | * @boot_data: boot data structure for setting processor boot address |
4a032199 SA |
90 | * @mem: internal memory regions data |
91 | * @num_mems: number of internal memory regions | |
e28edc57 | 92 | * @num_timers: number of rproc timer(s) |
69591e4a | 93 | * @num_wd_timers: number of rproc watchdog timers |
e28edc57 | 94 | * @timers: timer(s) info used by rproc |
5f31b232 SA |
95 | * @autosuspend_delay: auto-suspend delay value to be used for runtime pm |
96 | * @need_resume: if true a resume is needed in the system resume callback | |
34ed5a33 | 97 | * @rproc: rproc handle |
75242927 | 98 | * @reset: reset handle |
9077ac1a SA |
99 | * @pm_comp: completion primitive to sync for suspend response |
100 | * @fck: functional clock for the remoteproc | |
101 | * @suspend_acked: state machine flag to store the suspend request ack | |
34ed5a33 OBC |
102 | */ |
103 | struct omap_rproc { | |
8841a66a SA |
104 | struct mbox_chan *mbox; |
105 | struct mbox_client client; | |
75242927 | 106 | struct omap_rproc_boot_data *boot_data; |
4a032199 SA |
107 | struct omap_rproc_mem *mem; |
108 | int num_mems; | |
e28edc57 | 109 | int num_timers; |
69591e4a | 110 | int num_wd_timers; |
e28edc57 | 111 | struct omap_rproc_timer *timers; |
5f31b232 SA |
112 | int autosuspend_delay; |
113 | bool need_resume; | |
34ed5a33 | 114 | struct rproc *rproc; |
75242927 | 115 | struct reset_control *reset; |
9077ac1a SA |
116 | struct completion pm_comp; |
117 | struct clk *fck; | |
118 | bool suspend_acked; | |
75242927 SA |
119 | }; |
120 | ||
4a032199 SA |
121 | /** |
122 | * struct omap_rproc_mem_data - memory definitions for an omap remote processor | |
123 | * @name: name for this memory entry | |
124 | * @dev_addr: device address for the memory entry | |
125 | */ | |
126 | struct omap_rproc_mem_data { | |
127 | const char *name; | |
128 | const u32 dev_addr; | |
129 | }; | |
130 | ||
75242927 SA |
131 | /** |
132 | * struct omap_rproc_dev_data - device data for the omap remote processor | |
133 | * @device_name: device name of the remote processor | |
4a032199 | 134 | * @mems: memory definitions for this remote processor |
75242927 SA |
135 | */ |
136 | struct omap_rproc_dev_data { | |
137 | const char *device_name; | |
4a032199 | 138 | const struct omap_rproc_mem_data *mems; |
34ed5a33 OBC |
139 | }; |
140 | ||
e28edc57 SA |
141 | /** |
142 | * omap_rproc_request_timer() - request a timer for a remoteproc | |
143 | * @dev: device requesting the timer | |
144 | * @np: device node pointer to the desired timer | |
145 | * @timer: handle to a struct omap_rproc_timer to return the timer handle | |
146 | * | |
147 | * This helper function is used primarily to request a timer associated with | |
148 | * a remoteproc. The returned handle is stored in the .odt field of the | |
149 | * @timer structure passed in, and is used to invoke other timer specific | |
150 | * ops (like starting a timer either during device initialization or during | |
151 | * a resume operation, or for stopping/freeing a timer). | |
152 | * | |
153 | * Return: 0 on success, otherwise an appropriate failure | |
154 | */ | |
155 | static int omap_rproc_request_timer(struct device *dev, struct device_node *np, | |
156 | struct omap_rproc_timer *timer) | |
157 | { | |
158 | int ret; | |
159 | ||
160 | timer->odt = timer->timer_ops->request_by_node(np); | |
161 | if (!timer->odt) { | |
162 | dev_err(dev, "request for timer node %p failed\n", np); | |
163 | return -EBUSY; | |
164 | } | |
165 | ||
166 | ret = timer->timer_ops->set_source(timer->odt, OMAP_TIMER_SRC_SYS_CLK); | |
167 | if (ret) { | |
168 | dev_err(dev, "error setting OMAP_TIMER_SRC_SYS_CLK as source for timer node %p\n", | |
169 | np); | |
170 | timer->timer_ops->free(timer->odt); | |
171 | return ret; | |
172 | } | |
173 | ||
174 | /* clean counter, remoteproc code will set the value */ | |
e6d05acd | 175 | timer->timer_ops->set_load(timer->odt, 0); |
e28edc57 SA |
176 | |
177 | return 0; | |
178 | } | |
179 | ||
180 | /** | |
181 | * omap_rproc_start_timer() - start a timer for a remoteproc | |
182 | * @timer: handle to a OMAP rproc timer | |
183 | * | |
184 | * This helper function is used to start a timer associated with a remoteproc, | |
185 | * obtained using the request_timer ops. The helper function needs to be | |
186 | * invoked by the driver to start the timer (during device initialization) | |
187 | * or to just resume the timer. | |
188 | * | |
189 | * Return: 0 on success, otherwise a failure as returned by DMTimer ops | |
190 | */ | |
191 | static inline int omap_rproc_start_timer(struct omap_rproc_timer *timer) | |
192 | { | |
193 | return timer->timer_ops->start(timer->odt); | |
194 | } | |
195 | ||
196 | /** | |
197 | * omap_rproc_stop_timer() - stop a timer for a remoteproc | |
198 | * @timer: handle to a OMAP rproc timer | |
199 | * | |
200 | * This helper function is used to disable a timer associated with a | |
201 | * remoteproc, and needs to be called either during a device shutdown | |
202 | * or suspend operation. The separate helper function allows the driver | |
203 | * to just stop a timer without having to release the timer during a | |
204 | * suspend operation. | |
205 | * | |
206 | * Return: 0 on success, otherwise a failure as returned by DMTimer ops | |
207 | */ | |
208 | static inline int omap_rproc_stop_timer(struct omap_rproc_timer *timer) | |
209 | { | |
210 | return timer->timer_ops->stop(timer->odt); | |
211 | } | |
212 | ||
213 | /** | |
214 | * omap_rproc_release_timer() - release a timer for a remoteproc | |
215 | * @timer: handle to a OMAP rproc timer | |
216 | * | |
217 | * This helper function is used primarily to release a timer associated | |
218 | * with a remoteproc. The dmtimer will be available for other clients to | |
219 | * use once released. | |
220 | * | |
221 | * Return: 0 on success, otherwise a failure as returned by DMTimer ops | |
222 | */ | |
223 | static inline int omap_rproc_release_timer(struct omap_rproc_timer *timer) | |
224 | { | |
225 | return timer->timer_ops->free(timer->odt); | |
226 | } | |
227 | ||
69591e4a SA |
228 | /** |
229 | * omap_rproc_get_timer_irq() - get the irq for a timer | |
230 | * @timer: handle to a OMAP rproc timer | |
231 | * | |
232 | * This function is used to get the irq associated with a watchdog timer. The | |
233 | * function is called by the OMAP remoteproc driver to register a interrupt | |
234 | * handler to handle watchdog events on the remote processor. | |
235 | * | |
236 | * Return: irq id on success, otherwise a failure as returned by DMTimer ops | |
237 | */ | |
238 | static inline int omap_rproc_get_timer_irq(struct omap_rproc_timer *timer) | |
239 | { | |
240 | return timer->timer_ops->get_irq(timer->odt); | |
241 | } | |
242 | ||
243 | /** | |
244 | * omap_rproc_ack_timer_irq() - acknowledge a timer irq | |
245 | * @timer: handle to a OMAP rproc timer | |
246 | * | |
2d1ea19f | 247 | * This function is used to clear the irq associated with a watchdog timer. |
69591e4a SA |
248 | * The function is called by the OMAP remoteproc upon a watchdog event on the |
249 | * remote processor to clear the interrupt status of the watchdog timer. | |
250 | */ | |
251 | static inline void omap_rproc_ack_timer_irq(struct omap_rproc_timer *timer) | |
252 | { | |
253 | timer->timer_ops->write_status(timer->odt, OMAP_TIMER_INT_OVERFLOW); | |
254 | } | |
255 | ||
256 | /** | |
257 | * omap_rproc_watchdog_isr() - Watchdog ISR handler for remoteproc device | |
258 | * @irq: IRQ number associated with a watchdog timer | |
259 | * @data: IRQ handler data | |
260 | * | |
261 | * This ISR routine executes the required necessary low-level code to | |
262 | * acknowledge a watchdog timer interrupt. There can be multiple watchdog | |
263 | * timers associated with a rproc (like IPUs which have 2 watchdog timers, | |
264 | * one per Cortex M3/M4 core), so a lookup has to be performed to identify | |
265 | * the timer to acknowledge its interrupt. | |
266 | * | |
267 | * The function also invokes rproc_report_crash to report the watchdog event | |
268 | * to the remoteproc driver core, to trigger a recovery. | |
269 | * | |
270 | * Return: IRQ_HANDLED on success, otherwise IRQ_NONE | |
271 | */ | |
272 | static irqreturn_t omap_rproc_watchdog_isr(int irq, void *data) | |
273 | { | |
274 | struct rproc *rproc = data; | |
275 | struct omap_rproc *oproc = rproc->priv; | |
276 | struct device *dev = rproc->dev.parent; | |
277 | struct omap_rproc_timer *timers = oproc->timers; | |
278 | struct omap_rproc_timer *wd_timer = NULL; | |
279 | int num_timers = oproc->num_timers + oproc->num_wd_timers; | |
280 | int i; | |
281 | ||
282 | for (i = oproc->num_timers; i < num_timers; i++) { | |
283 | if (timers[i].irq > 0 && irq == timers[i].irq) { | |
284 | wd_timer = &timers[i]; | |
285 | break; | |
286 | } | |
287 | } | |
288 | ||
289 | if (!wd_timer) { | |
290 | dev_err(dev, "invalid timer\n"); | |
291 | return IRQ_NONE; | |
292 | } | |
293 | ||
294 | omap_rproc_ack_timer_irq(wd_timer); | |
295 | ||
296 | rproc_report_crash(rproc, RPROC_WATCHDOG); | |
297 | ||
298 | return IRQ_HANDLED; | |
299 | } | |
300 | ||
e28edc57 SA |
301 | /** |
302 | * omap_rproc_enable_timers() - enable the timers for a remoteproc | |
303 | * @rproc: handle of a remote processor | |
304 | * @configure: boolean flag used to acquire and configure the timer handle | |
305 | * | |
306 | * This function is used primarily to enable the timers associated with | |
2d1ea19f | 307 | * a remoteproc. The configure flag is provided to allow the driver |
e28edc57 SA |
308 | * to either acquire and start a timer (during device initialization) or |
309 | * to just start a timer (during a resume operation). | |
310 | * | |
311 | * Return: 0 on success, otherwise an appropriate failure | |
312 | */ | |
313 | static int omap_rproc_enable_timers(struct rproc *rproc, bool configure) | |
314 | { | |
315 | int i; | |
316 | int ret = 0; | |
317 | struct platform_device *tpdev; | |
318 | struct dmtimer_platform_data *tpdata; | |
319 | const struct omap_dm_timer_ops *timer_ops; | |
320 | struct omap_rproc *oproc = rproc->priv; | |
321 | struct omap_rproc_timer *timers = oproc->timers; | |
322 | struct device *dev = rproc->dev.parent; | |
323 | struct device_node *np = NULL; | |
69591e4a | 324 | int num_timers = oproc->num_timers + oproc->num_wd_timers; |
e28edc57 | 325 | |
69591e4a | 326 | if (!num_timers) |
e28edc57 SA |
327 | return 0; |
328 | ||
329 | if (!configure) | |
330 | goto start_timers; | |
331 | ||
69591e4a SA |
332 | for (i = 0; i < num_timers; i++) { |
333 | if (i < oproc->num_timers) | |
334 | np = of_parse_phandle(dev->of_node, "ti,timers", i); | |
335 | else | |
336 | np = of_parse_phandle(dev->of_node, | |
337 | "ti,watchdog-timers", | |
338 | (i - oproc->num_timers)); | |
e28edc57 SA |
339 | if (!np) { |
340 | ret = -ENXIO; | |
341 | dev_err(dev, "device node lookup for timer at index %d failed: %d\n", | |
69591e4a SA |
342 | i < oproc->num_timers ? i : |
343 | i - oproc->num_timers, ret); | |
e28edc57 SA |
344 | goto free_timers; |
345 | } | |
346 | ||
347 | tpdev = of_find_device_by_node(np); | |
348 | if (!tpdev) { | |
349 | ret = -ENODEV; | |
350 | dev_err(dev, "could not get timer platform device\n"); | |
351 | goto put_node; | |
352 | } | |
353 | ||
354 | tpdata = dev_get_platdata(&tpdev->dev); | |
355 | put_device(&tpdev->dev); | |
356 | if (!tpdata) { | |
357 | ret = -EINVAL; | |
358 | dev_err(dev, "dmtimer pdata structure NULL\n"); | |
359 | goto put_node; | |
360 | } | |
361 | ||
362 | timer_ops = tpdata->timer_ops; | |
363 | if (!timer_ops || !timer_ops->request_by_node || | |
364 | !timer_ops->set_source || !timer_ops->set_load || | |
365 | !timer_ops->free || !timer_ops->start || | |
69591e4a SA |
366 | !timer_ops->stop || !timer_ops->get_irq || |
367 | !timer_ops->write_status) { | |
e28edc57 SA |
368 | ret = -EINVAL; |
369 | dev_err(dev, "device does not have required timer ops\n"); | |
370 | goto put_node; | |
371 | } | |
372 | ||
69591e4a | 373 | timers[i].irq = -1; |
e28edc57 SA |
374 | timers[i].timer_ops = timer_ops; |
375 | ret = omap_rproc_request_timer(dev, np, &timers[i]); | |
376 | if (ret) { | |
377 | dev_err(dev, "request for timer %p failed: %d\n", np, | |
378 | ret); | |
379 | goto put_node; | |
380 | } | |
381 | of_node_put(np); | |
69591e4a SA |
382 | |
383 | if (i >= oproc->num_timers) { | |
384 | timers[i].irq = omap_rproc_get_timer_irq(&timers[i]); | |
385 | if (timers[i].irq < 0) { | |
386 | dev_err(dev, "get_irq for timer %p failed: %d\n", | |
387 | np, timers[i].irq); | |
388 | ret = -EBUSY; | |
389 | goto free_timers; | |
390 | } | |
391 | ||
392 | ret = request_irq(timers[i].irq, | |
393 | omap_rproc_watchdog_isr, IRQF_SHARED, | |
394 | "rproc-wdt", rproc); | |
395 | if (ret) { | |
396 | dev_err(dev, "error requesting irq for timer %p\n", | |
397 | np); | |
398 | omap_rproc_release_timer(&timers[i]); | |
399 | timers[i].odt = NULL; | |
400 | timers[i].timer_ops = NULL; | |
401 | timers[i].irq = -1; | |
402 | goto free_timers; | |
403 | } | |
404 | } | |
e28edc57 SA |
405 | } |
406 | ||
407 | start_timers: | |
69591e4a | 408 | for (i = 0; i < num_timers; i++) { |
e28edc57 SA |
409 | ret = omap_rproc_start_timer(&timers[i]); |
410 | if (ret) { | |
411 | dev_err(dev, "start timer %p failed failed: %d\n", np, | |
412 | ret); | |
413 | break; | |
414 | } | |
415 | } | |
416 | if (ret) { | |
417 | while (i >= 0) { | |
418 | omap_rproc_stop_timer(&timers[i]); | |
419 | i--; | |
420 | } | |
421 | goto put_node; | |
422 | } | |
423 | return 0; | |
424 | ||
425 | put_node: | |
426 | if (configure) | |
427 | of_node_put(np); | |
428 | free_timers: | |
429 | while (i--) { | |
69591e4a SA |
430 | if (i >= oproc->num_timers) |
431 | free_irq(timers[i].irq, rproc); | |
e28edc57 SA |
432 | omap_rproc_release_timer(&timers[i]); |
433 | timers[i].odt = NULL; | |
434 | timers[i].timer_ops = NULL; | |
69591e4a | 435 | timers[i].irq = -1; |
e28edc57 SA |
436 | } |
437 | ||
438 | return ret; | |
439 | } | |
440 | ||
441 | /** | |
442 | * omap_rproc_disable_timers() - disable the timers for a remoteproc | |
443 | * @rproc: handle of a remote processor | |
444 | * @configure: boolean flag used to release the timer handle | |
445 | * | |
446 | * This function is used primarily to disable the timers associated with | |
2d1ea19f | 447 | * a remoteproc. The configure flag is provided to allow the driver |
e28edc57 SA |
448 | * to either stop and release a timer (during device shutdown) or to just |
449 | * stop a timer (during a suspend operation). | |
450 | * | |
451 | * Return: 0 on success or no timers | |
452 | */ | |
453 | static int omap_rproc_disable_timers(struct rproc *rproc, bool configure) | |
454 | { | |
455 | int i; | |
456 | struct omap_rproc *oproc = rproc->priv; | |
457 | struct omap_rproc_timer *timers = oproc->timers; | |
69591e4a | 458 | int num_timers = oproc->num_timers + oproc->num_wd_timers; |
e28edc57 | 459 | |
69591e4a | 460 | if (!num_timers) |
e28edc57 SA |
461 | return 0; |
462 | ||
69591e4a | 463 | for (i = 0; i < num_timers; i++) { |
e28edc57 SA |
464 | omap_rproc_stop_timer(&timers[i]); |
465 | if (configure) { | |
69591e4a SA |
466 | if (i >= oproc->num_timers) |
467 | free_irq(timers[i].irq, rproc); | |
e28edc57 SA |
468 | omap_rproc_release_timer(&timers[i]); |
469 | timers[i].odt = NULL; | |
470 | timers[i].timer_ops = NULL; | |
69591e4a | 471 | timers[i].irq = -1; |
e28edc57 SA |
472 | } |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
34ed5a33 OBC |
478 | /** |
479 | * omap_rproc_mbox_callback() - inbound mailbox message handler | |
8841a66a | 480 | * @client: mailbox client pointer used for requesting the mailbox channel |
34ed5a33 OBC |
481 | * @data: mailbox payload |
482 | * | |
483 | * This handler is invoked by omap's mailbox driver whenever a mailbox | |
484 | * message is received. Usually, the mailbox payload simply contains | |
485 | * the index of the virtqueue that is kicked by the remote processor, | |
486 | * and we let remoteproc core handle it. | |
487 | * | |
488 | * In addition to virtqueue indices, we also have some out-of-band values | |
489 | * that indicates different events. Those values are deliberately very | |
490 | * big so they don't coincide with virtqueue indices. | |
491 | */ | |
8841a66a | 492 | static void omap_rproc_mbox_callback(struct mbox_client *client, void *data) |
34ed5a33 | 493 | { |
8841a66a SA |
494 | struct omap_rproc *oproc = container_of(client, struct omap_rproc, |
495 | client); | |
b5ab5e24 | 496 | struct device *dev = oproc->rproc->dev.parent; |
34ed5a33 | 497 | const char *name = oproc->rproc->name; |
8841a66a | 498 | u32 msg = (u32)data; |
34ed5a33 OBC |
499 | |
500 | dev_dbg(dev, "mbox msg: 0x%x\n", msg); | |
501 | ||
502 | switch (msg) { | |
503 | case RP_MBOX_CRASH: | |
232ba6ca SA |
504 | /* |
505 | * remoteproc detected an exception, notify the rproc core. | |
506 | * The remoteproc core will handle the recovery. | |
507 | */ | |
34ed5a33 | 508 | dev_err(dev, "omap rproc %s crashed\n", name); |
232ba6ca | 509 | rproc_report_crash(oproc->rproc, RPROC_FATAL_ERROR); |
34ed5a33 OBC |
510 | break; |
511 | case RP_MBOX_ECHO_REPLY: | |
512 | dev_info(dev, "received echo reply from %s\n", name); | |
513 | break; | |
9077ac1a | 514 | case RP_MBOX_SUSPEND_ACK: |
9077ac1a SA |
515 | case RP_MBOX_SUSPEND_CANCEL: |
516 | oproc->suspend_acked = msg == RP_MBOX_SUSPEND_ACK; | |
517 | complete(&oproc->pm_comp); | |
518 | break; | |
34ed5a33 | 519 | default: |
8135d1d2 SA |
520 | if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG) |
521 | return; | |
522 | if (msg > oproc->rproc->max_notifyid) { | |
523 | dev_dbg(dev, "dropping unknown message 0x%x", msg); | |
524 | return; | |
525 | } | |
55f34080 | 526 | /* msg contains the index of the triggered vring */ |
34ed5a33 OBC |
527 | if (rproc_vq_interrupt(oproc->rproc, msg) == IRQ_NONE) |
528 | dev_dbg(dev, "no message was found in vqid %d\n", msg); | |
529 | } | |
34ed5a33 OBC |
530 | } |
531 | ||
532 | /* kick a virtqueue */ | |
533 | static void omap_rproc_kick(struct rproc *rproc, int vqid) | |
534 | { | |
535 | struct omap_rproc *oproc = rproc->priv; | |
b5ab5e24 | 536 | struct device *dev = rproc->dev.parent; |
34ed5a33 OBC |
537 | int ret; |
538 | ||
5f31b232 SA |
539 | /* wake up the rproc before kicking it */ |
540 | ret = pm_runtime_get_sync(dev); | |
541 | if (WARN_ON(ret < 0)) { | |
542 | dev_err(dev, "pm_runtime_get_sync() failed during kick, ret = %d\n", | |
543 | ret); | |
544 | pm_runtime_put_noidle(dev); | |
545 | return; | |
546 | } | |
547 | ||
34ed5a33 | 548 | /* send the index of the triggered virtqueue in the mailbox payload */ |
8841a66a SA |
549 | ret = mbox_send_message(oproc->mbox, (void *)vqid); |
550 | if (ret < 0) | |
14096c13 AS |
551 | dev_err(dev, "failed to send mailbox message, status = %d\n", |
552 | ret); | |
5f31b232 SA |
553 | |
554 | pm_runtime_mark_last_busy(dev); | |
555 | pm_runtime_put_autosuspend(dev); | |
34ed5a33 OBC |
556 | } |
557 | ||
75242927 SA |
558 | /** |
559 | * omap_rproc_write_dsp_boot_addr() - set boot address for DSP remote processor | |
560 | * @rproc: handle of a remote processor | |
561 | * | |
562 | * Set boot address for a supported DSP remote processor. | |
feae0300 SA |
563 | * |
564 | * Return: 0 on success, or -EINVAL if boot address is not aligned properly | |
75242927 | 565 | */ |
feae0300 | 566 | static int omap_rproc_write_dsp_boot_addr(struct rproc *rproc) |
75242927 | 567 | { |
feae0300 | 568 | struct device *dev = rproc->dev.parent; |
75242927 SA |
569 | struct omap_rproc *oproc = rproc->priv; |
570 | struct omap_rproc_boot_data *bdata = oproc->boot_data; | |
571 | u32 offset = bdata->boot_reg; | |
0aaf1913 SA |
572 | u32 value; |
573 | u32 mask; | |
75242927 | 574 | |
feae0300 SA |
575 | if (rproc->bootaddr & (SZ_1K - 1)) { |
576 | dev_err(dev, "invalid boot address 0x%llx, must be aligned on a 1KB boundary\n", | |
577 | rproc->bootaddr); | |
578 | return -EINVAL; | |
579 | } | |
580 | ||
0aaf1913 SA |
581 | value = rproc->bootaddr >> bdata->boot_reg_shift; |
582 | mask = ~(SZ_1K - 1) >> bdata->boot_reg_shift; | |
583 | ||
584 | return regmap_update_bits(bdata->syscon, offset, mask, value); | |
75242927 SA |
585 | } |
586 | ||
34ed5a33 OBC |
587 | /* |
588 | * Power up the remote processor. | |
589 | * | |
590 | * This function will be invoked only after the firmware for this rproc | |
591 | * was loaded, parsed successfully, and all of its resource requirements | |
592 | * were met. | |
593 | */ | |
594 | static int omap_rproc_start(struct rproc *rproc) | |
595 | { | |
596 | struct omap_rproc *oproc = rproc->priv; | |
b5ab5e24 | 597 | struct device *dev = rproc->dev.parent; |
34ed5a33 | 598 | int ret; |
8841a66a | 599 | struct mbox_client *client = &oproc->client; |
34ed5a33 | 600 | |
feae0300 SA |
601 | if (oproc->boot_data) { |
602 | ret = omap_rproc_write_dsp_boot_addr(rproc); | |
603 | if (ret) | |
604 | return ret; | |
605 | } | |
4980f465 | 606 | |
8841a66a SA |
607 | client->dev = dev; |
608 | client->tx_done = NULL; | |
609 | client->rx_callback = omap_rproc_mbox_callback; | |
610 | client->tx_block = false; | |
611 | client->knows_txdone = false; | |
34ed5a33 | 612 | |
75242927 | 613 | oproc->mbox = mbox_request_channel(client, 0); |
34ed5a33 | 614 | if (IS_ERR(oproc->mbox)) { |
8841a66a SA |
615 | ret = -EBUSY; |
616 | dev_err(dev, "mbox_request_channel failed: %ld\n", | |
617 | PTR_ERR(oproc->mbox)); | |
34ed5a33 OBC |
618 | return ret; |
619 | } | |
620 | ||
621 | /* | |
622 | * Ping the remote processor. this is only for sanity-sake; | |
623 | * there is no functional effect whatsoever. | |
624 | * | |
625 | * Note that the reply will _not_ arrive immediately: this message | |
626 | * will wait in the mailbox fifo until the remote processor is booted. | |
627 | */ | |
8841a66a SA |
628 | ret = mbox_send_message(oproc->mbox, (void *)RP_MBOX_ECHO_REQUEST); |
629 | if (ret < 0) { | |
630 | dev_err(dev, "mbox_send_message failed: %d\n", ret); | |
34ed5a33 OBC |
631 | goto put_mbox; |
632 | } | |
633 | ||
e28edc57 SA |
634 | ret = omap_rproc_enable_timers(rproc, true); |
635 | if (ret) { | |
636 | dev_err(dev, "omap_rproc_enable_timers failed: %d\n", ret); | |
637 | goto put_mbox; | |
638 | } | |
639 | ||
75242927 | 640 | ret = reset_control_deassert(oproc->reset); |
34ed5a33 | 641 | if (ret) { |
75242927 | 642 | dev_err(dev, "reset control deassert failed: %d\n", ret); |
e28edc57 | 643 | goto disable_timers; |
34ed5a33 OBC |
644 | } |
645 | ||
5f31b232 SA |
646 | /* |
647 | * remote processor is up, so update the runtime pm status and | |
648 | * enable the auto-suspend. The device usage count is incremented | |
649 | * manually for balancing it for auto-suspend | |
650 | */ | |
651 | pm_runtime_set_active(dev); | |
652 | pm_runtime_use_autosuspend(dev); | |
653 | pm_runtime_get_noresume(dev); | |
654 | pm_runtime_enable(dev); | |
655 | pm_runtime_mark_last_busy(dev); | |
656 | pm_runtime_put_autosuspend(dev); | |
657 | ||
34ed5a33 OBC |
658 | return 0; |
659 | ||
e28edc57 SA |
660 | disable_timers: |
661 | omap_rproc_disable_timers(rproc, true); | |
34ed5a33 | 662 | put_mbox: |
8841a66a | 663 | mbox_free_channel(oproc->mbox); |
34ed5a33 OBC |
664 | return ret; |
665 | } | |
666 | ||
667 | /* power off the remote processor */ | |
668 | static int omap_rproc_stop(struct rproc *rproc) | |
669 | { | |
5f31b232 | 670 | struct device *dev = rproc->dev.parent; |
34ed5a33 OBC |
671 | struct omap_rproc *oproc = rproc->priv; |
672 | int ret; | |
673 | ||
5f31b232 SA |
674 | /* |
675 | * cancel any possible scheduled runtime suspend by incrementing | |
676 | * the device usage count, and resuming the device. The remoteproc | |
677 | * also needs to be woken up if suspended, to avoid the remoteproc | |
678 | * OS to continue to remember any context that it has saved, and | |
679 | * avoid potential issues in misindentifying a subsequent device | |
680 | * reboot as a power restore boot | |
681 | */ | |
682 | ret = pm_runtime_get_sync(dev); | |
683 | if (ret < 0) { | |
684 | pm_runtime_put_noidle(dev); | |
685 | return ret; | |
686 | } | |
687 | ||
75242927 | 688 | ret = reset_control_assert(oproc->reset); |
34ed5a33 | 689 | if (ret) |
5f31b232 | 690 | goto out; |
34ed5a33 | 691 | |
e28edc57 SA |
692 | ret = omap_rproc_disable_timers(rproc, true); |
693 | if (ret) | |
5f31b232 | 694 | goto enable_device; |
e28edc57 | 695 | |
8841a66a | 696 | mbox_free_channel(oproc->mbox); |
34ed5a33 | 697 | |
5f31b232 SA |
698 | /* |
699 | * update the runtime pm states and status now that the remoteproc | |
700 | * has stopped | |
701 | */ | |
702 | pm_runtime_disable(dev); | |
703 | pm_runtime_dont_use_autosuspend(dev); | |
704 | pm_runtime_put_noidle(dev); | |
705 | pm_runtime_set_suspended(dev); | |
706 | ||
34ed5a33 | 707 | return 0; |
5f31b232 SA |
708 | |
709 | enable_device: | |
710 | reset_control_deassert(oproc->reset); | |
711 | out: | |
712 | /* schedule the next auto-suspend */ | |
713 | pm_runtime_mark_last_busy(dev); | |
714 | pm_runtime_put_autosuspend(dev); | |
715 | return ret; | |
34ed5a33 OBC |
716 | } |
717 | ||
530a1b57 SA |
718 | /** |
719 | * omap_rproc_da_to_va() - internal memory translation helper | |
720 | * @rproc: remote processor to apply the address translation for | |
721 | * @da: device address to translate | |
722 | * @len: length of the memory buffer | |
723 | * | |
724 | * Custom function implementing the rproc .da_to_va ops to provide address | |
725 | * translation (device address to kernel virtual address) for internal RAMs | |
726 | * present in a DSP or IPU device). The translated addresses can be used | |
727 | * either by the remoteproc core for loading, or by any rpmsg bus drivers. | |
728 | * | |
729 | * Return: translated virtual address in kernel memory space on success, | |
730 | * or NULL on failure. | |
731 | */ | |
40df0a91 | 732 | static void *omap_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) |
530a1b57 SA |
733 | { |
734 | struct omap_rproc *oproc = rproc->priv; | |
735 | int i; | |
736 | u32 offset; | |
737 | ||
738 | if (len <= 0) | |
739 | return NULL; | |
740 | ||
741 | if (!oproc->num_mems) | |
742 | return NULL; | |
743 | ||
744 | for (i = 0; i < oproc->num_mems; i++) { | |
745 | if (da >= oproc->mem[i].dev_addr && da + len <= | |
746 | oproc->mem[i].dev_addr + oproc->mem[i].size) { | |
747 | offset = da - oproc->mem[i].dev_addr; | |
748 | /* __force to make sparse happy with type conversion */ | |
749 | return (__force void *)(oproc->mem[i].cpu_addr + | |
750 | offset); | |
751 | } | |
752 | } | |
753 | ||
754 | return NULL; | |
755 | } | |
756 | ||
c008fad2 | 757 | static const struct rproc_ops omap_rproc_ops = { |
34ed5a33 OBC |
758 | .start = omap_rproc_start, |
759 | .stop = omap_rproc_stop, | |
760 | .kick = omap_rproc_kick, | |
530a1b57 | 761 | .da_to_va = omap_rproc_da_to_va, |
34ed5a33 OBC |
762 | }; |
763 | ||
9077ac1a SA |
764 | #ifdef CONFIG_PM |
765 | static bool _is_rproc_in_standby(struct omap_rproc *oproc) | |
766 | { | |
767 | return ti_clk_is_in_standby(oproc->fck); | |
768 | } | |
769 | ||
770 | /* 1 sec is long enough time to let the remoteproc side suspend the device */ | |
771 | #define DEF_SUSPEND_TIMEOUT 1000 | |
5f31b232 | 772 | static int _omap_rproc_suspend(struct rproc *rproc, bool auto_suspend) |
9077ac1a SA |
773 | { |
774 | struct device *dev = rproc->dev.parent; | |
775 | struct omap_rproc *oproc = rproc->priv; | |
776 | unsigned long to = msecs_to_jiffies(DEF_SUSPEND_TIMEOUT); | |
777 | unsigned long ta = jiffies + to; | |
5f31b232 SA |
778 | u32 suspend_msg = auto_suspend ? |
779 | RP_MBOX_SUSPEND_AUTO : RP_MBOX_SUSPEND_SYSTEM; | |
9077ac1a SA |
780 | int ret; |
781 | ||
782 | reinit_completion(&oproc->pm_comp); | |
783 | oproc->suspend_acked = false; | |
5f31b232 | 784 | ret = mbox_send_message(oproc->mbox, (void *)suspend_msg); |
9077ac1a SA |
785 | if (ret < 0) { |
786 | dev_err(dev, "PM mbox_send_message failed: %d\n", ret); | |
787 | return ret; | |
788 | } | |
789 | ||
790 | ret = wait_for_completion_timeout(&oproc->pm_comp, to); | |
791 | if (!oproc->suspend_acked) | |
792 | return -EBUSY; | |
793 | ||
794 | /* | |
795 | * The remoteproc side is returning the ACK message before saving the | |
796 | * context, because the context saving is performed within a SYS/BIOS | |
797 | * function, and it cannot have any inter-dependencies against the IPC | |
798 | * layer. Also, as the SYS/BIOS needs to preserve properly the processor | |
799 | * register set, sending this ACK or signalling the completion of the | |
800 | * context save through a shared memory variable can never be the | |
801 | * absolute last thing to be executed on the remoteproc side, and the | |
802 | * MPU cannot use the ACK message as a sync point to put the remoteproc | |
803 | * into reset. The only way to ensure that the remote processor has | |
804 | * completed saving the context is to check that the module has reached | |
805 | * STANDBY state (after saving the context, the SYS/BIOS executes the | |
806 | * appropriate target-specific WFI instruction causing the module to | |
807 | * enter STANDBY). | |
808 | */ | |
809 | while (!_is_rproc_in_standby(oproc)) { | |
810 | if (time_after(jiffies, ta)) | |
811 | return -ETIME; | |
812 | schedule(); | |
813 | } | |
814 | ||
815 | ret = reset_control_assert(oproc->reset); | |
816 | if (ret) { | |
817 | dev_err(dev, "reset assert during suspend failed %d\n", ret); | |
818 | return ret; | |
819 | } | |
820 | ||
821 | ret = omap_rproc_disable_timers(rproc, false); | |
822 | if (ret) { | |
823 | dev_err(dev, "disabling timers during suspend failed %d\n", | |
824 | ret); | |
825 | goto enable_device; | |
826 | } | |
827 | ||
5f31b232 SA |
828 | /* |
829 | * IOMMUs would have to be disabled specifically for runtime suspend. | |
830 | * They are handled automatically through System PM callbacks for | |
831 | * regular system suspend | |
832 | */ | |
833 | if (auto_suspend) { | |
834 | ret = omap_iommu_domain_deactivate(rproc->domain); | |
835 | if (ret) { | |
836 | dev_err(dev, "iommu domain deactivate failed %d\n", | |
837 | ret); | |
838 | goto enable_timers; | |
839 | } | |
840 | } | |
841 | ||
9077ac1a SA |
842 | return 0; |
843 | ||
5f31b232 SA |
844 | enable_timers: |
845 | /* ignore errors on re-enabling code */ | |
846 | omap_rproc_enable_timers(rproc, false); | |
9077ac1a SA |
847 | enable_device: |
848 | reset_control_deassert(oproc->reset); | |
849 | return ret; | |
850 | } | |
851 | ||
5f31b232 | 852 | static int _omap_rproc_resume(struct rproc *rproc, bool auto_suspend) |
9077ac1a SA |
853 | { |
854 | struct device *dev = rproc->dev.parent; | |
855 | struct omap_rproc *oproc = rproc->priv; | |
856 | int ret; | |
857 | ||
5f31b232 SA |
858 | /* |
859 | * IOMMUs would have to be enabled specifically for runtime resume. | |
860 | * They would have been already enabled automatically through System | |
861 | * PM callbacks for regular system resume | |
862 | */ | |
863 | if (auto_suspend) { | |
864 | ret = omap_iommu_domain_activate(rproc->domain); | |
865 | if (ret) { | |
866 | dev_err(dev, "omap_iommu activate failed %d\n", ret); | |
867 | goto out; | |
868 | } | |
869 | } | |
870 | ||
9077ac1a SA |
871 | /* boot address could be lost after suspend, so restore it */ |
872 | if (oproc->boot_data) { | |
873 | ret = omap_rproc_write_dsp_boot_addr(rproc); | |
874 | if (ret) { | |
875 | dev_err(dev, "boot address restore failed %d\n", ret); | |
5f31b232 | 876 | goto suspend_iommu; |
9077ac1a SA |
877 | } |
878 | } | |
879 | ||
880 | ret = omap_rproc_enable_timers(rproc, false); | |
881 | if (ret) { | |
882 | dev_err(dev, "enabling timers during resume failed %d\n", ret); | |
5f31b232 | 883 | goto suspend_iommu; |
9077ac1a SA |
884 | } |
885 | ||
886 | ret = reset_control_deassert(oproc->reset); | |
887 | if (ret) { | |
888 | dev_err(dev, "reset deassert during resume failed %d\n", ret); | |
889 | goto disable_timers; | |
890 | } | |
891 | ||
892 | return 0; | |
893 | ||
894 | disable_timers: | |
895 | omap_rproc_disable_timers(rproc, false); | |
5f31b232 SA |
896 | suspend_iommu: |
897 | if (auto_suspend) | |
898 | omap_iommu_domain_deactivate(rproc->domain); | |
9077ac1a SA |
899 | out: |
900 | return ret; | |
901 | } | |
902 | ||
903 | static int __maybe_unused omap_rproc_suspend(struct device *dev) | |
904 | { | |
c34bfafd | 905 | struct rproc *rproc = dev_get_drvdata(dev); |
5f31b232 | 906 | struct omap_rproc *oproc = rproc->priv; |
9077ac1a SA |
907 | int ret = 0; |
908 | ||
909 | mutex_lock(&rproc->lock); | |
910 | if (rproc->state == RPROC_OFFLINE) | |
911 | goto out; | |
912 | ||
913 | if (rproc->state == RPROC_SUSPENDED) | |
914 | goto out; | |
915 | ||
916 | if (rproc->state != RPROC_RUNNING) { | |
917 | ret = -EBUSY; | |
918 | goto out; | |
919 | } | |
920 | ||
5f31b232 | 921 | ret = _omap_rproc_suspend(rproc, false); |
9077ac1a SA |
922 | if (ret) { |
923 | dev_err(dev, "suspend failed %d\n", ret); | |
924 | goto out; | |
925 | } | |
926 | ||
5f31b232 SA |
927 | /* |
928 | * remoteproc is running at the time of system suspend, so remember | |
929 | * it so as to wake it up during system resume | |
930 | */ | |
931 | oproc->need_resume = true; | |
9077ac1a | 932 | rproc->state = RPROC_SUSPENDED; |
5f31b232 | 933 | |
9077ac1a SA |
934 | out: |
935 | mutex_unlock(&rproc->lock); | |
936 | return ret; | |
937 | } | |
938 | ||
939 | static int __maybe_unused omap_rproc_resume(struct device *dev) | |
940 | { | |
c34bfafd | 941 | struct rproc *rproc = dev_get_drvdata(dev); |
5f31b232 | 942 | struct omap_rproc *oproc = rproc->priv; |
9077ac1a SA |
943 | int ret = 0; |
944 | ||
945 | mutex_lock(&rproc->lock); | |
946 | if (rproc->state == RPROC_OFFLINE) | |
947 | goto out; | |
948 | ||
949 | if (rproc->state != RPROC_SUSPENDED) { | |
950 | ret = -EBUSY; | |
951 | goto out; | |
952 | } | |
953 | ||
5f31b232 SA |
954 | /* |
955 | * remoteproc was auto-suspended at the time of system suspend, | |
956 | * so no need to wake-up the processor (leave it in suspended | |
957 | * state, will be woken up during a subsequent runtime_resume) | |
958 | */ | |
959 | if (!oproc->need_resume) | |
960 | goto out; | |
961 | ||
962 | ret = _omap_rproc_resume(rproc, false); | |
9077ac1a SA |
963 | if (ret) { |
964 | dev_err(dev, "resume failed %d\n", ret); | |
965 | goto out; | |
966 | } | |
967 | ||
5f31b232 SA |
968 | oproc->need_resume = false; |
969 | rproc->state = RPROC_RUNNING; | |
970 | ||
971 | pm_runtime_mark_last_busy(dev); | |
972 | out: | |
973 | mutex_unlock(&rproc->lock); | |
974 | return ret; | |
975 | } | |
976 | ||
977 | static int omap_rproc_runtime_suspend(struct device *dev) | |
978 | { | |
979 | struct rproc *rproc = dev_get_drvdata(dev); | |
980 | struct omap_rproc *oproc = rproc->priv; | |
981 | int ret; | |
982 | ||
983 | mutex_lock(&rproc->lock); | |
984 | if (rproc->state == RPROC_CRASHED) { | |
985 | dev_dbg(dev, "rproc cannot be runtime suspended when crashed!\n"); | |
986 | ret = -EBUSY; | |
987 | goto out; | |
988 | } | |
989 | ||
990 | if (WARN_ON(rproc->state != RPROC_RUNNING)) { | |
991 | dev_err(dev, "rproc cannot be runtime suspended when not running!\n"); | |
992 | ret = -EBUSY; | |
993 | goto out; | |
994 | } | |
995 | ||
996 | /* | |
997 | * do not even attempt suspend if the remote processor is not | |
998 | * idled for runtime auto-suspend | |
999 | */ | |
1000 | if (!_is_rproc_in_standby(oproc)) { | |
1001 | ret = -EBUSY; | |
1002 | goto abort; | |
1003 | } | |
1004 | ||
1005 | ret = _omap_rproc_suspend(rproc, true); | |
1006 | if (ret) | |
1007 | goto abort; | |
1008 | ||
1009 | rproc->state = RPROC_SUSPENDED; | |
1010 | mutex_unlock(&rproc->lock); | |
1011 | return 0; | |
1012 | ||
1013 | abort: | |
1014 | pm_runtime_mark_last_busy(dev); | |
1015 | out: | |
1016 | mutex_unlock(&rproc->lock); | |
1017 | return ret; | |
1018 | } | |
1019 | ||
1020 | static int omap_rproc_runtime_resume(struct device *dev) | |
1021 | { | |
1022 | struct rproc *rproc = dev_get_drvdata(dev); | |
1023 | int ret; | |
1024 | ||
1025 | mutex_lock(&rproc->lock); | |
1026 | if (WARN_ON(rproc->state != RPROC_SUSPENDED)) { | |
1027 | dev_err(dev, "rproc cannot be runtime resumed if not suspended! state=%d\n", | |
1028 | rproc->state); | |
1029 | ret = -EBUSY; | |
1030 | goto out; | |
1031 | } | |
1032 | ||
1033 | ret = _omap_rproc_resume(rproc, true); | |
1034 | if (ret) { | |
1035 | dev_err(dev, "runtime resume failed %d\n", ret); | |
1036 | goto out; | |
1037 | } | |
1038 | ||
9077ac1a SA |
1039 | rproc->state = RPROC_RUNNING; |
1040 | out: | |
1041 | mutex_unlock(&rproc->lock); | |
1042 | return ret; | |
1043 | } | |
1044 | #endif /* CONFIG_PM */ | |
1045 | ||
4a032199 SA |
1046 | static const struct omap_rproc_mem_data ipu_mems[] = { |
1047 | { .name = "l2ram", .dev_addr = 0x20000000 }, | |
1048 | { }, | |
1049 | }; | |
1050 | ||
0aaf1913 SA |
1051 | static const struct omap_rproc_mem_data dra7_dsp_mems[] = { |
1052 | { .name = "l2ram", .dev_addr = 0x800000 }, | |
1053 | { .name = "l1pram", .dev_addr = 0xe00000 }, | |
1054 | { .name = "l1dram", .dev_addr = 0xf00000 }, | |
1055 | { }, | |
1056 | }; | |
1057 | ||
75242927 SA |
1058 | static const struct omap_rproc_dev_data omap4_dsp_dev_data = { |
1059 | .device_name = "dsp", | |
1060 | }; | |
1061 | ||
1062 | static const struct omap_rproc_dev_data omap4_ipu_dev_data = { | |
1063 | .device_name = "ipu", | |
4a032199 | 1064 | .mems = ipu_mems, |
75242927 SA |
1065 | }; |
1066 | ||
1067 | static const struct omap_rproc_dev_data omap5_dsp_dev_data = { | |
1068 | .device_name = "dsp", | |
1069 | }; | |
1070 | ||
1071 | static const struct omap_rproc_dev_data omap5_ipu_dev_data = { | |
1072 | .device_name = "ipu", | |
4a032199 | 1073 | .mems = ipu_mems, |
75242927 SA |
1074 | }; |
1075 | ||
0aaf1913 SA |
1076 | static const struct omap_rproc_dev_data dra7_dsp_dev_data = { |
1077 | .device_name = "dsp", | |
1078 | .mems = dra7_dsp_mems, | |
1079 | }; | |
1080 | ||
1081 | static const struct omap_rproc_dev_data dra7_ipu_dev_data = { | |
1082 | .device_name = "ipu", | |
1083 | .mems = ipu_mems, | |
1084 | }; | |
1085 | ||
75242927 SA |
1086 | static const struct of_device_id omap_rproc_of_match[] = { |
1087 | { | |
1088 | .compatible = "ti,omap4-dsp", | |
1089 | .data = &omap4_dsp_dev_data, | |
1090 | }, | |
1091 | { | |
1092 | .compatible = "ti,omap4-ipu", | |
1093 | .data = &omap4_ipu_dev_data, | |
1094 | }, | |
1095 | { | |
1096 | .compatible = "ti,omap5-dsp", | |
1097 | .data = &omap5_dsp_dev_data, | |
1098 | }, | |
1099 | { | |
1100 | .compatible = "ti,omap5-ipu", | |
1101 | .data = &omap5_ipu_dev_data, | |
1102 | }, | |
0aaf1913 SA |
1103 | { |
1104 | .compatible = "ti,dra7-dsp", | |
1105 | .data = &dra7_dsp_dev_data, | |
1106 | }, | |
1107 | { | |
1108 | .compatible = "ti,dra7-ipu", | |
1109 | .data = &dra7_ipu_dev_data, | |
1110 | }, | |
75242927 SA |
1111 | { |
1112 | /* end */ | |
1113 | }, | |
1114 | }; | |
1115 | MODULE_DEVICE_TABLE(of, omap_rproc_of_match); | |
1116 | ||
1117 | static const char *omap_rproc_get_firmware(struct platform_device *pdev) | |
1118 | { | |
1119 | const char *fw_name; | |
1120 | int ret; | |
1121 | ||
1122 | ret = of_property_read_string(pdev->dev.of_node, "firmware-name", | |
1123 | &fw_name); | |
1124 | if (ret) | |
1125 | return ERR_PTR(ret); | |
1126 | ||
1127 | return fw_name; | |
1128 | } | |
1129 | ||
1130 | static int omap_rproc_get_boot_data(struct platform_device *pdev, | |
1131 | struct rproc *rproc) | |
1132 | { | |
1133 | struct device_node *np = pdev->dev.of_node; | |
1134 | struct omap_rproc *oproc = rproc->priv; | |
1135 | const struct omap_rproc_dev_data *data; | |
1136 | int ret; | |
1137 | ||
1138 | data = of_device_get_match_data(&pdev->dev); | |
1139 | if (!data) | |
1140 | return -ENODEV; | |
1141 | ||
1142 | if (!of_property_read_bool(np, "ti,bootreg")) | |
1143 | return 0; | |
1144 | ||
1145 | oproc->boot_data = devm_kzalloc(&pdev->dev, sizeof(*oproc->boot_data), | |
1146 | GFP_KERNEL); | |
1147 | if (!oproc->boot_data) | |
1148 | return -ENOMEM; | |
1149 | ||
1150 | oproc->boot_data->syscon = | |
1151 | syscon_regmap_lookup_by_phandle(np, "ti,bootreg"); | |
1152 | if (IS_ERR(oproc->boot_data->syscon)) { | |
1153 | ret = PTR_ERR(oproc->boot_data->syscon); | |
1154 | return ret; | |
1155 | } | |
1156 | ||
1157 | if (of_property_read_u32_index(np, "ti,bootreg", 1, | |
1158 | &oproc->boot_data->boot_reg)) { | |
1159 | dev_err(&pdev->dev, "couldn't get the boot register\n"); | |
1160 | return -EINVAL; | |
1161 | } | |
1162 | ||
0aaf1913 SA |
1163 | of_property_read_u32_index(np, "ti,bootreg", 2, |
1164 | &oproc->boot_data->boot_reg_shift); | |
1165 | ||
75242927 SA |
1166 | return 0; |
1167 | } | |
1168 | ||
4a032199 SA |
1169 | static int omap_rproc_of_get_internal_memories(struct platform_device *pdev, |
1170 | struct rproc *rproc) | |
1171 | { | |
1172 | struct omap_rproc *oproc = rproc->priv; | |
1173 | struct device *dev = &pdev->dev; | |
1174 | const struct omap_rproc_dev_data *data; | |
1175 | struct resource *res; | |
1176 | int num_mems; | |
1177 | int i; | |
1178 | ||
1179 | data = of_device_get_match_data(dev); | |
1180 | if (!data) | |
1181 | return -ENODEV; | |
1182 | ||
1183 | if (!data->mems) | |
1184 | return 0; | |
1185 | ||
1186 | num_mems = of_property_count_elems_of_size(dev->of_node, "reg", | |
1187 | sizeof(u32)) / 2; | |
1188 | ||
1189 | oproc->mem = devm_kcalloc(dev, num_mems, sizeof(*oproc->mem), | |
1190 | GFP_KERNEL); | |
1191 | if (!oproc->mem) | |
1192 | return -ENOMEM; | |
1193 | ||
1194 | for (i = 0; data->mems[i].name; i++) { | |
1195 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1196 | data->mems[i].name); | |
1197 | if (!res) { | |
1198 | dev_err(dev, "no memory defined for %s\n", | |
1199 | data->mems[i].name); | |
1200 | return -ENOMEM; | |
1201 | } | |
1202 | oproc->mem[i].cpu_addr = devm_ioremap_resource(dev, res); | |
1203 | if (IS_ERR(oproc->mem[i].cpu_addr)) { | |
1204 | dev_err(dev, "failed to parse and map %s memory\n", | |
1205 | data->mems[i].name); | |
1206 | return PTR_ERR(oproc->mem[i].cpu_addr); | |
1207 | } | |
1208 | oproc->mem[i].bus_addr = res->start; | |
1209 | oproc->mem[i].dev_addr = data->mems[i].dev_addr; | |
1210 | oproc->mem[i].size = resource_size(res); | |
1211 | ||
1212 | dev_dbg(dev, "memory %8s: bus addr %pa size 0x%x va %pK da 0x%x\n", | |
1213 | data->mems[i].name, &oproc->mem[i].bus_addr, | |
1214 | oproc->mem[i].size, oproc->mem[i].cpu_addr, | |
1215 | oproc->mem[i].dev_addr); | |
1216 | } | |
1217 | oproc->num_mems = num_mems; | |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
69591e4a SA |
1222 | #ifdef CONFIG_OMAP_REMOTEPROC_WATCHDOG |
1223 | static int omap_rproc_count_wdog_timers(struct device *dev) | |
1224 | { | |
1225 | struct device_node *np = dev->of_node; | |
1226 | int ret; | |
1227 | ||
1228 | ret = of_count_phandle_with_args(np, "ti,watchdog-timers", NULL); | |
1229 | if (ret <= 0) { | |
1230 | dev_dbg(dev, "device does not have watchdog timers, status = %d\n", | |
1231 | ret); | |
1232 | ret = 0; | |
1233 | } | |
1234 | ||
1235 | return ret; | |
1236 | } | |
1237 | #else | |
1238 | static int omap_rproc_count_wdog_timers(struct device *dev) | |
1239 | { | |
1240 | return 0; | |
1241 | } | |
1242 | #endif | |
1243 | ||
e28edc57 SA |
1244 | static int omap_rproc_of_get_timers(struct platform_device *pdev, |
1245 | struct rproc *rproc) | |
1246 | { | |
1247 | struct device_node *np = pdev->dev.of_node; | |
1248 | struct omap_rproc *oproc = rproc->priv; | |
1249 | struct device *dev = &pdev->dev; | |
69591e4a | 1250 | int num_timers; |
e28edc57 SA |
1251 | |
1252 | /* | |
1253 | * Timer nodes are directly used in client nodes as phandles, so | |
1254 | * retrieve the count using appropriate size | |
1255 | */ | |
1256 | oproc->num_timers = of_count_phandle_with_args(np, "ti,timers", NULL); | |
1257 | if (oproc->num_timers <= 0) { | |
1258 | dev_dbg(dev, "device does not have timers, status = %d\n", | |
1259 | oproc->num_timers); | |
1260 | oproc->num_timers = 0; | |
1261 | } | |
1262 | ||
69591e4a SA |
1263 | oproc->num_wd_timers = omap_rproc_count_wdog_timers(dev); |
1264 | ||
1265 | num_timers = oproc->num_timers + oproc->num_wd_timers; | |
1266 | if (num_timers) { | |
1267 | oproc->timers = devm_kcalloc(dev, num_timers, | |
e28edc57 SA |
1268 | sizeof(*oproc->timers), |
1269 | GFP_KERNEL); | |
1270 | if (!oproc->timers) | |
1271 | return -ENOMEM; | |
1272 | ||
69591e4a SA |
1273 | dev_dbg(dev, "device has %d tick timers and %d watchdog timers\n", |
1274 | oproc->num_timers, oproc->num_wd_timers); | |
e28edc57 SA |
1275 | } |
1276 | ||
1277 | return 0; | |
1278 | } | |
1279 | ||
0fe763c5 | 1280 | static int omap_rproc_probe(struct platform_device *pdev) |
34ed5a33 | 1281 | { |
75242927 | 1282 | struct device_node *np = pdev->dev.of_node; |
34ed5a33 OBC |
1283 | struct omap_rproc *oproc; |
1284 | struct rproc *rproc; | |
75242927 | 1285 | const char *firmware; |
34ed5a33 | 1286 | int ret; |
75242927 SA |
1287 | struct reset_control *reset; |
1288 | ||
1289 | if (!np) { | |
1290 | dev_err(&pdev->dev, "only DT-based devices are supported\n"); | |
1291 | return -ENODEV; | |
1292 | } | |
1293 | ||
1294 | reset = devm_reset_control_array_get_exclusive(&pdev->dev); | |
1295 | if (IS_ERR(reset)) | |
1296 | return PTR_ERR(reset); | |
1297 | ||
1298 | firmware = omap_rproc_get_firmware(pdev); | |
1299 | if (IS_ERR(firmware)) | |
1300 | return PTR_ERR(firmware); | |
34ed5a33 OBC |
1301 | |
1302 | ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1303 | if (ret) { | |
6b039762 | 1304 | dev_err(&pdev->dev, "dma_set_coherent_mask: %d\n", ret); |
34ed5a33 OBC |
1305 | return ret; |
1306 | } | |
1307 | ||
75242927 SA |
1308 | rproc = rproc_alloc(&pdev->dev, dev_name(&pdev->dev), &omap_rproc_ops, |
1309 | firmware, sizeof(*oproc)); | |
34ed5a33 OBC |
1310 | if (!rproc) |
1311 | return -ENOMEM; | |
1312 | ||
1313 | oproc = rproc->priv; | |
1314 | oproc->rproc = rproc; | |
75242927 | 1315 | oproc->reset = reset; |
315491e5 SA |
1316 | /* All existing OMAP IPU and DSP processors have an MMU */ |
1317 | rproc->has_iommu = true; | |
34ed5a33 | 1318 | |
4a032199 SA |
1319 | ret = omap_rproc_of_get_internal_memories(pdev, rproc); |
1320 | if (ret) | |
1321 | goto free_rproc; | |
1322 | ||
75242927 SA |
1323 | ret = omap_rproc_get_boot_data(pdev, rproc); |
1324 | if (ret) | |
1325 | goto free_rproc; | |
e28edc57 SA |
1326 | |
1327 | ret = omap_rproc_of_get_timers(pdev, rproc); | |
1328 | if (ret) | |
1329 | goto free_rproc; | |
75242927 | 1330 | |
9077ac1a | 1331 | init_completion(&oproc->pm_comp); |
5f31b232 SA |
1332 | oproc->autosuspend_delay = DEFAULT_AUTOSUSPEND_DELAY; |
1333 | ||
1334 | of_property_read_u32(pdev->dev.of_node, "ti,autosuspend-delay-ms", | |
1335 | &oproc->autosuspend_delay); | |
1336 | ||
1337 | pm_runtime_set_autosuspend_delay(&pdev->dev, oproc->autosuspend_delay); | |
9077ac1a SA |
1338 | |
1339 | oproc->fck = devm_clk_get(&pdev->dev, 0); | |
1340 | if (IS_ERR(oproc->fck)) { | |
1341 | ret = PTR_ERR(oproc->fck); | |
1342 | goto free_rproc; | |
1343 | } | |
1344 | ||
f4af5bd2 SA |
1345 | ret = of_reserved_mem_device_init(&pdev->dev); |
1346 | if (ret) { | |
1347 | dev_warn(&pdev->dev, "device does not have specific CMA pool.\n"); | |
1348 | dev_warn(&pdev->dev, "Typically this should be provided,\n"); | |
1349 | dev_warn(&pdev->dev, "only omit if you know what you are doing.\n"); | |
1350 | } | |
1351 | ||
34ed5a33 OBC |
1352 | platform_set_drvdata(pdev, rproc); |
1353 | ||
160e7c84 | 1354 | ret = rproc_add(rproc); |
34ed5a33 | 1355 | if (ret) |
f4af5bd2 | 1356 | goto release_mem; |
34ed5a33 OBC |
1357 | |
1358 | return 0; | |
1359 | ||
f4af5bd2 SA |
1360 | release_mem: |
1361 | of_reserved_mem_device_release(&pdev->dev); | |
34ed5a33 | 1362 | free_rproc: |
433c0e04 | 1363 | rproc_free(rproc); |
34ed5a33 OBC |
1364 | return ret; |
1365 | } | |
1366 | ||
141adf29 | 1367 | static void omap_rproc_remove(struct platform_device *pdev) |
34ed5a33 OBC |
1368 | { |
1369 | struct rproc *rproc = platform_get_drvdata(pdev); | |
1370 | ||
160e7c84 | 1371 | rproc_del(rproc); |
433c0e04 | 1372 | rproc_free(rproc); |
f4af5bd2 | 1373 | of_reserved_mem_device_release(&pdev->dev); |
34ed5a33 OBC |
1374 | } |
1375 | ||
9077ac1a SA |
1376 | static const struct dev_pm_ops omap_rproc_pm_ops = { |
1377 | SET_SYSTEM_SLEEP_PM_OPS(omap_rproc_suspend, omap_rproc_resume) | |
5f31b232 SA |
1378 | SET_RUNTIME_PM_OPS(omap_rproc_runtime_suspend, |
1379 | omap_rproc_runtime_resume, NULL) | |
9077ac1a SA |
1380 | }; |
1381 | ||
34ed5a33 OBC |
1382 | static struct platform_driver omap_rproc_driver = { |
1383 | .probe = omap_rproc_probe, | |
141adf29 | 1384 | .remove_new = omap_rproc_remove, |
34ed5a33 OBC |
1385 | .driver = { |
1386 | .name = "omap-rproc", | |
9077ac1a | 1387 | .pm = &omap_rproc_pm_ops, |
75242927 | 1388 | .of_match_table = omap_rproc_of_match, |
34ed5a33 OBC |
1389 | }, |
1390 | }; | |
1391 | ||
63d667bf | 1392 | module_platform_driver(omap_rproc_driver); |
34ed5a33 OBC |
1393 | |
1394 | MODULE_LICENSE("GPL v2"); | |
1395 | MODULE_DESCRIPTION("OMAP Remote Processor control driver"); |