[linux-2.6-block.git] / drivers / remoteproc / mtk_common.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
 */

#ifndef __RPROC_MTK_COMMON_H
#define __RPROC_MTK_COMMON_H

#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/remoteproc.h>
#include <linux/remoteproc/mtk_scp.h>

#define MT8183_SW_RSTN			0x0
#define MT8183_SW_RSTN_BIT		BIT(0)
#define MT8183_SCP_TO_HOST		0x1C
#define MT8183_SCP_IPC_INT_BIT		BIT(0)
#define MT8183_SCP_WDT_INT_BIT		BIT(8)
#define MT8183_HOST_TO_SCP		0x28
#define MT8183_HOST_IPC_INT_BIT		BIT(0)
#define MT8183_WDT_CFG			0x84
#define MT8183_SCP_CLK_SW_SEL		0x4000
#define MT8183_SCP_CLK_DIV_SEL		0x4024
#define MT8183_SCP_SRAM_PDN		0x402C
#define MT8183_SCP_L1_SRAM_PD		0x4080
#define MT8183_SCP_TCM_TAIL_SRAM_PD	0x4094

#define MT8183_SCP_CACHE_SEL(x)		(0x14000 + (x) * 0x3000)
#define MT8183_SCP_CACHE_CON		MT8183_SCP_CACHE_SEL(0)
#define MT8183_SCP_DCACHE_CON		MT8183_SCP_CACHE_SEL(1)
#define MT8183_SCP_CACHESIZE_8KB	BIT(8)
#define MT8183_SCP_CACHE_CON_WAYEN	BIT(10)

#define MT8192_L2TCM_SRAM_PD_0		0x10C0
#define MT8192_L2TCM_SRAM_PD_1		0x10C4
#define MT8192_L2TCM_SRAM_PD_2		0x10C8
#define MT8192_L1TCM_SRAM_PDN		0x102C
#define MT8192_CPU0_SRAM_PD		0x1080

#define MT8192_SCP2APMCU_IPC_SET	0x4080
#define MT8192_SCP2APMCU_IPC_CLR	0x4084
#define MT8192_SCP_IPC_INT_BIT		BIT(0)
#define MT8192_SCP2SPM_IPC_CLR		0x4094
#define MT8192_GIPC_IN_SET		0x4098
#define MT8192_HOST_IPC_INT_BIT		BIT(0)

#define MT8192_CORE0_SW_RSTN_CLR	0x10000
#define MT8192_CORE0_SW_RSTN_SET	0x10004
#define MT8192_CORE0_MEM_ATT_PREDEF	0x10008
#define MT8192_CORE0_WDT_IRQ		0x10030
#define MT8192_CORE0_WDT_CFG		0x10034

#define SCP_FW_VER_LEN			32
#define SCP_SHARE_BUFFER_SIZE		288

struct scp_run {
	u32 signaled;
	s8 fw_ver[SCP_FW_VER_LEN];
	u32 dec_capability;
	u32 enc_capability;
	wait_queue_head_t wq;
};

struct scp_ipi_desc {
	/* For protecting handler. */
	struct mutex lock;
	scp_ipi_handler_t handler;
	void *priv;
};

struct mtk_scp;

struct mtk_scp_of_data {
	int (*scp_clk_get)(struct mtk_scp *scp);
	int (*scp_before_load)(struct mtk_scp *scp);
	void (*scp_irq_handler)(struct mtk_scp *scp);
	void (*scp_reset_assert)(struct mtk_scp *scp);
	void (*scp_reset_deassert)(struct mtk_scp *scp);
	void (*scp_stop)(struct mtk_scp *scp);
	void *(*scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len);

	u32 host_to_scp_reg;
	u32 host_to_scp_int_bit;

	size_t ipi_buf_offset;
};

struct mtk_scp {
	struct device *dev;
	struct rproc *rproc;
	struct clk *clk;
	void __iomem *reg_base;
	void __iomem *sram_base;
	size_t sram_size;
	phys_addr_t sram_phys;
	void __iomem *l1tcm_base;
	size_t l1tcm_size;
	phys_addr_t l1tcm_phys;

	const struct mtk_scp_of_data *data;

	struct mtk_share_obj __iomem *recv_buf;
	struct mtk_share_obj __iomem *send_buf;
	struct scp_run run;
	/* To prevent multiple ipi_send run concurrently. */
	struct mutex send_lock;
	struct scp_ipi_desc ipi_desc[SCP_IPI_MAX];
	bool ipi_id_ack[SCP_IPI_MAX];
	wait_queue_head_t ack_wq;

	void *cpu_addr;
	dma_addr_t dma_addr;
	size_t dram_size;

	struct rproc_subdev *rpmsg_subdev;
};

/**
 * struct mtk_share_obj - SRAM buffer shared with AP and SCP
 *
 * @id:		IPI id
 * @len:	share buffer length
 * @share_buf:	share buffer data
 */
struct mtk_share_obj {
	u32 id;
	u32 len;
	u8 share_buf[SCP_SHARE_BUFFER_SIZE];
};

void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len);
void scp_ipi_lock(struct mtk_scp *scp, u32 id);
void scp_ipi_unlock(struct mtk_scp *scp, u32 id);

#endif
Commit	Line	Data
63c13d61 EL	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (c) 2019 MediaTek Inc.
	4	*/
	5
	6	#ifndef __RPROC_MTK_COMMON_H
	7	#define __RPROC_MTK_COMMON_H
	8
	9	#include <linux/interrupt.h>
	10	#include <linux/kernel.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/remoteproc.h>
	13	#include <linux/remoteproc/mtk_scp.h>
	14
	15	#define MT8183_SW_RSTN 0x0
	16	#define MT8183_SW_RSTN_BIT BIT(0)
	17	#define MT8183_SCP_TO_HOST 0x1C
	18	#define MT8183_SCP_IPC_INT_BIT BIT(0)
	19	#define MT8183_SCP_WDT_INT_BIT BIT(8)
	20	#define MT8183_HOST_TO_SCP 0x28
	21	#define MT8183_HOST_IPC_INT_BIT BIT(0)
	22	#define MT8183_WDT_CFG 0x84
	23	#define MT8183_SCP_CLK_SW_SEL 0x4000
	24	#define MT8183_SCP_CLK_DIV_SEL 0x4024
	25	#define MT8183_SCP_SRAM_PDN 0x402C
	26	#define MT8183_SCP_L1_SRAM_PD 0x4080
	27	#define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094
	28
	29	#define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000)
	30	#define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0)
	31	#define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1)
	32	#define MT8183_SCP_CACHESIZE_8KB BIT(8)
	33	#define MT8183_SCP_CACHE_CON_WAYEN BIT(10)
	34
0a441514 TBS	35	#define MT8192_L2TCM_SRAM_PD_0 0x10C0
	36	#define MT8192_L2TCM_SRAM_PD_1 0x10C4
	37	#define MT8192_L2TCM_SRAM_PD_2 0x10C8
	38	#define MT8192_L1TCM_SRAM_PDN 0x102C
	39	#define MT8192_CPU0_SRAM_PD 0x1080
fd0b6c1f	40
0a441514 TBS	41	#define MT8192_SCP2APMCU_IPC_SET 0x4080
0a441514 TBS	42	#define MT8192_SCP2APMCU_IPC_CLR 0x4084
fd0b6c1f	43	#define MT8192_SCP_IPC_INT_BIT BIT(0)
0a441514 TBS	44	#define MT8192_SCP2SPM_IPC_CLR 0x4094
0a441514 TBS	45	#define MT8192_GIPC_IN_SET 0x4098
fd0b6c1f PHS	46	#define MT8192_HOST_IPC_INT_BIT BIT(0)
fd0b6c1f PHS	47
0a441514 TBS	48	#define MT8192_CORE0_SW_RSTN_CLR 0x10000
0a441514 TBS	49	#define MT8192_CORE0_SW_RSTN_SET 0x10004
ff3ea536	50	#define MT8192_CORE0_MEM_ATT_PREDEF 0x10008
8c545f52	51	#define MT8192_CORE0_WDT_IRQ 0x10030
0a441514	52	#define MT8192_CORE0_WDT_CFG 0x10034
fd0b6c1f	53
63c13d61 EL	54	#define SCP_FW_VER_LEN 32
	55	#define SCP_SHARE_BUFFER_SIZE 288
	56
	57	struct scp_run {
	58	u32 signaled;
	59	s8 fw_ver[SCP_FW_VER_LEN];
	60	u32 dec_capability;
	61	u32 enc_capability;
	62	wait_queue_head_t wq;
	63	};
	64
	65	struct scp_ipi_desc {
	66	/* For protecting handler. */
	67	struct mutex lock;
	68	scp_ipi_handler_t handler;
	69	void *priv;
	70	};
	71
fd0b6c1f PHS	72	struct mtk_scp;
	73
	74	struct mtk_scp_of_data {
79111df4	75	int (scp_clk_get)(struct mtk_scp scp);
fd0b6c1f PHS	76	int (scp_before_load)(struct mtk_scp scp);
	77	void (scp_irq_handler)(struct mtk_scp scp);
	78	void (scp_reset_assert)(struct mtk_scp scp);
	79	void (scp_reset_deassert)(struct mtk_scp scp);
	80	void (scp_stop)(struct mtk_scp scp);
ca23ecfd	81	void (scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len);
fd0b6c1f PHS	82
	83	u32 host_to_scp_reg;
	84	u32 host_to_scp_int_bit;
3efa0ea7 TBS	85
3efa0ea7 TBS	86	size_t ipi_buf_offset;
fd0b6c1f PHS	87	};
fd0b6c1f PHS	88
63c13d61 EL	89	struct mtk_scp {
	90	struct device *dev;
	91	struct rproc *rproc;
	92	struct clk *clk;
	93	void __iomem *reg_base;
	94	void __iomem *sram_base;
	95	size_t sram_size;
ca23ecfd TBS	96	phys_addr_t sram_phys;
	97	void __iomem *l1tcm_base;
	98	size_t l1tcm_size;
	99	phys_addr_t l1tcm_phys;
63c13d61	100
fd0b6c1f PHS	101	const struct mtk_scp_of_data *data;
fd0b6c1f PHS	102
63c13d61 EL	103	struct mtk_share_obj __iomem *recv_buf;
	104	struct mtk_share_obj __iomem *send_buf;
	105	struct scp_run run;
	106	/* To prevent multiple ipi_send run concurrently. */
	107	struct mutex send_lock;
	108	struct scp_ipi_desc ipi_desc[SCP_IPI_MAX];
	109	bool ipi_id_ack[SCP_IPI_MAX];
	110	wait_queue_head_t ack_wq;
	111
903635cb	112	void *cpu_addr;
c2781e4d	113	dma_addr_t dma_addr;
63c13d61	114	size_t dram_size;
70179969 PHS	115
70179969 PHS	116	struct rproc_subdev *rpmsg_subdev;
63c13d61 EL	117	};
	118
	119	/**
	120	* struct mtk_share_obj - SRAM buffer shared with AP and SCP
	121	*
	122	* @id: IPI id
	123	* @len: share buffer length
	124	* @share_buf: share buffer data
	125	*/
	126	struct mtk_share_obj {
	127	u32 id;
	128	u32 len;
	129	u8 share_buf[SCP_SHARE_BUFFER_SIZE];
	130	};
	131
	132	void scp_memcpy_aligned(void __iomem dst, const void src, unsigned int len);
	133	void scp_ipi_lock(struct mtk_scp *scp, u32 id);
	134	void scp_ipi_unlock(struct mtk_scp *scp, u32 id);
	135
	136	#endif