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63c13d61 EL |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (c) 2019 MediaTek Inc. | |
4 | */ | |
5 | ||
6 | #ifndef __RPROC_MTK_COMMON_H | |
7 | #define __RPROC_MTK_COMMON_H | |
8 | ||
9 | #include <linux/interrupt.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/remoteproc.h> | |
13 | #include <linux/remoteproc/mtk_scp.h> | |
14 | ||
15 | #define MT8183_SW_RSTN 0x0 | |
16 | #define MT8183_SW_RSTN_BIT BIT(0) | |
17 | #define MT8183_SCP_TO_HOST 0x1C | |
18 | #define MT8183_SCP_IPC_INT_BIT BIT(0) | |
19 | #define MT8183_SCP_WDT_INT_BIT BIT(8) | |
20 | #define MT8183_HOST_TO_SCP 0x28 | |
21 | #define MT8183_HOST_IPC_INT_BIT BIT(0) | |
22 | #define MT8183_WDT_CFG 0x84 | |
23 | #define MT8183_SCP_CLK_SW_SEL 0x4000 | |
24 | #define MT8183_SCP_CLK_DIV_SEL 0x4024 | |
25 | #define MT8183_SCP_SRAM_PDN 0x402C | |
26 | #define MT8183_SCP_L1_SRAM_PD 0x4080 | |
27 | #define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094 | |
28 | ||
29 | #define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000) | |
30 | #define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0) | |
31 | #define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1) | |
32 | #define MT8183_SCP_CACHESIZE_8KB BIT(8) | |
33 | #define MT8183_SCP_CACHE_CON_WAYEN BIT(10) | |
34 | ||
80d69185 AKC |
35 | #define MT8186_SCP_L1_SRAM_PD_P1 0x40B0 |
36 | #define MT8186_SCP_L1_SRAM_PD_p2 0x40B4 | |
37 | ||
0a441514 TBS |
38 | #define MT8192_L2TCM_SRAM_PD_0 0x10C0 |
39 | #define MT8192_L2TCM_SRAM_PD_1 0x10C4 | |
40 | #define MT8192_L2TCM_SRAM_PD_2 0x10C8 | |
41 | #define MT8192_L1TCM_SRAM_PDN 0x102C | |
42 | #define MT8192_CPU0_SRAM_PD 0x1080 | |
fd0b6c1f | 43 | |
0a441514 TBS |
44 | #define MT8192_SCP2APMCU_IPC_SET 0x4080 |
45 | #define MT8192_SCP2APMCU_IPC_CLR 0x4084 | |
fd0b6c1f | 46 | #define MT8192_SCP_IPC_INT_BIT BIT(0) |
0a441514 TBS |
47 | #define MT8192_SCP2SPM_IPC_CLR 0x4094 |
48 | #define MT8192_GIPC_IN_SET 0x4098 | |
fd0b6c1f PHS |
49 | #define MT8192_HOST_IPC_INT_BIT BIT(0) |
50 | ||
0a441514 TBS |
51 | #define MT8192_CORE0_SW_RSTN_CLR 0x10000 |
52 | #define MT8192_CORE0_SW_RSTN_SET 0x10004 | |
ff3ea536 | 53 | #define MT8192_CORE0_MEM_ATT_PREDEF 0x10008 |
8c545f52 | 54 | #define MT8192_CORE0_WDT_IRQ 0x10030 |
0a441514 | 55 | #define MT8192_CORE0_WDT_CFG 0x10034 |
fd0b6c1f | 56 | |
f20e232d TS |
57 | #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) |
58 | ||
63c13d61 EL |
59 | #define SCP_FW_VER_LEN 32 |
60 | #define SCP_SHARE_BUFFER_SIZE 288 | |
61 | ||
62 | struct scp_run { | |
63 | u32 signaled; | |
64 | s8 fw_ver[SCP_FW_VER_LEN]; | |
65 | u32 dec_capability; | |
66 | u32 enc_capability; | |
67 | wait_queue_head_t wq; | |
68 | }; | |
69 | ||
70 | struct scp_ipi_desc { | |
71 | /* For protecting handler. */ | |
72 | struct mutex lock; | |
73 | scp_ipi_handler_t handler; | |
74 | void *priv; | |
75 | }; | |
76 | ||
fd0b6c1f PHS |
77 | struct mtk_scp; |
78 | ||
79 | struct mtk_scp_of_data { | |
79111df4 | 80 | int (*scp_clk_get)(struct mtk_scp *scp); |
fd0b6c1f PHS |
81 | int (*scp_before_load)(struct mtk_scp *scp); |
82 | void (*scp_irq_handler)(struct mtk_scp *scp); | |
83 | void (*scp_reset_assert)(struct mtk_scp *scp); | |
84 | void (*scp_reset_deassert)(struct mtk_scp *scp); | |
85 | void (*scp_stop)(struct mtk_scp *scp); | |
ca23ecfd | 86 | void *(*scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len); |
fd0b6c1f PHS |
87 | |
88 | u32 host_to_scp_reg; | |
89 | u32 host_to_scp_int_bit; | |
3efa0ea7 TBS |
90 | |
91 | size_t ipi_buf_offset; | |
fd0b6c1f PHS |
92 | }; |
93 | ||
63c13d61 EL |
94 | struct mtk_scp { |
95 | struct device *dev; | |
96 | struct rproc *rproc; | |
97 | struct clk *clk; | |
98 | void __iomem *reg_base; | |
99 | void __iomem *sram_base; | |
100 | size_t sram_size; | |
ca23ecfd TBS |
101 | phys_addr_t sram_phys; |
102 | void __iomem *l1tcm_base; | |
103 | size_t l1tcm_size; | |
104 | phys_addr_t l1tcm_phys; | |
63c13d61 | 105 | |
fd0b6c1f PHS |
106 | const struct mtk_scp_of_data *data; |
107 | ||
63c13d61 EL |
108 | struct mtk_share_obj __iomem *recv_buf; |
109 | struct mtk_share_obj __iomem *send_buf; | |
110 | struct scp_run run; | |
111 | /* To prevent multiple ipi_send run concurrently. */ | |
112 | struct mutex send_lock; | |
113 | struct scp_ipi_desc ipi_desc[SCP_IPI_MAX]; | |
114 | bool ipi_id_ack[SCP_IPI_MAX]; | |
115 | wait_queue_head_t ack_wq; | |
116 | ||
903635cb | 117 | void *cpu_addr; |
c2781e4d | 118 | dma_addr_t dma_addr; |
63c13d61 | 119 | size_t dram_size; |
70179969 PHS |
120 | |
121 | struct rproc_subdev *rpmsg_subdev; | |
63c13d61 EL |
122 | }; |
123 | ||
124 | /** | |
125 | * struct mtk_share_obj - SRAM buffer shared with AP and SCP | |
126 | * | |
127 | * @id: IPI id | |
128 | * @len: share buffer length | |
129 | * @share_buf: share buffer data | |
130 | */ | |
131 | struct mtk_share_obj { | |
132 | u32 id; | |
133 | u32 len; | |
134 | u8 share_buf[SCP_SHARE_BUFFER_SIZE]; | |
135 | }; | |
136 | ||
137 | void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len); | |
138 | void scp_ipi_lock(struct mtk_scp *scp, u32 id); | |
139 | void scp_ipi_unlock(struct mtk_scp *scp, u32 id); | |
140 | ||
141 | #endif |