regulator: Explicitly include correct DT includes
[linux-block.git] / drivers / regulator / twl-regulator.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
fa16a5c1 2/*
c4aa6f31 3 * twl-regulator.c -- support regulators in twl4030/twl6030 family chips
fa16a5c1
DB
4 *
5 * Copyright (C) 2008 David Brownell
fa16a5c1
DB
6 */
7
8#include <linux/module.h>
8f52a580
SR
9#include <linux/string.h>
10#include <linux/slab.h>
fa16a5c1
DB
11#include <linux/init.h>
12#include <linux/err.h>
13#include <linux/platform_device.h>
2098e95c 14#include <linux/of.h>
fa16a5c1
DB
15#include <linux/regulator/driver.h>
16#include <linux/regulator/machine.h>
2098e95c 17#include <linux/regulator/of_regulator.h>
a2054256 18#include <linux/mfd/twl.h>
2330b05c 19#include <linux/delay.h>
fa16a5c1
DB
20
21/*
cac28ae6 22 * The TWL4030/TW5030/TPS659x0 family chips include power management, a
fa16a5c1
DB
23 * USB OTG transceiver, an RTC, ADC, PWM, and lots more. Some versions
24 * include an audio codec, battery charger, and more voltage regulators.
25 * These chips are often used in OMAP-based systems.
26 *
27 * This driver implements software-based resource control for various
28 * voltage regulators. This is usually augmented with state machine
29 * based control.
30 */
31
32struct twlreg_info {
33 /* start of regulator's PM_RECEIVER control register bank */
34 u8 base;
35
c4aa6f31 36 /* twl resource ID, for resource control state machine */
fa16a5c1
DB
37 u8 id;
38
39 /* voltage in mV = table[VSEL]; table_len must be a power-of-two */
40 u8 table_len;
41 const u16 *table;
42
045f972f
JKS
43 /* State REMAP default configuration */
44 u8 remap;
45
fa16a5c1
DB
46 /* used by regulator core */
47 struct regulator_desc desc;
4d94aee5
GG
48
49 /* chip specific features */
3db39885 50 unsigned long features;
63bfff4e 51
63bfff4e
TK
52 /* data passed from board for external get/set voltage */
53 void *data;
fa16a5c1
DB
54};
55
56
57/* LDO control registers ... offset is from the base of its register bank.
58 * The first three registers of all power resource banks help hardware to
59 * manage the various resource groups.
60 */
441a4505 61/* Common offset in TWL4030/6030 */
fa16a5c1 62#define VREG_GRP 0
441a4505 63/* TWL4030 register offsets */
fa16a5c1
DB
64#define VREG_TYPE 1
65#define VREG_REMAP 2
66#define VREG_DEDICATED 3 /* LDO control */
ba305e31 67#define VREG_VOLTAGE_SMPS_4030 9
441a4505
RN
68/* TWL6030 register offsets */
69#define VREG_TRANS 1
70#define VREG_STATE 2
71#define VREG_VOLTAGE 3
4d94aee5 72#define VREG_VOLTAGE_SMPS 4
4d94aee5 73
fa16a5c1 74static inline int
441a4505 75twlreg_read(struct twlreg_info *info, unsigned slave_subgp, unsigned offset)
fa16a5c1
DB
76{
77 u8 value;
78 int status;
79
441a4505 80 status = twl_i2c_read_u8(slave_subgp,
fa16a5c1
DB
81 &value, info->base + offset);
82 return (status < 0) ? status : value;
83}
84
85static inline int
441a4505
RN
86twlreg_write(struct twlreg_info *info, unsigned slave_subgp, unsigned offset,
87 u8 value)
fa16a5c1 88{
441a4505 89 return twl_i2c_write_u8(slave_subgp,
fa16a5c1
DB
90 value, info->base + offset);
91}
92
93/*----------------------------------------------------------------------*/
94
95/* generic power resource operations, which work on all regulators */
96
c4aa6f31 97static int twlreg_grp(struct regulator_dev *rdev)
fa16a5c1 98{
441a4505
RN
99 return twlreg_read(rdev_get_drvdata(rdev), TWL_MODULE_PM_RECEIVER,
100 VREG_GRP);
fa16a5c1
DB
101}
102
103/*
104 * Enable/disable regulators by joining/leaving the P1 (processor) group.
105 * We assume nobody else is updating the DEV_GRP registers.
106 */
441a4505
RN
107/* definition for 4030 family */
108#define P3_GRP_4030 BIT(7) /* "peripherals" */
109#define P2_GRP_4030 BIT(6) /* secondary processor, modem, etc */
110#define P1_GRP_4030 BIT(5) /* CPU/Linux */
111/* definition for 6030 family */
112#define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */
113#define P2_GRP_6030 BIT(1) /* "peripherals" */
114#define P1_GRP_6030 BIT(0) /* CPU/Linux */
fa16a5c1 115
b2456779 116static int twl4030reg_is_enabled(struct regulator_dev *rdev)
fa16a5c1 117{
c4aa6f31 118 int state = twlreg_grp(rdev);
fa16a5c1
DB
119
120 if (state < 0)
121 return state;
122
b2456779
SH
123 return state & P1_GRP_4030;
124}
125
2330b05c
ID
126#define PB_I2C_BUSY BIT(0)
127#define PB_I2C_BWEN BIT(1)
128
129/* Wait until buffer empty/ready to send a word on power bus. */
130static int twl4030_wait_pb_ready(void)
131{
132
133 int ret;
134 int timeout = 10;
135 u8 val;
136
137 do {
138 ret = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
139 TWL4030_PM_MASTER_PB_CFG);
140 if (ret < 0)
141 return ret;
142
143 if (!(val & PB_I2C_BUSY))
144 return 0;
145
146 mdelay(1);
147 timeout--;
148 } while (timeout);
149
150 return -ETIMEDOUT;
151}
152
153/* Send a word over the powerbus */
154static int twl4030_send_pb_msg(unsigned msg)
155{
156 u8 val;
157 int ret;
158
159 /* save powerbus configuration */
160 ret = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
161 TWL4030_PM_MASTER_PB_CFG);
162 if (ret < 0)
163 return ret;
164
165 /* Enable i2c access to powerbus */
166 ret = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val | PB_I2C_BWEN,
167 TWL4030_PM_MASTER_PB_CFG);
168 if (ret < 0)
169 return ret;
170
171 ret = twl4030_wait_pb_ready();
172 if (ret < 0)
173 return ret;
174
175 ret = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, msg >> 8,
176 TWL4030_PM_MASTER_PB_WORD_MSB);
177 if (ret < 0)
178 return ret;
179
180 ret = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, msg & 0xff,
181 TWL4030_PM_MASTER_PB_WORD_LSB);
182 if (ret < 0)
183 return ret;
184
185 ret = twl4030_wait_pb_ready();
186 if (ret < 0)
187 return ret;
188
189 /* Restore powerbus configuration */
190 return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
74d8b45f 191 TWL4030_PM_MASTER_PB_CFG);
2330b05c
ID
192}
193
f8c2940b 194static int twl4030reg_enable(struct regulator_dev *rdev)
fa16a5c1
DB
195{
196 struct twlreg_info *info = rdev_get_drvdata(rdev);
197 int grp;
198
b6f476c2 199 grp = twlreg_grp(rdev);
fa16a5c1
DB
200 if (grp < 0)
201 return grp;
202
f8c2940b 203 grp |= P1_GRP_4030;
441a4505 204
c57dbcab 205 return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
f8c2940b
B
206}
207
0ff3897d 208static int twl4030reg_disable(struct regulator_dev *rdev)
fa16a5c1
DB
209{
210 struct twlreg_info *info = rdev_get_drvdata(rdev);
211 int grp;
212
b6f476c2 213 grp = twlreg_grp(rdev);
fa16a5c1
DB
214 if (grp < 0)
215 return grp;
216
0ff3897d 217 grp &= ~(P1_GRP_4030 | P2_GRP_4030 | P3_GRP_4030);
441a4505 218
c57dbcab 219 return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
0ff3897d
B
220}
221
9a0244ad 222static int twl4030reg_get_status(struct regulator_dev *rdev)
fa16a5c1 223{
c4aa6f31 224 int state = twlreg_grp(rdev);
fa16a5c1
DB
225
226 if (state < 0)
227 return state;
228 state &= 0x0f;
229
230 /* assume state != WARM_RESET; we'd not be running... */
231 if (!state)
232 return REGULATOR_STATUS_OFF;
233 return (state & BIT(3))
234 ? REGULATOR_STATUS_NORMAL
235 : REGULATOR_STATUS_STANDBY;
236}
237
1a39962f 238static int twl4030reg_set_mode(struct regulator_dev *rdev, unsigned mode)
fa16a5c1
DB
239{
240 struct twlreg_info *info = rdev_get_drvdata(rdev);
241 unsigned message;
fa16a5c1
DB
242
243 /* We can only set the mode through state machine commands... */
244 switch (mode) {
245 case REGULATOR_MODE_NORMAL:
246 message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_ACTIVE);
247 break;
248 case REGULATOR_MODE_STANDBY:
249 message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_SLEEP);
250 break;
251 default:
252 return -EINVAL;
253 }
254
2330b05c 255 return twl4030_send_pb_msg(message);
fa16a5c1
DB
256}
257
a221f95e
ID
258static inline unsigned int twl4030reg_map_mode(unsigned int mode)
259{
260 switch (mode) {
261 case RES_STATE_ACTIVE:
262 return REGULATOR_MODE_NORMAL;
263 case RES_STATE_SLEEP:
264 return REGULATOR_MODE_STANDBY;
265 default:
02f37039 266 return REGULATOR_MODE_INVALID;
a221f95e
ID
267 }
268}
269
fa16a5c1
DB
270/*----------------------------------------------------------------------*/
271
272/*
273 * Support for adjustable-voltage LDOs uses a four bit (or less) voltage
274 * select field in its control register. We use tables indexed by VSEL
275 * to record voltages in milliVolts. (Accuracy is about three percent.)
276 *
277 * Note that VSEL values for VAUX2 changed in twl5030 and newer silicon;
278 * currently handled by listing two slightly different VAUX2 regulators,
279 * only one of which will be configured.
280 *
281 * VSEL values documented as "TI cannot support these values" are flagged
282 * in these tables as UNSUP() values; we normally won't assign them.
d6bb69cf
AH
283 *
284 * VAUX3 at 3V is incorrectly listed in some TI manuals as unsupported.
285 * TI are revising the twl5030/tps659x0 specs to support that 3.0V setting.
fa16a5c1 286 */
fa16a5c1 287#define UNSUP_MASK 0x8000
fa16a5c1
DB
288
289#define UNSUP(x) (UNSUP_MASK | (x))
411a2df5
N
290#define IS_UNSUP(info, x) \
291 ((UNSUP_MASK & (x)) && \
292 !((info)->features & TWL4030_ALLOW_UNSUPPORTED))
fa16a5c1
DB
293#define LDO_MV(x) (~UNSUP_MASK & (x))
294
295
296static const u16 VAUX1_VSEL_table[] = {
297 UNSUP(1500), UNSUP(1800), 2500, 2800,
298 3000, 3000, 3000, 3000,
299};
300static const u16 VAUX2_4030_VSEL_table[] = {
301 UNSUP(1000), UNSUP(1000), UNSUP(1200), 1300,
302 1500, 1800, UNSUP(1850), 2500,
303 UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000),
304 UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
305};
306static const u16 VAUX2_VSEL_table[] = {
307 1700, 1700, 1900, 1300,
308 1500, 1800, 2000, 2500,
309 2100, 2800, 2200, 2300,
310 2400, 2400, 2400, 2400,
311};
312static const u16 VAUX3_VSEL_table[] = {
313 1500, 1800, 2500, 2800,
d6bb69cf 314 3000, 3000, 3000, 3000,
fa16a5c1
DB
315};
316static const u16 VAUX4_VSEL_table[] = {
317 700, 1000, 1200, UNSUP(1300),
318 1500, 1800, UNSUP(1850), 2500,
1897e742
DB
319 UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000),
320 UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
fa16a5c1
DB
321};
322static const u16 VMMC1_VSEL_table[] = {
323 1850, 2850, 3000, 3150,
324};
325static const u16 VMMC2_VSEL_table[] = {
326 UNSUP(1000), UNSUP(1000), UNSUP(1200), UNSUP(1300),
327 UNSUP(1500), UNSUP(1800), 1850, UNSUP(2500),
328 2600, 2800, 2850, 3000,
329 3150, 3150, 3150, 3150,
330};
331static const u16 VPLL1_VSEL_table[] = {
332 1000, 1200, 1300, 1800,
333 UNSUP(2800), UNSUP(3000), UNSUP(3000), UNSUP(3000),
334};
335static const u16 VPLL2_VSEL_table[] = {
336 700, 1000, 1200, 1300,
337 UNSUP(1500), 1800, UNSUP(1850), UNSUP(2500),
338 UNSUP(2600), UNSUP(2800), UNSUP(2850), UNSUP(3000),
339 UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
340};
341static const u16 VSIM_VSEL_table[] = {
342 UNSUP(1000), UNSUP(1200), UNSUP(1300), 1800,
343 2800, 3000, 3000, 3000,
344};
345static const u16 VDAC_VSEL_table[] = {
346 1200, 1300, 1800, 1800,
347};
07fc493f
JKS
348static const u16 VIO_VSEL_table[] = {
349 1800, 1850,
350};
351static const u16 VINTANA2_VSEL_table[] = {
352 2500, 2750,
353};
fa16a5c1 354
3829100a 355/* 600mV to 1450mV in 12.5 mV steps */
60ab7f41 356static const struct linear_range VDD1_ranges[] = {
3829100a
AK
357 REGULATOR_LINEAR_RANGE(600000, 0, 68, 12500)
358};
359
360/* 600mV to 1450mV in 12.5 mV steps, everything above = 1500mV */
60ab7f41 361static const struct linear_range VDD2_ranges[] = {
3829100a
AK
362 REGULATOR_LINEAR_RANGE(600000, 0, 68, 12500),
363 REGULATOR_LINEAR_RANGE(1500000, 69, 69, 12500)
364};
365
3e3d3be7 366static int twl4030ldo_list_voltage(struct regulator_dev *rdev, unsigned index)
66b659e6
DB
367{
368 struct twlreg_info *info = rdev_get_drvdata(rdev);
369 int mV = info->table[index];
370
411a2df5 371 return IS_UNSUP(info, mV) ? 0 : (LDO_MV(mV) * 1000);
66b659e6
DB
372}
373
fa16a5c1 374static int
dd16b1f8 375twl4030ldo_set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
fa16a5c1
DB
376{
377 struct twlreg_info *info = rdev_get_drvdata(rdev);
fa16a5c1 378
dd16b1f8
AL
379 return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE,
380 selector);
fa16a5c1
DB
381}
382
6949fbe5 383static int twl4030ldo_get_voltage_sel(struct regulator_dev *rdev)
fa16a5c1
DB
384{
385 struct twlreg_info *info = rdev_get_drvdata(rdev);
6949fbe5 386 int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE);
fa16a5c1
DB
387
388 if (vsel < 0)
389 return vsel;
390
391 vsel &= info->table_len - 1;
6949fbe5 392 return vsel;
fa16a5c1
DB
393}
394
401861f5 395static const struct regulator_ops twl4030ldo_ops = {
3e3d3be7 396 .list_voltage = twl4030ldo_list_voltage,
66b659e6 397
dd16b1f8 398 .set_voltage_sel = twl4030ldo_set_voltage_sel,
6949fbe5 399 .get_voltage_sel = twl4030ldo_get_voltage_sel,
3e3d3be7 400
f8c2940b 401 .enable = twl4030reg_enable,
0ff3897d 402 .disable = twl4030reg_disable,
b2456779 403 .is_enabled = twl4030reg_is_enabled,
3e3d3be7 404
1a39962f 405 .set_mode = twl4030reg_set_mode,
3e3d3be7 406
9a0244ad 407 .get_status = twl4030reg_get_status,
3e3d3be7
RN
408};
409
ba305e31
TK
410static int
411twl4030smps_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV,
412 unsigned *selector)
413{
414 struct twlreg_info *info = rdev_get_drvdata(rdev);
415 int vsel = DIV_ROUND_UP(min_uV - 600000, 12500);
416
8313a4fb 417 twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE_SMPS_4030, vsel);
63bfff4e 418
ba305e31
TK
419 return 0;
420}
421
422static int twl4030smps_get_voltage(struct regulator_dev *rdev)
423{
424 struct twlreg_info *info = rdev_get_drvdata(rdev);
63bfff4e
TK
425 int vsel;
426
63bfff4e 427 vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER,
ba305e31
TK
428 VREG_VOLTAGE_SMPS_4030);
429
430 return vsel * 12500 + 600000;
431}
432
401861f5 433static const struct regulator_ops twl4030smps_ops = {
3829100a
AK
434 .list_voltage = regulator_list_voltage_linear_range,
435
ba305e31
TK
436 .set_voltage = twl4030smps_set_voltage,
437 .get_voltage = twl4030smps_get_voltage,
438};
439
fa16a5c1
DB
440/*----------------------------------------------------------------------*/
441
401861f5 442static const struct regulator_ops twl4030fixed_ops = {
b3816d50 443 .list_voltage = regulator_list_voltage_linear,
b2456779 444
f8c2940b 445 .enable = twl4030reg_enable,
0ff3897d 446 .disable = twl4030reg_disable,
b2456779
SH
447 .is_enabled = twl4030reg_is_enabled,
448
1a39962f 449 .set_mode = twl4030reg_set_mode,
b2456779 450
9a0244ad 451 .get_status = twl4030reg_get_status,
b2456779
SH
452};
453
fa16a5c1
DB
454/*----------------------------------------------------------------------*/
455
2098e95c 456#define TWL4030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf) \
0ffff5a6 457static const struct twlreg_info TWL4030_INFO_##label = { \
fa16a5c1
DB
458 .base = offset, \
459 .id = num, \
460 .table_len = ARRAY_SIZE(label##_VSEL_table), \
461 .table = label##_VSEL_table, \
045f972f 462 .remap = remap_conf, \
fa16a5c1
DB
463 .desc = { \
464 .name = #label, \
3e3d3be7 465 .id = TWL4030_REG_##label, \
66b659e6 466 .n_voltages = ARRAY_SIZE(label##_VSEL_table), \
3e3d3be7
RN
467 .ops = &twl4030ldo_ops, \
468 .type = REGULATOR_VOLTAGE, \
469 .owner = THIS_MODULE, \
fca53d86 470 .enable_time = turnon_delay, \
a221f95e 471 .of_map_mode = twl4030reg_map_mode, \
3e3d3be7
RN
472 }, \
473 }
474
3829100a
AK
475#define TWL4030_ADJUSTABLE_SMPS(label, offset, num, turnon_delay, remap_conf, \
476 n_volt) \
0ffff5a6 477static const struct twlreg_info TWL4030_INFO_##label = { \
ba305e31
TK
478 .base = offset, \
479 .id = num, \
ba305e31
TK
480 .remap = remap_conf, \
481 .desc = { \
482 .name = #label, \
483 .id = TWL4030_REG_##label, \
484 .ops = &twl4030smps_ops, \
485 .type = REGULATOR_VOLTAGE, \
486 .owner = THIS_MODULE, \
fca53d86 487 .enable_time = turnon_delay, \
a221f95e 488 .of_map_mode = twl4030reg_map_mode, \
3829100a
AK
489 .n_voltages = n_volt, \
490 .n_linear_ranges = ARRAY_SIZE(label ## _ranges), \
491 .linear_ranges = label ## _ranges, \
ba305e31
TK
492 }, \
493 }
494
dab780a3
NR
495#define TWL4030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \
496 remap_conf) \
0ffff5a6 497static const struct twlreg_info TWLFIXED_INFO_##label = { \
fa16a5c1
DB
498 .base = offset, \
499 .id = num, \
045f972f 500 .remap = remap_conf, \
fa16a5c1
DB
501 .desc = { \
502 .name = #label, \
dab780a3 503 .id = TWL4030##_REG_##label, \
66b659e6 504 .n_voltages = 1, \
dab780a3 505 .ops = &twl4030fixed_ops, \
fa16a5c1
DB
506 .type = REGULATOR_VOLTAGE, \
507 .owner = THIS_MODULE, \
b3816d50 508 .min_uV = mVolts * 1000, \
fca53d86 509 .enable_time = turnon_delay, \
dab780a3 510 .of_map_mode = twl4030reg_map_mode, \
8e6de4a3
B
511 }, \
512 }
513
fa16a5c1
DB
514/*
515 * We list regulators here if systems need some level of
516 * software control over them after boot.
517 */
2098e95c
RN
518TWL4030_ADJUSTABLE_LDO(VAUX1, 0x17, 1, 100, 0x08);
519TWL4030_ADJUSTABLE_LDO(VAUX2_4030, 0x1b, 2, 100, 0x08);
520TWL4030_ADJUSTABLE_LDO(VAUX2, 0x1b, 2, 100, 0x08);
521TWL4030_ADJUSTABLE_LDO(VAUX3, 0x1f, 3, 100, 0x08);
522TWL4030_ADJUSTABLE_LDO(VAUX4, 0x23, 4, 100, 0x08);
523TWL4030_ADJUSTABLE_LDO(VMMC1, 0x27, 5, 100, 0x08);
524TWL4030_ADJUSTABLE_LDO(VMMC2, 0x2b, 6, 100, 0x08);
525TWL4030_ADJUSTABLE_LDO(VPLL1, 0x2f, 7, 100, 0x00);
526TWL4030_ADJUSTABLE_LDO(VPLL2, 0x33, 8, 100, 0x08);
527TWL4030_ADJUSTABLE_LDO(VSIM, 0x37, 9, 100, 0x00);
528TWL4030_ADJUSTABLE_LDO(VDAC, 0x3b, 10, 100, 0x08);
529TWL4030_ADJUSTABLE_LDO(VINTANA2, 0x43, 12, 100, 0x08);
530TWL4030_ADJUSTABLE_LDO(VIO, 0x4b, 14, 1000, 0x08);
3829100a
AK
531TWL4030_ADJUSTABLE_SMPS(VDD1, 0x55, 15, 1000, 0x08, 68);
532TWL4030_ADJUSTABLE_SMPS(VDD2, 0x63, 16, 1000, 0x08, 69);
2098e95c 533/* VUSBCP is managed *only* by the USB subchip */
908d6d52 534TWL4030_FIXED_LDO(VINTANA1, 0x3f, 1500, 11, 100, 0x08);
2098e95c
RN
535TWL4030_FIXED_LDO(VINTDIG, 0x47, 1500, 13, 100, 0x08);
536TWL4030_FIXED_LDO(VUSB1V5, 0x71, 1500, 17, 100, 0x08);
537TWL4030_FIXED_LDO(VUSB1V8, 0x74, 1800, 18, 100, 0x08);
538TWL4030_FIXED_LDO(VUSB3V1, 0x77, 3100, 19, 150, 0x08);
4d94aee5 539
2098e95c
RN
540#define TWL_OF_MATCH(comp, family, label) \
541 { \
542 .compatible = comp, \
543 .data = &family##_INFO_##label, \
544 }
545
546#define TWL4030_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL4030, label)
547#define TWL6030_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6030, label)
89ce43fb 548#define TWL6032_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6032, label)
2098e95c 549#define TWLFIXED_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLFIXED, label)
2098e95c
RN
550#define TWLSMPS_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLSMPS, label)
551
3d68dfe3 552static const struct of_device_id twl_of_match[] = {
2098e95c
RN
553 TWL4030_OF_MATCH("ti,twl4030-vaux1", VAUX1),
554 TWL4030_OF_MATCH("ti,twl4030-vaux2", VAUX2_4030),
555 TWL4030_OF_MATCH("ti,twl5030-vaux2", VAUX2),
556 TWL4030_OF_MATCH("ti,twl4030-vaux3", VAUX3),
557 TWL4030_OF_MATCH("ti,twl4030-vaux4", VAUX4),
558 TWL4030_OF_MATCH("ti,twl4030-vmmc1", VMMC1),
559 TWL4030_OF_MATCH("ti,twl4030-vmmc2", VMMC2),
560 TWL4030_OF_MATCH("ti,twl4030-vpll1", VPLL1),
561 TWL4030_OF_MATCH("ti,twl4030-vpll2", VPLL2),
562 TWL4030_OF_MATCH("ti,twl4030-vsim", VSIM),
563 TWL4030_OF_MATCH("ti,twl4030-vdac", VDAC),
564 TWL4030_OF_MATCH("ti,twl4030-vintana2", VINTANA2),
565 TWL4030_OF_MATCH("ti,twl4030-vio", VIO),
566 TWL4030_OF_MATCH("ti,twl4030-vdd1", VDD1),
567 TWL4030_OF_MATCH("ti,twl4030-vdd2", VDD2),
908d6d52 568 TWLFIXED_OF_MATCH("ti,twl4030-vintana1", VINTANA1),
2098e95c
RN
569 TWLFIXED_OF_MATCH("ti,twl4030-vintdig", VINTDIG),
570 TWLFIXED_OF_MATCH("ti,twl4030-vusb1v5", VUSB1V5),
571 TWLFIXED_OF_MATCH("ti,twl4030-vusb1v8", VUSB1V8),
572 TWLFIXED_OF_MATCH("ti,twl4030-vusb3v1", VUSB3V1),
2098e95c
RN
573 {},
574};
575MODULE_DEVICE_TABLE(of, twl_of_match);
576
a5023574 577static int twlreg_probe(struct platform_device *pdev)
fa16a5c1 578{
8313a4fb 579 int id;
fa16a5c1 580 struct twlreg_info *info;
0ffff5a6 581 const struct twlreg_info *template;
fa16a5c1
DB
582 struct regulator_init_data *initdata;
583 struct regulation_constraints *c;
584 struct regulator_dev *rdev;
c172708d 585 struct regulator_config config = { };
2098e95c 586
93997a05 587 template = of_device_get_match_data(&pdev->dev);
0ffff5a6 588 if (!template)
fa16a5c1
DB
589 return -ENODEV;
590
25d82337
NR
591 id = template->desc.id;
592 initdata = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node,
593 &template->desc);
fa16a5c1
DB
594 if (!initdata)
595 return -EINVAL;
596
cd01e32d 597 info = devm_kmemdup(&pdev->dev, template, sizeof(*info), GFP_KERNEL);
0ffff5a6
AB
598 if (!info)
599 return -ENOMEM;
600
fa16a5c1
DB
601 /* Constrain board-specific capabilities according to what
602 * this driver and the chip itself can actually do.
603 */
604 c = &initdata->constraints;
fa16a5c1
DB
605 c->valid_modes_mask &= REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY;
606 c->valid_ops_mask &= REGULATOR_CHANGE_VOLTAGE
607 | REGULATOR_CHANGE_MODE
608 | REGULATOR_CHANGE_STATUS;
2098e95c 609 switch (id) {
205e5cd3
JKS
610 case TWL4030_REG_VIO:
611 case TWL4030_REG_VDD1:
612 case TWL4030_REG_VDD2:
613 case TWL4030_REG_VPLL1:
614 case TWL4030_REG_VINTANA1:
615 case TWL4030_REG_VINTANA2:
616 case TWL4030_REG_VINTDIG:
617 c->always_on = true;
618 break;
619 default:
620 break;
621 }
fa16a5c1 622
c172708d
MB
623 config.dev = &pdev->dev;
624 config.init_data = initdata;
625 config.driver_data = info;
626 config.of_node = pdev->dev.of_node;
627
00ce070e 628 rdev = devm_regulator_register(&pdev->dev, &info->desc, &config);
fa16a5c1
DB
629 if (IS_ERR(rdev)) {
630 dev_err(&pdev->dev, "can't register %s, %ld\n",
631 info->desc.name, PTR_ERR(rdev));
632 return PTR_ERR(rdev);
633 }
634 platform_set_drvdata(pdev, rdev);
635
cac28ae6 636 twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_REMAP, info->remap);
30010fa5 637
fa16a5c1
DB
638 /* NOTE: many regulators support short-circuit IRQs (presentable
639 * as REGULATOR_OVER_CURRENT notifications?) configured via:
640 * - SC_CONFIG
641 * - SC_DETECT1 (vintana2, vmmc1/2, vaux1/2/3/4)
642 * - SC_DETECT2 (vusb, vdac, vio, vdd1/2, vpll2)
643 * - IT_CONFIG
644 */
645
646 return 0;
647}
648
cac28ae6 649MODULE_ALIAS("platform:twl4030_reg");
fa16a5c1 650
c4aa6f31
RN
651static struct platform_driver twlreg_driver = {
652 .probe = twlreg_probe,
fa16a5c1 653 /* NOTE: short name, to work around driver model truncation of
c4aa6f31 654 * "twl_regulator.12" (and friends) to "twl_regulator.1".
fa16a5c1 655 */
2098e95c 656 .driver = {
cac28ae6 657 .name = "twl4030_reg",
259b93b2 658 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2098e95c
RN
659 .of_match_table = of_match_ptr(twl_of_match),
660 },
fa16a5c1
DB
661};
662
c4aa6f31 663static int __init twlreg_init(void)
fa16a5c1 664{
c4aa6f31 665 return platform_driver_register(&twlreg_driver);
fa16a5c1 666}
c4aa6f31 667subsys_initcall(twlreg_init);
fa16a5c1 668
c4aa6f31 669static void __exit twlreg_exit(void)
fa16a5c1 670{
c4aa6f31 671 platform_driver_unregister(&twlreg_driver);
fa16a5c1 672}
c4aa6f31 673module_exit(twlreg_exit)
fa16a5c1 674
cac28ae6 675MODULE_DESCRIPTION("TWL4030 regulator driver");
fa16a5c1 676MODULE_LICENSE("GPL");