Commit | Line | Data |
---|---|---|
518fb721 GG |
1 | /* |
2 | * tps65910.c -- TI tps65910 | |
3 | * | |
4 | * Copyright 2010 Texas Instruments Inc. | |
5 | * | |
6 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
7 | * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
518fb721 GG |
23 | #include <linux/slab.h> |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mfd/tps65910.h> | |
6790178f | 26 | #include <linux/regulator/of_regulator.h> |
518fb721 | 27 | |
518fb721 | 28 | #define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
1e0c66f4 LD |
29 | #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ |
30 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ | |
f30b0716 LD |
31 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ |
32 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
518fb721 | 33 | |
d9fe28f9 AL |
34 | /* supported VIO voltages in microvolts */ |
35 | static const unsigned int VIO_VSEL_table[] = { | |
36 | 1500000, 1800000, 2500000, 3300000, | |
518fb721 GG |
37 | }; |
38 | ||
a320e3c3 JEC |
39 | /* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
40 | ||
a9a5659a AC |
41 | /* supported VRTC voltages in microvolts */ |
42 | static const unsigned int VRTC_VSEL_table[] = { | |
43 | 1800000, | |
44 | }; | |
45 | ||
d9fe28f9 AL |
46 | /* supported VDD3 voltages in microvolts */ |
47 | static const unsigned int VDD3_VSEL_table[] = { | |
48 | 5000000, | |
518fb721 GG |
49 | }; |
50 | ||
d9fe28f9 AL |
51 | /* supported VDIG1 voltages in microvolts */ |
52 | static const unsigned int VDIG1_VSEL_table[] = { | |
53 | 1200000, 1500000, 1800000, 2700000, | |
518fb721 GG |
54 | }; |
55 | ||
d9fe28f9 AL |
56 | /* supported VDIG2 voltages in microvolts */ |
57 | static const unsigned int VDIG2_VSEL_table[] = { | |
58 | 1000000, 1100000, 1200000, 1800000, | |
518fb721 GG |
59 | }; |
60 | ||
d9fe28f9 AL |
61 | /* supported VPLL voltages in microvolts */ |
62 | static const unsigned int VPLL_VSEL_table[] = { | |
63 | 1000000, 1100000, 1800000, 2500000, | |
518fb721 GG |
64 | }; |
65 | ||
d9fe28f9 AL |
66 | /* supported VDAC voltages in microvolts */ |
67 | static const unsigned int VDAC_VSEL_table[] = { | |
68 | 1800000, 2600000, 2800000, 2850000, | |
518fb721 GG |
69 | }; |
70 | ||
d9fe28f9 AL |
71 | /* supported VAUX1 voltages in microvolts */ |
72 | static const unsigned int VAUX1_VSEL_table[] = { | |
73 | 1800000, 2500000, 2800000, 2850000, | |
518fb721 GG |
74 | }; |
75 | ||
d9fe28f9 AL |
76 | /* supported VAUX2 voltages in microvolts */ |
77 | static const unsigned int VAUX2_VSEL_table[] = { | |
78 | 1800000, 2800000, 2900000, 3300000, | |
518fb721 GG |
79 | }; |
80 | ||
d9fe28f9 AL |
81 | /* supported VAUX33 voltages in microvolts */ |
82 | static const unsigned int VAUX33_VSEL_table[] = { | |
83 | 1800000, 2000000, 2800000, 3300000, | |
518fb721 GG |
84 | }; |
85 | ||
d9fe28f9 AL |
86 | /* supported VMMC voltages in microvolts */ |
87 | static const unsigned int VMMC_VSEL_table[] = { | |
88 | 1800000, 2800000, 3000000, 3300000, | |
518fb721 GG |
89 | }; |
90 | ||
91 | struct tps_info { | |
92 | const char *name; | |
19228a6a | 93 | const char *vin_name; |
7d38a3cb | 94 | u8 n_voltages; |
d9fe28f9 | 95 | const unsigned int *voltage_table; |
0651eed5 | 96 | int enable_time_us; |
518fb721 GG |
97 | }; |
98 | ||
99 | static struct tps_info tps65910_regs[] = { | |
100 | { | |
33a6943d | 101 | .name = "vrtc", |
19228a6a | 102 | .vin_name = "vcc7", |
a9a5659a AC |
103 | .n_voltages = ARRAY_SIZE(VRTC_VSEL_table), |
104 | .voltage_table = VRTC_VSEL_table, | |
0651eed5 | 105 | .enable_time_us = 2200, |
518fb721 GG |
106 | }, |
107 | { | |
33a6943d | 108 | .name = "vio", |
19228a6a | 109 | .vin_name = "vccio", |
7d38a3cb LD |
110 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
111 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 112 | .enable_time_us = 350, |
518fb721 GG |
113 | }, |
114 | { | |
33a6943d | 115 | .name = "vdd1", |
19228a6a | 116 | .vin_name = "vcc1", |
0651eed5 | 117 | .enable_time_us = 350, |
518fb721 GG |
118 | }, |
119 | { | |
33a6943d | 120 | .name = "vdd2", |
19228a6a | 121 | .vin_name = "vcc2", |
0651eed5 | 122 | .enable_time_us = 350, |
518fb721 GG |
123 | }, |
124 | { | |
33a6943d | 125 | .name = "vdd3", |
7d38a3cb LD |
126 | .n_voltages = ARRAY_SIZE(VDD3_VSEL_table), |
127 | .voltage_table = VDD3_VSEL_table, | |
0651eed5 | 128 | .enable_time_us = 200, |
518fb721 GG |
129 | }, |
130 | { | |
33a6943d | 131 | .name = "vdig1", |
19228a6a | 132 | .vin_name = "vcc6", |
7d38a3cb LD |
133 | .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), |
134 | .voltage_table = VDIG1_VSEL_table, | |
0651eed5 | 135 | .enable_time_us = 100, |
518fb721 GG |
136 | }, |
137 | { | |
33a6943d | 138 | .name = "vdig2", |
19228a6a | 139 | .vin_name = "vcc6", |
7d38a3cb LD |
140 | .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), |
141 | .voltage_table = VDIG2_VSEL_table, | |
0651eed5 | 142 | .enable_time_us = 100, |
518fb721 GG |
143 | }, |
144 | { | |
33a6943d | 145 | .name = "vpll", |
19228a6a | 146 | .vin_name = "vcc5", |
7d38a3cb LD |
147 | .n_voltages = ARRAY_SIZE(VPLL_VSEL_table), |
148 | .voltage_table = VPLL_VSEL_table, | |
0651eed5 | 149 | .enable_time_us = 100, |
518fb721 GG |
150 | }, |
151 | { | |
33a6943d | 152 | .name = "vdac", |
19228a6a | 153 | .vin_name = "vcc5", |
7d38a3cb LD |
154 | .n_voltages = ARRAY_SIZE(VDAC_VSEL_table), |
155 | .voltage_table = VDAC_VSEL_table, | |
0651eed5 | 156 | .enable_time_us = 100, |
518fb721 GG |
157 | }, |
158 | { | |
33a6943d | 159 | .name = "vaux1", |
19228a6a | 160 | .vin_name = "vcc4", |
7d38a3cb LD |
161 | .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), |
162 | .voltage_table = VAUX1_VSEL_table, | |
0651eed5 | 163 | .enable_time_us = 100, |
518fb721 GG |
164 | }, |
165 | { | |
33a6943d | 166 | .name = "vaux2", |
19228a6a | 167 | .vin_name = "vcc4", |
7d38a3cb LD |
168 | .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), |
169 | .voltage_table = VAUX2_VSEL_table, | |
0651eed5 | 170 | .enable_time_us = 100, |
518fb721 GG |
171 | }, |
172 | { | |
33a6943d | 173 | .name = "vaux33", |
19228a6a | 174 | .vin_name = "vcc3", |
7d38a3cb LD |
175 | .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), |
176 | .voltage_table = VAUX33_VSEL_table, | |
0651eed5 | 177 | .enable_time_us = 100, |
518fb721 GG |
178 | }, |
179 | { | |
33a6943d | 180 | .name = "vmmc", |
19228a6a | 181 | .vin_name = "vcc3", |
7d38a3cb LD |
182 | .n_voltages = ARRAY_SIZE(VMMC_VSEL_table), |
183 | .voltage_table = VMMC_VSEL_table, | |
0651eed5 | 184 | .enable_time_us = 100, |
518fb721 GG |
185 | }, |
186 | }; | |
187 | ||
a320e3c3 | 188 | static struct tps_info tps65911_regs[] = { |
c2f8efd7 | 189 | { |
33a6943d | 190 | .name = "vrtc", |
19228a6a | 191 | .vin_name = "vcc7", |
0651eed5 | 192 | .enable_time_us = 2200, |
c2f8efd7 | 193 | }, |
a320e3c3 | 194 | { |
33a6943d | 195 | .name = "vio", |
19228a6a | 196 | .vin_name = "vccio", |
7d38a3cb LD |
197 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
198 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 199 | .enable_time_us = 350, |
a320e3c3 JEC |
200 | }, |
201 | { | |
33a6943d | 202 | .name = "vdd1", |
19228a6a | 203 | .vin_name = "vcc1", |
7be53188 | 204 | .n_voltages = 0x4C, |
0651eed5 | 205 | .enable_time_us = 350, |
a320e3c3 JEC |
206 | }, |
207 | { | |
33a6943d | 208 | .name = "vdd2", |
19228a6a | 209 | .vin_name = "vcc2", |
7be53188 | 210 | .n_voltages = 0x4C, |
0651eed5 | 211 | .enable_time_us = 350, |
a320e3c3 JEC |
212 | }, |
213 | { | |
33a6943d | 214 | .name = "vddctrl", |
7be53188 | 215 | .n_voltages = 0x44, |
0651eed5 | 216 | .enable_time_us = 900, |
a320e3c3 JEC |
217 | }, |
218 | { | |
33a6943d | 219 | .name = "ldo1", |
19228a6a | 220 | .vin_name = "vcc6", |
7be53188 | 221 | .n_voltages = 0x33, |
0651eed5 | 222 | .enable_time_us = 420, |
a320e3c3 JEC |
223 | }, |
224 | { | |
33a6943d | 225 | .name = "ldo2", |
19228a6a | 226 | .vin_name = "vcc6", |
7be53188 | 227 | .n_voltages = 0x33, |
0651eed5 | 228 | .enable_time_us = 420, |
a320e3c3 JEC |
229 | }, |
230 | { | |
33a6943d | 231 | .name = "ldo3", |
19228a6a | 232 | .vin_name = "vcc5", |
7be53188 | 233 | .n_voltages = 0x1A, |
0651eed5 | 234 | .enable_time_us = 230, |
a320e3c3 JEC |
235 | }, |
236 | { | |
33a6943d | 237 | .name = "ldo4", |
19228a6a | 238 | .vin_name = "vcc5", |
7be53188 | 239 | .n_voltages = 0x33, |
0651eed5 | 240 | .enable_time_us = 230, |
a320e3c3 JEC |
241 | }, |
242 | { | |
33a6943d | 243 | .name = "ldo5", |
19228a6a | 244 | .vin_name = "vcc4", |
7be53188 | 245 | .n_voltages = 0x1A, |
0651eed5 | 246 | .enable_time_us = 230, |
a320e3c3 JEC |
247 | }, |
248 | { | |
33a6943d | 249 | .name = "ldo6", |
19228a6a | 250 | .vin_name = "vcc3", |
7be53188 | 251 | .n_voltages = 0x1A, |
0651eed5 | 252 | .enable_time_us = 230, |
a320e3c3 JEC |
253 | }, |
254 | { | |
33a6943d | 255 | .name = "ldo7", |
19228a6a | 256 | .vin_name = "vcc3", |
7be53188 | 257 | .n_voltages = 0x1A, |
0651eed5 | 258 | .enable_time_us = 230, |
a320e3c3 JEC |
259 | }, |
260 | { | |
33a6943d | 261 | .name = "ldo8", |
19228a6a | 262 | .vin_name = "vcc3", |
7be53188 | 263 | .n_voltages = 0x1A, |
0651eed5 | 264 | .enable_time_us = 230, |
a320e3c3 JEC |
265 | }, |
266 | }; | |
267 | ||
1e0c66f4 LD |
268 | #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) |
269 | static unsigned int tps65910_ext_sleep_control[] = { | |
270 | 0, | |
271 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
272 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
273 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
274 | EXT_CONTROL_REG_BITS(VDD3, 1, 3), | |
275 | EXT_CONTROL_REG_BITS(VDIG1, 0, 1), | |
276 | EXT_CONTROL_REG_BITS(VDIG2, 0, 2), | |
277 | EXT_CONTROL_REG_BITS(VPLL, 0, 6), | |
278 | EXT_CONTROL_REG_BITS(VDAC, 0, 7), | |
279 | EXT_CONTROL_REG_BITS(VAUX1, 0, 3), | |
280 | EXT_CONTROL_REG_BITS(VAUX2, 0, 4), | |
281 | EXT_CONTROL_REG_BITS(VAUX33, 0, 5), | |
282 | EXT_CONTROL_REG_BITS(VMMC, 0, 0), | |
283 | }; | |
284 | ||
285 | static unsigned int tps65911_ext_sleep_control[] = { | |
286 | 0, | |
287 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
288 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
289 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
290 | EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), | |
291 | EXT_CONTROL_REG_BITS(LDO1, 0, 1), | |
292 | EXT_CONTROL_REG_BITS(LDO2, 0, 2), | |
293 | EXT_CONTROL_REG_BITS(LDO3, 0, 7), | |
294 | EXT_CONTROL_REG_BITS(LDO4, 0, 6), | |
295 | EXT_CONTROL_REG_BITS(LDO5, 0, 3), | |
296 | EXT_CONTROL_REG_BITS(LDO6, 0, 0), | |
297 | EXT_CONTROL_REG_BITS(LDO7, 0, 5), | |
298 | EXT_CONTROL_REG_BITS(LDO8, 0, 4), | |
299 | }; | |
300 | ||
518fb721 | 301 | struct tps65910_reg { |
39aa9b6e | 302 | struct regulator_desc *desc; |
518fb721 | 303 | struct tps65910 *mfd; |
39aa9b6e AL |
304 | struct regulator_dev **rdev; |
305 | struct tps_info **info; | |
39aa9b6e | 306 | int num_regulators; |
518fb721 | 307 | int mode; |
a320e3c3 | 308 | int (*get_ctrl_reg)(int); |
1e0c66f4 LD |
309 | unsigned int *ext_sleep_control; |
310 | unsigned int board_ext_control[TPS65910_NUM_REGS]; | |
518fb721 GG |
311 | }; |
312 | ||
518fb721 GG |
313 | static int tps65910_get_ctrl_register(int id) |
314 | { | |
315 | switch (id) { | |
316 | case TPS65910_REG_VRTC: | |
317 | return TPS65910_VRTC; | |
318 | case TPS65910_REG_VIO: | |
319 | return TPS65910_VIO; | |
320 | case TPS65910_REG_VDD1: | |
321 | return TPS65910_VDD1; | |
322 | case TPS65910_REG_VDD2: | |
323 | return TPS65910_VDD2; | |
324 | case TPS65910_REG_VDD3: | |
325 | return TPS65910_VDD3; | |
326 | case TPS65910_REG_VDIG1: | |
327 | return TPS65910_VDIG1; | |
328 | case TPS65910_REG_VDIG2: | |
329 | return TPS65910_VDIG2; | |
330 | case TPS65910_REG_VPLL: | |
331 | return TPS65910_VPLL; | |
332 | case TPS65910_REG_VDAC: | |
333 | return TPS65910_VDAC; | |
334 | case TPS65910_REG_VAUX1: | |
335 | return TPS65910_VAUX1; | |
336 | case TPS65910_REG_VAUX2: | |
337 | return TPS65910_VAUX2; | |
338 | case TPS65910_REG_VAUX33: | |
339 | return TPS65910_VAUX33; | |
340 | case TPS65910_REG_VMMC: | |
341 | return TPS65910_VMMC; | |
342 | default: | |
343 | return -EINVAL; | |
344 | } | |
345 | } | |
346 | ||
a320e3c3 JEC |
347 | static int tps65911_get_ctrl_register(int id) |
348 | { | |
349 | switch (id) { | |
350 | case TPS65910_REG_VRTC: | |
351 | return TPS65910_VRTC; | |
352 | case TPS65910_REG_VIO: | |
353 | return TPS65910_VIO; | |
354 | case TPS65910_REG_VDD1: | |
355 | return TPS65910_VDD1; | |
356 | case TPS65910_REG_VDD2: | |
357 | return TPS65910_VDD2; | |
358 | case TPS65911_REG_VDDCTRL: | |
359 | return TPS65911_VDDCTRL; | |
360 | case TPS65911_REG_LDO1: | |
361 | return TPS65911_LDO1; | |
362 | case TPS65911_REG_LDO2: | |
363 | return TPS65911_LDO2; | |
364 | case TPS65911_REG_LDO3: | |
365 | return TPS65911_LDO3; | |
366 | case TPS65911_REG_LDO4: | |
367 | return TPS65911_LDO4; | |
368 | case TPS65911_REG_LDO5: | |
369 | return TPS65911_LDO5; | |
370 | case TPS65911_REG_LDO6: | |
371 | return TPS65911_LDO6; | |
372 | case TPS65911_REG_LDO7: | |
373 | return TPS65911_LDO7; | |
374 | case TPS65911_REG_LDO8: | |
375 | return TPS65911_LDO8; | |
376 | default: | |
377 | return -EINVAL; | |
378 | } | |
379 | } | |
380 | ||
518fb721 GG |
381 | static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) |
382 | { | |
383 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
384 | struct tps65910 *mfd = pmic->mfd; | |
385 | int reg, value, id = rdev_get_id(dev); | |
a320e3c3 JEC |
386 | |
387 | reg = pmic->get_ctrl_reg(id); | |
518fb721 GG |
388 | if (reg < 0) |
389 | return reg; | |
390 | ||
391 | switch (mode) { | |
392 | case REGULATOR_MODE_NORMAL: | |
faa95fde AL |
393 | return tps65910_reg_update_bits(pmic->mfd, reg, |
394 | LDO_ST_MODE_BIT | LDO_ST_ON_BIT, | |
395 | LDO_ST_ON_BIT); | |
518fb721 GG |
396 | case REGULATOR_MODE_IDLE: |
397 | value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; | |
3f7e8275 | 398 | return tps65910_reg_set_bits(mfd, reg, value); |
518fb721 | 399 | case REGULATOR_MODE_STANDBY: |
3f7e8275 | 400 | return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); |
518fb721 GG |
401 | } |
402 | ||
403 | return -EINVAL; | |
404 | } | |
405 | ||
406 | static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |
407 | { | |
408 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde | 409 | int ret, reg, value, id = rdev_get_id(dev); |
518fb721 | 410 | |
a320e3c3 | 411 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
412 | if (reg < 0) |
413 | return reg; | |
414 | ||
faa95fde AL |
415 | ret = tps65910_reg_read(pmic->mfd, reg, &value); |
416 | if (ret < 0) | |
417 | return ret; | |
518fb721 | 418 | |
58599393 | 419 | if (!(value & LDO_ST_ON_BIT)) |
518fb721 GG |
420 | return REGULATOR_MODE_STANDBY; |
421 | else if (value & LDO_ST_MODE_BIT) | |
422 | return REGULATOR_MODE_IDLE; | |
423 | else | |
424 | return REGULATOR_MODE_NORMAL; | |
425 | } | |
426 | ||
18039e0f | 427 | static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
518fb721 GG |
428 | { |
429 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde | 430 | int ret, id = rdev_get_id(dev); |
a320e3c3 | 431 | int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
518fb721 GG |
432 | |
433 | switch (id) { | |
434 | case TPS65910_REG_VDD1: | |
faa95fde AL |
435 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_OP, &opvsel); |
436 | if (ret < 0) | |
437 | return ret; | |
438 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1, &mult); | |
439 | if (ret < 0) | |
440 | return ret; | |
518fb721 | 441 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
faa95fde AL |
442 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_SR, &srvsel); |
443 | if (ret < 0) | |
444 | return ret; | |
518fb721 GG |
445 | sr = opvsel & VDD1_OP_CMD_MASK; |
446 | opvsel &= VDD1_OP_SEL_MASK; | |
447 | srvsel &= VDD1_SR_SEL_MASK; | |
a320e3c3 | 448 | vselmax = 75; |
518fb721 GG |
449 | break; |
450 | case TPS65910_REG_VDD2: | |
faa95fde AL |
451 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_OP, &opvsel); |
452 | if (ret < 0) | |
453 | return ret; | |
454 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2, &mult); | |
455 | if (ret < 0) | |
456 | return ret; | |
518fb721 | 457 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
faa95fde AL |
458 | ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_SR, &srvsel); |
459 | if (ret < 0) | |
460 | return ret; | |
518fb721 GG |
461 | sr = opvsel & VDD2_OP_CMD_MASK; |
462 | opvsel &= VDD2_OP_SEL_MASK; | |
463 | srvsel &= VDD2_SR_SEL_MASK; | |
a320e3c3 JEC |
464 | vselmax = 75; |
465 | break; | |
466 | case TPS65911_REG_VDDCTRL: | |
faa95fde AL |
467 | ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_OP, |
468 | &opvsel); | |
469 | if (ret < 0) | |
470 | return ret; | |
471 | ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_SR, | |
472 | &srvsel); | |
473 | if (ret < 0) | |
474 | return ret; | |
a320e3c3 JEC |
475 | sr = opvsel & VDDCTRL_OP_CMD_MASK; |
476 | opvsel &= VDDCTRL_OP_SEL_MASK; | |
477 | srvsel &= VDDCTRL_SR_SEL_MASK; | |
478 | vselmax = 64; | |
518fb721 GG |
479 | break; |
480 | } | |
481 | ||
482 | /* multiplier 0 == 1 but 2,3 normal */ | |
483 | if (!mult) | |
484 | mult=1; | |
485 | ||
486 | if (sr) { | |
a320e3c3 JEC |
487 | /* normalise to valid range */ |
488 | if (srvsel < 3) | |
489 | srvsel = 3; | |
490 | if (srvsel > vselmax) | |
491 | srvsel = vselmax; | |
18039e0f | 492 | return srvsel - 3; |
518fb721 GG |
493 | } else { |
494 | ||
a320e3c3 JEC |
495 | /* normalise to valid range*/ |
496 | if (opvsel < 3) | |
497 | opvsel = 3; | |
498 | if (opvsel > vselmax) | |
499 | opvsel = vselmax; | |
18039e0f | 500 | return opvsel - 3; |
518fb721 | 501 | } |
18039e0f | 502 | return -EINVAL; |
518fb721 GG |
503 | } |
504 | ||
1f904fd1 | 505 | static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721 GG |
506 | { |
507 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde | 508 | int ret, reg, value, id = rdev_get_id(dev); |
518fb721 | 509 | |
a320e3c3 | 510 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
511 | if (reg < 0) |
512 | return reg; | |
513 | ||
faa95fde AL |
514 | ret = tps65910_reg_read(pmic->mfd, reg, &value); |
515 | if (ret < 0) | |
516 | return ret; | |
518fb721 GG |
517 | |
518 | switch (id) { | |
519 | case TPS65910_REG_VIO: | |
520 | case TPS65910_REG_VDIG1: | |
521 | case TPS65910_REG_VDIG2: | |
522 | case TPS65910_REG_VPLL: | |
523 | case TPS65910_REG_VDAC: | |
524 | case TPS65910_REG_VAUX1: | |
525 | case TPS65910_REG_VAUX2: | |
526 | case TPS65910_REG_VAUX33: | |
527 | case TPS65910_REG_VMMC: | |
528 | value &= LDO_SEL_MASK; | |
529 | value >>= LDO_SEL_SHIFT; | |
530 | break; | |
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
534 | ||
1f904fd1 | 535 | return value; |
518fb721 GG |
536 | } |
537 | ||
538 | static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) | |
539 | { | |
d9fe28f9 | 540 | return dev->desc->volt_table[0]; |
518fb721 GG |
541 | } |
542 | ||
1f904fd1 | 543 | static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3 JEC |
544 | { |
545 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
faa95fde AL |
546 | int ret, id = rdev_get_id(dev); |
547 | unsigned int value, reg; | |
a320e3c3 JEC |
548 | |
549 | reg = pmic->get_ctrl_reg(id); | |
550 | ||
faa95fde AL |
551 | ret = tps65910_reg_read(pmic->mfd, reg, &value); |
552 | if (ret < 0) | |
553 | return ret; | |
a320e3c3 JEC |
554 | |
555 | switch (id) { | |
556 | case TPS65911_REG_LDO1: | |
557 | case TPS65911_REG_LDO2: | |
558 | case TPS65911_REG_LDO4: | |
559 | value &= LDO1_SEL_MASK; | |
560 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
561 | break; |
562 | case TPS65911_REG_LDO3: | |
563 | case TPS65911_REG_LDO5: | |
564 | case TPS65911_REG_LDO6: | |
565 | case TPS65911_REG_LDO7: | |
566 | case TPS65911_REG_LDO8: | |
567 | value &= LDO3_SEL_MASK; | |
568 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
569 | break; |
570 | case TPS65910_REG_VIO: | |
e882eae8 LD |
571 | value &= LDO_SEL_MASK; |
572 | value >>= LDO_SEL_SHIFT; | |
1f904fd1 | 573 | break; |
a320e3c3 JEC |
574 | default: |
575 | return -EINVAL; | |
576 | } | |
577 | ||
1f904fd1 | 578 | return value; |
a320e3c3 JEC |
579 | } |
580 | ||
94732b97 AL |
581 | static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, |
582 | unsigned selector) | |
518fb721 GG |
583 | { |
584 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
585 | int id = rdev_get_id(dev), vsel; | |
a320e3c3 | 586 | int dcdc_mult = 0; |
518fb721 | 587 | |
a320e3c3 JEC |
588 | switch (id) { |
589 | case TPS65910_REG_VDD1: | |
780dc9ba | 590 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
591 | if (dcdc_mult == 1) |
592 | dcdc_mult--; | |
780dc9ba | 593 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721 | 594 | |
faa95fde AL |
595 | tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD1, |
596 | VDD1_VGAIN_SEL_MASK, | |
597 | dcdc_mult << VDD1_VGAIN_SEL_SHIFT); | |
598 | tps65910_reg_write(pmic->mfd, TPS65910_VDD1_OP, vsel); | |
a320e3c3 JEC |
599 | break; |
600 | case TPS65910_REG_VDD2: | |
780dc9ba | 601 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
602 | if (dcdc_mult == 1) |
603 | dcdc_mult--; | |
780dc9ba | 604 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3 | 605 | |
faa95fde AL |
606 | tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD2, |
607 | VDD1_VGAIN_SEL_MASK, | |
608 | dcdc_mult << VDD2_VGAIN_SEL_SHIFT); | |
609 | tps65910_reg_write(pmic->mfd, TPS65910_VDD2_OP, vsel); | |
a320e3c3 JEC |
610 | break; |
611 | case TPS65911_REG_VDDCTRL: | |
c4632aed | 612 | vsel = selector + 3; |
faa95fde | 613 | tps65910_reg_write(pmic->mfd, TPS65911_VDDCTRL_OP, vsel); |
518fb721 GG |
614 | } |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
94732b97 AL |
619 | static int tps65910_set_voltage_sel(struct regulator_dev *dev, |
620 | unsigned selector) | |
518fb721 GG |
621 | { |
622 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
623 | int reg, id = rdev_get_id(dev); | |
624 | ||
a320e3c3 | 625 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
626 | if (reg < 0) |
627 | return reg; | |
628 | ||
629 | switch (id) { | |
630 | case TPS65910_REG_VIO: | |
631 | case TPS65910_REG_VDIG1: | |
632 | case TPS65910_REG_VDIG2: | |
633 | case TPS65910_REG_VPLL: | |
634 | case TPS65910_REG_VDAC: | |
635 | case TPS65910_REG_VAUX1: | |
636 | case TPS65910_REG_VAUX2: | |
637 | case TPS65910_REG_VAUX33: | |
638 | case TPS65910_REG_VMMC: | |
faa95fde AL |
639 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, |
640 | selector << LDO_SEL_SHIFT); | |
518fb721 GG |
641 | } |
642 | ||
643 | return -EINVAL; | |
644 | } | |
645 | ||
94732b97 AL |
646 | static int tps65911_set_voltage_sel(struct regulator_dev *dev, |
647 | unsigned selector) | |
a320e3c3 JEC |
648 | { |
649 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
650 | int reg, id = rdev_get_id(dev); | |
651 | ||
652 | reg = pmic->get_ctrl_reg(id); | |
653 | if (reg < 0) | |
654 | return reg; | |
655 | ||
656 | switch (id) { | |
657 | case TPS65911_REG_LDO1: | |
658 | case TPS65911_REG_LDO2: | |
659 | case TPS65911_REG_LDO4: | |
faa95fde AL |
660 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK, |
661 | selector << LDO_SEL_SHIFT); | |
a320e3c3 JEC |
662 | case TPS65911_REG_LDO3: |
663 | case TPS65911_REG_LDO5: | |
664 | case TPS65911_REG_LDO6: | |
665 | case TPS65911_REG_LDO7: | |
666 | case TPS65911_REG_LDO8: | |
faa95fde AL |
667 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK, |
668 | selector << LDO_SEL_SHIFT); | |
e882eae8 | 669 | case TPS65910_REG_VIO: |
faa95fde AL |
670 | return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, |
671 | selector << LDO_SEL_SHIFT); | |
a320e3c3 JEC |
672 | } |
673 | ||
674 | return -EINVAL; | |
675 | } | |
676 | ||
677 | ||
518fb721 GG |
678 | static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, |
679 | unsigned selector) | |
680 | { | |
a320e3c3 | 681 | int volt, mult = 1, id = rdev_get_id(dev); |
518fb721 | 682 | |
a320e3c3 JEC |
683 | switch (id) { |
684 | case TPS65910_REG_VDD1: | |
685 | case TPS65910_REG_VDD2: | |
780dc9ba | 686 | mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 | 687 | volt = VDD1_2_MIN_VOLT + |
780dc9ba | 688 | (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bc | 689 | break; |
a320e3c3 JEC |
690 | case TPS65911_REG_VDDCTRL: |
691 | volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); | |
d04156bc AL |
692 | break; |
693 | default: | |
694 | BUG(); | |
695 | return -EINVAL; | |
a320e3c3 | 696 | } |
518fb721 GG |
697 | |
698 | return volt * 100 * mult; | |
699 | } | |
700 | ||
a320e3c3 JEC |
701 | static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) |
702 | { | |
703 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
704 | int step_mv = 0, id = rdev_get_id(dev); | |
705 | ||
706 | switch(id) { | |
707 | case TPS65911_REG_LDO1: | |
708 | case TPS65911_REG_LDO2: | |
709 | case TPS65911_REG_LDO4: | |
710 | /* The first 5 values of the selector correspond to 1V */ | |
711 | if (selector < 5) | |
712 | selector = 0; | |
713 | else | |
714 | selector -= 4; | |
715 | ||
716 | step_mv = 50; | |
717 | break; | |
718 | case TPS65911_REG_LDO3: | |
719 | case TPS65911_REG_LDO5: | |
720 | case TPS65911_REG_LDO6: | |
721 | case TPS65911_REG_LDO7: | |
722 | case TPS65911_REG_LDO8: | |
723 | /* The first 3 values of the selector correspond to 1V */ | |
724 | if (selector < 3) | |
725 | selector = 0; | |
726 | else | |
727 | selector -= 2; | |
728 | ||
729 | step_mv = 100; | |
730 | break; | |
731 | case TPS65910_REG_VIO: | |
d9fe28f9 | 732 | return pmic->info[id]->voltage_table[selector]; |
a320e3c3 JEC |
733 | default: |
734 | return -EINVAL; | |
735 | } | |
736 | ||
737 | return (LDO_MIN_VOLT + selector * step_mv) * 1000; | |
738 | } | |
739 | ||
518fb721 GG |
740 | /* Regulator ops (except VRTC) */ |
741 | static struct regulator_ops tps65910_ops_dcdc = { | |
a40a9c43 AL |
742 | .is_enabled = regulator_is_enabled_regmap, |
743 | .enable = regulator_enable_regmap, | |
744 | .disable = regulator_disable_regmap, | |
518fb721 GG |
745 | .set_mode = tps65910_set_mode, |
746 | .get_mode = tps65910_get_mode, | |
18039e0f | 747 | .get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97 | 748 | .set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
01bc3a14 | 749 | .set_voltage_time_sel = regulator_set_voltage_time_sel, |
518fb721 | 750 | .list_voltage = tps65910_list_voltage_dcdc, |
9fa8175f | 751 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
752 | }; |
753 | ||
754 | static struct regulator_ops tps65910_ops_vdd3 = { | |
a40a9c43 AL |
755 | .is_enabled = regulator_is_enabled_regmap, |
756 | .enable = regulator_enable_regmap, | |
757 | .disable = regulator_disable_regmap, | |
518fb721 GG |
758 | .set_mode = tps65910_set_mode, |
759 | .get_mode = tps65910_get_mode, | |
760 | .get_voltage = tps65910_get_voltage_vdd3, | |
d9fe28f9 | 761 | .list_voltage = regulator_list_voltage_table, |
9fa8175f | 762 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
763 | }; |
764 | ||
765 | static struct regulator_ops tps65910_ops = { | |
a40a9c43 AL |
766 | .is_enabled = regulator_is_enabled_regmap, |
767 | .enable = regulator_enable_regmap, | |
768 | .disable = regulator_disable_regmap, | |
518fb721 GG |
769 | .set_mode = tps65910_set_mode, |
770 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 771 | .get_voltage_sel = tps65910_get_voltage_sel, |
94732b97 | 772 | .set_voltage_sel = tps65910_set_voltage_sel, |
d9fe28f9 | 773 | .list_voltage = regulator_list_voltage_table, |
9fa8175f | 774 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
775 | }; |
776 | ||
a320e3c3 | 777 | static struct regulator_ops tps65911_ops = { |
a40a9c43 AL |
778 | .is_enabled = regulator_is_enabled_regmap, |
779 | .enable = regulator_enable_regmap, | |
780 | .disable = regulator_disable_regmap, | |
a320e3c3 JEC |
781 | .set_mode = tps65910_set_mode, |
782 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 783 | .get_voltage_sel = tps65911_get_voltage_sel, |
94732b97 | 784 | .set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3 | 785 | .list_voltage = tps65911_list_voltage, |
9fa8175f | 786 | .map_voltage = regulator_map_voltage_ascend, |
a320e3c3 JEC |
787 | }; |
788 | ||
1e0c66f4 LD |
789 | static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, |
790 | int id, int ext_sleep_config) | |
791 | { | |
792 | struct tps65910 *mfd = pmic->mfd; | |
793 | u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; | |
794 | u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); | |
795 | int ret; | |
796 | ||
797 | /* | |
798 | * Regulator can not be control from multiple external input EN1, EN2 | |
799 | * and EN3 together. | |
800 | */ | |
801 | if (ext_sleep_config & EXT_SLEEP_CONTROL) { | |
802 | int en_count; | |
803 | en_count = ((ext_sleep_config & | |
804 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); | |
805 | en_count += ((ext_sleep_config & | |
806 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); | |
807 | en_count += ((ext_sleep_config & | |
808 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); | |
f30b0716 LD |
809 | en_count += ((ext_sleep_config & |
810 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); | |
1e0c66f4 LD |
811 | if (en_count > 1) { |
812 | dev_err(mfd->dev, | |
813 | "External sleep control flag is not proper\n"); | |
814 | return -EINVAL; | |
815 | } | |
816 | } | |
817 | ||
818 | pmic->board_ext_control[id] = ext_sleep_config; | |
819 | ||
820 | /* External EN1 control */ | |
821 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | |
3f7e8275 | 822 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
823 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
824 | else | |
3f7e8275 | 825 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
826 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
827 | if (ret < 0) { | |
828 | dev_err(mfd->dev, | |
829 | "Error in configuring external control EN1\n"); | |
830 | return ret; | |
831 | } | |
832 | ||
833 | /* External EN2 control */ | |
834 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | |
3f7e8275 | 835 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
836 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
837 | else | |
3f7e8275 | 838 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
839 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
840 | if (ret < 0) { | |
841 | dev_err(mfd->dev, | |
842 | "Error in configuring external control EN2\n"); | |
843 | return ret; | |
844 | } | |
845 | ||
846 | /* External EN3 control for TPS65910 LDO only */ | |
847 | if ((tps65910_chip_id(mfd) == TPS65910) && | |
848 | (id >= TPS65910_REG_VDIG1)) { | |
849 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | |
3f7e8275 | 850 | ret = tps65910_reg_set_bits(mfd, |
1e0c66f4 LD |
851 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
852 | else | |
3f7e8275 | 853 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
854 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
855 | if (ret < 0) { | |
856 | dev_err(mfd->dev, | |
857 | "Error in configuring external control EN3\n"); | |
858 | return ret; | |
859 | } | |
860 | } | |
861 | ||
862 | /* Return if no external control is selected */ | |
863 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | |
864 | /* Clear all sleep controls */ | |
3f7e8275 | 865 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
866 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
867 | if (!ret) | |
3f7e8275 | 868 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 LD |
869 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
870 | if (ret < 0) | |
871 | dev_err(mfd->dev, | |
872 | "Error in configuring SLEEP register\n"); | |
873 | return ret; | |
874 | } | |
875 | ||
876 | /* | |
877 | * For regulator that has separate operational and sleep register make | |
878 | * sure that operational is used and clear sleep register to turn | |
879 | * regulator off when external control is inactive | |
880 | */ | |
881 | if ((id == TPS65910_REG_VDD1) || | |
882 | (id == TPS65910_REG_VDD2) || | |
883 | ((id == TPS65911_REG_VDDCTRL) && | |
884 | (tps65910_chip_id(mfd) == TPS65911))) { | |
885 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | |
886 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | |
faa95fde AL |
887 | int opvsel, srvsel; |
888 | ||
889 | ret = tps65910_reg_read(pmic->mfd, op_reg_add, &opvsel); | |
890 | if (ret < 0) | |
891 | return ret; | |
892 | ret = tps65910_reg_read(pmic->mfd, sr_reg_add, &srvsel); | |
893 | if (ret < 0) | |
894 | return ret; | |
895 | ||
1e0c66f4 LD |
896 | if (opvsel & VDD1_OP_CMD_MASK) { |
897 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | |
faa95fde AL |
898 | |
899 | ret = tps65910_reg_write(pmic->mfd, op_reg_add, | |
900 | reg_val); | |
1e0c66f4 LD |
901 | if (ret < 0) { |
902 | dev_err(mfd->dev, | |
903 | "Error in configuring op register\n"); | |
904 | return ret; | |
905 | } | |
906 | } | |
faa95fde | 907 | ret = tps65910_reg_write(pmic->mfd, sr_reg_add, 0); |
1e0c66f4 LD |
908 | if (ret < 0) { |
909 | dev_err(mfd->dev, "Error in settting sr register\n"); | |
910 | return ret; | |
911 | } | |
912 | } | |
913 | ||
3f7e8275 | 914 | ret = tps65910_reg_clear_bits(mfd, |
1e0c66f4 | 915 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
f30b0716 LD |
916 | if (!ret) { |
917 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
3f7e8275 | 918 | ret = tps65910_reg_set_bits(mfd, |
f30b0716 LD |
919 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
920 | else | |
3f7e8275 | 921 | ret = tps65910_reg_clear_bits(mfd, |
f30b0716 LD |
922 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
923 | } | |
1e0c66f4 LD |
924 | if (ret < 0) |
925 | dev_err(mfd->dev, | |
926 | "Error in configuring SLEEP register\n"); | |
f30b0716 | 927 | |
1e0c66f4 LD |
928 | return ret; |
929 | } | |
930 | ||
6790178f RK |
931 | #ifdef CONFIG_OF |
932 | ||
933 | static struct of_regulator_match tps65910_matches[] = { | |
33a6943d LD |
934 | { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, |
935 | { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, | |
936 | { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, | |
937 | { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, | |
938 | { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, | |
939 | { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, | |
940 | { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, | |
941 | { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, | |
942 | { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, | |
943 | { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, | |
944 | { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, | |
945 | { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, | |
946 | { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, | |
6790178f RK |
947 | }; |
948 | ||
949 | static struct of_regulator_match tps65911_matches[] = { | |
33a6943d LD |
950 | { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, |
951 | { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, | |
952 | { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, | |
953 | { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, | |
954 | { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, | |
955 | { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, | |
956 | { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, | |
957 | { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, | |
958 | { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, | |
959 | { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, | |
960 | { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, | |
961 | { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, | |
962 | { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, | |
6790178f RK |
963 | }; |
964 | ||
965 | static struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
966 | struct platform_device *pdev, |
967 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f RK |
968 | { |
969 | struct tps65910_board *pmic_plat_data; | |
970 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c92f5dd2 | 971 | struct device_node *np, *regulators; |
6790178f RK |
972 | struct of_regulator_match *matches; |
973 | unsigned int prop; | |
974 | int idx = 0, ret, count; | |
975 | ||
976 | pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), | |
977 | GFP_KERNEL); | |
978 | ||
979 | if (!pmic_plat_data) { | |
980 | dev_err(&pdev->dev, "Failure to alloc pdata for regulators.\n"); | |
981 | return NULL; | |
982 | } | |
983 | ||
c92f5dd2 | 984 | np = of_node_get(pdev->dev.parent->of_node); |
6790178f | 985 | regulators = of_find_node_by_name(np, "regulators"); |
92ab953b LD |
986 | if (!regulators) { |
987 | dev_err(&pdev->dev, "regulator node not found\n"); | |
988 | return NULL; | |
989 | } | |
6790178f RK |
990 | |
991 | switch (tps65910_chip_id(tps65910)) { | |
992 | case TPS65910: | |
993 | count = ARRAY_SIZE(tps65910_matches); | |
994 | matches = tps65910_matches; | |
995 | break; | |
996 | case TPS65911: | |
997 | count = ARRAY_SIZE(tps65911_matches); | |
998 | matches = tps65911_matches; | |
999 | break; | |
1000 | default: | |
c92f5dd2 | 1001 | of_node_put(regulators); |
7e9a57e6 | 1002 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
6790178f RK |
1003 | return NULL; |
1004 | } | |
1005 | ||
08337fda | 1006 | ret = of_regulator_match(&pdev->dev, regulators, matches, count); |
c92f5dd2 | 1007 | of_node_put(regulators); |
6790178f RK |
1008 | if (ret < 0) { |
1009 | dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", | |
1010 | ret); | |
1011 | return NULL; | |
1012 | } | |
1013 | ||
84df8c12 LD |
1014 | *tps65910_reg_matches = matches; |
1015 | ||
6790178f RK |
1016 | for (idx = 0; idx < count; idx++) { |
1017 | if (!matches[idx].init_data || !matches[idx].of_node) | |
1018 | continue; | |
1019 | ||
1020 | pmic_plat_data->tps65910_pmic_init_data[idx] = | |
1021 | matches[idx].init_data; | |
1022 | ||
1023 | ret = of_property_read_u32(matches[idx].of_node, | |
1024 | "ti,regulator-ext-sleep-control", &prop); | |
1025 | if (!ret) | |
1026 | pmic_plat_data->regulator_ext_sleep_control[idx] = prop; | |
19228a6a | 1027 | |
6790178f RK |
1028 | } |
1029 | ||
1030 | return pmic_plat_data; | |
1031 | } | |
1032 | #else | |
1033 | static inline struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1034 | struct platform_device *pdev, |
1035 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f | 1036 | { |
84df8c12 | 1037 | *tps65910_reg_matches = NULL; |
74ea0e59 | 1038 | return NULL; |
6790178f RK |
1039 | } |
1040 | #endif | |
1041 | ||
a5023574 | 1042 | static int tps65910_probe(struct platform_device *pdev) |
518fb721 GG |
1043 | { |
1044 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c172708d | 1045 | struct regulator_config config = { }; |
a320e3c3 | 1046 | struct tps_info *info; |
518fb721 GG |
1047 | struct regulator_init_data *reg_data; |
1048 | struct regulator_dev *rdev; | |
1049 | struct tps65910_reg *pmic; | |
1050 | struct tps65910_board *pmic_plat_data; | |
84df8c12 | 1051 | struct of_regulator_match *tps65910_reg_matches = NULL; |
518fb721 GG |
1052 | int i, err; |
1053 | ||
1054 | pmic_plat_data = dev_get_platdata(tps65910->dev); | |
6790178f | 1055 | if (!pmic_plat_data && tps65910->dev->of_node) |
84df8c12 LD |
1056 | pmic_plat_data = tps65910_parse_dt_reg_data(pdev, |
1057 | &tps65910_reg_matches); | |
6790178f | 1058 | |
7e9a57e6 LD |
1059 | if (!pmic_plat_data) { |
1060 | dev_err(&pdev->dev, "Platform data not found\n"); | |
518fb721 | 1061 | return -EINVAL; |
7e9a57e6 | 1062 | } |
518fb721 | 1063 | |
9eb0c421 | 1064 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
7e9a57e6 LD |
1065 | if (!pmic) { |
1066 | dev_err(&pdev->dev, "Memory allocation failed for pmic\n"); | |
518fb721 | 1067 | return -ENOMEM; |
7e9a57e6 | 1068 | } |
518fb721 | 1069 | |
518fb721 GG |
1070 | pmic->mfd = tps65910; |
1071 | platform_set_drvdata(pdev, pmic); | |
1072 | ||
1073 | /* Give control of all register to control port */ | |
3f7e8275 | 1074 | tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL, |
518fb721 GG |
1075 | DEVCTRL_SR_CTL_I2C_SEL_MASK); |
1076 | ||
a320e3c3 JEC |
1077 | switch(tps65910_chip_id(tps65910)) { |
1078 | case TPS65910: | |
1079 | pmic->get_ctrl_reg = &tps65910_get_ctrl_register; | |
39aa9b6e | 1080 | pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f4 | 1081 | pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3 | 1082 | info = tps65910_regs; |
d04156bc | 1083 | break; |
a320e3c3 JEC |
1084 | case TPS65911: |
1085 | pmic->get_ctrl_reg = &tps65911_get_ctrl_register; | |
39aa9b6e | 1086 | pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f4 | 1087 | pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3 | 1088 | info = tps65911_regs; |
d04156bc | 1089 | break; |
a320e3c3 | 1090 | default: |
7e9a57e6 | 1091 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
a320e3c3 JEC |
1092 | return -ENODEV; |
1093 | } | |
1094 | ||
68d8c1cd | 1095 | pmic->desc = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1096 | sizeof(struct regulator_desc), GFP_KERNEL); |
1097 | if (!pmic->desc) { | |
68d8c1cd LD |
1098 | dev_err(&pdev->dev, "Memory alloc fails for desc\n"); |
1099 | return -ENOMEM; | |
39aa9b6e AL |
1100 | } |
1101 | ||
68d8c1cd | 1102 | pmic->info = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1103 | sizeof(struct tps_info *), GFP_KERNEL); |
1104 | if (!pmic->info) { | |
68d8c1cd LD |
1105 | dev_err(&pdev->dev, "Memory alloc fails for info\n"); |
1106 | return -ENOMEM; | |
39aa9b6e AL |
1107 | } |
1108 | ||
68d8c1cd | 1109 | pmic->rdev = devm_kzalloc(&pdev->dev, pmic->num_regulators * |
39aa9b6e AL |
1110 | sizeof(struct regulator_dev *), GFP_KERNEL); |
1111 | if (!pmic->rdev) { | |
68d8c1cd LD |
1112 | dev_err(&pdev->dev, "Memory alloc fails for rdev\n"); |
1113 | return -ENOMEM; | |
39aa9b6e AL |
1114 | } |
1115 | ||
c1fc1480 KM |
1116 | for (i = 0; i < pmic->num_regulators && i < TPS65910_NUM_REGS; |
1117 | i++, info++) { | |
1118 | ||
1119 | reg_data = pmic_plat_data->tps65910_pmic_init_data[i]; | |
1120 | ||
1121 | /* Regulator API handles empty constraints but not NULL | |
1122 | * constraints */ | |
1123 | if (!reg_data) | |
1124 | continue; | |
1125 | ||
518fb721 GG |
1126 | /* Register the regulators */ |
1127 | pmic->info[i] = info; | |
1128 | ||
1129 | pmic->desc[i].name = info->name; | |
d2cfdb05 | 1130 | pmic->desc[i].supply_name = info->vin_name; |
77fa44d0 | 1131 | pmic->desc[i].id = i; |
7d38a3cb | 1132 | pmic->desc[i].n_voltages = info->n_voltages; |
94f48ab3 | 1133 | pmic->desc[i].enable_time = info->enable_time_us; |
518fb721 | 1134 | |
a320e3c3 | 1135 | if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721 | 1136 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba AM |
1137 | pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * |
1138 | VDD1_2_NUM_VOLT_COARSE; | |
01bc3a14 | 1139 | pmic->desc[i].ramp_delay = 12500; |
a320e3c3 | 1140 | } else if (i == TPS65910_REG_VDD3) { |
01bc3a14 | 1141 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1142 | pmic->desc[i].ops = &tps65910_ops_vdd3; |
d9fe28f9 | 1143 | pmic->desc[i].volt_table = info->voltage_table; |
01bc3a14 | 1144 | } else { |
a320e3c3 | 1145 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
01bc3a14 AL |
1146 | pmic->desc[i].ramp_delay = 5000; |
1147 | } | |
a320e3c3 | 1148 | } else { |
d9fe28f9 | 1149 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1150 | pmic->desc[i].ops = &tps65910_ops; |
d9fe28f9 AL |
1151 | pmic->desc[i].volt_table = info->voltage_table; |
1152 | } else { | |
a320e3c3 | 1153 | pmic->desc[i].ops = &tps65911_ops; |
d9fe28f9 | 1154 | } |
a320e3c3 | 1155 | } |
518fb721 | 1156 | |
1e0c66f4 LD |
1157 | err = tps65910_set_ext_sleep_config(pmic, i, |
1158 | pmic_plat_data->regulator_ext_sleep_control[i]); | |
1159 | /* | |
1160 | * Failing on regulator for configuring externally control | |
1161 | * is not a serious issue, just throw warning. | |
1162 | */ | |
1163 | if (err < 0) | |
1164 | dev_warn(tps65910->dev, | |
1165 | "Failed to initialise ext control config\n"); | |
1166 | ||
518fb721 GG |
1167 | pmic->desc[i].type = REGULATOR_VOLTAGE; |
1168 | pmic->desc[i].owner = THIS_MODULE; | |
a40a9c43 AL |
1169 | pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
1170 | pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; | |
518fb721 | 1171 | |
c172708d MB |
1172 | config.dev = tps65910->dev; |
1173 | config.init_data = reg_data; | |
1174 | config.driver_data = pmic; | |
a40a9c43 | 1175 | config.regmap = tps65910->regmap; |
c172708d | 1176 | |
84df8c12 LD |
1177 | if (tps65910_reg_matches) |
1178 | config.of_node = tps65910_reg_matches[i].of_node; | |
6790178f | 1179 | |
c172708d | 1180 | rdev = regulator_register(&pmic->desc[i], &config); |
518fb721 GG |
1181 | if (IS_ERR(rdev)) { |
1182 | dev_err(tps65910->dev, | |
1183 | "failed to register %s regulator\n", | |
1184 | pdev->name); | |
1185 | err = PTR_ERR(rdev); | |
39aa9b6e | 1186 | goto err_unregister_regulator; |
518fb721 GG |
1187 | } |
1188 | ||
1189 | /* Save regulator for cleanup */ | |
1190 | pmic->rdev[i] = rdev; | |
1191 | } | |
1192 | return 0; | |
1193 | ||
39aa9b6e | 1194 | err_unregister_regulator: |
518fb721 GG |
1195 | while (--i >= 0) |
1196 | regulator_unregister(pmic->rdev[i]); | |
518fb721 GG |
1197 | return err; |
1198 | } | |
1199 | ||
8dc995f5 | 1200 | static int tps65910_remove(struct platform_device *pdev) |
518fb721 | 1201 | { |
39aa9b6e | 1202 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); |
518fb721 GG |
1203 | int i; |
1204 | ||
39aa9b6e AL |
1205 | for (i = 0; i < pmic->num_regulators; i++) |
1206 | regulator_unregister(pmic->rdev[i]); | |
518fb721 | 1207 | |
518fb721 GG |
1208 | return 0; |
1209 | } | |
1210 | ||
1e0c66f4 LD |
1211 | static void tps65910_shutdown(struct platform_device *pdev) |
1212 | { | |
1213 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); | |
1214 | int i; | |
1215 | ||
1216 | /* | |
1217 | * Before bootloader jumps to kernel, it makes sure that required | |
1218 | * external control signals are in desired state so that given rails | |
1219 | * can be configure accordingly. | |
1220 | * If rails are configured to be controlled from external control | |
1221 | * then before shutting down/rebooting the system, the external | |
1222 | * control configuration need to be remove from the rails so that | |
1223 | * its output will be available as per register programming even | |
1224 | * if external controls are removed. This is require when the POR | |
1225 | * value of the control signals are not in active state and before | |
1226 | * bootloader initializes it, the system requires the rail output | |
1227 | * to be active for booting. | |
1228 | */ | |
1229 | for (i = 0; i < pmic->num_regulators; i++) { | |
1230 | int err; | |
1231 | if (!pmic->rdev[i]) | |
1232 | continue; | |
1233 | ||
1234 | err = tps65910_set_ext_sleep_config(pmic, i, 0); | |
1235 | if (err < 0) | |
1236 | dev_err(&pdev->dev, | |
1237 | "Error in clearing external control\n"); | |
1238 | } | |
1239 | } | |
1240 | ||
518fb721 GG |
1241 | static struct platform_driver tps65910_driver = { |
1242 | .driver = { | |
1243 | .name = "tps65910-pmic", | |
1244 | .owner = THIS_MODULE, | |
1245 | }, | |
1246 | .probe = tps65910_probe, | |
5eb9f2b9 | 1247 | .remove = tps65910_remove, |
1e0c66f4 | 1248 | .shutdown = tps65910_shutdown, |
518fb721 GG |
1249 | }; |
1250 | ||
1251 | static int __init tps65910_init(void) | |
1252 | { | |
1253 | return platform_driver_register(&tps65910_driver); | |
1254 | } | |
1255 | subsys_initcall(tps65910_init); | |
1256 | ||
1257 | static void __exit tps65910_cleanup(void) | |
1258 | { | |
1259 | platform_driver_unregister(&tps65910_driver); | |
1260 | } | |
1261 | module_exit(tps65910_cleanup); | |
1262 | ||
1263 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
ae0e6544 | 1264 | MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721 GG |
1265 | MODULE_LICENSE("GPL v2"); |
1266 | MODULE_ALIAS("platform:tps65910-pmic"); |