Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
518fb721 GG |
2 | /* |
3 | * tps65910.c -- TI tps65910 | |
4 | * | |
5 | * Copyright 2010 Texas Instruments Inc. | |
6 | * | |
7 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
8 | * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> | |
518fb721 GG |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/err.h> | |
d16da513 | 15 | #include <linux/of.h> |
518fb721 GG |
16 | #include <linux/platform_device.h> |
17 | #include <linux/regulator/driver.h> | |
18 | #include <linux/regulator/machine.h> | |
518fb721 GG |
19 | #include <linux/slab.h> |
20 | #include <linux/gpio.h> | |
21 | #include <linux/mfd/tps65910.h> | |
6790178f | 22 | #include <linux/regulator/of_regulator.h> |
518fb721 | 23 | |
518fb721 | 24 | #define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
1e0c66f4 LD |
25 | #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ |
26 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ | |
f30b0716 LD |
27 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ |
28 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
518fb721 | 29 | |
d9fe28f9 AL |
30 | /* supported VIO voltages in microvolts */ |
31 | static const unsigned int VIO_VSEL_table[] = { | |
32 | 1500000, 1800000, 2500000, 3300000, | |
518fb721 GG |
33 | }; |
34 | ||
a320e3c3 JEC |
35 | /* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
36 | ||
a9a5659a AC |
37 | /* supported VRTC voltages in microvolts */ |
38 | static const unsigned int VRTC_VSEL_table[] = { | |
39 | 1800000, | |
40 | }; | |
41 | ||
d9fe28f9 AL |
42 | /* supported VDD3 voltages in microvolts */ |
43 | static const unsigned int VDD3_VSEL_table[] = { | |
44 | 5000000, | |
518fb721 GG |
45 | }; |
46 | ||
d9fe28f9 AL |
47 | /* supported VDIG1 voltages in microvolts */ |
48 | static const unsigned int VDIG1_VSEL_table[] = { | |
49 | 1200000, 1500000, 1800000, 2700000, | |
518fb721 GG |
50 | }; |
51 | ||
d9fe28f9 AL |
52 | /* supported VDIG2 voltages in microvolts */ |
53 | static const unsigned int VDIG2_VSEL_table[] = { | |
54 | 1000000, 1100000, 1200000, 1800000, | |
518fb721 GG |
55 | }; |
56 | ||
d9fe28f9 AL |
57 | /* supported VPLL voltages in microvolts */ |
58 | static const unsigned int VPLL_VSEL_table[] = { | |
59 | 1000000, 1100000, 1800000, 2500000, | |
518fb721 GG |
60 | }; |
61 | ||
d9fe28f9 AL |
62 | /* supported VDAC voltages in microvolts */ |
63 | static const unsigned int VDAC_VSEL_table[] = { | |
64 | 1800000, 2600000, 2800000, 2850000, | |
518fb721 GG |
65 | }; |
66 | ||
d9fe28f9 AL |
67 | /* supported VAUX1 voltages in microvolts */ |
68 | static const unsigned int VAUX1_VSEL_table[] = { | |
69 | 1800000, 2500000, 2800000, 2850000, | |
518fb721 GG |
70 | }; |
71 | ||
d9fe28f9 AL |
72 | /* supported VAUX2 voltages in microvolts */ |
73 | static const unsigned int VAUX2_VSEL_table[] = { | |
74 | 1800000, 2800000, 2900000, 3300000, | |
518fb721 GG |
75 | }; |
76 | ||
d9fe28f9 AL |
77 | /* supported VAUX33 voltages in microvolts */ |
78 | static const unsigned int VAUX33_VSEL_table[] = { | |
79 | 1800000, 2000000, 2800000, 3300000, | |
518fb721 GG |
80 | }; |
81 | ||
d9fe28f9 AL |
82 | /* supported VMMC voltages in microvolts */ |
83 | static const unsigned int VMMC_VSEL_table[] = { | |
84 | 1800000, 2800000, 3000000, 3300000, | |
518fb721 GG |
85 | }; |
86 | ||
03746dcb MP |
87 | /* supported BBCH voltages in microvolts */ |
88 | static const unsigned int VBB_VSEL_table[] = { | |
89 | 3000000, 2520000, 3150000, 5000000, | |
90 | }; | |
91 | ||
518fb721 GG |
92 | struct tps_info { |
93 | const char *name; | |
19228a6a | 94 | const char *vin_name; |
7d38a3cb | 95 | u8 n_voltages; |
d9fe28f9 | 96 | const unsigned int *voltage_table; |
0651eed5 | 97 | int enable_time_us; |
518fb721 GG |
98 | }; |
99 | ||
100 | static struct tps_info tps65910_regs[] = { | |
101 | { | |
33a6943d | 102 | .name = "vrtc", |
19228a6a | 103 | .vin_name = "vcc7", |
a9a5659a AC |
104 | .n_voltages = ARRAY_SIZE(VRTC_VSEL_table), |
105 | .voltage_table = VRTC_VSEL_table, | |
0651eed5 | 106 | .enable_time_us = 2200, |
518fb721 GG |
107 | }, |
108 | { | |
33a6943d | 109 | .name = "vio", |
19228a6a | 110 | .vin_name = "vccio", |
7d38a3cb LD |
111 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
112 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 113 | .enable_time_us = 350, |
518fb721 GG |
114 | }, |
115 | { | |
33a6943d | 116 | .name = "vdd1", |
19228a6a | 117 | .vin_name = "vcc1", |
0651eed5 | 118 | .enable_time_us = 350, |
518fb721 GG |
119 | }, |
120 | { | |
33a6943d | 121 | .name = "vdd2", |
19228a6a | 122 | .vin_name = "vcc2", |
0651eed5 | 123 | .enable_time_us = 350, |
518fb721 GG |
124 | }, |
125 | { | |
33a6943d | 126 | .name = "vdd3", |
7d38a3cb LD |
127 | .n_voltages = ARRAY_SIZE(VDD3_VSEL_table), |
128 | .voltage_table = VDD3_VSEL_table, | |
0651eed5 | 129 | .enable_time_us = 200, |
518fb721 GG |
130 | }, |
131 | { | |
33a6943d | 132 | .name = "vdig1", |
19228a6a | 133 | .vin_name = "vcc6", |
7d38a3cb LD |
134 | .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), |
135 | .voltage_table = VDIG1_VSEL_table, | |
0651eed5 | 136 | .enable_time_us = 100, |
518fb721 GG |
137 | }, |
138 | { | |
33a6943d | 139 | .name = "vdig2", |
19228a6a | 140 | .vin_name = "vcc6", |
7d38a3cb LD |
141 | .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), |
142 | .voltage_table = VDIG2_VSEL_table, | |
0651eed5 | 143 | .enable_time_us = 100, |
518fb721 GG |
144 | }, |
145 | { | |
33a6943d | 146 | .name = "vpll", |
19228a6a | 147 | .vin_name = "vcc5", |
7d38a3cb LD |
148 | .n_voltages = ARRAY_SIZE(VPLL_VSEL_table), |
149 | .voltage_table = VPLL_VSEL_table, | |
0651eed5 | 150 | .enable_time_us = 100, |
518fb721 GG |
151 | }, |
152 | { | |
33a6943d | 153 | .name = "vdac", |
19228a6a | 154 | .vin_name = "vcc5", |
7d38a3cb LD |
155 | .n_voltages = ARRAY_SIZE(VDAC_VSEL_table), |
156 | .voltage_table = VDAC_VSEL_table, | |
0651eed5 | 157 | .enable_time_us = 100, |
518fb721 GG |
158 | }, |
159 | { | |
33a6943d | 160 | .name = "vaux1", |
19228a6a | 161 | .vin_name = "vcc4", |
7d38a3cb LD |
162 | .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), |
163 | .voltage_table = VAUX1_VSEL_table, | |
0651eed5 | 164 | .enable_time_us = 100, |
518fb721 GG |
165 | }, |
166 | { | |
33a6943d | 167 | .name = "vaux2", |
19228a6a | 168 | .vin_name = "vcc4", |
7d38a3cb LD |
169 | .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), |
170 | .voltage_table = VAUX2_VSEL_table, | |
0651eed5 | 171 | .enable_time_us = 100, |
518fb721 GG |
172 | }, |
173 | { | |
33a6943d | 174 | .name = "vaux33", |
19228a6a | 175 | .vin_name = "vcc3", |
7d38a3cb LD |
176 | .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), |
177 | .voltage_table = VAUX33_VSEL_table, | |
0651eed5 | 178 | .enable_time_us = 100, |
518fb721 GG |
179 | }, |
180 | { | |
33a6943d | 181 | .name = "vmmc", |
19228a6a | 182 | .vin_name = "vcc3", |
7d38a3cb LD |
183 | .n_voltages = ARRAY_SIZE(VMMC_VSEL_table), |
184 | .voltage_table = VMMC_VSEL_table, | |
0651eed5 | 185 | .enable_time_us = 100, |
518fb721 | 186 | }, |
03746dcb MP |
187 | { |
188 | .name = "vbb", | |
189 | .vin_name = "vcc7", | |
190 | .n_voltages = ARRAY_SIZE(VBB_VSEL_table), | |
191 | .voltage_table = VBB_VSEL_table, | |
192 | }, | |
518fb721 GG |
193 | }; |
194 | ||
a320e3c3 | 195 | static struct tps_info tps65911_regs[] = { |
c2f8efd7 | 196 | { |
33a6943d | 197 | .name = "vrtc", |
19228a6a | 198 | .vin_name = "vcc7", |
0651eed5 | 199 | .enable_time_us = 2200, |
c2f8efd7 | 200 | }, |
a320e3c3 | 201 | { |
33a6943d | 202 | .name = "vio", |
19228a6a | 203 | .vin_name = "vccio", |
7d38a3cb LD |
204 | .n_voltages = ARRAY_SIZE(VIO_VSEL_table), |
205 | .voltage_table = VIO_VSEL_table, | |
0651eed5 | 206 | .enable_time_us = 350, |
a320e3c3 JEC |
207 | }, |
208 | { | |
33a6943d | 209 | .name = "vdd1", |
19228a6a | 210 | .vin_name = "vcc1", |
7be53188 | 211 | .n_voltages = 0x4C, |
0651eed5 | 212 | .enable_time_us = 350, |
a320e3c3 JEC |
213 | }, |
214 | { | |
33a6943d | 215 | .name = "vdd2", |
19228a6a | 216 | .vin_name = "vcc2", |
7be53188 | 217 | .n_voltages = 0x4C, |
0651eed5 | 218 | .enable_time_us = 350, |
a320e3c3 JEC |
219 | }, |
220 | { | |
33a6943d | 221 | .name = "vddctrl", |
7be53188 | 222 | .n_voltages = 0x44, |
0651eed5 | 223 | .enable_time_us = 900, |
a320e3c3 JEC |
224 | }, |
225 | { | |
33a6943d | 226 | .name = "ldo1", |
19228a6a | 227 | .vin_name = "vcc6", |
7be53188 | 228 | .n_voltages = 0x33, |
0651eed5 | 229 | .enable_time_us = 420, |
a320e3c3 JEC |
230 | }, |
231 | { | |
33a6943d | 232 | .name = "ldo2", |
19228a6a | 233 | .vin_name = "vcc6", |
7be53188 | 234 | .n_voltages = 0x33, |
0651eed5 | 235 | .enable_time_us = 420, |
a320e3c3 JEC |
236 | }, |
237 | { | |
33a6943d | 238 | .name = "ldo3", |
19228a6a | 239 | .vin_name = "vcc5", |
7be53188 | 240 | .n_voltages = 0x1A, |
0651eed5 | 241 | .enable_time_us = 230, |
a320e3c3 JEC |
242 | }, |
243 | { | |
33a6943d | 244 | .name = "ldo4", |
19228a6a | 245 | .vin_name = "vcc5", |
7be53188 | 246 | .n_voltages = 0x33, |
0651eed5 | 247 | .enable_time_us = 230, |
a320e3c3 JEC |
248 | }, |
249 | { | |
33a6943d | 250 | .name = "ldo5", |
19228a6a | 251 | .vin_name = "vcc4", |
7be53188 | 252 | .n_voltages = 0x1A, |
0651eed5 | 253 | .enable_time_us = 230, |
a320e3c3 JEC |
254 | }, |
255 | { | |
33a6943d | 256 | .name = "ldo6", |
19228a6a | 257 | .vin_name = "vcc3", |
7be53188 | 258 | .n_voltages = 0x1A, |
0651eed5 | 259 | .enable_time_us = 230, |
a320e3c3 JEC |
260 | }, |
261 | { | |
33a6943d | 262 | .name = "ldo7", |
19228a6a | 263 | .vin_name = "vcc3", |
7be53188 | 264 | .n_voltages = 0x1A, |
0651eed5 | 265 | .enable_time_us = 230, |
a320e3c3 JEC |
266 | }, |
267 | { | |
33a6943d | 268 | .name = "ldo8", |
19228a6a | 269 | .vin_name = "vcc3", |
7be53188 | 270 | .n_voltages = 0x1A, |
0651eed5 | 271 | .enable_time_us = 230, |
a320e3c3 JEC |
272 | }, |
273 | }; | |
274 | ||
1e0c66f4 LD |
275 | #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) |
276 | static unsigned int tps65910_ext_sleep_control[] = { | |
277 | 0, | |
278 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
279 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
280 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
281 | EXT_CONTROL_REG_BITS(VDD3, 1, 3), | |
282 | EXT_CONTROL_REG_BITS(VDIG1, 0, 1), | |
283 | EXT_CONTROL_REG_BITS(VDIG2, 0, 2), | |
284 | EXT_CONTROL_REG_BITS(VPLL, 0, 6), | |
285 | EXT_CONTROL_REG_BITS(VDAC, 0, 7), | |
286 | EXT_CONTROL_REG_BITS(VAUX1, 0, 3), | |
287 | EXT_CONTROL_REG_BITS(VAUX2, 0, 4), | |
288 | EXT_CONTROL_REG_BITS(VAUX33, 0, 5), | |
289 | EXT_CONTROL_REG_BITS(VMMC, 0, 0), | |
290 | }; | |
291 | ||
292 | static unsigned int tps65911_ext_sleep_control[] = { | |
293 | 0, | |
294 | EXT_CONTROL_REG_BITS(VIO, 1, 0), | |
295 | EXT_CONTROL_REG_BITS(VDD1, 1, 1), | |
296 | EXT_CONTROL_REG_BITS(VDD2, 1, 2), | |
297 | EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), | |
298 | EXT_CONTROL_REG_BITS(LDO1, 0, 1), | |
299 | EXT_CONTROL_REG_BITS(LDO2, 0, 2), | |
300 | EXT_CONTROL_REG_BITS(LDO3, 0, 7), | |
301 | EXT_CONTROL_REG_BITS(LDO4, 0, 6), | |
302 | EXT_CONTROL_REG_BITS(LDO5, 0, 3), | |
303 | EXT_CONTROL_REG_BITS(LDO6, 0, 0), | |
304 | EXT_CONTROL_REG_BITS(LDO7, 0, 5), | |
305 | EXT_CONTROL_REG_BITS(LDO8, 0, 4), | |
306 | }; | |
307 | ||
518fb721 | 308 | struct tps65910_reg { |
39aa9b6e | 309 | struct regulator_desc *desc; |
518fb721 | 310 | struct tps65910 *mfd; |
39aa9b6e AL |
311 | struct regulator_dev **rdev; |
312 | struct tps_info **info; | |
39aa9b6e | 313 | int num_regulators; |
518fb721 | 314 | int mode; |
a320e3c3 | 315 | int (*get_ctrl_reg)(int); |
1e0c66f4 LD |
316 | unsigned int *ext_sleep_control; |
317 | unsigned int board_ext_control[TPS65910_NUM_REGS]; | |
518fb721 GG |
318 | }; |
319 | ||
518fb721 GG |
320 | static int tps65910_get_ctrl_register(int id) |
321 | { | |
322 | switch (id) { | |
323 | case TPS65910_REG_VRTC: | |
324 | return TPS65910_VRTC; | |
325 | case TPS65910_REG_VIO: | |
326 | return TPS65910_VIO; | |
327 | case TPS65910_REG_VDD1: | |
328 | return TPS65910_VDD1; | |
329 | case TPS65910_REG_VDD2: | |
330 | return TPS65910_VDD2; | |
331 | case TPS65910_REG_VDD3: | |
332 | return TPS65910_VDD3; | |
333 | case TPS65910_REG_VDIG1: | |
334 | return TPS65910_VDIG1; | |
335 | case TPS65910_REG_VDIG2: | |
336 | return TPS65910_VDIG2; | |
337 | case TPS65910_REG_VPLL: | |
338 | return TPS65910_VPLL; | |
339 | case TPS65910_REG_VDAC: | |
340 | return TPS65910_VDAC; | |
341 | case TPS65910_REG_VAUX1: | |
342 | return TPS65910_VAUX1; | |
343 | case TPS65910_REG_VAUX2: | |
344 | return TPS65910_VAUX2; | |
345 | case TPS65910_REG_VAUX33: | |
346 | return TPS65910_VAUX33; | |
347 | case TPS65910_REG_VMMC: | |
348 | return TPS65910_VMMC; | |
03746dcb MP |
349 | case TPS65910_REG_VBB: |
350 | return TPS65910_BBCH; | |
518fb721 GG |
351 | default: |
352 | return -EINVAL; | |
353 | } | |
354 | } | |
355 | ||
a320e3c3 JEC |
356 | static int tps65911_get_ctrl_register(int id) |
357 | { | |
358 | switch (id) { | |
359 | case TPS65910_REG_VRTC: | |
360 | return TPS65910_VRTC; | |
361 | case TPS65910_REG_VIO: | |
362 | return TPS65910_VIO; | |
363 | case TPS65910_REG_VDD1: | |
364 | return TPS65910_VDD1; | |
365 | case TPS65910_REG_VDD2: | |
366 | return TPS65910_VDD2; | |
367 | case TPS65911_REG_VDDCTRL: | |
368 | return TPS65911_VDDCTRL; | |
369 | case TPS65911_REG_LDO1: | |
370 | return TPS65911_LDO1; | |
371 | case TPS65911_REG_LDO2: | |
372 | return TPS65911_LDO2; | |
373 | case TPS65911_REG_LDO3: | |
374 | return TPS65911_LDO3; | |
375 | case TPS65911_REG_LDO4: | |
376 | return TPS65911_LDO4; | |
377 | case TPS65911_REG_LDO5: | |
378 | return TPS65911_LDO5; | |
379 | case TPS65911_REG_LDO6: | |
380 | return TPS65911_LDO6; | |
381 | case TPS65911_REG_LDO7: | |
382 | return TPS65911_LDO7; | |
383 | case TPS65911_REG_LDO8: | |
384 | return TPS65911_LDO8; | |
385 | default: | |
386 | return -EINVAL; | |
387 | } | |
388 | } | |
389 | ||
518fb721 GG |
390 | static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) |
391 | { | |
392 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
bd8e2cad MM |
393 | struct regmap *regmap = rdev_get_regmap(dev); |
394 | int reg, id = rdev_get_id(dev); | |
a320e3c3 JEC |
395 | |
396 | reg = pmic->get_ctrl_reg(id); | |
518fb721 GG |
397 | if (reg < 0) |
398 | return reg; | |
399 | ||
400 | switch (mode) { | |
401 | case REGULATOR_MODE_NORMAL: | |
bd8e2cad MM |
402 | return regmap_update_bits(regmap, reg, |
403 | LDO_ST_MODE_BIT | LDO_ST_ON_BIT, | |
404 | LDO_ST_ON_BIT); | |
518fb721 | 405 | case REGULATOR_MODE_IDLE: |
bd8e2cad MM |
406 | return regmap_set_bits(regmap, reg, |
407 | LDO_ST_ON_BIT | LDO_ST_MODE_BIT); | |
518fb721 | 408 | case REGULATOR_MODE_STANDBY: |
bd8e2cad | 409 | return regmap_clear_bits(regmap, reg, LDO_ST_ON_BIT); |
518fb721 GG |
410 | } |
411 | ||
412 | return -EINVAL; | |
413 | } | |
414 | ||
415 | static unsigned int tps65910_get_mode(struct regulator_dev *dev) | |
416 | { | |
417 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
bd8e2cad | 418 | struct regmap *regmap = rdev_get_regmap(dev); |
faa95fde | 419 | int ret, reg, value, id = rdev_get_id(dev); |
518fb721 | 420 | |
a320e3c3 | 421 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
422 | if (reg < 0) |
423 | return reg; | |
424 | ||
bd8e2cad | 425 | ret = regmap_read(regmap, reg, &value); |
faa95fde AL |
426 | if (ret < 0) |
427 | return ret; | |
518fb721 | 428 | |
58599393 | 429 | if (!(value & LDO_ST_ON_BIT)) |
518fb721 GG |
430 | return REGULATOR_MODE_STANDBY; |
431 | else if (value & LDO_ST_MODE_BIT) | |
432 | return REGULATOR_MODE_IDLE; | |
433 | else | |
434 | return REGULATOR_MODE_NORMAL; | |
435 | } | |
436 | ||
18039e0f | 437 | static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
518fb721 | 438 | { |
bd8e2cad | 439 | struct regmap *regmap = rdev_get_regmap(dev); |
faa95fde | 440 | int ret, id = rdev_get_id(dev); |
a320e3c3 | 441 | int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
518fb721 GG |
442 | |
443 | switch (id) { | |
444 | case TPS65910_REG_VDD1: | |
bd8e2cad | 445 | ret = regmap_read(regmap, TPS65910_VDD1_OP, &opvsel); |
faa95fde AL |
446 | if (ret < 0) |
447 | return ret; | |
bd8e2cad | 448 | ret = regmap_read(regmap, TPS65910_VDD1, &mult); |
faa95fde AL |
449 | if (ret < 0) |
450 | return ret; | |
518fb721 | 451 | mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
bd8e2cad | 452 | ret = regmap_read(regmap, TPS65910_VDD1_SR, &srvsel); |
faa95fde AL |
453 | if (ret < 0) |
454 | return ret; | |
518fb721 GG |
455 | sr = opvsel & VDD1_OP_CMD_MASK; |
456 | opvsel &= VDD1_OP_SEL_MASK; | |
457 | srvsel &= VDD1_SR_SEL_MASK; | |
a320e3c3 | 458 | vselmax = 75; |
518fb721 GG |
459 | break; |
460 | case TPS65910_REG_VDD2: | |
bd8e2cad | 461 | ret = regmap_read(regmap, TPS65910_VDD2_OP, &opvsel); |
faa95fde AL |
462 | if (ret < 0) |
463 | return ret; | |
bd8e2cad | 464 | ret = regmap_read(regmap, TPS65910_VDD2, &mult); |
faa95fde AL |
465 | if (ret < 0) |
466 | return ret; | |
518fb721 | 467 | mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
bd8e2cad | 468 | ret = regmap_read(regmap, TPS65910_VDD2_SR, &srvsel); |
faa95fde AL |
469 | if (ret < 0) |
470 | return ret; | |
518fb721 GG |
471 | sr = opvsel & VDD2_OP_CMD_MASK; |
472 | opvsel &= VDD2_OP_SEL_MASK; | |
473 | srvsel &= VDD2_SR_SEL_MASK; | |
a320e3c3 JEC |
474 | vselmax = 75; |
475 | break; | |
476 | case TPS65911_REG_VDDCTRL: | |
bd8e2cad | 477 | ret = regmap_read(regmap, TPS65911_VDDCTRL_OP, &opvsel); |
faa95fde AL |
478 | if (ret < 0) |
479 | return ret; | |
bd8e2cad | 480 | ret = regmap_read(regmap, TPS65911_VDDCTRL_SR, &srvsel); |
faa95fde AL |
481 | if (ret < 0) |
482 | return ret; | |
a320e3c3 JEC |
483 | sr = opvsel & VDDCTRL_OP_CMD_MASK; |
484 | opvsel &= VDDCTRL_OP_SEL_MASK; | |
485 | srvsel &= VDDCTRL_SR_SEL_MASK; | |
486 | vselmax = 64; | |
518fb721 GG |
487 | break; |
488 | } | |
489 | ||
490 | /* multiplier 0 == 1 but 2,3 normal */ | |
491 | if (!mult) | |
4b579270 | 492 | mult = 1; |
518fb721 GG |
493 | |
494 | if (sr) { | |
a320e3c3 JEC |
495 | /* normalise to valid range */ |
496 | if (srvsel < 3) | |
497 | srvsel = 3; | |
498 | if (srvsel > vselmax) | |
499 | srvsel = vselmax; | |
18039e0f | 500 | return srvsel - 3; |
518fb721 GG |
501 | } else { |
502 | ||
a320e3c3 JEC |
503 | /* normalise to valid range*/ |
504 | if (opvsel < 3) | |
505 | opvsel = 3; | |
506 | if (opvsel > vselmax) | |
507 | opvsel = vselmax; | |
18039e0f | 508 | return opvsel - 3; |
518fb721 | 509 | } |
18039e0f | 510 | return -EINVAL; |
518fb721 GG |
511 | } |
512 | ||
1f904fd1 | 513 | static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721 GG |
514 | { |
515 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
bd8e2cad | 516 | struct regmap *regmap = rdev_get_regmap(dev); |
faa95fde | 517 | int ret, reg, value, id = rdev_get_id(dev); |
518fb721 | 518 | |
a320e3c3 | 519 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
520 | if (reg < 0) |
521 | return reg; | |
522 | ||
bd8e2cad | 523 | ret = regmap_read(regmap, reg, &value); |
faa95fde AL |
524 | if (ret < 0) |
525 | return ret; | |
518fb721 GG |
526 | |
527 | switch (id) { | |
528 | case TPS65910_REG_VIO: | |
529 | case TPS65910_REG_VDIG1: | |
530 | case TPS65910_REG_VDIG2: | |
531 | case TPS65910_REG_VPLL: | |
532 | case TPS65910_REG_VDAC: | |
533 | case TPS65910_REG_VAUX1: | |
534 | case TPS65910_REG_VAUX2: | |
535 | case TPS65910_REG_VAUX33: | |
536 | case TPS65910_REG_VMMC: | |
537 | value &= LDO_SEL_MASK; | |
538 | value >>= LDO_SEL_SHIFT; | |
539 | break; | |
03746dcb MP |
540 | case TPS65910_REG_VBB: |
541 | value &= BBCH_BBSEL_MASK; | |
542 | value >>= BBCH_BBSEL_SHIFT; | |
543 | break; | |
518fb721 GG |
544 | default: |
545 | return -EINVAL; | |
546 | } | |
547 | ||
1f904fd1 | 548 | return value; |
518fb721 GG |
549 | } |
550 | ||
551 | static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) | |
552 | { | |
d9fe28f9 | 553 | return dev->desc->volt_table[0]; |
518fb721 GG |
554 | } |
555 | ||
1f904fd1 | 556 | static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3 JEC |
557 | { |
558 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
bd8e2cad | 559 | struct regmap *regmap = rdev_get_regmap(dev); |
faa95fde AL |
560 | int ret, id = rdev_get_id(dev); |
561 | unsigned int value, reg; | |
a320e3c3 JEC |
562 | |
563 | reg = pmic->get_ctrl_reg(id); | |
564 | ||
bd8e2cad | 565 | ret = regmap_read(regmap, reg, &value); |
faa95fde AL |
566 | if (ret < 0) |
567 | return ret; | |
a320e3c3 JEC |
568 | |
569 | switch (id) { | |
570 | case TPS65911_REG_LDO1: | |
571 | case TPS65911_REG_LDO2: | |
572 | case TPS65911_REG_LDO4: | |
573 | value &= LDO1_SEL_MASK; | |
574 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
575 | break; |
576 | case TPS65911_REG_LDO3: | |
577 | case TPS65911_REG_LDO5: | |
578 | case TPS65911_REG_LDO6: | |
579 | case TPS65911_REG_LDO7: | |
580 | case TPS65911_REG_LDO8: | |
581 | value &= LDO3_SEL_MASK; | |
582 | value >>= LDO_SEL_SHIFT; | |
a320e3c3 JEC |
583 | break; |
584 | case TPS65910_REG_VIO: | |
e882eae8 LD |
585 | value &= LDO_SEL_MASK; |
586 | value >>= LDO_SEL_SHIFT; | |
1f904fd1 | 587 | break; |
a320e3c3 JEC |
588 | default: |
589 | return -EINVAL; | |
590 | } | |
591 | ||
1f904fd1 | 592 | return value; |
a320e3c3 JEC |
593 | } |
594 | ||
94732b97 AL |
595 | static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, |
596 | unsigned selector) | |
518fb721 | 597 | { |
bd8e2cad | 598 | struct regmap *regmap = rdev_get_regmap(dev); |
518fb721 | 599 | int id = rdev_get_id(dev), vsel; |
a320e3c3 | 600 | int dcdc_mult = 0; |
518fb721 | 601 | |
a320e3c3 JEC |
602 | switch (id) { |
603 | case TPS65910_REG_VDD1: | |
780dc9ba | 604 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
605 | if (dcdc_mult == 1) |
606 | dcdc_mult--; | |
780dc9ba | 607 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721 | 608 | |
bd8e2cad MM |
609 | regmap_update_bits(regmap, TPS65910_VDD1, VDD1_VGAIN_SEL_MASK, |
610 | dcdc_mult << VDD1_VGAIN_SEL_SHIFT); | |
611 | regmap_write(regmap, TPS65910_VDD1_OP, vsel); | |
a320e3c3 JEC |
612 | break; |
613 | case TPS65910_REG_VDD2: | |
780dc9ba | 614 | dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 JEC |
615 | if (dcdc_mult == 1) |
616 | dcdc_mult--; | |
780dc9ba | 617 | vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3 | 618 | |
bd8e2cad MM |
619 | regmap_update_bits(regmap, TPS65910_VDD2, VDD1_VGAIN_SEL_MASK, |
620 | dcdc_mult << VDD2_VGAIN_SEL_SHIFT); | |
621 | regmap_write(regmap, TPS65910_VDD2_OP, vsel); | |
a320e3c3 JEC |
622 | break; |
623 | case TPS65911_REG_VDDCTRL: | |
c4632aed | 624 | vsel = selector + 3; |
bd8e2cad MM |
625 | regmap_write(regmap, TPS65911_VDDCTRL_OP, vsel); |
626 | break; | |
518fb721 GG |
627 | } |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
94732b97 AL |
632 | static int tps65910_set_voltage_sel(struct regulator_dev *dev, |
633 | unsigned selector) | |
518fb721 GG |
634 | { |
635 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
bd8e2cad | 636 | struct regmap *regmap = rdev_get_regmap(dev); |
518fb721 GG |
637 | int reg, id = rdev_get_id(dev); |
638 | ||
a320e3c3 | 639 | reg = pmic->get_ctrl_reg(id); |
518fb721 GG |
640 | if (reg < 0) |
641 | return reg; | |
642 | ||
643 | switch (id) { | |
644 | case TPS65910_REG_VIO: | |
645 | case TPS65910_REG_VDIG1: | |
646 | case TPS65910_REG_VDIG2: | |
647 | case TPS65910_REG_VPLL: | |
648 | case TPS65910_REG_VDAC: | |
649 | case TPS65910_REG_VAUX1: | |
650 | case TPS65910_REG_VAUX2: | |
651 | case TPS65910_REG_VAUX33: | |
652 | case TPS65910_REG_VMMC: | |
bd8e2cad MM |
653 | return regmap_update_bits(regmap, reg, LDO_SEL_MASK, |
654 | selector << LDO_SEL_SHIFT); | |
03746dcb | 655 | case TPS65910_REG_VBB: |
bd8e2cad MM |
656 | return regmap_update_bits(regmap, reg, BBCH_BBSEL_MASK, |
657 | selector << BBCH_BBSEL_SHIFT); | |
518fb721 GG |
658 | } |
659 | ||
660 | return -EINVAL; | |
661 | } | |
662 | ||
94732b97 AL |
663 | static int tps65911_set_voltage_sel(struct regulator_dev *dev, |
664 | unsigned selector) | |
a320e3c3 JEC |
665 | { |
666 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
bd8e2cad | 667 | struct regmap *regmap = rdev_get_regmap(dev); |
a320e3c3 JEC |
668 | int reg, id = rdev_get_id(dev); |
669 | ||
670 | reg = pmic->get_ctrl_reg(id); | |
671 | if (reg < 0) | |
672 | return reg; | |
673 | ||
674 | switch (id) { | |
675 | case TPS65911_REG_LDO1: | |
676 | case TPS65911_REG_LDO2: | |
677 | case TPS65911_REG_LDO4: | |
bd8e2cad MM |
678 | return regmap_update_bits(regmap, reg, LDO1_SEL_MASK, |
679 | selector << LDO_SEL_SHIFT); | |
a320e3c3 JEC |
680 | case TPS65911_REG_LDO3: |
681 | case TPS65911_REG_LDO5: | |
682 | case TPS65911_REG_LDO6: | |
683 | case TPS65911_REG_LDO7: | |
684 | case TPS65911_REG_LDO8: | |
bd8e2cad MM |
685 | return regmap_update_bits(regmap, reg, LDO3_SEL_MASK, |
686 | selector << LDO_SEL_SHIFT); | |
e882eae8 | 687 | case TPS65910_REG_VIO: |
bd8e2cad MM |
688 | return regmap_update_bits(regmap, reg, LDO_SEL_MASK, |
689 | selector << LDO_SEL_SHIFT); | |
03746dcb | 690 | case TPS65910_REG_VBB: |
bd8e2cad MM |
691 | return regmap_update_bits(regmap, reg, BBCH_BBSEL_MASK, |
692 | selector << BBCH_BBSEL_SHIFT); | |
a320e3c3 JEC |
693 | } |
694 | ||
695 | return -EINVAL; | |
696 | } | |
697 | ||
698 | ||
518fb721 GG |
699 | static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, |
700 | unsigned selector) | |
701 | { | |
a320e3c3 | 702 | int volt, mult = 1, id = rdev_get_id(dev); |
518fb721 | 703 | |
a320e3c3 JEC |
704 | switch (id) { |
705 | case TPS65910_REG_VDD1: | |
706 | case TPS65910_REG_VDD2: | |
780dc9ba | 707 | mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3 | 708 | volt = VDD1_2_MIN_VOLT + |
4b579270 | 709 | (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bc | 710 | break; |
a320e3c3 JEC |
711 | case TPS65911_REG_VDDCTRL: |
712 | volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); | |
d04156bc AL |
713 | break; |
714 | default: | |
715 | BUG(); | |
716 | return -EINVAL; | |
a320e3c3 | 717 | } |
518fb721 GG |
718 | |
719 | return volt * 100 * mult; | |
720 | } | |
721 | ||
a320e3c3 JEC |
722 | static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) |
723 | { | |
724 | struct tps65910_reg *pmic = rdev_get_drvdata(dev); | |
725 | int step_mv = 0, id = rdev_get_id(dev); | |
726 | ||
4b579270 | 727 | switch (id) { |
a320e3c3 JEC |
728 | case TPS65911_REG_LDO1: |
729 | case TPS65911_REG_LDO2: | |
730 | case TPS65911_REG_LDO4: | |
731 | /* The first 5 values of the selector correspond to 1V */ | |
732 | if (selector < 5) | |
733 | selector = 0; | |
734 | else | |
735 | selector -= 4; | |
736 | ||
737 | step_mv = 50; | |
738 | break; | |
739 | case TPS65911_REG_LDO3: | |
740 | case TPS65911_REG_LDO5: | |
741 | case TPS65911_REG_LDO6: | |
742 | case TPS65911_REG_LDO7: | |
743 | case TPS65911_REG_LDO8: | |
744 | /* The first 3 values of the selector correspond to 1V */ | |
745 | if (selector < 3) | |
746 | selector = 0; | |
747 | else | |
748 | selector -= 2; | |
749 | ||
750 | step_mv = 100; | |
751 | break; | |
752 | case TPS65910_REG_VIO: | |
d9fe28f9 | 753 | return pmic->info[id]->voltage_table[selector]; |
a320e3c3 JEC |
754 | default: |
755 | return -EINVAL; | |
756 | } | |
757 | ||
758 | return (LDO_MIN_VOLT + selector * step_mv) * 1000; | |
759 | } | |
760 | ||
518fb721 | 761 | /* Regulator ops (except VRTC) */ |
385d41d7 | 762 | static const struct regulator_ops tps65910_ops_dcdc = { |
a40a9c43 AL |
763 | .is_enabled = regulator_is_enabled_regmap, |
764 | .enable = regulator_enable_regmap, | |
765 | .disable = regulator_disable_regmap, | |
518fb721 GG |
766 | .set_mode = tps65910_set_mode, |
767 | .get_mode = tps65910_get_mode, | |
18039e0f | 768 | .get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97 | 769 | .set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
01bc3a14 | 770 | .set_voltage_time_sel = regulator_set_voltage_time_sel, |
518fb721 | 771 | .list_voltage = tps65910_list_voltage_dcdc, |
9fa8175f | 772 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
773 | }; |
774 | ||
385d41d7 | 775 | static const struct regulator_ops tps65910_ops_vdd3 = { |
a40a9c43 AL |
776 | .is_enabled = regulator_is_enabled_regmap, |
777 | .enable = regulator_enable_regmap, | |
778 | .disable = regulator_disable_regmap, | |
518fb721 GG |
779 | .set_mode = tps65910_set_mode, |
780 | .get_mode = tps65910_get_mode, | |
781 | .get_voltage = tps65910_get_voltage_vdd3, | |
d9fe28f9 | 782 | .list_voltage = regulator_list_voltage_table, |
9fa8175f | 783 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
784 | }; |
785 | ||
385d41d7 | 786 | static const struct regulator_ops tps65910_ops_vbb = { |
03746dcb MP |
787 | .is_enabled = regulator_is_enabled_regmap, |
788 | .enable = regulator_enable_regmap, | |
789 | .disable = regulator_disable_regmap, | |
790 | .set_mode = tps65910_set_mode, | |
791 | .get_mode = tps65910_get_mode, | |
792 | .get_voltage_sel = tps65910_get_voltage_sel, | |
793 | .set_voltage_sel = tps65910_set_voltage_sel, | |
794 | .list_voltage = regulator_list_voltage_table, | |
795 | .map_voltage = regulator_map_voltage_iterate, | |
796 | }; | |
797 | ||
385d41d7 | 798 | static const struct regulator_ops tps65910_ops = { |
a40a9c43 AL |
799 | .is_enabled = regulator_is_enabled_regmap, |
800 | .enable = regulator_enable_regmap, | |
801 | .disable = regulator_disable_regmap, | |
518fb721 GG |
802 | .set_mode = tps65910_set_mode, |
803 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 804 | .get_voltage_sel = tps65910_get_voltage_sel, |
94732b97 | 805 | .set_voltage_sel = tps65910_set_voltage_sel, |
d9fe28f9 | 806 | .list_voltage = regulator_list_voltage_table, |
9fa8175f | 807 | .map_voltage = regulator_map_voltage_ascend, |
518fb721 GG |
808 | }; |
809 | ||
385d41d7 | 810 | static const struct regulator_ops tps65911_ops = { |
a40a9c43 AL |
811 | .is_enabled = regulator_is_enabled_regmap, |
812 | .enable = regulator_enable_regmap, | |
813 | .disable = regulator_disable_regmap, | |
a320e3c3 JEC |
814 | .set_mode = tps65910_set_mode, |
815 | .get_mode = tps65910_get_mode, | |
1f904fd1 | 816 | .get_voltage_sel = tps65911_get_voltage_sel, |
94732b97 | 817 | .set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3 | 818 | .list_voltage = tps65911_list_voltage, |
9fa8175f | 819 | .map_voltage = regulator_map_voltage_ascend, |
a320e3c3 JEC |
820 | }; |
821 | ||
1e0c66f4 LD |
822 | static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, |
823 | int id, int ext_sleep_config) | |
824 | { | |
825 | struct tps65910 *mfd = pmic->mfd; | |
826 | u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; | |
827 | u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); | |
828 | int ret; | |
829 | ||
830 | /* | |
831 | * Regulator can not be control from multiple external input EN1, EN2 | |
832 | * and EN3 together. | |
833 | */ | |
834 | if (ext_sleep_config & EXT_SLEEP_CONTROL) { | |
835 | int en_count; | |
836 | en_count = ((ext_sleep_config & | |
837 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); | |
838 | en_count += ((ext_sleep_config & | |
839 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); | |
840 | en_count += ((ext_sleep_config & | |
841 | TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); | |
f30b0716 LD |
842 | en_count += ((ext_sleep_config & |
843 | TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); | |
1e0c66f4 LD |
844 | if (en_count > 1) { |
845 | dev_err(mfd->dev, | |
846 | "External sleep control flag is not proper\n"); | |
847 | return -EINVAL; | |
848 | } | |
849 | } | |
850 | ||
851 | pmic->board_ext_control[id] = ext_sleep_config; | |
852 | ||
853 | /* External EN1 control */ | |
854 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) | |
bd8e2cad | 855 | ret = regmap_set_bits(mfd->regmap, |
1e0c66f4 LD |
856 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
857 | else | |
bd8e2cad | 858 | ret = regmap_clear_bits(mfd->regmap, |
1e0c66f4 LD |
859 | TPS65910_EN1_LDO_ASS + regoffs, bit_pos); |
860 | if (ret < 0) { | |
861 | dev_err(mfd->dev, | |
862 | "Error in configuring external control EN1\n"); | |
863 | return ret; | |
864 | } | |
865 | ||
866 | /* External EN2 control */ | |
867 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) | |
bd8e2cad | 868 | ret = regmap_set_bits(mfd->regmap, |
1e0c66f4 LD |
869 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
870 | else | |
bd8e2cad | 871 | ret = regmap_clear_bits(mfd->regmap, |
1e0c66f4 LD |
872 | TPS65910_EN2_LDO_ASS + regoffs, bit_pos); |
873 | if (ret < 0) { | |
874 | dev_err(mfd->dev, | |
875 | "Error in configuring external control EN2\n"); | |
876 | return ret; | |
877 | } | |
878 | ||
879 | /* External EN3 control for TPS65910 LDO only */ | |
880 | if ((tps65910_chip_id(mfd) == TPS65910) && | |
881 | (id >= TPS65910_REG_VDIG1)) { | |
882 | if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) | |
bd8e2cad | 883 | ret = regmap_set_bits(mfd->regmap, |
1e0c66f4 LD |
884 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
885 | else | |
bd8e2cad | 886 | ret = regmap_clear_bits(mfd->regmap, |
1e0c66f4 LD |
887 | TPS65910_EN3_LDO_ASS + regoffs, bit_pos); |
888 | if (ret < 0) { | |
889 | dev_err(mfd->dev, | |
890 | "Error in configuring external control EN3\n"); | |
891 | return ret; | |
892 | } | |
893 | } | |
894 | ||
895 | /* Return if no external control is selected */ | |
896 | if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { | |
897 | /* Clear all sleep controls */ | |
bd8e2cad | 898 | ret = regmap_clear_bits(mfd->regmap, |
1e0c66f4 LD |
899 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
900 | if (!ret) | |
bd8e2cad | 901 | ret = regmap_clear_bits(mfd->regmap, |
1e0c66f4 LD |
902 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
903 | if (ret < 0) | |
904 | dev_err(mfd->dev, | |
905 | "Error in configuring SLEEP register\n"); | |
906 | return ret; | |
907 | } | |
908 | ||
909 | /* | |
910 | * For regulator that has separate operational and sleep register make | |
911 | * sure that operational is used and clear sleep register to turn | |
912 | * regulator off when external control is inactive | |
913 | */ | |
914 | if ((id == TPS65910_REG_VDD1) || | |
915 | (id == TPS65910_REG_VDD2) || | |
916 | ((id == TPS65911_REG_VDDCTRL) && | |
917 | (tps65910_chip_id(mfd) == TPS65911))) { | |
918 | int op_reg_add = pmic->get_ctrl_reg(id) + 1; | |
919 | int sr_reg_add = pmic->get_ctrl_reg(id) + 2; | |
faa95fde AL |
920 | int opvsel, srvsel; |
921 | ||
bd8e2cad | 922 | ret = regmap_read(mfd->regmap, op_reg_add, &opvsel); |
faa95fde AL |
923 | if (ret < 0) |
924 | return ret; | |
bd8e2cad | 925 | ret = regmap_read(mfd->regmap, sr_reg_add, &srvsel); |
faa95fde AL |
926 | if (ret < 0) |
927 | return ret; | |
928 | ||
1e0c66f4 LD |
929 | if (opvsel & VDD1_OP_CMD_MASK) { |
930 | u8 reg_val = srvsel & VDD1_OP_SEL_MASK; | |
faa95fde | 931 | |
bd8e2cad | 932 | ret = regmap_write(mfd->regmap, op_reg_add, reg_val); |
1e0c66f4 LD |
933 | if (ret < 0) { |
934 | dev_err(mfd->dev, | |
935 | "Error in configuring op register\n"); | |
936 | return ret; | |
937 | } | |
938 | } | |
bd8e2cad | 939 | ret = regmap_write(mfd->regmap, sr_reg_add, 0); |
1e0c66f4 | 940 | if (ret < 0) { |
6d3be300 | 941 | dev_err(mfd->dev, "Error in setting sr register\n"); |
1e0c66f4 LD |
942 | return ret; |
943 | } | |
944 | } | |
945 | ||
bd8e2cad | 946 | ret = regmap_clear_bits(mfd->regmap, |
1e0c66f4 | 947 | TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
f30b0716 LD |
948 | if (!ret) { |
949 | if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) | |
bd8e2cad | 950 | ret = regmap_set_bits(mfd->regmap, |
f30b0716 LD |
951 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
952 | else | |
bd8e2cad | 953 | ret = regmap_clear_bits(mfd->regmap, |
f30b0716 LD |
954 | TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); |
955 | } | |
1e0c66f4 LD |
956 | if (ret < 0) |
957 | dev_err(mfd->dev, | |
958 | "Error in configuring SLEEP register\n"); | |
f30b0716 | 959 | |
1e0c66f4 LD |
960 | return ret; |
961 | } | |
962 | ||
6790178f RK |
963 | #ifdef CONFIG_OF |
964 | ||
965 | static struct of_regulator_match tps65910_matches[] = { | |
33a6943d LD |
966 | { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, |
967 | { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, | |
968 | { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, | |
969 | { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, | |
970 | { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, | |
971 | { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, | |
972 | { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, | |
973 | { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, | |
974 | { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, | |
975 | { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, | |
976 | { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, | |
977 | { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, | |
978 | { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, | |
03746dcb | 979 | { .name = "vbb", .driver_data = (void *) &tps65910_regs[13] }, |
6790178f RK |
980 | }; |
981 | ||
982 | static struct of_regulator_match tps65911_matches[] = { | |
33a6943d LD |
983 | { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, |
984 | { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, | |
985 | { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, | |
986 | { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, | |
987 | { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, | |
988 | { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, | |
989 | { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, | |
990 | { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, | |
991 | { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, | |
992 | { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, | |
993 | { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, | |
994 | { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, | |
995 | { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, | |
6790178f RK |
996 | }; |
997 | ||
998 | static struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
999 | struct platform_device *pdev, |
1000 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f RK |
1001 | { |
1002 | struct tps65910_board *pmic_plat_data; | |
1003 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c92f5dd2 | 1004 | struct device_node *np, *regulators; |
6790178f RK |
1005 | struct of_regulator_match *matches; |
1006 | unsigned int prop; | |
1007 | int idx = 0, ret, count; | |
1008 | ||
1009 | pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), | |
1010 | GFP_KERNEL); | |
bcb2c0d6 | 1011 | if (!pmic_plat_data) |
6790178f | 1012 | return NULL; |
6790178f | 1013 | |
b8b27a44 | 1014 | np = pdev->dev.parent->of_node; |
4ae1ff7f | 1015 | regulators = of_get_child_by_name(np, "regulators"); |
92ab953b LD |
1016 | if (!regulators) { |
1017 | dev_err(&pdev->dev, "regulator node not found\n"); | |
1018 | return NULL; | |
1019 | } | |
6790178f RK |
1020 | |
1021 | switch (tps65910_chip_id(tps65910)) { | |
1022 | case TPS65910: | |
1023 | count = ARRAY_SIZE(tps65910_matches); | |
1024 | matches = tps65910_matches; | |
1025 | break; | |
1026 | case TPS65911: | |
1027 | count = ARRAY_SIZE(tps65911_matches); | |
1028 | matches = tps65911_matches; | |
1029 | break; | |
1030 | default: | |
c92f5dd2 | 1031 | of_node_put(regulators); |
7e9a57e6 | 1032 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
6790178f RK |
1033 | return NULL; |
1034 | } | |
1035 | ||
08337fda | 1036 | ret = of_regulator_match(&pdev->dev, regulators, matches, count); |
c92f5dd2 | 1037 | of_node_put(regulators); |
6790178f RK |
1038 | if (ret < 0) { |
1039 | dev_err(&pdev->dev, "Error parsing regulator init data: %d\n", | |
1040 | ret); | |
1041 | return NULL; | |
1042 | } | |
1043 | ||
84df8c12 LD |
1044 | *tps65910_reg_matches = matches; |
1045 | ||
6790178f | 1046 | for (idx = 0; idx < count; idx++) { |
23b11348 | 1047 | if (!matches[idx].of_node) |
6790178f RK |
1048 | continue; |
1049 | ||
1050 | pmic_plat_data->tps65910_pmic_init_data[idx] = | |
1051 | matches[idx].init_data; | |
1052 | ||
1053 | ret = of_property_read_u32(matches[idx].of_node, | |
1054 | "ti,regulator-ext-sleep-control", &prop); | |
1055 | if (!ret) | |
1056 | pmic_plat_data->regulator_ext_sleep_control[idx] = prop; | |
19228a6a | 1057 | |
6790178f RK |
1058 | } |
1059 | ||
1060 | return pmic_plat_data; | |
1061 | } | |
1062 | #else | |
1063 | static inline struct tps65910_board *tps65910_parse_dt_reg_data( | |
84df8c12 LD |
1064 | struct platform_device *pdev, |
1065 | struct of_regulator_match **tps65910_reg_matches) | |
6790178f | 1066 | { |
84df8c12 | 1067 | *tps65910_reg_matches = NULL; |
74ea0e59 | 1068 | return NULL; |
6790178f RK |
1069 | } |
1070 | #endif | |
1071 | ||
a5023574 | 1072 | static int tps65910_probe(struct platform_device *pdev) |
518fb721 GG |
1073 | { |
1074 | struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); | |
c172708d | 1075 | struct regulator_config config = { }; |
a320e3c3 | 1076 | struct tps_info *info; |
518fb721 GG |
1077 | struct regulator_dev *rdev; |
1078 | struct tps65910_reg *pmic; | |
1079 | struct tps65910_board *pmic_plat_data; | |
84df8c12 | 1080 | struct of_regulator_match *tps65910_reg_matches = NULL; |
518fb721 GG |
1081 | int i, err; |
1082 | ||
1083 | pmic_plat_data = dev_get_platdata(tps65910->dev); | |
6790178f | 1084 | if (!pmic_plat_data && tps65910->dev->of_node) |
84df8c12 LD |
1085 | pmic_plat_data = tps65910_parse_dt_reg_data(pdev, |
1086 | &tps65910_reg_matches); | |
6790178f | 1087 | |
7e9a57e6 LD |
1088 | if (!pmic_plat_data) { |
1089 | dev_err(&pdev->dev, "Platform data not found\n"); | |
518fb721 | 1090 | return -EINVAL; |
7e9a57e6 | 1091 | } |
518fb721 | 1092 | |
9eb0c421 | 1093 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
bcb2c0d6 | 1094 | if (!pmic) |
518fb721 GG |
1095 | return -ENOMEM; |
1096 | ||
518fb721 GG |
1097 | pmic->mfd = tps65910; |
1098 | platform_set_drvdata(pdev, pmic); | |
1099 | ||
1100 | /* Give control of all register to control port */ | |
bd8e2cad | 1101 | err = regmap_set_bits(pmic->mfd->regmap, TPS65910_DEVCTRL, |
518fb721 | 1102 | DEVCTRL_SR_CTL_I2C_SEL_MASK); |
cd07e370 KL |
1103 | if (err < 0) |
1104 | return err; | |
518fb721 | 1105 | |
4b579270 | 1106 | switch (tps65910_chip_id(tps65910)) { |
a320e3c3 | 1107 | case TPS65910: |
fe953904 | 1108 | BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65910_regs)); |
a320e3c3 | 1109 | pmic->get_ctrl_reg = &tps65910_get_ctrl_register; |
39aa9b6e | 1110 | pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f4 | 1111 | pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3 | 1112 | info = tps65910_regs; |
8f9165c9 JR |
1113 | /* Work around silicon erratum SWCZ010: output programmed |
1114 | * voltage level can go higher than expected or crash | |
1115 | * Workaround: use no synchronization of DCDC clocks | |
1116 | */ | |
bd8e2cad | 1117 | regmap_clear_bits(pmic->mfd->regmap, TPS65910_DCDCCTRL, |
8f9165c9 | 1118 | DCDCCTRL_DCDCCKSYNC_MASK); |
d04156bc | 1119 | break; |
a320e3c3 | 1120 | case TPS65911: |
fe953904 | 1121 | BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65911_regs)); |
a320e3c3 | 1122 | pmic->get_ctrl_reg = &tps65911_get_ctrl_register; |
39aa9b6e | 1123 | pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f4 | 1124 | pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3 | 1125 | info = tps65911_regs; |
d04156bc | 1126 | break; |
a320e3c3 | 1127 | default: |
7e9a57e6 | 1128 | dev_err(&pdev->dev, "Invalid tps chip version\n"); |
a320e3c3 JEC |
1129 | return -ENODEV; |
1130 | } | |
1131 | ||
a86854d0 KC |
1132 | pmic->desc = devm_kcalloc(&pdev->dev, |
1133 | pmic->num_regulators, | |
1134 | sizeof(struct regulator_desc), | |
1135 | GFP_KERNEL); | |
bcb2c0d6 | 1136 | if (!pmic->desc) |
68d8c1cd | 1137 | return -ENOMEM; |
39aa9b6e | 1138 | |
a86854d0 KC |
1139 | pmic->info = devm_kcalloc(&pdev->dev, |
1140 | pmic->num_regulators, | |
1141 | sizeof(struct tps_info *), | |
1142 | GFP_KERNEL); | |
bcb2c0d6 | 1143 | if (!pmic->info) |
68d8c1cd | 1144 | return -ENOMEM; |
39aa9b6e | 1145 | |
a86854d0 KC |
1146 | pmic->rdev = devm_kcalloc(&pdev->dev, |
1147 | pmic->num_regulators, | |
1148 | sizeof(struct regulator_dev *), | |
1149 | GFP_KERNEL); | |
bcb2c0d6 | 1150 | if (!pmic->rdev) |
68d8c1cd | 1151 | return -ENOMEM; |
39aa9b6e | 1152 | |
fe953904 | 1153 | for (i = 0; i < pmic->num_regulators; i++, info++) { |
518fb721 GG |
1154 | /* Register the regulators */ |
1155 | pmic->info[i] = info; | |
1156 | ||
1157 | pmic->desc[i].name = info->name; | |
d2cfdb05 | 1158 | pmic->desc[i].supply_name = info->vin_name; |
77fa44d0 | 1159 | pmic->desc[i].id = i; |
7d38a3cb | 1160 | pmic->desc[i].n_voltages = info->n_voltages; |
94f48ab3 | 1161 | pmic->desc[i].enable_time = info->enable_time_us; |
518fb721 | 1162 | |
a320e3c3 | 1163 | if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721 | 1164 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba AM |
1165 | pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * |
1166 | VDD1_2_NUM_VOLT_COARSE; | |
01bc3a14 | 1167 | pmic->desc[i].ramp_delay = 12500; |
a320e3c3 | 1168 | } else if (i == TPS65910_REG_VDD3) { |
01bc3a14 | 1169 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1170 | pmic->desc[i].ops = &tps65910_ops_vdd3; |
d9fe28f9 | 1171 | pmic->desc[i].volt_table = info->voltage_table; |
01bc3a14 | 1172 | } else { |
a320e3c3 | 1173 | pmic->desc[i].ops = &tps65910_ops_dcdc; |
01bc3a14 AL |
1174 | pmic->desc[i].ramp_delay = 5000; |
1175 | } | |
03746dcb MP |
1176 | } else if (i == TPS65910_REG_VBB && |
1177 | tps65910_chip_id(tps65910) == TPS65910) { | |
1178 | pmic->desc[i].ops = &tps65910_ops_vbb; | |
1179 | pmic->desc[i].volt_table = info->voltage_table; | |
a320e3c3 | 1180 | } else { |
d9fe28f9 | 1181 | if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3 | 1182 | pmic->desc[i].ops = &tps65910_ops; |
d9fe28f9 AL |
1183 | pmic->desc[i].volt_table = info->voltage_table; |
1184 | } else { | |
a320e3c3 | 1185 | pmic->desc[i].ops = &tps65911_ops; |
d9fe28f9 | 1186 | } |
a320e3c3 | 1187 | } |
518fb721 | 1188 | |
1e0c66f4 LD |
1189 | err = tps65910_set_ext_sleep_config(pmic, i, |
1190 | pmic_plat_data->regulator_ext_sleep_control[i]); | |
1191 | /* | |
1192 | * Failing on regulator for configuring externally control | |
1193 | * is not a serious issue, just throw warning. | |
1194 | */ | |
1195 | if (err < 0) | |
1196 | dev_warn(tps65910->dev, | |
1197 | "Failed to initialise ext control config\n"); | |
1198 | ||
518fb721 GG |
1199 | pmic->desc[i].type = REGULATOR_VOLTAGE; |
1200 | pmic->desc[i].owner = THIS_MODULE; | |
a40a9c43 | 1201 | pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
b8903eb9 | 1202 | pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; |
518fb721 | 1203 | |
c172708d | 1204 | config.dev = tps65910->dev; |
23b11348 | 1205 | config.init_data = pmic_plat_data->tps65910_pmic_init_data[i]; |
c172708d | 1206 | config.driver_data = pmic; |
a40a9c43 | 1207 | config.regmap = tps65910->regmap; |
c172708d | 1208 | |
84df8c12 LD |
1209 | if (tps65910_reg_matches) |
1210 | config.of_node = tps65910_reg_matches[i].of_node; | |
6790178f | 1211 | |
95095e42 SK |
1212 | rdev = devm_regulator_register(&pdev->dev, &pmic->desc[i], |
1213 | &config); | |
e301df76 DO |
1214 | if (IS_ERR(rdev)) |
1215 | return dev_err_probe(tps65910->dev, PTR_ERR(rdev), | |
1216 | "failed to register %s regulator\n", | |
1217 | pdev->name); | |
518fb721 GG |
1218 | |
1219 | /* Save regulator for cleanup */ | |
1220 | pmic->rdev[i] = rdev; | |
1221 | } | |
1222 | return 0; | |
518fb721 GG |
1223 | } |
1224 | ||
1e0c66f4 LD |
1225 | static void tps65910_shutdown(struct platform_device *pdev) |
1226 | { | |
1227 | struct tps65910_reg *pmic = platform_get_drvdata(pdev); | |
1228 | int i; | |
1229 | ||
1230 | /* | |
1231 | * Before bootloader jumps to kernel, it makes sure that required | |
1232 | * external control signals are in desired state so that given rails | |
1233 | * can be configure accordingly. | |
1234 | * If rails are configured to be controlled from external control | |
1235 | * then before shutting down/rebooting the system, the external | |
1236 | * control configuration need to be remove from the rails so that | |
1237 | * its output will be available as per register programming even | |
1238 | * if external controls are removed. This is require when the POR | |
1239 | * value of the control signals are not in active state and before | |
1240 | * bootloader initializes it, the system requires the rail output | |
1241 | * to be active for booting. | |
1242 | */ | |
1243 | for (i = 0; i < pmic->num_regulators; i++) { | |
1244 | int err; | |
1245 | if (!pmic->rdev[i]) | |
1246 | continue; | |
1247 | ||
1248 | err = tps65910_set_ext_sleep_config(pmic, i, 0); | |
1249 | if (err < 0) | |
1250 | dev_err(&pdev->dev, | |
1251 | "Error in clearing external control\n"); | |
1252 | } | |
1253 | } | |
1254 | ||
518fb721 GG |
1255 | static struct platform_driver tps65910_driver = { |
1256 | .driver = { | |
1257 | .name = "tps65910-pmic", | |
259b93b2 | 1258 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
518fb721 GG |
1259 | }, |
1260 | .probe = tps65910_probe, | |
1e0c66f4 | 1261 | .shutdown = tps65910_shutdown, |
518fb721 GG |
1262 | }; |
1263 | ||
1264 | static int __init tps65910_init(void) | |
1265 | { | |
1266 | return platform_driver_register(&tps65910_driver); | |
1267 | } | |
1268 | subsys_initcall(tps65910_init); | |
1269 | ||
1270 | static void __exit tps65910_cleanup(void) | |
1271 | { | |
1272 | platform_driver_unregister(&tps65910_driver); | |
1273 | } | |
1274 | module_exit(tps65910_cleanup); | |
1275 | ||
1276 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
ae0e6544 | 1277 | MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721 GG |
1278 | MODULE_LICENSE("GPL v2"); |
1279 | MODULE_ALIAS("platform:tps65910-pmic"); |