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regulator: s5m8767: Document new binding for Buck9 GPIO control
[linux-2.6-block.git] / drivers / regulator / s5m8767.c
CommitLineData
9767ec7f
SK		 1/*
2 * s5m8767.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
9767ec7f 14#include <linux/err.h>
26aec009 15#include <linux/of_gpio.h>
9767ec7f
SK		 16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/machine.h>
54227bcf
SK		 20#include <linux/mfd/samsung/core.h>
21#include <linux/mfd/samsung/s5m8767.h>
26aec009 22#include <linux/regulator/of_regulator.h>
d13733f4 23#include <linux/regmap.h>
26aec009
ADK		 24
25#define S5M8767_OPMODE_NORMAL_MODE 0x1
9767ec7f
SK		 26
27struct s5m8767_info {
28 struct device *dev;
63063bfb 29 struct sec_pmic_dev *iodev;
9767ec7f
SK		 30 int num_regulators;
31 struct regulator_dev **rdev;
63063bfb 32 struct sec_opmode_data *opmode;
9767ec7f
SK		 33
34 int ramp_delay;
35 bool buck2_ramp;
36 bool buck3_ramp;
37 bool buck4_ramp;
38
39 bool buck2_gpiodvs;
40 bool buck3_gpiodvs;
41 bool buck4_gpiodvs;
42 u8 buck2_vol[8];
43 u8 buck3_vol[8];
44 u8 buck4_vol[8];
45 int buck_gpios[3];
c848bc85 46 int buck_ds[3];
9767ec7f
SK		 47 int buck_gpioindex;
48};
49
63063bfb 50struct sec_voltage_desc {
9767ec7f
SK		 51 int max;
52 int min;
53 int step;
54};
55
63063bfb 56static const struct sec_voltage_desc buck_voltage_val1 = {
9767ec7f
SK		 57 .max = 2225000,
58 .min = 650000,
59 .step = 6250,
60};
61
63063bfb 62static const struct sec_voltage_desc buck_voltage_val2 = {
9767ec7f
SK		 63 .max = 1600000,
64 .min = 600000,
65 .step = 6250,
66};
67
63063bfb 68static const struct sec_voltage_desc buck_voltage_val3 = {
9767ec7f
SK		 69 .max = 3000000,
70 .min = 750000,
71 .step = 12500,
72};
73
63063bfb 74static const struct sec_voltage_desc ldo_voltage_val1 = {
9767ec7f
SK		 75 .max = 3950000,
76 .min = 800000,
77 .step = 50000,
78};
79
63063bfb 80static const struct sec_voltage_desc ldo_voltage_val2 = {
9767ec7f
SK		 81 .max = 2375000,
82 .min = 800000,
83 .step = 25000,
84};
85
63063bfb 86static const struct sec_voltage_desc *reg_voltage_map[] = {
9767ec7f
SK		 87 [S5M8767_LDO1] = &ldo_voltage_val2,
88 [S5M8767_LDO2] = &ldo_voltage_val2,
89 [S5M8767_LDO3] = &ldo_voltage_val1,
90 [S5M8767_LDO4] = &ldo_voltage_val1,
91 [S5M8767_LDO5] = &ldo_voltage_val1,
92 [S5M8767_LDO6] = &ldo_voltage_val2,
93 [S5M8767_LDO7] = &ldo_voltage_val2,
94 [S5M8767_LDO8] = &ldo_voltage_val2,
95 [S5M8767_LDO9] = &ldo_voltage_val1,
96 [S5M8767_LDO10] = &ldo_voltage_val1,
97 [S5M8767_LDO11] = &ldo_voltage_val1,
98 [S5M8767_LDO12] = &ldo_voltage_val1,
99 [S5M8767_LDO13] = &ldo_voltage_val1,
100 [S5M8767_LDO14] = &ldo_voltage_val1,
101 [S5M8767_LDO15] = &ldo_voltage_val2,
102 [S5M8767_LDO16] = &ldo_voltage_val1,
103 [S5M8767_LDO17] = &ldo_voltage_val1,
104 [S5M8767_LDO18] = &ldo_voltage_val1,
105 [S5M8767_LDO19] = &ldo_voltage_val1,
106 [S5M8767_LDO20] = &ldo_voltage_val1,
107 [S5M8767_LDO21] = &ldo_voltage_val1,
108 [S5M8767_LDO22] = &ldo_voltage_val1,
109 [S5M8767_LDO23] = &ldo_voltage_val1,
110 [S5M8767_LDO24] = &ldo_voltage_val1,
111 [S5M8767_LDO25] = &ldo_voltage_val1,
112 [S5M8767_LDO26] = &ldo_voltage_val1,
113 [S5M8767_LDO27] = &ldo_voltage_val1,
114 [S5M8767_LDO28] = &ldo_voltage_val1,
115 [S5M8767_BUCK1] = &buck_voltage_val1,
116 [S5M8767_BUCK2] = &buck_voltage_val2,
117 [S5M8767_BUCK3] = &buck_voltage_val2,
118 [S5M8767_BUCK4] = &buck_voltage_val2,
119 [S5M8767_BUCK5] = &buck_voltage_val1,
120 [S5M8767_BUCK6] = &buck_voltage_val1,
463616ea
KK		 121 [S5M8767_BUCK7] = &buck_voltage_val3,
122 [S5M8767_BUCK8] = &buck_voltage_val3,
9767ec7f
SK		 123 [S5M8767_BUCK9] = &buck_voltage_val3,
124};
125
5ceba7ba 126static unsigned int s5m8767_opmode_reg[][4] = {
7e44bb83
SK		 127 /* {OFF, ON, LOWPOWER, SUSPEND} */
128 /* LDO1 ... LDO28 */
129 {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
130 {0x0, 0x3, 0x2, 0x1},
131 {0x0, 0x3, 0x2, 0x1},
132 {0x0, 0x0, 0x0, 0x0},
133 {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
134 {0x0, 0x3, 0x2, 0x1},
135 {0x0, 0x3, 0x2, 0x1},
136 {0x0, 0x3, 0x2, 0x1},
137 {0x0, 0x3, 0x2, 0x1},
138 {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
139 {0x0, 0x3, 0x2, 0x1},
140 {0x0, 0x3, 0x2, 0x1},
141 {0x0, 0x3, 0x2, 0x1},
142 {0x0, 0x3, 0x2, 0x1},
143 {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
144 {0x0, 0x3, 0x2, 0x1},
145 {0x0, 0x3, 0x2, 0x1},
146 {0x0, 0x0, 0x0, 0x0},
147 {0x0, 0x3, 0x2, 0x1},
148 {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
149 {0x0, 0x3, 0x2, 0x1},
150 {0x0, 0x3, 0x2, 0x1},
151 {0x0, 0x0, 0x0, 0x0},
152 {0x0, 0x3, 0x2, 0x1},
153 {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
154 {0x0, 0x3, 0x2, 0x1},
155 {0x0, 0x3, 0x2, 0x1},
156 {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
157
158 /* BUCK1 ... BUCK9 */
159 {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
160 {0x0, 0x3, 0x1, 0x1},
161 {0x0, 0x3, 0x1, 0x1},
162 {0x0, 0x3, 0x1, 0x1},
163 {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
164 {0x0, 0x3, 0x1, 0x1},
165 {0x0, 0x3, 0x1, 0x1},
166 {0x0, 0x3, 0x1, 0x1},
167 {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
168};
169
170static int s5m8767_get_register(struct regulator_dev *rdev, int *reg,
171 int *enable_ctrl)
9767ec7f 172{
9bb096ff 173 int i, reg_id = rdev_get_id(rdev);
7e44bb83
SK		 174 unsigned int mode;
175 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
9767ec7f
SK		 176
177 switch (reg_id) {
178 case S5M8767_LDO1 ... S5M8767_LDO2:
179 *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
180 break;
181 case S5M8767_LDO3 ... S5M8767_LDO28:
182 *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
183 break;
184 case S5M8767_BUCK1:
185 *reg = S5M8767_REG_BUCK1CTRL1;
186 break;
187 case S5M8767_BUCK2 ... S5M8767_BUCK4:
188 *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
189 break;
190 case S5M8767_BUCK5:
191 *reg = S5M8767_REG_BUCK5CTRL1;
192 break;
193 case S5M8767_BUCK6 ... S5M8767_BUCK9:
194 *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
195 break;
196 default:
197 return -EINVAL;
198 }
199
9bb096ff
ADK		 200 for (i = 0; i < s5m8767->num_regulators; i++) {
201 if (s5m8767->opmode[i].id == reg_id) {
202 mode = s5m8767->opmode[i].mode;
203 break;
204 }
205 }
206
207 if (i < s5m8767->num_regulators)
208 *enable_ctrl =
209 s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
210
9767ec7f
SK		 211 return 0;
212}
213
214static int s5m8767_reg_is_enabled(struct regulator_dev *rdev)
215{
216 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
217 int ret, reg;
79b53d19 218 int enable_ctrl;
3ef30398 219 unsigned int val;
9767ec7f 220
7e44bb83 221 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
9767ec7f
SK		 222 if (ret == -EINVAL)
223 return 1;
224 else if (ret)
225 return ret;
226
d13733f4 227 ret = regmap_read(s5m8767->iodev->regmap_pmic, reg, &val);
9767ec7f
SK		 228 if (ret)
229 return ret;
230
79b53d19 231 return (val & S5M8767_ENCTRL_MASK) == enable_ctrl;
9767ec7f
SK		 232}
233
234static int s5m8767_reg_enable(struct regulator_dev *rdev)
235{
236 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
237 int ret, reg;
79b53d19 238 int enable_ctrl;
9767ec7f 239
7e44bb83 240 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
9767ec7f
SK		 241 if (ret)
242 return ret;
243
d13733f4
KK		 244 return regmap_update_bits(s5m8767->iodev->regmap_pmic, reg,
245 S5M8767_ENCTRL_MASK, enable_ctrl);
9767ec7f
SK		 246}
247
248static int s5m8767_reg_disable(struct regulator_dev *rdev)
249{
250 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
d13733f4 251 int ret, reg, enable_ctrl;
9767ec7f 252
7e44bb83 253 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
9767ec7f
SK		 254 if (ret)
255 return ret;
256
d13733f4
KK		 257 return regmap_update_bits(s5m8767->iodev->regmap_pmic, reg,
258 S5M8767_ENCTRL_MASK, ~S5M8767_ENCTRL_MASK);
9767ec7f
SK		 259}
260
31a932e1 261static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
9767ec7f 262{
9767ec7f
SK		 263 int reg;
264
265 switch (reg_id) {
266 case S5M8767_LDO1 ... S5M8767_LDO2:
267 reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
268 break;
269 case S5M8767_LDO3 ... S5M8767_LDO28:
270 reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
271 break;
272 case S5M8767_BUCK1:
273 reg = S5M8767_REG_BUCK1CTRL2;
274 break;
275 case S5M8767_BUCK2:
da130ab2 276 reg = S5M8767_REG_BUCK2DVS1;
0a41685f
AL		 277 if (s5m8767->buck2_gpiodvs)
278 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 279 break;
280 case S5M8767_BUCK3:
da130ab2 281 reg = S5M8767_REG_BUCK3DVS1;
0a41685f
AL		 282 if (s5m8767->buck3_gpiodvs)
283 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 284 break;
285 case S5M8767_BUCK4:
da130ab2 286 reg = S5M8767_REG_BUCK4DVS1;
0a41685f
AL		 287 if (s5m8767->buck4_gpiodvs)
288 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 289 break;
290 case S5M8767_BUCK5:
291 reg = S5M8767_REG_BUCK5CTRL2;
292 break;
293 case S5M8767_BUCK6 ... S5M8767_BUCK9:
294 reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
295 break;
296 default:
297 return -EINVAL;
298 }
299
31a932e1 300 return reg;
9767ec7f
SK		 301}
302
854f73ec
AL		 303static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
304 int min_vol)
9767ec7f 305{
5b5e977c 306 int selector = 0;
9767ec7f
SK		 307
308 if (desc == NULL)
309 return -EINVAL;
310
854f73ec 311 if (min_vol > desc->max)
9767ec7f
SK		 312 return -EINVAL;
313
94e85a3c
AL		 314 if (min_vol < desc->min)
315 min_vol = desc->min;
316
317 selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
9767ec7f 318
854f73ec 319 if (desc->min + desc->step * selector > desc->max)
9767ec7f
SK		 320 return -EINVAL;
321
5b5e977c 322 return selector;
9767ec7f
SK		 323}
324
df2643cf 325static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
321d2aba
AL		 326{
327 int temp_index = s5m8767->buck_gpioindex;
328
329 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
330 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
331 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
df2643cf
SK		 332
333 return 0;
321d2aba
AL		 334}
335
df2643cf 336static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
321d2aba
AL		 337{
338 int temp_index = s5m8767->buck_gpioindex;
339
340 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
341 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
342 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
df2643cf
SK		 343
344 return 0;
321d2aba
AL		 345}
346
df2643cf
SK		 347static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
348 unsigned selector)
9767ec7f
SK		 349{
350 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
20a14b84 351 int reg_id = rdev_get_id(rdev);
31a932e1 352 int old_index, index = 0;
321d2aba 353 u8 *buck234_vol = NULL;
9767ec7f
SK		 354
355 switch (reg_id) {
356 case S5M8767_LDO1 ... S5M8767_LDO28:
9767ec7f
SK		 357 break;
358 case S5M8767_BUCK1 ... S5M8767_BUCK6:
321d2aba
AL		 359 if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
360 buck234_vol = &s5m8767->buck2_vol[0];
361 else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
362 buck234_vol = &s5m8767->buck3_vol[0];
363 else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
364 buck234_vol = &s5m8767->buck4_vol[0];
9767ec7f
SK		 365 break;
366 case S5M8767_BUCK7 ... S5M8767_BUCK8:
367 return -EINVAL;
368 case S5M8767_BUCK9:
9767ec7f
SK		 369 break;
370 default:
371 return -EINVAL;
372 }
373
321d2aba
AL		 374 /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
375 if (buck234_vol) {
df2643cf 376 while (*buck234_vol != selector) {
321d2aba
AL		 377 buck234_vol++;
378 index++;
379 }
380 old_index = s5m8767->buck_gpioindex;
381 s5m8767->buck_gpioindex = index;
382
383 if (index > old_index)
df2643cf 384 return s5m8767_set_high(s5m8767);
321d2aba 385 else
df2643cf 386 return s5m8767_set_low(s5m8767);
321d2aba 387 } else {
31a932e1 388 return regulator_set_voltage_sel_regmap(rdev, selector);
321d2aba 389 }
9767ec7f
SK		 390}
391
9767ec7f
SK		 392static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
393 unsigned int old_sel,
394 unsigned int new_sel)
395{
396 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
63063bfb 397 const struct sec_voltage_desc *desc;
20a14b84 398 int reg_id = rdev_get_id(rdev);
9767ec7f 399
9767ec7f
SK		 400 desc = reg_voltage_map[reg_id];
401
9d88fc0b 402 if ((old_sel < new_sel) && s5m8767->ramp_delay)
89e0f0e4 403 return DIV_ROUND_UP(desc->step * (new_sel - old_sel),
0f8b9c77 404 s5m8767->ramp_delay * 1000);
89e0f0e4 405 return 0;
9767ec7f
SK		 406}
407
d35aad0c 408static struct regulator_ops s5m8767_ops = {
e2eb169b 409 .list_voltage = regulator_list_voltage_linear,
9767ec7f
SK		 410 .is_enabled = s5m8767_reg_is_enabled,
411 .enable = s5m8767_reg_enable,
412 .disable = s5m8767_reg_disable,
31a932e1 413 .get_voltage_sel = regulator_get_voltage_sel_regmap,
df2643cf 414 .set_voltage_sel = s5m8767_set_voltage_sel,
9767ec7f
SK		 415 .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
416};
417
e2eb169b 418static struct regulator_ops s5m8767_buck78_ops = {
463616ea 419 .list_voltage = regulator_list_voltage_linear,
e2eb169b
AL		 420 .is_enabled = s5m8767_reg_is_enabled,
421 .enable = s5m8767_reg_enable,
422 .disable = s5m8767_reg_disable,
463616ea
KK		 423 .get_voltage_sel = regulator_get_voltage_sel_regmap,
424 .set_voltage_sel = regulator_set_voltage_sel_regmap,
e2eb169b
AL		 425};
426
65896e73
AL		 427#define s5m8767_regulator_desc(_name) { \
428 .name = #_name, \
429 .id = S5M8767_##_name, \
430 .ops = &s5m8767_ops, \
9767ec7f
SK		 431 .type = REGULATOR_VOLTAGE, \
432 .owner = THIS_MODULE, \
433}
434
e2eb169b
AL		 435#define s5m8767_regulator_buck78_desc(_name) { \
436 .name = #_name, \
437 .id = S5M8767_##_name, \
438 .ops = &s5m8767_buck78_ops, \
439 .type = REGULATOR_VOLTAGE, \
440 .owner = THIS_MODULE, \
441}
442
9767ec7f 443static struct regulator_desc regulators[] = {
65896e73
AL		 444 s5m8767_regulator_desc(LDO1),
445 s5m8767_regulator_desc(LDO2),
446 s5m8767_regulator_desc(LDO3),
447 s5m8767_regulator_desc(LDO4),
448 s5m8767_regulator_desc(LDO5),
449 s5m8767_regulator_desc(LDO6),
450 s5m8767_regulator_desc(LDO7),
451 s5m8767_regulator_desc(LDO8),
452 s5m8767_regulator_desc(LDO9),
453 s5m8767_regulator_desc(LDO10),
454 s5m8767_regulator_desc(LDO11),
455 s5m8767_regulator_desc(LDO12),
456 s5m8767_regulator_desc(LDO13),
457 s5m8767_regulator_desc(LDO14),
458 s5m8767_regulator_desc(LDO15),
459 s5m8767_regulator_desc(LDO16),
460 s5m8767_regulator_desc(LDO17),
461 s5m8767_regulator_desc(LDO18),
462 s5m8767_regulator_desc(LDO19),
463 s5m8767_regulator_desc(LDO20),
464 s5m8767_regulator_desc(LDO21),
465 s5m8767_regulator_desc(LDO22),
466 s5m8767_regulator_desc(LDO23),
467 s5m8767_regulator_desc(LDO24),
468 s5m8767_regulator_desc(LDO25),
469 s5m8767_regulator_desc(LDO26),
470 s5m8767_regulator_desc(LDO27),
471 s5m8767_regulator_desc(LDO28),
472 s5m8767_regulator_desc(BUCK1),
473 s5m8767_regulator_desc(BUCK2),
474 s5m8767_regulator_desc(BUCK3),
475 s5m8767_regulator_desc(BUCK4),
476 s5m8767_regulator_desc(BUCK5),
477 s5m8767_regulator_desc(BUCK6),
e2eb169b
AL		 478 s5m8767_regulator_buck78_desc(BUCK7),
479 s5m8767_regulator_buck78_desc(BUCK8),
65896e73 480 s5m8767_regulator_desc(BUCK9),
9767ec7f
SK		 481};
482
ee1e0994
KK		 483/*
484 * Enable GPIO control over BUCK9 in regulator_config for that regulator.
485 */
486static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767,
487 struct sec_regulator_data *rdata,
488 struct regulator_config *config)
489{
490 int i, mode = 0;
491
492 if (rdata->id != S5M8767_BUCK9)
493 return;
494
495 /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */
496 for (i = 0; i < s5m8767->num_regulators; i++) {
497 const struct sec_opmode_data *opmode = &s5m8767->opmode[i];
498 if (opmode->id == rdata->id) {
499 mode = s5m8767_opmode_reg[rdata->id][opmode->mode];
500 break;
501 }
502 }
503 if (mode != S5M8767_ENCTRL_USE_GPIO) {
504 dev_warn(s5m8767->dev,
505 "ext-control for %s: mismatched op_mode (%x), ignoring\n",
506 rdata->reg_node->name, mode);
507 return;
508 }
509
510 if (!gpio_is_valid(rdata->ext_control_gpio)) {
511 dev_warn(s5m8767->dev,
512 "ext-control for %s: GPIO not valid, ignoring\n",
513 rdata->reg_node->name);
514 return;
515 }
516
517 config->ena_gpio = rdata->ext_control_gpio;
518 config->ena_gpio_flags = GPIOF_OUT_INIT_HIGH;
519}
520
521/*
522 * Turn on GPIO control over BUCK9.
523 */
524static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767,
525 struct regulator_dev *rdev)
526{
527 int ret, reg, enable_ctrl;
528
529 if (rdev_get_id(rdev) != S5M8767_BUCK9)
530 return -EINVAL;
531
532 ret = s5m8767_get_register(rdev, &reg, &enable_ctrl);
533 if (ret)
534 return ret;
535
536 return regmap_update_bits(s5m8767->iodev->regmap_pmic,
537 reg, S5M8767_ENCTRL_MASK,
538 S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT);
539}
540
541
26aec009
ADK		 542#ifdef CONFIG_OF
543static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
544 struct sec_platform_data *pdata,
545 struct device_node *pmic_np)
546{
547 int i, gpio;
548
549 for (i = 0; i < 3; i++) {
550 gpio = of_get_named_gpio(pmic_np,
551 "s5m8767,pmic-buck-dvs-gpios", i);
552 if (!gpio_is_valid(gpio)) {
553 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
554 return -EINVAL;
555 }
556 pdata->buck_gpios[i] = gpio;
557 }
558 return 0;
559}
560
561static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
562 struct sec_platform_data *pdata,
563 struct device_node *pmic_np)
564{
565 int i, gpio;
566
567 for (i = 0; i < 3; i++) {
568 gpio = of_get_named_gpio(pmic_np,
569 "s5m8767,pmic-buck-ds-gpios", i);
570 if (!gpio_is_valid(gpio)) {
571 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
572 return -EINVAL;
573 }
574 pdata->buck_ds[i] = gpio;
575 }
576 return 0;
577}
578
ee1e0994
KK		 579static void s5m8767_pmic_dt_parse_ext_control_gpio(struct sec_pmic_dev *iodev,
580 struct sec_regulator_data *rdata,
581 struct device_node *reg_np)
582{
583 rdata->ext_control_gpio = of_get_named_gpio(reg_np,
584 "s5m8767,pmic-ext-control-gpios", 0);
585 if (!gpio_is_valid(rdata->ext_control_gpio))
586 rdata->ext_control_gpio = 0;
587}
588
cbb0ed49 589static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 590 struct sec_platform_data *pdata)
591{
cbb0ed49 592 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009
ADK		 593 struct device_node *pmic_np, *regulators_np, *reg_np;
594 struct sec_regulator_data *rdata;
595 struct sec_opmode_data *rmode;
04f9f068 596 unsigned int i, dvs_voltage_nr = 8, ret;
26aec009
ADK		 597
598 pmic_np = iodev->dev->of_node;
599 if (!pmic_np) {
600 dev_err(iodev->dev, "could not find pmic sub-node\n");
601 return -ENODEV;
602 }
603
604 regulators_np = of_find_node_by_name(pmic_np, "regulators");
605 if (!regulators_np) {
606 dev_err(iodev->dev, "could not find regulators sub-node\n");
607 return -EINVAL;
608 }
609
610 /* count the number of regulators to be supported in pmic */
1f91b6f6 611 pdata->num_regulators = of_get_child_count(regulators_np);
26aec009 612
cbb0ed49 613 rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) *
26aec009
ADK		 614 pdata->num_regulators, GFP_KERNEL);
615 if (!rdata) {
616 dev_err(iodev->dev,
617 "could not allocate memory for regulator data\n");
618 return -ENOMEM;
619 }
620
cbb0ed49 621 rmode = devm_kzalloc(&pdev->dev, sizeof(*rmode) *
26aec009 622 pdata->num_regulators, GFP_KERNEL);
720a9717 623 if (!rmode) {
26aec009
ADK		 624 dev_err(iodev->dev,
625 "could not allocate memory for regulator mode\n");
626 return -ENOMEM;
627 }
628
629 pdata->regulators = rdata;
630 pdata->opmode = rmode;
631 for_each_child_of_node(regulators_np, reg_np) {
632 for (i = 0; i < ARRAY_SIZE(regulators); i++)
633 if (!of_node_cmp(reg_np->name, regulators[i].name))
634 break;
635
636 if (i == ARRAY_SIZE(regulators)) {
637 dev_warn(iodev->dev,
638 "don't know how to configure regulator %s\n",
639 reg_np->name);
640 continue;
641 }
642
ee1e0994
KK		 643 s5m8767_pmic_dt_parse_ext_control_gpio(iodev, rdata, reg_np);
644
26aec009
ADK		 645 rdata->id = i;
646 rdata->initdata = of_get_regulator_init_data(
cbb0ed49 647 &pdev->dev, reg_np);
26aec009
ADK		 648 rdata->reg_node = reg_np;
649 rdata++;
650 rmode->id = i;
651 if (of_property_read_u32(reg_np, "op_mode",
652 &rmode->mode)) {
653 dev_warn(iodev->dev,
654 "no op_mode property property at %s\n",
655 reg_np->full_name);
656
657 rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
658 }
659 rmode++;
660 }
661
04f9f068 662 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) {
26aec009
ADK		 663 pdata->buck2_gpiodvs = true;
664
04f9f068
CC		 665 if (of_property_read_u32_array(pmic_np,
666 "s5m8767,pmic-buck2-dvs-voltage",
667 pdata->buck2_voltage, dvs_voltage_nr)) {
668 dev_err(iodev->dev, "buck2 voltages not specified\n");
669 return -EINVAL;
670 }
671 }
672
673 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) {
26aec009
ADK		 674 pdata->buck3_gpiodvs = true;
675
04f9f068
CC		 676 if (of_property_read_u32_array(pmic_np,
677 "s5m8767,pmic-buck3-dvs-voltage",
678 pdata->buck3_voltage, dvs_voltage_nr)) {
679 dev_err(iodev->dev, "buck3 voltages not specified\n");
680 return -EINVAL;
681 }
682 }
683
684 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) {
26aec009
ADK		 685 pdata->buck4_gpiodvs = true;
686
04f9f068
CC		 687 if (of_property_read_u32_array(pmic_np,
688 "s5m8767,pmic-buck4-dvs-voltage",
689 pdata->buck4_voltage, dvs_voltage_nr)) {
690 dev_err(iodev->dev, "buck4 voltages not specified\n");
691 return -EINVAL;
692 }
693 }
694
26aec009
ADK		 695 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
696 pdata->buck4_gpiodvs) {
697 ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
698 if (ret)
699 return -EINVAL;
700
701 if (of_property_read_u32(pmic_np,
702 "s5m8767,pmic-buck-default-dvs-idx",
703 &pdata->buck_default_idx)) {
704 pdata->buck_default_idx = 0;
705 } else {
706 if (pdata->buck_default_idx >= 8) {
707 pdata->buck_default_idx = 0;
708 dev_info(iodev->dev,
709 "invalid value for default dvs index, use 0\n");
710 }
711 }
26aec009
ADK		 712 }
713
714 ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
715 if (ret)
716 return -EINVAL;
717
033054e8
CC		 718 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL))
719 pdata->buck2_ramp_enable = true;
26aec009 720
033054e8
CC		 721 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL))
722 pdata->buck3_ramp_enable = true;
26aec009 723
033054e8
CC		 724 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL))
725 pdata->buck4_ramp_enable = true;
726
727 if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
728 || pdata->buck4_ramp_enable) {
729 if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
730 &pdata->buck_ramp_delay))
731 pdata->buck_ramp_delay = 0;
26aec009
ADK		 732 }
733
734 return 0;
735}
736#else
cbb0ed49 737static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 738 struct sec_platform_data *pdata)
739{
740 return 0;
741}
742#endif /* CONFIG_OF */
743
a5023574 744static int s5m8767_pmic_probe(struct platform_device *pdev)
9767ec7f 745{
63063bfb 746 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009 747 struct sec_platform_data *pdata = iodev->pdata;
c172708d 748 struct regulator_config config = { };
9767ec7f
SK		 749 struct regulator_dev **rdev;
750 struct s5m8767_info *s5m8767;
c848bc85 751 int i, ret, size, buck_init;
9767ec7f 752
e81d7bc8
AL		 753 if (!pdata) {
754 dev_err(pdev->dev.parent, "Platform data not supplied\n");
755 return -ENODEV;
756 }
757
26aec009 758 if (iodev->dev->of_node) {
cbb0ed49 759 ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
26aec009
ADK		 760 if (ret)
761 return ret;
762 }
763
6c4efe24
AL		 764 if (pdata->buck2_gpiodvs) {
765 if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
766 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
767 return -EINVAL;
768 }
769 }
770
771 if (pdata->buck3_gpiodvs) {
772 if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
773 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
774 return -EINVAL;
775 }
776 }
777
778 if (pdata->buck4_gpiodvs) {
779 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
780 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
781 return -EINVAL;
782 }
783 }
784
9767ec7f
SK		 785 s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
786 GFP_KERNEL);
787 if (!s5m8767)
788 return -ENOMEM;
789
790 size = sizeof(struct regulator_dev *) * (S5M8767_REG_MAX - 2);
791 s5m8767->rdev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
792 if (!s5m8767->rdev)
793 return -ENOMEM;
794
795 rdev = s5m8767->rdev;
796 s5m8767->dev = &pdev->dev;
797 s5m8767->iodev = iodev;
9bb096ff 798 s5m8767->num_regulators = pdata->num_regulators;
9767ec7f 799 platform_set_drvdata(pdev, s5m8767);
9767ec7f
SK		 800
801 s5m8767->buck_gpioindex = pdata->buck_default_idx;
802 s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
803 s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
804 s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
805 s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
806 s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
807 s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
c848bc85
SK		 808 s5m8767->buck_ds[0] = pdata->buck_ds[0];
809 s5m8767->buck_ds[1] = pdata->buck_ds[1];
810 s5m8767->buck_ds[2] = pdata->buck_ds[2];
811
9767ec7f
SK		 812 s5m8767->ramp_delay = pdata->buck_ramp_delay;
813 s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
814 s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
815 s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
7e44bb83 816 s5m8767->opmode = pdata->opmode;
9767ec7f 817
c848bc85 818 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 819 pdata->buck2_init);
c848bc85 820
d13733f4
KK		 821 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2,
822 buck_init);
c848bc85
SK		 823
824 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 825 pdata->buck3_init);
c848bc85 826
d13733f4
KK		 827 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2,
828 buck_init);
c848bc85
SK		 829
830 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 831 pdata->buck4_init);
c848bc85 832
d13733f4
KK		 833 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2,
834 buck_init);
c848bc85 835
9767ec7f
SK		 836 for (i = 0; i < 8; i++) {
837 if (s5m8767->buck2_gpiodvs) {
838 s5m8767->buck2_vol[i] =
5b5e977c 839 s5m8767_convert_voltage_to_sel(
9767ec7f 840 &buck_voltage_val2,
854f73ec 841 pdata->buck2_voltage[i]);
9767ec7f
SK		 842 }
843
844 if (s5m8767->buck3_gpiodvs) {
845 s5m8767->buck3_vol[i] =
5b5e977c 846 s5m8767_convert_voltage_to_sel(
9767ec7f 847 &buck_voltage_val2,
854f73ec 848 pdata->buck3_voltage[i]);
9767ec7f
SK		 849 }
850
851 if (s5m8767->buck4_gpiodvs) {
852 s5m8767->buck4_vol[i] =
5b5e977c 853 s5m8767_convert_voltage_to_sel(
9767ec7f 854 &buck_voltage_val2,
854f73ec 855 pdata->buck4_voltage[i]);
9767ec7f
SK		 856 }
857 }
858
76c854d1
ADK		 859 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
860 pdata->buck4_gpiodvs) {
861
862 if (!gpio_is_valid(pdata->buck_gpios[0]) ||
863 !gpio_is_valid(pdata->buck_gpios[1]) ||
864 !gpio_is_valid(pdata->buck_gpios[2])) {
865 dev_err(&pdev->dev, "GPIO NOT VALID\n");
866 return -EINVAL;
867 }
868
5febb3c9
AL		 869 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
870 "S5M8767 SET1");
871 if (ret)
872 return ret;
873
874 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
875 "S5M8767 SET2");
876 if (ret)
877 return ret;
878
879 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
880 "S5M8767 SET3");
881 if (ret)
882 return ret;
883
c848bc85
SK		 884 /* SET1 GPIO */
885 gpio_direction_output(pdata->buck_gpios[0],
886 (s5m8767->buck_gpioindex >> 2) & 0x1);
887 /* SET2 GPIO */
888 gpio_direction_output(pdata->buck_gpios[1],
889 (s5m8767->buck_gpioindex >> 1) & 0x1);
890 /* SET3 GPIO */
891 gpio_direction_output(pdata->buck_gpios[2],
892 (s5m8767->buck_gpioindex >> 0) & 0x1);
9767ec7f
SK		 893 }
894
5febb3c9
AL		 895 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
896 if (ret)
897 return ret;
c848bc85 898
5febb3c9
AL		 899 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
900 if (ret)
901 return ret;
c848bc85 902
5febb3c9
AL		 903 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
904 if (ret)
905 return ret;
c848bc85
SK		 906
907 /* DS2 GPIO */
908 gpio_direction_output(pdata->buck_ds[0], 0x0);
909 /* DS3 GPIO */
910 gpio_direction_output(pdata->buck_ds[1], 0x0);
911 /* DS4 GPIO */
912 gpio_direction_output(pdata->buck_ds[2], 0x0);
913
914 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
915 pdata->buck4_gpiodvs) {
d13733f4
KK		 916 regmap_update_bits(s5m8767->iodev->regmap_pmic,
917 S5M8767_REG_BUCK2CTRL, 1 << 1,
918 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1));
919 regmap_update_bits(s5m8767->iodev->regmap_pmic,
920 S5M8767_REG_BUCK3CTRL, 1 << 1,
921 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1));
922 regmap_update_bits(s5m8767->iodev->regmap_pmic,
923 S5M8767_REG_BUCK4CTRL, 1 << 1,
924 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1));
c848bc85 925 }
9767ec7f
SK		 926
927 /* Initialize GPIO DVS registers */
928 for (i = 0; i < 8; i++) {
929 if (s5m8767->buck2_gpiodvs) {
d13733f4
KK		 930 regmap_write(s5m8767->iodev->regmap_pmic,
931 S5M8767_REG_BUCK2DVS1 + i,
932 s5m8767->buck2_vol[i]);
9767ec7f
SK		 933 }
934
935 if (s5m8767->buck3_gpiodvs) {
d13733f4
KK		 936 regmap_write(s5m8767->iodev->regmap_pmic,
937 S5M8767_REG_BUCK3DVS1 + i,
938 s5m8767->buck3_vol[i]);
9767ec7f
SK		 939 }
940
941 if (s5m8767->buck4_gpiodvs) {
d13733f4
KK		 942 regmap_write(s5m8767->iodev->regmap_pmic,
943 S5M8767_REG_BUCK4DVS1 + i,
944 s5m8767->buck4_vol[i]);
9767ec7f
SK		 945 }
946 }
9767ec7f
SK		 947
948 if (s5m8767->buck2_ramp)
d13733f4
KK		 949 regmap_update_bits(s5m8767->iodev->regmap_pmic,
950 S5M8767_REG_DVSRAMP, 0x08, 0x08);
9767ec7f
SK		 951
952 if (s5m8767->buck3_ramp)
d13733f4
KK		 953 regmap_update_bits(s5m8767->iodev->regmap_pmic,
954 S5M8767_REG_DVSRAMP, 0x04, 0x04);
9767ec7f
SK		 955
956 if (s5m8767->buck4_ramp)
d13733f4
KK		 957 regmap_update_bits(s5m8767->iodev->regmap_pmic,
958 S5M8767_REG_DVSRAMP, 0x02, 0x02);
9767ec7f
SK		 959
960 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
961 || s5m8767->buck4_ramp) {
f37ff6b6 962 unsigned int val;
9767ec7f 963 switch (s5m8767->ramp_delay) {
1af142c6 964 case 5:
f37ff6b6 965 val = S5M8767_DVS_BUCK_RAMP_5;
1af142c6
SK		 966 break;
967 case 10:
f37ff6b6 968 val = S5M8767_DVS_BUCK_RAMP_10;
047ec220 969 break;
9767ec7f 970 case 25:
f37ff6b6 971 val = S5M8767_DVS_BUCK_RAMP_25;
047ec220 972 break;
9767ec7f 973 case 50:
f37ff6b6 974 val = S5M8767_DVS_BUCK_RAMP_50;
047ec220 975 break;
9767ec7f 976 case 100:
f37ff6b6 977 val = S5M8767_DVS_BUCK_RAMP_100;
047ec220 978 break;
9767ec7f 979 default:
f37ff6b6 980 val = S5M8767_DVS_BUCK_RAMP_10;
9767ec7f 981 }
d13733f4
KK		 982 regmap_update_bits(s5m8767->iodev->regmap_pmic,
983 S5M8767_REG_DVSRAMP,
984 S5M8767_DVS_BUCK_RAMP_MASK,
985 val << S5M8767_DVS_BUCK_RAMP_SHIFT);
9767ec7f
SK		 986 }
987
988 for (i = 0; i < pdata->num_regulators; i++) {
63063bfb 989 const struct sec_voltage_desc *desc;
9767ec7f
SK		 990 int id = pdata->regulators[i].id;
991
992 desc = reg_voltage_map[id];
e2eb169b 993 if (desc) {
9767ec7f
SK		 994 regulators[id].n_voltages =
995 (desc->max - desc->min) / desc->step + 1;
e2eb169b
AL		 996 regulators[id].min_uV = desc->min;
997 regulators[id].uV_step = desc->step;
31a932e1
AL		 998 regulators[id].vsel_reg =
999 s5m8767_get_vsel_reg(id, s5m8767);
1000 if (id < S5M8767_BUCK1)
1001 regulators[id].vsel_mask = 0x3f;
1002 else
1003 regulators[id].vsel_mask = 0xff;
e2eb169b 1004 }
9767ec7f 1005
c172708d
MB		 1006 config.dev = s5m8767->dev;
1007 config.init_data = pdata->regulators[i].initdata;
1008 config.driver_data = s5m8767;
3e1e4a5f 1009 config.regmap = iodev->regmap_pmic;
26aec009 1010 config.of_node = pdata->regulators[i].reg_node;
ee1e0994
KK		 1011 if (pdata->regulators[i].ext_control_gpio)
1012 s5m8767_regulator_config_ext_control(s5m8767,
1013 &pdata->regulators[i], &config);
c172708d 1014
f0db475d
MB		 1015 rdev[i] = devm_regulator_register(&pdev->dev, &regulators[id],
1016 &config);
9767ec7f
SK		 1017 if (IS_ERR(rdev[i])) {
1018 ret = PTR_ERR(rdev[i]);
1019 dev_err(s5m8767->dev, "regulator init failed for %d\n",
1020 id);
f0db475d 1021 return ret;
9767ec7f 1022 }
ee1e0994
KK		 1023
1024 if (pdata->regulators[i].ext_control_gpio) {
1025 ret = s5m8767_enable_ext_control(s5m8767, rdev[i]);
1026 if (ret < 0) {
1027 dev_err(s5m8767->dev,
1028 "failed to enable gpio control over %s: %d\n",
1029 rdev[i]->desc->name, ret);
1030 return ret;
1031 }
1032 }
9767ec7f
SK		 1033 }
1034
9767ec7f
SK		 1035 return 0;
1036}
1037
1038static const struct platform_device_id s5m8767_pmic_id[] = {
1039 { "s5m8767-pmic", 0},
1040 { },
1041};
1042MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
1043
1044static struct platform_driver s5m8767_pmic_driver = {
1045 .driver = {
1046 .name = "s5m8767-pmic",
1047 .owner = THIS_MODULE,
1048 },
1049 .probe = s5m8767_pmic_probe,
9767ec7f
SK		 1050 .id_table = s5m8767_pmic_id,
1051};
1052
1053static int __init s5m8767_pmic_init(void)
1054{
1055 return platform_driver_register(&s5m8767_pmic_driver);
1056}
1057subsys_initcall(s5m8767_pmic_init);
1058
1059static void __exit s5m8767_pmic_exit(void)
1060{
1061 platform_driver_unregister(&s5m8767_pmic_driver);
1062}
1063module_exit(s5m8767_pmic_exit);
1064
1065/* Module information */
1066MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
1067MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver");
1068MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)