projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
bonding: add proper __rcu annotation for curr_active_slave
[linux-2.6-block.git] / drivers / regulator / s5m8767.c
CommitLineData
9767ec7f
SK		 1/*
2 * s5m8767.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
9767ec7f 14#include <linux/err.h>
26aec009 15#include <linux/of_gpio.h>
9767ec7f
SK		 16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/machine.h>
54227bcf
SK		 20#include <linux/mfd/samsung/core.h>
21#include <linux/mfd/samsung/s5m8767.h>
26aec009 22#include <linux/regulator/of_regulator.h>
d13733f4 23#include <linux/regmap.h>
26aec009
ADK		 24
25#define S5M8767_OPMODE_NORMAL_MODE 0x1
9767ec7f
SK		 26
27struct s5m8767_info {
28 struct device *dev;
63063bfb 29 struct sec_pmic_dev *iodev;
9767ec7f 30 int num_regulators;
63063bfb 31 struct sec_opmode_data *opmode;
9767ec7f
SK		 32
33 int ramp_delay;
34 bool buck2_ramp;
35 bool buck3_ramp;
36 bool buck4_ramp;
37
38 bool buck2_gpiodvs;
39 bool buck3_gpiodvs;
40 bool buck4_gpiodvs;
41 u8 buck2_vol[8];
42 u8 buck3_vol[8];
43 u8 buck4_vol[8];
44 int buck_gpios[3];
c848bc85 45 int buck_ds[3];
9767ec7f
SK		 46 int buck_gpioindex;
47};
48
63063bfb 49struct sec_voltage_desc {
9767ec7f
SK		 50 int max;
51 int min;
52 int step;
53};
54
63063bfb 55static const struct sec_voltage_desc buck_voltage_val1 = {
9767ec7f
SK		 56 .max = 2225000,
57 .min = 650000,
58 .step = 6250,
59};
60
63063bfb 61static const struct sec_voltage_desc buck_voltage_val2 = {
9767ec7f
SK		 62 .max = 1600000,
63 .min = 600000,
64 .step = 6250,
65};
66
63063bfb 67static const struct sec_voltage_desc buck_voltage_val3 = {
9767ec7f
SK		 68 .max = 3000000,
69 .min = 750000,
70 .step = 12500,
71};
72
63063bfb 73static const struct sec_voltage_desc ldo_voltage_val1 = {
9767ec7f
SK		 74 .max = 3950000,
75 .min = 800000,
76 .step = 50000,
77};
78
63063bfb 79static const struct sec_voltage_desc ldo_voltage_val2 = {
9767ec7f
SK		 80 .max = 2375000,
81 .min = 800000,
82 .step = 25000,
83};
84
63063bfb 85static const struct sec_voltage_desc *reg_voltage_map[] = {
9767ec7f
SK		 86 [S5M8767_LDO1] = &ldo_voltage_val2,
87 [S5M8767_LDO2] = &ldo_voltage_val2,
88 [S5M8767_LDO3] = &ldo_voltage_val1,
89 [S5M8767_LDO4] = &ldo_voltage_val1,
90 [S5M8767_LDO5] = &ldo_voltage_val1,
91 [S5M8767_LDO6] = &ldo_voltage_val2,
92 [S5M8767_LDO7] = &ldo_voltage_val2,
93 [S5M8767_LDO8] = &ldo_voltage_val2,
94 [S5M8767_LDO9] = &ldo_voltage_val1,
95 [S5M8767_LDO10] = &ldo_voltage_val1,
96 [S5M8767_LDO11] = &ldo_voltage_val1,
97 [S5M8767_LDO12] = &ldo_voltage_val1,
98 [S5M8767_LDO13] = &ldo_voltage_val1,
99 [S5M8767_LDO14] = &ldo_voltage_val1,
100 [S5M8767_LDO15] = &ldo_voltage_val2,
101 [S5M8767_LDO16] = &ldo_voltage_val1,
102 [S5M8767_LDO17] = &ldo_voltage_val1,
103 [S5M8767_LDO18] = &ldo_voltage_val1,
104 [S5M8767_LDO19] = &ldo_voltage_val1,
105 [S5M8767_LDO20] = &ldo_voltage_val1,
106 [S5M8767_LDO21] = &ldo_voltage_val1,
107 [S5M8767_LDO22] = &ldo_voltage_val1,
108 [S5M8767_LDO23] = &ldo_voltage_val1,
109 [S5M8767_LDO24] = &ldo_voltage_val1,
110 [S5M8767_LDO25] = &ldo_voltage_val1,
111 [S5M8767_LDO26] = &ldo_voltage_val1,
112 [S5M8767_LDO27] = &ldo_voltage_val1,
113 [S5M8767_LDO28] = &ldo_voltage_val1,
114 [S5M8767_BUCK1] = &buck_voltage_val1,
115 [S5M8767_BUCK2] = &buck_voltage_val2,
116 [S5M8767_BUCK3] = &buck_voltage_val2,
117 [S5M8767_BUCK4] = &buck_voltage_val2,
118 [S5M8767_BUCK5] = &buck_voltage_val1,
119 [S5M8767_BUCK6] = &buck_voltage_val1,
463616ea
KK		 120 [S5M8767_BUCK7] = &buck_voltage_val3,
121 [S5M8767_BUCK8] = &buck_voltage_val3,
9767ec7f
SK		 122 [S5M8767_BUCK9] = &buck_voltage_val3,
123};
124
5ceba7ba 125static unsigned int s5m8767_opmode_reg[][4] = {
7e44bb83
SK		 126 /* {OFF, ON, LOWPOWER, SUSPEND} */
127 /* LDO1 ... LDO28 */
128 {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
129 {0x0, 0x3, 0x2, 0x1},
130 {0x0, 0x3, 0x2, 0x1},
131 {0x0, 0x0, 0x0, 0x0},
132 {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
133 {0x0, 0x3, 0x2, 0x1},
134 {0x0, 0x3, 0x2, 0x1},
135 {0x0, 0x3, 0x2, 0x1},
136 {0x0, 0x3, 0x2, 0x1},
137 {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
138 {0x0, 0x3, 0x2, 0x1},
139 {0x0, 0x3, 0x2, 0x1},
140 {0x0, 0x3, 0x2, 0x1},
141 {0x0, 0x3, 0x2, 0x1},
142 {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
143 {0x0, 0x3, 0x2, 0x1},
144 {0x0, 0x3, 0x2, 0x1},
145 {0x0, 0x0, 0x0, 0x0},
146 {0x0, 0x3, 0x2, 0x1},
147 {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
148 {0x0, 0x3, 0x2, 0x1},
149 {0x0, 0x3, 0x2, 0x1},
150 {0x0, 0x0, 0x0, 0x0},
151 {0x0, 0x3, 0x2, 0x1},
152 {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
153 {0x0, 0x3, 0x2, 0x1},
154 {0x0, 0x3, 0x2, 0x1},
155 {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
156
157 /* BUCK1 ... BUCK9 */
158 {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
159 {0x0, 0x3, 0x1, 0x1},
160 {0x0, 0x3, 0x1, 0x1},
161 {0x0, 0x3, 0x1, 0x1},
162 {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
163 {0x0, 0x3, 0x1, 0x1},
164 {0x0, 0x3, 0x1, 0x1},
165 {0x0, 0x3, 0x1, 0x1},
166 {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
167};
168
9c4c6055
AL		 169static int s5m8767_get_register(struct s5m8767_info *s5m8767, int reg_id,
170 int *reg, int *enable_ctrl)
9767ec7f 171{
9c4c6055 172 int i;
7e44bb83 173 unsigned int mode;
9767ec7f
SK		 174
175 switch (reg_id) {
176 case S5M8767_LDO1 ... S5M8767_LDO2:
177 *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
178 break;
179 case S5M8767_LDO3 ... S5M8767_LDO28:
180 *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
181 break;
182 case S5M8767_BUCK1:
183 *reg = S5M8767_REG_BUCK1CTRL1;
184 break;
185 case S5M8767_BUCK2 ... S5M8767_BUCK4:
186 *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
187 break;
188 case S5M8767_BUCK5:
189 *reg = S5M8767_REG_BUCK5CTRL1;
190 break;
191 case S5M8767_BUCK6 ... S5M8767_BUCK9:
192 *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
193 break;
194 default:
195 return -EINVAL;
196 }
197
9bb096ff
ADK		 198 for (i = 0; i < s5m8767->num_regulators; i++) {
199 if (s5m8767->opmode[i].id == reg_id) {
200 mode = s5m8767->opmode[i].mode;
201 break;
202 }
203 }
204
205 if (i < s5m8767->num_regulators)
206 *enable_ctrl =
207 s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
208
9767ec7f
SK		 209 return 0;
210}
211
31a932e1 212static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
9767ec7f 213{
9767ec7f
SK		 214 int reg;
215
216 switch (reg_id) {
217 case S5M8767_LDO1 ... S5M8767_LDO2:
218 reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
219 break;
220 case S5M8767_LDO3 ... S5M8767_LDO28:
221 reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
222 break;
223 case S5M8767_BUCK1:
224 reg = S5M8767_REG_BUCK1CTRL2;
225 break;
226 case S5M8767_BUCK2:
da130ab2 227 reg = S5M8767_REG_BUCK2DVS1;
0a41685f
AL		 228 if (s5m8767->buck2_gpiodvs)
229 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 230 break;
231 case S5M8767_BUCK3:
da130ab2 232 reg = S5M8767_REG_BUCK3DVS1;
0a41685f
AL		 233 if (s5m8767->buck3_gpiodvs)
234 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 235 break;
236 case S5M8767_BUCK4:
da130ab2 237 reg = S5M8767_REG_BUCK4DVS1;
0a41685f
AL		 238 if (s5m8767->buck4_gpiodvs)
239 reg += s5m8767->buck_gpioindex;
9767ec7f
SK		 240 break;
241 case S5M8767_BUCK5:
242 reg = S5M8767_REG_BUCK5CTRL2;
243 break;
244 case S5M8767_BUCK6 ... S5M8767_BUCK9:
245 reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
246 break;
247 default:
248 return -EINVAL;
249 }
250
31a932e1 251 return reg;
9767ec7f
SK		 252}
253
854f73ec
AL		 254static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
255 int min_vol)
9767ec7f 256{
5b5e977c 257 int selector = 0;
9767ec7f
SK		 258
259 if (desc == NULL)
260 return -EINVAL;
261
854f73ec 262 if (min_vol > desc->max)
9767ec7f
SK		 263 return -EINVAL;
264
94e85a3c
AL		 265 if (min_vol < desc->min)
266 min_vol = desc->min;
267
268 selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
9767ec7f 269
854f73ec 270 if (desc->min + desc->step * selector > desc->max)
9767ec7f
SK		 271 return -EINVAL;
272
5b5e977c 273 return selector;
9767ec7f
SK		 274}
275
df2643cf 276static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
321d2aba
AL		 277{
278 int temp_index = s5m8767->buck_gpioindex;
279
280 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
281 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
282 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
df2643cf
SK		 283
284 return 0;
321d2aba
AL		 285}
286
df2643cf 287static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
321d2aba
AL		 288{
289 int temp_index = s5m8767->buck_gpioindex;
290
291 gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
292 gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
293 gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
df2643cf
SK		 294
295 return 0;
321d2aba
AL		 296}
297
df2643cf
SK		 298static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
299 unsigned selector)
9767ec7f
SK		 300{
301 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
20a14b84 302 int reg_id = rdev_get_id(rdev);
31a932e1 303 int old_index, index = 0;
321d2aba 304 u8 *buck234_vol = NULL;
9767ec7f
SK		 305
306 switch (reg_id) {
307 case S5M8767_LDO1 ... S5M8767_LDO28:
9767ec7f
SK		 308 break;
309 case S5M8767_BUCK1 ... S5M8767_BUCK6:
321d2aba
AL		 310 if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
311 buck234_vol = &s5m8767->buck2_vol[0];
312 else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
313 buck234_vol = &s5m8767->buck3_vol[0];
314 else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
315 buck234_vol = &s5m8767->buck4_vol[0];
9767ec7f
SK		 316 break;
317 case S5M8767_BUCK7 ... S5M8767_BUCK8:
318 return -EINVAL;
319 case S5M8767_BUCK9:
9767ec7f
SK		 320 break;
321 default:
322 return -EINVAL;
323 }
324
321d2aba
AL		 325 /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
326 if (buck234_vol) {
df2643cf 327 while (*buck234_vol != selector) {
321d2aba
AL		 328 buck234_vol++;
329 index++;
330 }
331 old_index = s5m8767->buck_gpioindex;
332 s5m8767->buck_gpioindex = index;
333
334 if (index > old_index)
df2643cf 335 return s5m8767_set_high(s5m8767);
321d2aba 336 else
df2643cf 337 return s5m8767_set_low(s5m8767);
321d2aba 338 } else {
31a932e1 339 return regulator_set_voltage_sel_regmap(rdev, selector);
321d2aba 340 }
9767ec7f
SK		 341}
342
9767ec7f
SK		 343static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
344 unsigned int old_sel,
345 unsigned int new_sel)
346{
347 struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
63063bfb 348 const struct sec_voltage_desc *desc;
20a14b84 349 int reg_id = rdev_get_id(rdev);
9767ec7f 350
9767ec7f
SK		 351 desc = reg_voltage_map[reg_id];
352
9d88fc0b 353 if ((old_sel < new_sel) && s5m8767->ramp_delay)
89e0f0e4 354 return DIV_ROUND_UP(desc->step * (new_sel - old_sel),
0f8b9c77 355 s5m8767->ramp_delay * 1000);
89e0f0e4 356 return 0;
9767ec7f
SK		 357}
358
d35aad0c 359static struct regulator_ops s5m8767_ops = {
e2eb169b 360 .list_voltage = regulator_list_voltage_linear,
9c4c6055
AL		 361 .is_enabled = regulator_is_enabled_regmap,
362 .enable = regulator_enable_regmap,
363 .disable = regulator_disable_regmap,
31a932e1 364 .get_voltage_sel = regulator_get_voltage_sel_regmap,
df2643cf 365 .set_voltage_sel = s5m8767_set_voltage_sel,
9767ec7f
SK		 366 .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
367};
368
e2eb169b 369static struct regulator_ops s5m8767_buck78_ops = {
463616ea 370 .list_voltage = regulator_list_voltage_linear,
9c4c6055
AL		 371 .is_enabled = regulator_is_enabled_regmap,
372 .enable = regulator_enable_regmap,
373 .disable = regulator_disable_regmap,
463616ea
KK		 374 .get_voltage_sel = regulator_get_voltage_sel_regmap,
375 .set_voltage_sel = regulator_set_voltage_sel_regmap,
e2eb169b
AL		 376};
377
65896e73
AL		 378#define s5m8767_regulator_desc(_name) { \
379 .name = #_name, \
380 .id = S5M8767_##_name, \
381 .ops = &s5m8767_ops, \
9767ec7f
SK		 382 .type = REGULATOR_VOLTAGE, \
383 .owner = THIS_MODULE, \
384}
385
e2eb169b
AL		 386#define s5m8767_regulator_buck78_desc(_name) { \
387 .name = #_name, \
388 .id = S5M8767_##_name, \
389 .ops = &s5m8767_buck78_ops, \
390 .type = REGULATOR_VOLTAGE, \
391 .owner = THIS_MODULE, \
392}
393
9767ec7f 394static struct regulator_desc regulators[] = {
65896e73
AL		 395 s5m8767_regulator_desc(LDO1),
396 s5m8767_regulator_desc(LDO2),
397 s5m8767_regulator_desc(LDO3),
398 s5m8767_regulator_desc(LDO4),
399 s5m8767_regulator_desc(LDO5),
400 s5m8767_regulator_desc(LDO6),
401 s5m8767_regulator_desc(LDO7),
402 s5m8767_regulator_desc(LDO8),
403 s5m8767_regulator_desc(LDO9),
404 s5m8767_regulator_desc(LDO10),
405 s5m8767_regulator_desc(LDO11),
406 s5m8767_regulator_desc(LDO12),
407 s5m8767_regulator_desc(LDO13),
408 s5m8767_regulator_desc(LDO14),
409 s5m8767_regulator_desc(LDO15),
410 s5m8767_regulator_desc(LDO16),
411 s5m8767_regulator_desc(LDO17),
412 s5m8767_regulator_desc(LDO18),
413 s5m8767_regulator_desc(LDO19),
414 s5m8767_regulator_desc(LDO20),
415 s5m8767_regulator_desc(LDO21),
416 s5m8767_regulator_desc(LDO22),
417 s5m8767_regulator_desc(LDO23),
418 s5m8767_regulator_desc(LDO24),
419 s5m8767_regulator_desc(LDO25),
420 s5m8767_regulator_desc(LDO26),
421 s5m8767_regulator_desc(LDO27),
422 s5m8767_regulator_desc(LDO28),
423 s5m8767_regulator_desc(BUCK1),
424 s5m8767_regulator_desc(BUCK2),
425 s5m8767_regulator_desc(BUCK3),
426 s5m8767_regulator_desc(BUCK4),
427 s5m8767_regulator_desc(BUCK5),
428 s5m8767_regulator_desc(BUCK6),
e2eb169b
AL		 429 s5m8767_regulator_buck78_desc(BUCK7),
430 s5m8767_regulator_buck78_desc(BUCK8),
65896e73 431 s5m8767_regulator_desc(BUCK9),
9767ec7f
SK		 432};
433
ee1e0994
KK		 434/*
435 * Enable GPIO control over BUCK9 in regulator_config for that regulator.
436 */
437static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767,
438 struct sec_regulator_data *rdata,
439 struct regulator_config *config)
440{
441 int i, mode = 0;
442
443 if (rdata->id != S5M8767_BUCK9)
444 return;
445
446 /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */
447 for (i = 0; i < s5m8767->num_regulators; i++) {
448 const struct sec_opmode_data *opmode = &s5m8767->opmode[i];
449 if (opmode->id == rdata->id) {
450 mode = s5m8767_opmode_reg[rdata->id][opmode->mode];
451 break;
452 }
453 }
454 if (mode != S5M8767_ENCTRL_USE_GPIO) {
455 dev_warn(s5m8767->dev,
456 "ext-control for %s: mismatched op_mode (%x), ignoring\n",
457 rdata->reg_node->name, mode);
458 return;
459 }
460
461 if (!gpio_is_valid(rdata->ext_control_gpio)) {
462 dev_warn(s5m8767->dev,
463 "ext-control for %s: GPIO not valid, ignoring\n",
464 rdata->reg_node->name);
465 return;
466 }
467
468 config->ena_gpio = rdata->ext_control_gpio;
469 config->ena_gpio_flags = GPIOF_OUT_INIT_HIGH;
470}
471
472/*
473 * Turn on GPIO control over BUCK9.
474 */
475static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767,
476 struct regulator_dev *rdev)
477{
9c4c6055 478 int id = rdev_get_id(rdev);
ee1e0994
KK		 479 int ret, reg, enable_ctrl;
480
9c4c6055 481 if (id != S5M8767_BUCK9)
ee1e0994
KK		 482 return -EINVAL;
483
9c4c6055 484 ret = s5m8767_get_register(s5m8767, id, &reg, &enable_ctrl);
ee1e0994
KK		 485 if (ret)
486 return ret;
487
488 return regmap_update_bits(s5m8767->iodev->regmap_pmic,
489 reg, S5M8767_ENCTRL_MASK,
490 S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT);
491}
492
493
26aec009
ADK		 494#ifdef CONFIG_OF
495static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
496 struct sec_platform_data *pdata,
497 struct device_node *pmic_np)
498{
499 int i, gpio;
500
501 for (i = 0; i < 3; i++) {
502 gpio = of_get_named_gpio(pmic_np,
503 "s5m8767,pmic-buck-dvs-gpios", i);
504 if (!gpio_is_valid(gpio)) {
505 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
506 return -EINVAL;
507 }
508 pdata->buck_gpios[i] = gpio;
509 }
510 return 0;
511}
512
513static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
514 struct sec_platform_data *pdata,
515 struct device_node *pmic_np)
516{
517 int i, gpio;
518
519 for (i = 0; i < 3; i++) {
520 gpio = of_get_named_gpio(pmic_np,
521 "s5m8767,pmic-buck-ds-gpios", i);
522 if (!gpio_is_valid(gpio)) {
523 dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
524 return -EINVAL;
525 }
526 pdata->buck_ds[i] = gpio;
527 }
528 return 0;
529}
530
cbb0ed49 531static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 532 struct sec_platform_data *pdata)
533{
cbb0ed49 534 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009
ADK		 535 struct device_node *pmic_np, *regulators_np, *reg_np;
536 struct sec_regulator_data *rdata;
537 struct sec_opmode_data *rmode;
04f9f068 538 unsigned int i, dvs_voltage_nr = 8, ret;
26aec009
ADK		 539
540 pmic_np = iodev->dev->of_node;
541 if (!pmic_np) {
542 dev_err(iodev->dev, "could not find pmic sub-node\n");
543 return -ENODEV;
544 }
545
4e52c03d 546 regulators_np = of_get_child_by_name(pmic_np, "regulators");
26aec009
ADK		 547 if (!regulators_np) {
548 dev_err(iodev->dev, "could not find regulators sub-node\n");
549 return -EINVAL;
550 }
551
552 /* count the number of regulators to be supported in pmic */
1f91b6f6 553 pdata->num_regulators = of_get_child_count(regulators_np);
26aec009 554
cbb0ed49 555 rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) *
26aec009 556 pdata->num_regulators, GFP_KERNEL);
4754b421 557 if (!rdata)
26aec009 558 return -ENOMEM;
26aec009 559
cbb0ed49 560 rmode = devm_kzalloc(&pdev->dev, sizeof(*rmode) *
26aec009 561 pdata->num_regulators, GFP_KERNEL);
4754b421 562 if (!rmode)
26aec009 563 return -ENOMEM;
26aec009
ADK		 564
565 pdata->regulators = rdata;
566 pdata->opmode = rmode;
567 for_each_child_of_node(regulators_np, reg_np) {
568 for (i = 0; i < ARRAY_SIZE(regulators); i++)
569 if (!of_node_cmp(reg_np->name, regulators[i].name))
570 break;
571
572 if (i == ARRAY_SIZE(regulators)) {
573 dev_warn(iodev->dev,
574 "don't know how to configure regulator %s\n",
575 reg_np->name);
576 continue;
577 }
578
eba430c7
KK		 579 rdata->ext_control_gpio = of_get_named_gpio(reg_np,
580 "s5m8767,pmic-ext-control-gpios", 0);
ee1e0994 581
26aec009
ADK		 582 rdata->id = i;
583 rdata->initdata = of_get_regulator_init_data(
cbb0ed49 584 &pdev->dev, reg_np);
26aec009
ADK		 585 rdata->reg_node = reg_np;
586 rdata++;
587 rmode->id = i;
588 if (of_property_read_u32(reg_np, "op_mode",
589 &rmode->mode)) {
590 dev_warn(iodev->dev,
591 "no op_mode property property at %s\n",
592 reg_np->full_name);
593
594 rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
595 }
596 rmode++;
597 }
598
b7db01f3
SK		 599 of_node_put(regulators_np);
600
04f9f068 601 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) {
26aec009
ADK		 602 pdata->buck2_gpiodvs = true;
603
04f9f068
CC		 604 if (of_property_read_u32_array(pmic_np,
605 "s5m8767,pmic-buck2-dvs-voltage",
606 pdata->buck2_voltage, dvs_voltage_nr)) {
607 dev_err(iodev->dev, "buck2 voltages not specified\n");
608 return -EINVAL;
609 }
610 }
611
612 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) {
26aec009
ADK		 613 pdata->buck3_gpiodvs = true;
614
04f9f068
CC		 615 if (of_property_read_u32_array(pmic_np,
616 "s5m8767,pmic-buck3-dvs-voltage",
617 pdata->buck3_voltage, dvs_voltage_nr)) {
618 dev_err(iodev->dev, "buck3 voltages not specified\n");
619 return -EINVAL;
620 }
621 }
622
623 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) {
26aec009
ADK		 624 pdata->buck4_gpiodvs = true;
625
04f9f068
CC		 626 if (of_property_read_u32_array(pmic_np,
627 "s5m8767,pmic-buck4-dvs-voltage",
628 pdata->buck4_voltage, dvs_voltage_nr)) {
629 dev_err(iodev->dev, "buck4 voltages not specified\n");
630 return -EINVAL;
631 }
632 }
633
26aec009
ADK		 634 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
635 pdata->buck4_gpiodvs) {
636 ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
637 if (ret)
638 return -EINVAL;
639
640 if (of_property_read_u32(pmic_np,
641 "s5m8767,pmic-buck-default-dvs-idx",
642 &pdata->buck_default_idx)) {
643 pdata->buck_default_idx = 0;
644 } else {
645 if (pdata->buck_default_idx >= 8) {
646 pdata->buck_default_idx = 0;
647 dev_info(iodev->dev,
648 "invalid value for default dvs index, use 0\n");
649 }
650 }
26aec009
ADK		 651 }
652
653 ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
654 if (ret)
655 return -EINVAL;
656
033054e8
CC		 657 if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL))
658 pdata->buck2_ramp_enable = true;
26aec009 659
033054e8
CC		 660 if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL))
661 pdata->buck3_ramp_enable = true;
26aec009 662
033054e8
CC		 663 if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL))
664 pdata->buck4_ramp_enable = true;
665
666 if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
667 || pdata->buck4_ramp_enable) {
668 if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
669 &pdata->buck_ramp_delay))
670 pdata->buck_ramp_delay = 0;
26aec009
ADK		 671 }
672
673 return 0;
674}
675#else
cbb0ed49 676static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
26aec009
ADK		 677 struct sec_platform_data *pdata)
678{
679 return 0;
680}
681#endif /* CONFIG_OF */
682
a5023574 683static int s5m8767_pmic_probe(struct platform_device *pdev)
9767ec7f 684{
63063bfb 685 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
26aec009 686 struct sec_platform_data *pdata = iodev->pdata;
c172708d 687 struct regulator_config config = { };
9767ec7f 688 struct s5m8767_info *s5m8767;
c848bc85 689 int i, ret, size, buck_init;
9767ec7f 690
e81d7bc8
AL		 691 if (!pdata) {
692 dev_err(pdev->dev.parent, "Platform data not supplied\n");
693 return -ENODEV;
694 }
695
26aec009 696 if (iodev->dev->of_node) {
cbb0ed49 697 ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
26aec009
ADK		 698 if (ret)
699 return ret;
700 }
701
6c4efe24
AL		 702 if (pdata->buck2_gpiodvs) {
703 if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
704 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
705 return -EINVAL;
706 }
707 }
708
709 if (pdata->buck3_gpiodvs) {
710 if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
711 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
712 return -EINVAL;
713 }
714 }
715
716 if (pdata->buck4_gpiodvs) {
717 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
718 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
719 return -EINVAL;
720 }
721 }
722
9767ec7f
SK		 723 s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
724 GFP_KERNEL);
725 if (!s5m8767)
726 return -ENOMEM;
727
728 size = sizeof(struct regulator_dev *) * (S5M8767_REG_MAX - 2);
9767ec7f 729
9767ec7f
SK		 730 s5m8767->dev = &pdev->dev;
731 s5m8767->iodev = iodev;
9bb096ff 732 s5m8767->num_regulators = pdata->num_regulators;
9767ec7f 733 platform_set_drvdata(pdev, s5m8767);
9767ec7f
SK		 734
735 s5m8767->buck_gpioindex = pdata->buck_default_idx;
736 s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
737 s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
738 s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
739 s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
740 s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
741 s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
c848bc85
SK		 742 s5m8767->buck_ds[0] = pdata->buck_ds[0];
743 s5m8767->buck_ds[1] = pdata->buck_ds[1];
744 s5m8767->buck_ds[2] = pdata->buck_ds[2];
745
9767ec7f
SK		 746 s5m8767->ramp_delay = pdata->buck_ramp_delay;
747 s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
748 s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
749 s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
7e44bb83 750 s5m8767->opmode = pdata->opmode;
9767ec7f 751
c848bc85 752 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 753 pdata->buck2_init);
c848bc85 754
d13733f4
KK		 755 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2,
756 buck_init);
c848bc85
SK		 757
758 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 759 pdata->buck3_init);
c848bc85 760
d13733f4
KK		 761 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2,
762 buck_init);
c848bc85
SK		 763
764 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
854f73ec 765 pdata->buck4_init);
c848bc85 766
d13733f4
KK		 767 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2,
768 buck_init);
c848bc85 769
9767ec7f
SK		 770 for (i = 0; i < 8; i++) {
771 if (s5m8767->buck2_gpiodvs) {
772 s5m8767->buck2_vol[i] =
5b5e977c 773 s5m8767_convert_voltage_to_sel(
9767ec7f 774 &buck_voltage_val2,
854f73ec 775 pdata->buck2_voltage[i]);
9767ec7f
SK		 776 }
777
778 if (s5m8767->buck3_gpiodvs) {
779 s5m8767->buck3_vol[i] =
5b5e977c 780 s5m8767_convert_voltage_to_sel(
9767ec7f 781 &buck_voltage_val2,
854f73ec 782 pdata->buck3_voltage[i]);
9767ec7f
SK		 783 }
784
785 if (s5m8767->buck4_gpiodvs) {
786 s5m8767->buck4_vol[i] =
5b5e977c 787 s5m8767_convert_voltage_to_sel(
9767ec7f 788 &buck_voltage_val2,
854f73ec 789 pdata->buck4_voltage[i]);
9767ec7f
SK		 790 }
791 }
792
76c854d1
ADK		 793 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
794 pdata->buck4_gpiodvs) {
795
796 if (!gpio_is_valid(pdata->buck_gpios[0]) ||
797 !gpio_is_valid(pdata->buck_gpios[1]) ||
798 !gpio_is_valid(pdata->buck_gpios[2])) {
799 dev_err(&pdev->dev, "GPIO NOT VALID\n");
800 return -EINVAL;
801 }
802
5febb3c9
AL		 803 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
804 "S5M8767 SET1");
805 if (ret)
806 return ret;
807
808 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
809 "S5M8767 SET2");
810 if (ret)
811 return ret;
812
813 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
814 "S5M8767 SET3");
815 if (ret)
816 return ret;
817
c848bc85
SK		 818 /* SET1 GPIO */
819 gpio_direction_output(pdata->buck_gpios[0],
820 (s5m8767->buck_gpioindex >> 2) & 0x1);
821 /* SET2 GPIO */
822 gpio_direction_output(pdata->buck_gpios[1],
823 (s5m8767->buck_gpioindex >> 1) & 0x1);
824 /* SET3 GPIO */
825 gpio_direction_output(pdata->buck_gpios[2],
826 (s5m8767->buck_gpioindex >> 0) & 0x1);
9767ec7f
SK		 827 }
828
5febb3c9
AL		 829 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
830 if (ret)
831 return ret;
c848bc85 832
5febb3c9
AL		 833 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
834 if (ret)
835 return ret;
c848bc85 836
5febb3c9
AL		 837 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
838 if (ret)
839 return ret;
c848bc85
SK		 840
841 /* DS2 GPIO */
842 gpio_direction_output(pdata->buck_ds[0], 0x0);
843 /* DS3 GPIO */
844 gpio_direction_output(pdata->buck_ds[1], 0x0);
845 /* DS4 GPIO */
846 gpio_direction_output(pdata->buck_ds[2], 0x0);
847
848 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
849 pdata->buck4_gpiodvs) {
d13733f4
KK		 850 regmap_update_bits(s5m8767->iodev->regmap_pmic,
851 S5M8767_REG_BUCK2CTRL, 1 << 1,
852 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1));
853 regmap_update_bits(s5m8767->iodev->regmap_pmic,
854 S5M8767_REG_BUCK3CTRL, 1 << 1,
855 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1));
856 regmap_update_bits(s5m8767->iodev->regmap_pmic,
857 S5M8767_REG_BUCK4CTRL, 1 << 1,
858 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1));
c848bc85 859 }
9767ec7f
SK		 860
861 /* Initialize GPIO DVS registers */
862 for (i = 0; i < 8; i++) {
863 if (s5m8767->buck2_gpiodvs) {
d13733f4
KK		 864 regmap_write(s5m8767->iodev->regmap_pmic,
865 S5M8767_REG_BUCK2DVS1 + i,
866 s5m8767->buck2_vol[i]);
9767ec7f
SK		 867 }
868
869 if (s5m8767->buck3_gpiodvs) {
d13733f4
KK		 870 regmap_write(s5m8767->iodev->regmap_pmic,
871 S5M8767_REG_BUCK3DVS1 + i,
872 s5m8767->buck3_vol[i]);
9767ec7f
SK		 873 }
874
875 if (s5m8767->buck4_gpiodvs) {
d13733f4
KK		 876 regmap_write(s5m8767->iodev->regmap_pmic,
877 S5M8767_REG_BUCK4DVS1 + i,
878 s5m8767->buck4_vol[i]);
9767ec7f
SK		 879 }
880 }
9767ec7f
SK		 881
882 if (s5m8767->buck2_ramp)
d13733f4
KK		 883 regmap_update_bits(s5m8767->iodev->regmap_pmic,
884 S5M8767_REG_DVSRAMP, 0x08, 0x08);
9767ec7f
SK		 885
886 if (s5m8767->buck3_ramp)
d13733f4
KK		 887 regmap_update_bits(s5m8767->iodev->regmap_pmic,
888 S5M8767_REG_DVSRAMP, 0x04, 0x04);
9767ec7f
SK		 889
890 if (s5m8767->buck4_ramp)
d13733f4
KK		 891 regmap_update_bits(s5m8767->iodev->regmap_pmic,
892 S5M8767_REG_DVSRAMP, 0x02, 0x02);
9767ec7f
SK		 893
894 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
895 || s5m8767->buck4_ramp) {
f37ff6b6 896 unsigned int val;
9767ec7f 897 switch (s5m8767->ramp_delay) {
1af142c6 898 case 5:
f37ff6b6 899 val = S5M8767_DVS_BUCK_RAMP_5;
1af142c6
SK		 900 break;
901 case 10:
f37ff6b6 902 val = S5M8767_DVS_BUCK_RAMP_10;
047ec220 903 break;
9767ec7f 904 case 25:
f37ff6b6 905 val = S5M8767_DVS_BUCK_RAMP_25;
047ec220 906 break;
9767ec7f 907 case 50:
f37ff6b6 908 val = S5M8767_DVS_BUCK_RAMP_50;
047ec220 909 break;
9767ec7f 910 case 100:
f37ff6b6 911 val = S5M8767_DVS_BUCK_RAMP_100;
047ec220 912 break;
9767ec7f 913 default:
f37ff6b6 914 val = S5M8767_DVS_BUCK_RAMP_10;
9767ec7f 915 }
d13733f4
KK		 916 regmap_update_bits(s5m8767->iodev->regmap_pmic,
917 S5M8767_REG_DVSRAMP,
918 S5M8767_DVS_BUCK_RAMP_MASK,
919 val << S5M8767_DVS_BUCK_RAMP_SHIFT);
9767ec7f
SK		 920 }
921
922 for (i = 0; i < pdata->num_regulators; i++) {
63063bfb 923 const struct sec_voltage_desc *desc;
9767ec7f 924 int id = pdata->regulators[i].id;
9c4c6055 925 int enable_reg, enable_val;
e80fb721 926 struct regulator_dev *rdev;
9767ec7f
SK		 927
928 desc = reg_voltage_map[id];
e2eb169b 929 if (desc) {
9767ec7f
SK		 930 regulators[id].n_voltages =
931 (desc->max - desc->min) / desc->step + 1;
e2eb169b
AL		 932 regulators[id].min_uV = desc->min;
933 regulators[id].uV_step = desc->step;
31a932e1
AL		 934 regulators[id].vsel_reg =
935 s5m8767_get_vsel_reg(id, s5m8767);
936 if (id < S5M8767_BUCK1)
937 regulators[id].vsel_mask = 0x3f;
938 else
939 regulators[id].vsel_mask = 0xff;
9c4c6055
AL		 940
941 s5m8767_get_register(s5m8767, id, &enable_reg,
942 &enable_val);
943 regulators[id].enable_reg = enable_reg;
944 regulators[id].enable_mask = S5M8767_ENCTRL_MASK;
945 regulators[id].enable_val = enable_val;
e2eb169b 946 }
9767ec7f 947
c172708d
MB		 948 config.dev = s5m8767->dev;
949 config.init_data = pdata->regulators[i].initdata;
950 config.driver_data = s5m8767;
3e1e4a5f 951 config.regmap = iodev->regmap_pmic;
26aec009 952 config.of_node = pdata->regulators[i].reg_node;
eba430c7
KK		 953 config.ena_gpio = -EINVAL;
954 config.ena_gpio_flags = 0;
955 if (gpio_is_valid(pdata->regulators[i].ext_control_gpio))
ee1e0994
KK		 956 s5m8767_regulator_config_ext_control(s5m8767,
957 &pdata->regulators[i], &config);
c172708d 958
e80fb721 959 rdev = devm_regulator_register(&pdev->dev, &regulators[id],
f0db475d 960 &config);
e80fb721
KK		 961 if (IS_ERR(rdev)) {
962 ret = PTR_ERR(rdev);
9767ec7f
SK		 963 dev_err(s5m8767->dev, "regulator init failed for %d\n",
964 id);
f0db475d 965 return ret;
9767ec7f 966 }
ee1e0994 967
eba430c7 968 if (gpio_is_valid(pdata->regulators[i].ext_control_gpio)) {
e80fb721 969 ret = s5m8767_enable_ext_control(s5m8767, rdev);
ee1e0994
KK		 970 if (ret < 0) {
971 dev_err(s5m8767->dev,
972 "failed to enable gpio control over %s: %d\n",
e80fb721 973 rdev->desc->name, ret);
ee1e0994
KK		 974 return ret;
975 }
976 }
9767ec7f
SK		 977 }
978
9767ec7f
SK		 979 return 0;
980}
981
982static const struct platform_device_id s5m8767_pmic_id[] = {
983 { "s5m8767-pmic", 0},
984 { },
985};
986MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
987
988static struct platform_driver s5m8767_pmic_driver = {
989 .driver = {
990 .name = "s5m8767-pmic",
991 .owner = THIS_MODULE,
992 },
993 .probe = s5m8767_pmic_probe,
9767ec7f
SK		 994 .id_table = s5m8767_pmic_id,
995};
996
997static int __init s5m8767_pmic_init(void)
998{
999 return platform_driver_register(&s5m8767_pmic_driver);
1000}
1001subsys_initcall(s5m8767_pmic_init);
1002
1003static void __exit s5m8767_pmic_exit(void)
1004{
1005 platform_driver_unregister(&s5m8767_pmic_driver);
1006}
1007module_exit(s5m8767_pmic_exit);
1008
1009/* Module information */
1010MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
1011MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver");
1012MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)