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e92a4047 SB |
1 | /* |
2 | * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/bitops.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/ktime.h> | |
25 | #include <linux/regulator/driver.h> | |
26 | #include <linux/regmap.h> | |
27 | #include <linux/list.h> | |
0caecaa8 IL |
28 | #include <linux/mfd/syscon.h> |
29 | #include <linux/io.h> | |
e92a4047 | 30 | |
e2adfacd SB |
31 | /* Pin control enable input pins. */ |
32 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00 | |
33 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01 | |
34 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02 | |
35 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04 | |
36 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08 | |
37 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10 | |
38 | ||
39 | /* Pin control high power mode input pins. */ | |
40 | #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00 | |
41 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01 | |
42 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02 | |
43 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04 | |
44 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08 | |
45 | #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10 | |
46 | #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20 | |
47 | ||
48 | /* | |
49 | * Used with enable parameters to specify that hardware default register values | |
50 | * should be left unaltered. | |
51 | */ | |
52 | #define SPMI_REGULATOR_USE_HW_DEFAULT 2 | |
53 | ||
54 | /* Soft start strength of a voltage switch type regulator */ | |
55 | enum spmi_vs_soft_start_str { | |
56 | SPMI_VS_SOFT_START_STR_0P05_UA = 0, | |
57 | SPMI_VS_SOFT_START_STR_0P25_UA, | |
58 | SPMI_VS_SOFT_START_STR_0P55_UA, | |
59 | SPMI_VS_SOFT_START_STR_0P75_UA, | |
60 | SPMI_VS_SOFT_START_STR_HW_DEFAULT, | |
61 | }; | |
62 | ||
63 | /** | |
64 | * struct spmi_regulator_init_data - spmi-regulator initialization data | |
65 | * @pin_ctrl_enable: Bit mask specifying which hardware pins should be | |
66 | * used to enable the regulator, if any | |
67 | * Value should be an ORing of | |
68 | * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If | |
69 | * the bit specified by | |
70 | * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is | |
71 | * set, then pin control enable hardware registers | |
72 | * will not be modified. | |
73 | * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be | |
74 | * used to force the regulator into high power | |
75 | * mode, if any | |
76 | * Value should be an ORing of | |
77 | * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If | |
78 | * the bit specified by | |
79 | * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is | |
80 | * set, then pin control mode hardware registers | |
81 | * will not be modified. | |
82 | * @vs_soft_start_strength: This parameter sets the soft start strength for | |
83 | * voltage switch type regulators. Its value | |
84 | * should be one of SPMI_VS_SOFT_START_STR_*. If | |
85 | * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT, | |
86 | * then the soft start strength will be left at its | |
87 | * default hardware value. | |
88 | */ | |
89 | struct spmi_regulator_init_data { | |
90 | unsigned pin_ctrl_enable; | |
91 | unsigned pin_ctrl_hpm; | |
92 | enum spmi_vs_soft_start_str vs_soft_start_strength; | |
93 | }; | |
94 | ||
e92a4047 SB |
95 | /* These types correspond to unique register layouts. */ |
96 | enum spmi_regulator_logical_type { | |
97 | SPMI_REGULATOR_LOGICAL_TYPE_SMPS, | |
98 | SPMI_REGULATOR_LOGICAL_TYPE_LDO, | |
99 | SPMI_REGULATOR_LOGICAL_TYPE_VS, | |
100 | SPMI_REGULATOR_LOGICAL_TYPE_BOOST, | |
101 | SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS, | |
102 | SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP, | |
103 | SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO, | |
104 | SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS, | |
105 | SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, | |
106 | SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, | |
107 | }; | |
108 | ||
109 | enum spmi_regulator_type { | |
110 | SPMI_REGULATOR_TYPE_BUCK = 0x03, | |
111 | SPMI_REGULATOR_TYPE_LDO = 0x04, | |
112 | SPMI_REGULATOR_TYPE_VS = 0x05, | |
113 | SPMI_REGULATOR_TYPE_BOOST = 0x1b, | |
114 | SPMI_REGULATOR_TYPE_FTS = 0x1c, | |
115 | SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f, | |
116 | SPMI_REGULATOR_TYPE_ULT_LDO = 0x21, | |
117 | SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22, | |
118 | }; | |
119 | ||
120 | enum spmi_regulator_subtype { | |
121 | SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08, | |
122 | SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09, | |
123 | SPMI_REGULATOR_SUBTYPE_N50 = 0x01, | |
124 | SPMI_REGULATOR_SUBTYPE_N150 = 0x02, | |
125 | SPMI_REGULATOR_SUBTYPE_N300 = 0x03, | |
126 | SPMI_REGULATOR_SUBTYPE_N600 = 0x04, | |
127 | SPMI_REGULATOR_SUBTYPE_N1200 = 0x05, | |
128 | SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06, | |
129 | SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07, | |
130 | SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14, | |
131 | SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15, | |
132 | SPMI_REGULATOR_SUBTYPE_P50 = 0x08, | |
133 | SPMI_REGULATOR_SUBTYPE_P150 = 0x09, | |
134 | SPMI_REGULATOR_SUBTYPE_P300 = 0x0a, | |
135 | SPMI_REGULATOR_SUBTYPE_P600 = 0x0b, | |
136 | SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c, | |
137 | SPMI_REGULATOR_SUBTYPE_LN = 0x10, | |
138 | SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28, | |
139 | SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29, | |
140 | SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a, | |
141 | SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b, | |
142 | SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c, | |
143 | SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d, | |
144 | SPMI_REGULATOR_SUBTYPE_LV100 = 0x01, | |
145 | SPMI_REGULATOR_SUBTYPE_LV300 = 0x02, | |
146 | SPMI_REGULATOR_SUBTYPE_MV300 = 0x08, | |
147 | SPMI_REGULATOR_SUBTYPE_MV500 = 0x09, | |
148 | SPMI_REGULATOR_SUBTYPE_HDMI = 0x10, | |
149 | SPMI_REGULATOR_SUBTYPE_OTG = 0x11, | |
150 | SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01, | |
151 | SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08, | |
152 | SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09, | |
153 | SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01, | |
154 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d, | |
155 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, | |
156 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, | |
157 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, | |
158 | }; | |
159 | ||
160 | enum spmi_common_regulator_registers { | |
161 | SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01, | |
162 | SPMI_COMMON_REG_TYPE = 0x04, | |
163 | SPMI_COMMON_REG_SUBTYPE = 0x05, | |
164 | SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40, | |
165 | SPMI_COMMON_REG_VOLTAGE_SET = 0x41, | |
166 | SPMI_COMMON_REG_MODE = 0x45, | |
167 | SPMI_COMMON_REG_ENABLE = 0x46, | |
168 | SPMI_COMMON_REG_PULL_DOWN = 0x48, | |
169 | SPMI_COMMON_REG_SOFT_START = 0x4c, | |
170 | SPMI_COMMON_REG_STEP_CTRL = 0x61, | |
171 | }; | |
172 | ||
173 | enum spmi_vs_registers { | |
174 | SPMI_VS_REG_OCP = 0x4a, | |
175 | SPMI_VS_REG_SOFT_START = 0x4c, | |
176 | }; | |
177 | ||
178 | enum spmi_boost_registers { | |
179 | SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a, | |
180 | }; | |
181 | ||
182 | enum spmi_boost_byp_registers { | |
183 | SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, | |
184 | }; | |
185 | ||
0caecaa8 IL |
186 | enum spmi_saw3_registers { |
187 | SAW3_SECURE = 0x00, | |
188 | SAW3_ID = 0x04, | |
189 | SAW3_SPM_STS = 0x0C, | |
190 | SAW3_AVS_STS = 0x10, | |
191 | SAW3_PMIC_STS = 0x14, | |
192 | SAW3_RST = 0x18, | |
193 | SAW3_VCTL = 0x1C, | |
194 | SAW3_AVS_CTL = 0x20, | |
195 | SAW3_AVS_LIMIT = 0x24, | |
196 | SAW3_AVS_DLY = 0x28, | |
197 | SAW3_AVS_HYSTERESIS = 0x2C, | |
198 | SAW3_SPM_STS2 = 0x38, | |
199 | SAW3_SPM_PMIC_DATA_3 = 0x4C, | |
200 | SAW3_VERSION = 0xFD0, | |
201 | }; | |
202 | ||
e92a4047 SB |
203 | /* Used for indexing into ctrl_reg. These are offets from 0x40 */ |
204 | enum spmi_common_control_register_index { | |
205 | SPMI_COMMON_IDX_VOLTAGE_RANGE = 0, | |
206 | SPMI_COMMON_IDX_VOLTAGE_SET = 1, | |
207 | SPMI_COMMON_IDX_MODE = 5, | |
208 | SPMI_COMMON_IDX_ENABLE = 6, | |
209 | }; | |
210 | ||
211 | /* Common regulator control register layout */ | |
212 | #define SPMI_COMMON_ENABLE_MASK 0x80 | |
213 | #define SPMI_COMMON_ENABLE 0x80 | |
214 | #define SPMI_COMMON_DISABLE 0x00 | |
215 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08 | |
216 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04 | |
217 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02 | |
218 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01 | |
219 | #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f | |
220 | ||
221 | /* Common regulator mode register layout */ | |
222 | #define SPMI_COMMON_MODE_HPM_MASK 0x80 | |
223 | #define SPMI_COMMON_MODE_AUTO_MASK 0x40 | |
224 | #define SPMI_COMMON_MODE_BYPASS_MASK 0x20 | |
225 | #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10 | |
226 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08 | |
227 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04 | |
228 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02 | |
229 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01 | |
230 | #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f | |
231 | ||
232 | /* Common regulator pull down control register layout */ | |
233 | #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 | |
234 | ||
235 | /* LDO regulator current limit control register layout */ | |
236 | #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80 | |
237 | ||
238 | /* LDO regulator soft start control register layout */ | |
239 | #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80 | |
240 | ||
241 | /* VS regulator over current protection control register layout */ | |
242 | #define SPMI_VS_OCP_OVERRIDE 0x01 | |
243 | #define SPMI_VS_OCP_NO_OVERRIDE 0x00 | |
244 | ||
245 | /* VS regulator soft start control register layout */ | |
246 | #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80 | |
247 | #define SPMI_VS_SOFT_START_SEL_MASK 0x03 | |
248 | ||
249 | /* Boost regulator current limit control register layout */ | |
250 | #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80 | |
251 | #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07 | |
252 | ||
253 | #define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10 | |
254 | #define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30 | |
255 | #define SPMI_VS_OCP_FALL_DELAY_US 90 | |
256 | #define SPMI_VS_OCP_FAULT_DELAY_US 20000 | |
257 | ||
258 | #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18 | |
259 | #define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3 | |
260 | #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 | |
261 | #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 | |
262 | ||
263 | /* Clock rate in kHz of the FTSMPS regulator reference clock. */ | |
264 | #define SPMI_FTSMPS_CLOCK_RATE 19200 | |
265 | ||
266 | /* Minimum voltage stepper delay for each step. */ | |
267 | #define SPMI_FTSMPS_STEP_DELAY 8 | |
2cf7b99c | 268 | #define SPMI_DEFAULT_STEP_DELAY 20 |
e92a4047 SB |
269 | |
270 | /* | |
271 | * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to | |
272 | * adjust the step rate in order to account for oscillator variance. | |
273 | */ | |
274 | #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 | |
275 | #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 | |
276 | ||
e92a4047 SB |
277 | /* VSET value to decide the range of ULT SMPS */ |
278 | #define ULT_SMPS_RANGE_SPLIT 0x60 | |
279 | ||
280 | /** | |
281 | * struct spmi_voltage_range - regulator set point voltage mapping description | |
282 | * @min_uV: Minimum programmable output voltage resulting from | |
283 | * set point register value 0x00 | |
284 | * @max_uV: Maximum programmable output voltage | |
285 | * @step_uV: Output voltage increase resulting from the set point | |
286 | * register value increasing by 1 | |
287 | * @set_point_min_uV: Minimum allowed voltage | |
288 | * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order | |
289 | * to pick which range should be used in the case of | |
290 | * overlapping set points. | |
291 | * @n_voltages: Number of preferred voltage set points present in this | |
292 | * range | |
293 | * @range_sel: Voltage range register value corresponding to this range | |
294 | * | |
295 | * The following relationships must be true for the values used in this struct: | |
296 | * (max_uV - min_uV) % step_uV == 0 | |
297 | * (set_point_min_uV - min_uV) % step_uV == 0* | |
298 | * (set_point_max_uV - min_uV) % step_uV == 0* | |
299 | * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1 | |
300 | * | |
301 | * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to | |
302 | * specify that the voltage range has meaning, but is not preferred. | |
303 | */ | |
304 | struct spmi_voltage_range { | |
305 | int min_uV; | |
306 | int max_uV; | |
307 | int step_uV; | |
308 | int set_point_min_uV; | |
309 | int set_point_max_uV; | |
310 | unsigned n_voltages; | |
311 | u8 range_sel; | |
312 | }; | |
313 | ||
314 | /* | |
315 | * The ranges specified in the spmi_voltage_set_points struct must be listed | |
316 | * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV. | |
317 | */ | |
318 | struct spmi_voltage_set_points { | |
319 | struct spmi_voltage_range *range; | |
320 | int count; | |
321 | unsigned n_voltages; | |
322 | }; | |
323 | ||
324 | struct spmi_regulator { | |
325 | struct regulator_desc desc; | |
326 | struct device *dev; | |
327 | struct delayed_work ocp_work; | |
328 | struct regmap *regmap; | |
329 | struct spmi_voltage_set_points *set_points; | |
330 | enum spmi_regulator_logical_type logical_type; | |
331 | int ocp_irq; | |
332 | int ocp_count; | |
333 | int ocp_max_retries; | |
334 | int ocp_retry_delay_ms; | |
335 | int hpm_min_load; | |
336 | int slew_rate; | |
337 | ktime_t vs_enable_time; | |
338 | u16 base; | |
339 | struct list_head node; | |
340 | }; | |
341 | ||
342 | struct spmi_regulator_mapping { | |
343 | enum spmi_regulator_type type; | |
344 | enum spmi_regulator_subtype subtype; | |
345 | enum spmi_regulator_logical_type logical_type; | |
346 | u32 revision_min; | |
347 | u32 revision_max; | |
348 | struct regulator_ops *ops; | |
349 | struct spmi_voltage_set_points *set_points; | |
350 | int hpm_min_load; | |
351 | }; | |
352 | ||
353 | struct spmi_regulator_data { | |
354 | const char *name; | |
355 | u16 base; | |
356 | const char *supply; | |
357 | const char *ocp; | |
358 | u16 force_type; | |
359 | }; | |
360 | ||
361 | #define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \ | |
362 | _logical_type, _ops_val, _set_points_val, _hpm_min_load) \ | |
363 | { \ | |
364 | .type = SPMI_REGULATOR_TYPE_##_type, \ | |
365 | .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ | |
366 | .revision_min = _dig_major_min, \ | |
367 | .revision_max = _dig_major_max, \ | |
368 | .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \ | |
369 | .ops = &spmi_##_ops_val##_ops, \ | |
370 | .set_points = &_set_points_val##_set_points, \ | |
371 | .hpm_min_load = _hpm_min_load, \ | |
372 | } | |
373 | ||
374 | #define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \ | |
375 | { \ | |
376 | .type = SPMI_REGULATOR_TYPE_VS, \ | |
377 | .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ | |
378 | .revision_min = _dig_major_min, \ | |
379 | .revision_max = _dig_major_max, \ | |
380 | .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \ | |
381 | .ops = &spmi_vs_ops, \ | |
382 | } | |
383 | ||
384 | #define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \ | |
385 | _set_point_max_uV, _max_uV, _step_uV) \ | |
386 | { \ | |
387 | .min_uV = _min_uV, \ | |
388 | .max_uV = _max_uV, \ | |
389 | .set_point_min_uV = _set_point_min_uV, \ | |
390 | .set_point_max_uV = _set_point_max_uV, \ | |
391 | .step_uV = _step_uV, \ | |
392 | .range_sel = _range_sel, \ | |
393 | } | |
394 | ||
395 | #define DEFINE_SPMI_SET_POINTS(name) \ | |
396 | struct spmi_voltage_set_points name##_set_points = { \ | |
397 | .range = name##_ranges, \ | |
398 | .count = ARRAY_SIZE(name##_ranges), \ | |
399 | } | |
400 | ||
401 | /* | |
402 | * These tables contain the physically available PMIC regulator voltage setpoint | |
403 | * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed | |
404 | * to ensure that the setpoints available to software are monotonically | |
405 | * increasing and unique. The set_voltage callback functions expect these | |
406 | * properties to hold. | |
407 | */ | |
408 | static struct spmi_voltage_range pldo_ranges[] = { | |
409 | SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), | |
410 | SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000), | |
411 | SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000), | |
412 | }; | |
413 | ||
414 | static struct spmi_voltage_range nldo1_ranges[] = { | |
415 | SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), | |
416 | }; | |
417 | ||
418 | static struct spmi_voltage_range nldo2_ranges[] = { | |
419 | SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500), | |
420 | SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250), | |
421 | SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500), | |
422 | }; | |
423 | ||
424 | static struct spmi_voltage_range nldo3_ranges[] = { | |
425 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), | |
426 | SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500), | |
427 | SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500), | |
428 | }; | |
429 | ||
430 | static struct spmi_voltage_range ln_ldo_ranges[] = { | |
431 | SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000), | |
432 | SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000), | |
433 | }; | |
434 | ||
435 | static struct spmi_voltage_range smps_ranges[] = { | |
436 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), | |
437 | SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), | |
438 | }; | |
439 | ||
440 | static struct spmi_voltage_range ftsmps_ranges[] = { | |
441 | SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), | |
442 | SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), | |
443 | }; | |
444 | ||
445 | static struct spmi_voltage_range ftsmps2p5_ranges[] = { | |
446 | SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000), | |
447 | SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000), | |
448 | }; | |
449 | ||
450 | static struct spmi_voltage_range boost_ranges[] = { | |
451 | SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000), | |
452 | }; | |
453 | ||
454 | static struct spmi_voltage_range boost_byp_ranges[] = { | |
455 | SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000), | |
456 | }; | |
457 | ||
458 | static struct spmi_voltage_range ult_lo_smps_ranges[] = { | |
459 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), | |
460 | SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000), | |
461 | }; | |
462 | ||
463 | static struct spmi_voltage_range ult_ho_smps_ranges[] = { | |
464 | SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000), | |
465 | }; | |
466 | ||
467 | static struct spmi_voltage_range ult_nldo_ranges[] = { | |
468 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), | |
469 | }; | |
470 | ||
471 | static struct spmi_voltage_range ult_pldo_ranges[] = { | |
472 | SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500), | |
473 | }; | |
474 | ||
475 | static DEFINE_SPMI_SET_POINTS(pldo); | |
476 | static DEFINE_SPMI_SET_POINTS(nldo1); | |
477 | static DEFINE_SPMI_SET_POINTS(nldo2); | |
478 | static DEFINE_SPMI_SET_POINTS(nldo3); | |
479 | static DEFINE_SPMI_SET_POINTS(ln_ldo); | |
480 | static DEFINE_SPMI_SET_POINTS(smps); | |
481 | static DEFINE_SPMI_SET_POINTS(ftsmps); | |
482 | static DEFINE_SPMI_SET_POINTS(ftsmps2p5); | |
483 | static DEFINE_SPMI_SET_POINTS(boost); | |
484 | static DEFINE_SPMI_SET_POINTS(boost_byp); | |
485 | static DEFINE_SPMI_SET_POINTS(ult_lo_smps); | |
486 | static DEFINE_SPMI_SET_POINTS(ult_ho_smps); | |
487 | static DEFINE_SPMI_SET_POINTS(ult_nldo); | |
488 | static DEFINE_SPMI_SET_POINTS(ult_pldo); | |
489 | ||
490 | static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, | |
491 | int len) | |
492 | { | |
493 | return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); | |
494 | } | |
495 | ||
496 | static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr, | |
497 | u8 *buf, int len) | |
498 | { | |
499 | return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len); | |
500 | } | |
501 | ||
502 | static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val, | |
503 | u8 mask) | |
504 | { | |
505 | return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); | |
506 | } | |
507 | ||
e92a4047 SB |
508 | static int spmi_regulator_vs_enable(struct regulator_dev *rdev) |
509 | { | |
510 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
511 | ||
512 | if (vreg->ocp_irq) { | |
513 | vreg->ocp_count = 0; | |
514 | vreg->vs_enable_time = ktime_get(); | |
515 | } | |
516 | ||
9d485332 | 517 | return regulator_enable_regmap(rdev); |
e92a4047 SB |
518 | } |
519 | ||
e2adfacd SB |
520 | static int spmi_regulator_vs_ocp(struct regulator_dev *rdev) |
521 | { | |
522 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
523 | u8 reg = SPMI_VS_OCP_OVERRIDE; | |
524 | ||
525 | return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1); | |
526 | } | |
527 | ||
e92a4047 | 528 | static int spmi_regulator_select_voltage(struct spmi_regulator *vreg, |
1b5b1968 | 529 | int min_uV, int max_uV) |
e92a4047 SB |
530 | { |
531 | const struct spmi_voltage_range *range; | |
532 | int uV = min_uV; | |
533 | int lim_min_uV, lim_max_uV, i, range_id, range_max_uV; | |
1b5b1968 | 534 | int selector, voltage_sel; |
e92a4047 SB |
535 | |
536 | /* Check if request voltage is outside of physically settable range. */ | |
537 | lim_min_uV = vreg->set_points->range[0].set_point_min_uV; | |
538 | lim_max_uV = | |
539 | vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV; | |
540 | ||
541 | if (uV < lim_min_uV && max_uV >= lim_min_uV) | |
542 | uV = lim_min_uV; | |
543 | ||
544 | if (uV < lim_min_uV || uV > lim_max_uV) { | |
545 | dev_err(vreg->dev, | |
546 | "request v=[%d, %d] is outside possible v=[%d, %d]\n", | |
547 | min_uV, max_uV, lim_min_uV, lim_max_uV); | |
548 | return -EINVAL; | |
549 | } | |
550 | ||
551 | /* Find the range which uV is inside of. */ | |
552 | for (i = vreg->set_points->count - 1; i > 0; i--) { | |
553 | range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV; | |
554 | if (uV > range_max_uV && range_max_uV > 0) | |
555 | break; | |
556 | } | |
557 | ||
558 | range_id = i; | |
559 | range = &vreg->set_points->range[range_id]; | |
e92a4047 SB |
560 | |
561 | /* | |
562 | * Force uV to be an allowed set point by applying a ceiling function to | |
563 | * the uV value. | |
564 | */ | |
1b5b1968 SB |
565 | voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); |
566 | uV = voltage_sel * range->step_uV + range->min_uV; | |
e92a4047 SB |
567 | |
568 | if (uV > max_uV) { | |
569 | dev_err(vreg->dev, | |
570 | "request v=[%d, %d] cannot be met by any set point; " | |
571 | "next set point: %d\n", | |
572 | min_uV, max_uV, uV); | |
573 | return -EINVAL; | |
574 | } | |
575 | ||
1b5b1968 | 576 | selector = 0; |
e92a4047 | 577 | for (i = 0; i < range_id; i++) |
1b5b1968 SB |
578 | selector += vreg->set_points->range[i].n_voltages; |
579 | selector += (uV - range->set_point_min_uV) / range->step_uV; | |
e92a4047 | 580 | |
1b5b1968 SB |
581 | return selector; |
582 | } | |
583 | ||
584 | static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg, | |
585 | unsigned selector, u8 *range_sel, | |
586 | u8 *voltage_sel) | |
587 | { | |
588 | const struct spmi_voltage_range *range, *end; | |
ab953b9d | 589 | unsigned offset; |
1b5b1968 SB |
590 | |
591 | range = vreg->set_points->range; | |
592 | end = range + vreg->set_points->count; | |
593 | ||
594 | for (; range < end; range++) { | |
595 | if (selector < range->n_voltages) { | |
ab953b9d SB |
596 | /* |
597 | * hardware selectors between set point min and real | |
598 | * min are invalid so we ignore them | |
599 | */ | |
600 | offset = range->set_point_min_uV - range->min_uV; | |
601 | offset /= range->step_uV; | |
602 | *voltage_sel = selector + offset; | |
1b5b1968 SB |
603 | *range_sel = range->range_sel; |
604 | return 0; | |
605 | } | |
606 | ||
607 | selector -= range->n_voltages; | |
608 | } | |
609 | ||
610 | return -EINVAL; | |
611 | } | |
612 | ||
613 | static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel, | |
614 | const struct spmi_voltage_range *range) | |
615 | { | |
ab953b9d SB |
616 | unsigned sw_sel = 0; |
617 | unsigned offset, max_hw_sel; | |
1b5b1968 | 618 | const struct spmi_voltage_range *r = vreg->set_points->range; |
ab953b9d SB |
619 | const struct spmi_voltage_range *end = r + vreg->set_points->count; |
620 | ||
621 | for (; r < end; r++) { | |
622 | if (r == range && range->n_voltages) { | |
623 | /* | |
624 | * hardware selectors between set point min and real | |
625 | * min and between set point max and real max are | |
626 | * invalid so we return an error if they're | |
627 | * programmed into the hardware | |
628 | */ | |
629 | offset = range->set_point_min_uV - range->min_uV; | |
630 | offset /= range->step_uV; | |
631 | if (hw_sel < offset) | |
632 | return -EINVAL; | |
633 | ||
634 | max_hw_sel = range->set_point_max_uV - range->min_uV; | |
635 | max_hw_sel /= range->step_uV; | |
636 | if (hw_sel > max_hw_sel) | |
637 | return -EINVAL; | |
638 | ||
639 | return sw_sel + hw_sel - offset; | |
640 | } | |
1b5b1968 | 641 | sw_sel += r->n_voltages; |
1b5b1968 SB |
642 | } |
643 | ||
ab953b9d | 644 | return -EINVAL; |
e92a4047 SB |
645 | } |
646 | ||
647 | static const struct spmi_voltage_range * | |
648 | spmi_regulator_find_range(struct spmi_regulator *vreg) | |
649 | { | |
650 | u8 range_sel; | |
651 | const struct spmi_voltage_range *range, *end; | |
652 | ||
653 | range = vreg->set_points->range; | |
654 | end = range + vreg->set_points->count; | |
655 | ||
656 | spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1); | |
657 | ||
658 | for (; range < end; range++) | |
659 | if (range->range_sel == range_sel) | |
660 | return range; | |
661 | ||
662 | return NULL; | |
663 | } | |
664 | ||
665 | static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, | |
1b5b1968 | 666 | int min_uV, int max_uV) |
e92a4047 SB |
667 | { |
668 | const struct spmi_voltage_range *range; | |
669 | int uV = min_uV; | |
1b5b1968 | 670 | int i, selector; |
e92a4047 SB |
671 | |
672 | range = spmi_regulator_find_range(vreg); | |
673 | if (!range) | |
674 | goto different_range; | |
675 | ||
676 | if (uV < range->min_uV && max_uV >= range->min_uV) | |
677 | uV = range->min_uV; | |
678 | ||
679 | if (uV < range->min_uV || uV > range->max_uV) { | |
680 | /* Current range doesn't support the requested voltage. */ | |
681 | goto different_range; | |
682 | } | |
683 | ||
684 | /* | |
685 | * Force uV to be an allowed set point by applying a ceiling function to | |
686 | * the uV value. | |
687 | */ | |
1b5b1968 SB |
688 | uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); |
689 | uV = uV * range->step_uV + range->min_uV; | |
e92a4047 SB |
690 | |
691 | if (uV > max_uV) { | |
692 | /* | |
693 | * No set point in the current voltage range is within the | |
694 | * requested min_uV to max_uV range. | |
695 | */ | |
696 | goto different_range; | |
697 | } | |
698 | ||
1b5b1968 | 699 | selector = 0; |
e92a4047 SB |
700 | for (i = 0; i < vreg->set_points->count; i++) { |
701 | if (uV >= vreg->set_points->range[i].set_point_min_uV | |
9b2dfee3 | 702 | && uV <= vreg->set_points->range[i].set_point_max_uV) { |
1b5b1968 | 703 | selector += |
e92a4047 SB |
704 | (uV - vreg->set_points->range[i].set_point_min_uV) |
705 | / vreg->set_points->range[i].step_uV; | |
706 | break; | |
9b2dfee3 | 707 | } |
e92a4047 | 708 | |
1b5b1968 | 709 | selector += vreg->set_points->range[i].n_voltages; |
e92a4047 SB |
710 | } |
711 | ||
1b5b1968 | 712 | if (selector >= vreg->set_points->n_voltages) |
e92a4047 SB |
713 | goto different_range; |
714 | ||
b1d21a24 | 715 | return selector; |
e92a4047 SB |
716 | |
717 | different_range: | |
1b5b1968 | 718 | return spmi_regulator_select_voltage(vreg, min_uV, max_uV); |
e92a4047 SB |
719 | } |
720 | ||
1b5b1968 SB |
721 | static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev, |
722 | int min_uV, int max_uV) | |
e92a4047 SB |
723 | { |
724 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
e92a4047 SB |
725 | |
726 | /* | |
727 | * Favor staying in the current voltage range if possible. This avoids | |
728 | * voltage spikes that occur when changing the voltage range. | |
729 | */ | |
1b5b1968 SB |
730 | return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV); |
731 | } | |
732 | ||
733 | static int | |
734 | spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector) | |
735 | { | |
736 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
737 | int ret; | |
738 | u8 buf[2]; | |
739 | u8 range_sel, voltage_sel; | |
740 | ||
741 | ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); | |
e92a4047 SB |
742 | if (ret) |
743 | return ret; | |
744 | ||
745 | buf[0] = range_sel; | |
746 | buf[1] = voltage_sel; | |
747 | return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2); | |
748 | } | |
749 | ||
750 | static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev, | |
751 | unsigned int old_selector, unsigned int new_selector) | |
752 | { | |
753 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
754 | const struct spmi_voltage_range *range; | |
755 | int diff_uV; | |
756 | ||
757 | range = spmi_regulator_find_range(vreg); | |
758 | if (!range) | |
759 | return -EINVAL; | |
760 | ||
761 | diff_uV = abs(new_selector - old_selector) * range->step_uV; | |
762 | ||
763 | return DIV_ROUND_UP(diff_uV, vreg->slew_rate); | |
764 | } | |
765 | ||
766 | static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev) | |
767 | { | |
768 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
769 | const struct spmi_voltage_range *range; | |
770 | u8 voltage_sel; | |
771 | ||
772 | spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); | |
773 | ||
774 | range = spmi_regulator_find_range(vreg); | |
775 | if (!range) | |
1b5b1968 | 776 | return -EINVAL; |
e92a4047 | 777 | |
1b5b1968 | 778 | return spmi_hw_selector_to_sw(vreg, voltage_sel, range); |
e92a4047 SB |
779 | } |
780 | ||
1b5b1968 SB |
781 | static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev, |
782 | int min_uV, int max_uV) | |
e92a4047 SB |
783 | { |
784 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
e92a4047 | 785 | |
1b5b1968 SB |
786 | return spmi_regulator_select_voltage(vreg, min_uV, max_uV); |
787 | } | |
788 | ||
789 | static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev, | |
790 | unsigned selector) | |
791 | { | |
792 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
793 | u8 sel = selector; | |
e92a4047 SB |
794 | |
795 | /* | |
796 | * Certain types of regulators do not have a range select register so | |
797 | * only voltage set register needs to be written. | |
798 | */ | |
799 | return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1); | |
800 | } | |
801 | ||
802 | static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev) | |
803 | { | |
804 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1b5b1968 SB |
805 | u8 selector; |
806 | int ret; | |
e92a4047 | 807 | |
1b5b1968 SB |
808 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1); |
809 | if (ret) | |
810 | return ret; | |
e92a4047 | 811 | |
1b5b1968 | 812 | return selector; |
e92a4047 SB |
813 | } |
814 | ||
815 | static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev, | |
1b5b1968 | 816 | unsigned selector) |
e92a4047 SB |
817 | { |
818 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
819 | int ret; | |
820 | u8 range_sel, voltage_sel; | |
821 | ||
1b5b1968 | 822 | ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); |
e92a4047 SB |
823 | if (ret) |
824 | return ret; | |
825 | ||
826 | /* | |
827 | * Calculate VSET based on range | |
828 | * In case of range 0: voltage_sel is a 7 bit value, can be written | |
829 | * witout any modification. | |
830 | * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to | |
831 | * [011]. | |
832 | */ | |
833 | if (range_sel == 1) | |
834 | voltage_sel |= ULT_SMPS_RANGE_SPLIT; | |
835 | ||
0f94bffa | 836 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET, |
1b5b1968 | 837 | voltage_sel, 0xff); |
e92a4047 SB |
838 | } |
839 | ||
840 | static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev) | |
841 | { | |
842 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
843 | const struct spmi_voltage_range *range; | |
844 | u8 voltage_sel; | |
845 | ||
846 | spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); | |
847 | ||
848 | range = spmi_regulator_find_range(vreg); | |
849 | if (!range) | |
1b5b1968 | 850 | return -EINVAL; |
e92a4047 SB |
851 | |
852 | if (range->range_sel == 1) | |
853 | voltage_sel &= ~ULT_SMPS_RANGE_SPLIT; | |
854 | ||
1b5b1968 | 855 | return spmi_hw_selector_to_sw(vreg, voltage_sel, range); |
e92a4047 SB |
856 | } |
857 | ||
858 | static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, | |
859 | unsigned selector) | |
860 | { | |
861 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
862 | int uV = 0; | |
863 | int i; | |
864 | ||
865 | if (selector >= vreg->set_points->n_voltages) | |
866 | return 0; | |
867 | ||
868 | for (i = 0; i < vreg->set_points->count; i++) { | |
9b2dfee3 | 869 | if (selector < vreg->set_points->range[i].n_voltages) { |
e92a4047 SB |
870 | uV = selector * vreg->set_points->range[i].step_uV |
871 | + vreg->set_points->range[i].set_point_min_uV; | |
872 | break; | |
9b2dfee3 | 873 | } |
e92a4047 SB |
874 | |
875 | selector -= vreg->set_points->range[i].n_voltages; | |
876 | } | |
877 | ||
878 | return uV; | |
879 | } | |
880 | ||
881 | static int | |
882 | spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable) | |
883 | { | |
884 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
885 | u8 mask = SPMI_COMMON_MODE_BYPASS_MASK; | |
886 | u8 val = 0; | |
887 | ||
888 | if (enable) | |
889 | val = mask; | |
890 | ||
891 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); | |
892 | } | |
893 | ||
894 | static int | |
895 | spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable) | |
896 | { | |
897 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
898 | u8 val; | |
899 | int ret; | |
900 | ||
901 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1); | |
902 | *enable = val & SPMI_COMMON_MODE_BYPASS_MASK; | |
903 | ||
904 | return ret; | |
905 | } | |
906 | ||
907 | static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev) | |
908 | { | |
909 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
910 | u8 reg; | |
911 | ||
912 | spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); | |
913 | ||
914 | if (reg & SPMI_COMMON_MODE_HPM_MASK) | |
915 | return REGULATOR_MODE_NORMAL; | |
916 | ||
e2adfacd SB |
917 | if (reg & SPMI_COMMON_MODE_AUTO_MASK) |
918 | return REGULATOR_MODE_FAST; | |
919 | ||
e92a4047 SB |
920 | return REGULATOR_MODE_IDLE; |
921 | } | |
922 | ||
923 | static int | |
924 | spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) | |
925 | { | |
926 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
e2adfacd | 927 | u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; |
e92a4047 SB |
928 | u8 val = 0; |
929 | ||
930 | if (mode == REGULATOR_MODE_NORMAL) | |
e2adfacd SB |
931 | val = SPMI_COMMON_MODE_HPM_MASK; |
932 | else if (mode == REGULATOR_MODE_FAST) | |
933 | val = SPMI_COMMON_MODE_AUTO_MASK; | |
e92a4047 SB |
934 | |
935 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); | |
936 | } | |
937 | ||
938 | static int | |
939 | spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) | |
940 | { | |
941 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
942 | unsigned int mode; | |
943 | ||
944 | if (load_uA >= vreg->hpm_min_load) | |
945 | mode = REGULATOR_MODE_NORMAL; | |
946 | else | |
947 | mode = REGULATOR_MODE_IDLE; | |
948 | ||
949 | return spmi_regulator_common_set_mode(rdev, mode); | |
950 | } | |
951 | ||
952 | static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev) | |
953 | { | |
954 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
955 | unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; | |
956 | ||
957 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN, | |
958 | mask, mask); | |
959 | } | |
960 | ||
961 | static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev) | |
962 | { | |
963 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
964 | unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK; | |
965 | ||
966 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START, | |
967 | mask, mask); | |
968 | } | |
969 | ||
970 | static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA) | |
971 | { | |
972 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
973 | enum spmi_regulator_logical_type type = vreg->logical_type; | |
974 | unsigned int current_reg; | |
975 | u8 reg; | |
976 | u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK | | |
977 | SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; | |
978 | int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500; | |
979 | ||
980 | if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST) | |
981 | current_reg = SPMI_BOOST_REG_CURRENT_LIMIT; | |
982 | else | |
983 | current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT; | |
984 | ||
985 | if (ilim_uA > max || ilim_uA <= 0) | |
986 | return -EINVAL; | |
987 | ||
988 | reg = (ilim_uA - 1) / 500; | |
989 | reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; | |
990 | ||
991 | return spmi_vreg_update_bits(vreg, current_reg, reg, mask); | |
992 | } | |
993 | ||
994 | static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg) | |
995 | { | |
996 | int ret; | |
997 | ||
998 | ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, | |
999 | SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK); | |
1000 | ||
1001 | vreg->vs_enable_time = ktime_get(); | |
1002 | ||
1003 | ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, | |
1004 | SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK); | |
1005 | ||
1006 | return ret; | |
1007 | } | |
1008 | ||
1009 | static void spmi_regulator_vs_ocp_work(struct work_struct *work) | |
1010 | { | |
1011 | struct delayed_work *dwork = to_delayed_work(work); | |
1012 | struct spmi_regulator *vreg | |
1013 | = container_of(dwork, struct spmi_regulator, ocp_work); | |
1014 | ||
1015 | spmi_regulator_vs_clear_ocp(vreg); | |
1016 | } | |
1017 | ||
1018 | static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data) | |
1019 | { | |
1020 | struct spmi_regulator *vreg = data; | |
1021 | ktime_t ocp_irq_time; | |
1022 | s64 ocp_trigger_delay_us; | |
1023 | ||
1024 | ocp_irq_time = ktime_get(); | |
1025 | ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time, | |
1026 | vreg->vs_enable_time); | |
1027 | ||
1028 | /* | |
1029 | * Reset the OCP count if there is a large delay between switch enable | |
1030 | * and when OCP triggers. This is indicative of a hotplug event as | |
1031 | * opposed to a fault. | |
1032 | */ | |
1033 | if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US) | |
1034 | vreg->ocp_count = 0; | |
1035 | ||
1036 | /* Wait for switch output to settle back to 0 V after OCP triggered. */ | |
1037 | udelay(SPMI_VS_OCP_FALL_DELAY_US); | |
1038 | ||
1039 | vreg->ocp_count++; | |
1040 | ||
1041 | if (vreg->ocp_count == 1) { | |
1042 | /* Immediately clear the over current condition. */ | |
1043 | spmi_regulator_vs_clear_ocp(vreg); | |
1044 | } else if (vreg->ocp_count <= vreg->ocp_max_retries) { | |
1045 | /* Schedule the over current clear task to run later. */ | |
1046 | schedule_delayed_work(&vreg->ocp_work, | |
1047 | msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1); | |
1048 | } else { | |
1049 | dev_err(vreg->dev, | |
1050 | "OCP triggered %d times; no further retries\n", | |
1051 | vreg->ocp_count); | |
1052 | } | |
1053 | ||
1054 | return IRQ_HANDLED; | |
1055 | } | |
1056 | ||
0caecaa8 IL |
1057 | #define SAW3_VCTL_DATA_MASK 0xFF |
1058 | #define SAW3_VCTL_CLEAR_MASK 0x700FF | |
1059 | #define SAW3_AVS_CTL_EN_MASK 0x1 | |
1060 | #define SAW3_AVS_CTL_TGGL_MASK 0x8000000 | |
1061 | #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00 | |
1062 | ||
1063 | static struct regmap *saw_regmap = NULL; | |
1064 | ||
1065 | static void spmi_saw_set_vdd(void *data) | |
1066 | { | |
1067 | u32 vctl, data3, avs_ctl, pmic_sts; | |
1068 | bool avs_enabled = false; | |
1069 | unsigned long timeout; | |
1070 | u8 voltage_sel = *(u8 *)data; | |
1071 | ||
1072 | regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl); | |
1073 | regmap_read(saw_regmap, SAW3_VCTL, &vctl); | |
1074 | regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3); | |
1075 | ||
1076 | /* select the band */ | |
1077 | vctl &= ~SAW3_VCTL_CLEAR_MASK; | |
1078 | vctl |= (u32)voltage_sel; | |
1079 | ||
1080 | data3 &= ~SAW3_VCTL_CLEAR_MASK; | |
1081 | data3 |= (u32)voltage_sel; | |
1082 | ||
1083 | /* If AVS is enabled, switch it off during the voltage change */ | |
1084 | avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl; | |
1085 | if (avs_enabled) { | |
1086 | avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK; | |
1087 | regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); | |
1088 | } | |
1089 | ||
1090 | regmap_write(saw_regmap, SAW3_RST, 1); | |
1091 | regmap_write(saw_regmap, SAW3_VCTL, vctl); | |
1092 | regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3); | |
1093 | ||
1094 | timeout = jiffies + usecs_to_jiffies(100); | |
1095 | do { | |
1096 | regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts); | |
1097 | pmic_sts &= SAW3_VCTL_DATA_MASK; | |
1098 | if (pmic_sts == (u32)voltage_sel) | |
1099 | break; | |
1100 | ||
1101 | cpu_relax(); | |
1102 | ||
1103 | } while (time_before(jiffies, timeout)); | |
1104 | ||
1105 | /* After successful voltage change, switch the AVS back on */ | |
1106 | if (avs_enabled) { | |
1107 | pmic_sts &= 0x3f; | |
1108 | avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK; | |
1109 | avs_ctl |= ((pmic_sts - 4) << 10); | |
1110 | avs_ctl |= (pmic_sts << 17); | |
1111 | avs_ctl |= SAW3_AVS_CTL_TGGL_MASK; | |
1112 | regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | static int | |
1117 | spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector) | |
1118 | { | |
1119 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1120 | int ret; | |
1121 | u8 range_sel, voltage_sel; | |
1122 | ||
1123 | ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); | |
1124 | if (ret) | |
1125 | return ret; | |
1126 | ||
1127 | if (0 != range_sel) { | |
1128 | dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \ | |
1129 | range_sel, voltage_sel); | |
1130 | return -EINVAL; | |
1131 | } | |
1132 | ||
1133 | /* Always do the SAW register writes on the first CPU */ | |
1134 | return smp_call_function_single(0, spmi_saw_set_vdd, \ | |
1135 | &voltage_sel, true); | |
1136 | } | |
1137 | ||
1138 | static struct regulator_ops spmi_saw_ops = {}; | |
1139 | ||
e92a4047 | 1140 | static struct regulator_ops spmi_smps_ops = { |
9d485332 AL |
1141 | .enable = regulator_enable_regmap, |
1142 | .disable = regulator_disable_regmap, | |
1143 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1144 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
2cf7b99c | 1145 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 SB |
1146 | .get_voltage_sel = spmi_regulator_common_get_voltage, |
1147 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1148 | .list_voltage = spmi_regulator_common_list_voltage, |
1149 | .set_mode = spmi_regulator_common_set_mode, | |
1150 | .get_mode = spmi_regulator_common_get_mode, | |
1151 | .set_load = spmi_regulator_common_set_load, | |
1152 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1153 | }; | |
1154 | ||
1155 | static struct regulator_ops spmi_ldo_ops = { | |
9d485332 AL |
1156 | .enable = regulator_enable_regmap, |
1157 | .disable = regulator_disable_regmap, | |
1158 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1159 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
1160 | .get_voltage_sel = spmi_regulator_common_get_voltage, | |
1161 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1162 | .list_voltage = spmi_regulator_common_list_voltage, |
1163 | .set_mode = spmi_regulator_common_set_mode, | |
1164 | .get_mode = spmi_regulator_common_get_mode, | |
1165 | .set_load = spmi_regulator_common_set_load, | |
1166 | .set_bypass = spmi_regulator_common_set_bypass, | |
1167 | .get_bypass = spmi_regulator_common_get_bypass, | |
1168 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1169 | .set_soft_start = spmi_regulator_common_set_soft_start, | |
1170 | }; | |
1171 | ||
1172 | static struct regulator_ops spmi_ln_ldo_ops = { | |
9d485332 AL |
1173 | .enable = regulator_enable_regmap, |
1174 | .disable = regulator_disable_regmap, | |
1175 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1176 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
1177 | .get_voltage_sel = spmi_regulator_common_get_voltage, | |
1178 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1179 | .list_voltage = spmi_regulator_common_list_voltage, |
1180 | .set_bypass = spmi_regulator_common_set_bypass, | |
1181 | .get_bypass = spmi_regulator_common_get_bypass, | |
1182 | }; | |
1183 | ||
1184 | static struct regulator_ops spmi_vs_ops = { | |
1185 | .enable = spmi_regulator_vs_enable, | |
9d485332 AL |
1186 | .disable = regulator_disable_regmap, |
1187 | .is_enabled = regulator_is_enabled_regmap, | |
e92a4047 SB |
1188 | .set_pull_down = spmi_regulator_common_set_pull_down, |
1189 | .set_soft_start = spmi_regulator_common_set_soft_start, | |
e2adfacd | 1190 | .set_over_current_protection = spmi_regulator_vs_ocp, |
919163f6 SB |
1191 | .set_mode = spmi_regulator_common_set_mode, |
1192 | .get_mode = spmi_regulator_common_get_mode, | |
e92a4047 SB |
1193 | }; |
1194 | ||
1195 | static struct regulator_ops spmi_boost_ops = { | |
9d485332 AL |
1196 | .enable = regulator_enable_regmap, |
1197 | .disable = regulator_disable_regmap, | |
1198 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1199 | .set_voltage_sel = spmi_regulator_single_range_set_voltage, |
1200 | .get_voltage_sel = spmi_regulator_single_range_get_voltage, | |
1201 | .map_voltage = spmi_regulator_single_map_voltage, | |
e92a4047 SB |
1202 | .list_voltage = spmi_regulator_common_list_voltage, |
1203 | .set_input_current_limit = spmi_regulator_set_ilim, | |
1204 | }; | |
1205 | ||
1206 | static struct regulator_ops spmi_ftsmps_ops = { | |
9d485332 AL |
1207 | .enable = regulator_enable_regmap, |
1208 | .disable = regulator_disable_regmap, | |
1209 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1210 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
e92a4047 | 1211 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 SB |
1212 | .get_voltage_sel = spmi_regulator_common_get_voltage, |
1213 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1214 | .list_voltage = spmi_regulator_common_list_voltage, |
1215 | .set_mode = spmi_regulator_common_set_mode, | |
1216 | .get_mode = spmi_regulator_common_get_mode, | |
1217 | .set_load = spmi_regulator_common_set_load, | |
1218 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1219 | }; | |
1220 | ||
1221 | static struct regulator_ops spmi_ult_lo_smps_ops = { | |
9d485332 AL |
1222 | .enable = regulator_enable_regmap, |
1223 | .disable = regulator_disable_regmap, | |
1224 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1225 | .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage, |
2cf7b99c | 1226 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 | 1227 | .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage, |
e92a4047 SB |
1228 | .list_voltage = spmi_regulator_common_list_voltage, |
1229 | .set_mode = spmi_regulator_common_set_mode, | |
1230 | .get_mode = spmi_regulator_common_get_mode, | |
1231 | .set_load = spmi_regulator_common_set_load, | |
1232 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1233 | }; | |
1234 | ||
1235 | static struct regulator_ops spmi_ult_ho_smps_ops = { | |
9d485332 AL |
1236 | .enable = regulator_enable_regmap, |
1237 | .disable = regulator_disable_regmap, | |
1238 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1239 | .set_voltage_sel = spmi_regulator_single_range_set_voltage, |
2cf7b99c | 1240 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 SB |
1241 | .get_voltage_sel = spmi_regulator_single_range_get_voltage, |
1242 | .map_voltage = spmi_regulator_single_map_voltage, | |
e92a4047 SB |
1243 | .list_voltage = spmi_regulator_common_list_voltage, |
1244 | .set_mode = spmi_regulator_common_set_mode, | |
1245 | .get_mode = spmi_regulator_common_get_mode, | |
1246 | .set_load = spmi_regulator_common_set_load, | |
1247 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1248 | }; | |
1249 | ||
1250 | static struct regulator_ops spmi_ult_ldo_ops = { | |
9d485332 AL |
1251 | .enable = regulator_enable_regmap, |
1252 | .disable = regulator_disable_regmap, | |
1253 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1254 | .set_voltage_sel = spmi_regulator_single_range_set_voltage, |
1255 | .get_voltage_sel = spmi_regulator_single_range_get_voltage, | |
1256 | .map_voltage = spmi_regulator_single_map_voltage, | |
e92a4047 SB |
1257 | .list_voltage = spmi_regulator_common_list_voltage, |
1258 | .set_mode = spmi_regulator_common_set_mode, | |
1259 | .get_mode = spmi_regulator_common_get_mode, | |
1260 | .set_load = spmi_regulator_common_set_load, | |
1261 | .set_bypass = spmi_regulator_common_set_bypass, | |
1262 | .get_bypass = spmi_regulator_common_get_bypass, | |
1263 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1264 | .set_soft_start = spmi_regulator_common_set_soft_start, | |
1265 | }; | |
1266 | ||
1267 | /* Maximum possible digital major revision value */ | |
1268 | #define INF 0xFF | |
1269 | ||
1270 | static const struct spmi_regulator_mapping supported_regulators[] = { | |
1271 | /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ | |
1272 | SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), | |
1273 | SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), | |
1274 | SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), | |
1275 | SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), | |
1276 | SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000), | |
1277 | SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000), | |
1278 | SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000), | |
1279 | SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000), | |
1280 | SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000), | |
1281 | SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000), | |
1282 | SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000), | |
1283 | SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000), | |
1284 | SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000), | |
1285 | SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000), | |
1286 | SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000), | |
1287 | SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0), | |
1288 | SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000), | |
1289 | SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000), | |
1290 | SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), | |
1291 | SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), | |
1292 | SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), | |
1293 | SPMI_VREG_VS(LV100, 0, INF), | |
1294 | SPMI_VREG_VS(LV300, 0, INF), | |
1295 | SPMI_VREG_VS(MV300, 0, INF), | |
1296 | SPMI_VREG_VS(MV500, 0, INF), | |
1297 | SPMI_VREG_VS(HDMI, 0, INF), | |
1298 | SPMI_VREG_VS(OTG, 0, INF), | |
1299 | SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0), | |
1300 | SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000), | |
1301 | SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000), | |
1302 | SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0), | |
1303 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps, | |
1304 | ult_lo_smps, 100000), | |
1305 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps, | |
1306 | ult_lo_smps, 100000), | |
1307 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps, | |
1308 | ult_lo_smps, 100000), | |
1309 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps, | |
1310 | ult_ho_smps, 100000), | |
1311 | SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
1312 | SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
1313 | SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
1314 | SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
1315 | SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
1316 | SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
1317 | SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
1318 | SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
1319 | SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
1320 | SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), | |
1321 | }; | |
1322 | ||
1323 | static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) | |
1324 | { | |
1325 | unsigned int n; | |
1326 | struct spmi_voltage_range *range = points->range; | |
1327 | ||
1328 | for (; range < points->range + points->count; range++) { | |
1329 | n = 0; | |
1330 | if (range->set_point_max_uV) { | |
1331 | n = range->set_point_max_uV - range->set_point_min_uV; | |
419d06a1 | 1332 | n = (n / range->step_uV) + 1; |
e92a4047 SB |
1333 | } |
1334 | range->n_voltages = n; | |
1335 | points->n_voltages += n; | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) | |
1340 | { | |
1341 | const struct spmi_regulator_mapping *mapping; | |
1342 | int ret, i; | |
1343 | u32 dig_major_rev; | |
1344 | u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1]; | |
1345 | u8 type, subtype; | |
1346 | ||
1347 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version, | |
1348 | ARRAY_SIZE(version)); | |
1349 | if (ret) { | |
6ee5c044 | 1350 | dev_dbg(vreg->dev, "could not read version registers\n"); |
e92a4047 SB |
1351 | return ret; |
1352 | } | |
1353 | dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV | |
1354 | - SPMI_COMMON_REG_DIG_MAJOR_REV]; | |
0caecaa8 | 1355 | |
e92a4047 SB |
1356 | if (!force_type) { |
1357 | type = version[SPMI_COMMON_REG_TYPE - | |
1358 | SPMI_COMMON_REG_DIG_MAJOR_REV]; | |
1359 | subtype = version[SPMI_COMMON_REG_SUBTYPE - | |
1360 | SPMI_COMMON_REG_DIG_MAJOR_REV]; | |
1361 | } else { | |
1362 | type = force_type >> 8; | |
1363 | subtype = force_type; | |
1364 | } | |
1365 | ||
1366 | for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { | |
1367 | mapping = &supported_regulators[i]; | |
1368 | if (mapping->type == type && mapping->subtype == subtype | |
1369 | && mapping->revision_min <= dig_major_rev | |
1370 | && mapping->revision_max >= dig_major_rev) | |
1371 | goto found; | |
1372 | } | |
1373 | ||
1374 | dev_err(vreg->dev, | |
1375 | "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", | |
1376 | vreg->desc.name, type, subtype, dig_major_rev); | |
1377 | ||
1378 | return -ENODEV; | |
1379 | ||
1380 | found: | |
1381 | vreg->logical_type = mapping->logical_type; | |
1382 | vreg->set_points = mapping->set_points; | |
1383 | vreg->hpm_min_load = mapping->hpm_min_load; | |
1384 | vreg->desc.ops = mapping->ops; | |
1385 | ||
1386 | if (mapping->set_points) { | |
1387 | if (!mapping->set_points->n_voltages) | |
1388 | spmi_calculate_num_voltages(mapping->set_points); | |
1389 | vreg->desc.n_voltages = mapping->set_points->n_voltages; | |
1390 | } | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
2cf7b99c | 1395 | static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) |
e92a4047 SB |
1396 | { |
1397 | int ret; | |
1398 | u8 reg = 0; | |
2cf7b99c | 1399 | int step, delay, slew_rate, step_delay; |
e92a4047 SB |
1400 | const struct spmi_voltage_range *range; |
1401 | ||
1402 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); | |
1403 | if (ret) { | |
1404 | dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); | |
1405 | return ret; | |
1406 | } | |
1407 | ||
1408 | range = spmi_regulator_find_range(vreg); | |
1409 | if (!range) | |
1410 | return -EINVAL; | |
1411 | ||
2cf7b99c SB |
1412 | switch (vreg->logical_type) { |
1413 | case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: | |
1414 | step_delay = SPMI_FTSMPS_STEP_DELAY; | |
1415 | break; | |
1416 | default: | |
1417 | step_delay = SPMI_DEFAULT_STEP_DELAY; | |
1418 | break; | |
1419 | } | |
1420 | ||
e92a4047 SB |
1421 | step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK; |
1422 | step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT; | |
1423 | ||
1424 | delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK; | |
1425 | delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT; | |
1426 | ||
1427 | /* slew_rate has units of uV/us */ | |
1428 | slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step); | |
2cf7b99c | 1429 | slew_rate /= 1000 * (step_delay << delay); |
e92a4047 SB |
1430 | slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM; |
1431 | slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN; | |
1432 | ||
1433 | /* Ensure that the slew rate is greater than 0 */ | |
1434 | vreg->slew_rate = max(slew_rate, 1); | |
1435 | ||
1436 | return ret; | |
1437 | } | |
1438 | ||
e2adfacd SB |
1439 | static int spmi_regulator_init_registers(struct spmi_regulator *vreg, |
1440 | const struct spmi_regulator_init_data *data) | |
1441 | { | |
1442 | int ret; | |
1443 | enum spmi_regulator_logical_type type; | |
1444 | u8 ctrl_reg[8], reg, mask; | |
1445 | ||
1446 | type = vreg->logical_type; | |
1447 | ||
1448 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); | |
1449 | if (ret) | |
1450 | return ret; | |
1451 | ||
1452 | /* Set up enable pin control. */ | |
1453 | if ((type == SPMI_REGULATOR_LOGICAL_TYPE_SMPS | |
1454 | || type == SPMI_REGULATOR_LOGICAL_TYPE_LDO | |
1455 | || type == SPMI_REGULATOR_LOGICAL_TYPE_VS) | |
1456 | && !(data->pin_ctrl_enable | |
1457 | & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) { | |
1458 | ctrl_reg[SPMI_COMMON_IDX_ENABLE] &= | |
1459 | ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; | |
1460 | ctrl_reg[SPMI_COMMON_IDX_ENABLE] |= | |
1461 | data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; | |
1462 | } | |
1463 | ||
1464 | /* Set up mode pin control. */ | |
1465 | if ((type == SPMI_REGULATOR_LOGICAL_TYPE_SMPS | |
1466 | || type == SPMI_REGULATOR_LOGICAL_TYPE_LDO) | |
1467 | && !(data->pin_ctrl_hpm | |
1468 | & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) { | |
1469 | ctrl_reg[SPMI_COMMON_IDX_MODE] &= | |
1470 | ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK; | |
1471 | ctrl_reg[SPMI_COMMON_IDX_MODE] |= | |
1472 | data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK; | |
1473 | } | |
1474 | ||
1475 | if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS | |
1476 | && !(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) { | |
1477 | ctrl_reg[SPMI_COMMON_IDX_MODE] &= | |
1478 | ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; | |
1479 | ctrl_reg[SPMI_COMMON_IDX_MODE] |= | |
1480 | data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; | |
1481 | } | |
1482 | ||
1483 | if ((type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS | |
1484 | || type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS | |
1485 | || type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO) | |
1486 | && !(data->pin_ctrl_hpm | |
1487 | & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) { | |
1488 | ctrl_reg[SPMI_COMMON_IDX_MODE] &= | |
1489 | ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; | |
1490 | ctrl_reg[SPMI_COMMON_IDX_MODE] |= | |
1491 | data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; | |
1492 | } | |
1493 | ||
1494 | /* Write back any control register values that were modified. */ | |
1495 | ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); | |
1496 | if (ret) | |
1497 | return ret; | |
1498 | ||
1499 | /* Set soft start strength and over current protection for VS. */ | |
1500 | if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) { | |
1501 | if (data->vs_soft_start_strength | |
1502 | != SPMI_VS_SOFT_START_STR_HW_DEFAULT) { | |
1503 | reg = data->vs_soft_start_strength | |
1504 | & SPMI_VS_SOFT_START_SEL_MASK; | |
1505 | mask = SPMI_VS_SOFT_START_SEL_MASK; | |
1506 | return spmi_vreg_update_bits(vreg, | |
1507 | SPMI_VS_REG_SOFT_START, | |
1508 | reg, mask); | |
1509 | } | |
1510 | } | |
1511 | ||
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg, | |
1516 | struct device_node *node, struct spmi_regulator_init_data *data) | |
1517 | { | |
1518 | /* | |
1519 | * Initialize configuration parameters to use hardware default in case | |
1520 | * no value is specified via device tree. | |
1521 | */ | |
1522 | data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT; | |
1523 | data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT; | |
1524 | data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT; | |
1525 | ||
1526 | /* These bindings are optional, so it is okay if they aren't found. */ | |
1527 | of_property_read_u32(node, "qcom,ocp-max-retries", | |
1528 | &vreg->ocp_max_retries); | |
1529 | of_property_read_u32(node, "qcom,ocp-retry-delay", | |
1530 | &vreg->ocp_retry_delay_ms); | |
1531 | of_property_read_u32(node, "qcom,pin-ctrl-enable", | |
1532 | &data->pin_ctrl_enable); | |
1533 | of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm); | |
1534 | of_property_read_u32(node, "qcom,vs-soft-start-strength", | |
1535 | &data->vs_soft_start_strength); | |
1536 | } | |
1537 | ||
e92a4047 SB |
1538 | static unsigned int spmi_regulator_of_map_mode(unsigned int mode) |
1539 | { | |
e2adfacd | 1540 | if (mode == 1) |
e92a4047 | 1541 | return REGULATOR_MODE_NORMAL; |
e2adfacd SB |
1542 | if (mode == 2) |
1543 | return REGULATOR_MODE_FAST; | |
e92a4047 SB |
1544 | |
1545 | return REGULATOR_MODE_IDLE; | |
1546 | } | |
1547 | ||
1548 | static int spmi_regulator_of_parse(struct device_node *node, | |
1549 | const struct regulator_desc *desc, | |
1550 | struct regulator_config *config) | |
1551 | { | |
e2adfacd | 1552 | struct spmi_regulator_init_data data = { }; |
e92a4047 SB |
1553 | struct spmi_regulator *vreg = config->driver_data; |
1554 | struct device *dev = config->dev; | |
1555 | int ret; | |
1556 | ||
e2adfacd SB |
1557 | spmi_regulator_get_dt_config(vreg, node, &data); |
1558 | ||
1559 | if (!vreg->ocp_max_retries) | |
1560 | vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES; | |
1561 | if (!vreg->ocp_retry_delay_ms) | |
1562 | vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS; | |
1563 | ||
1564 | ret = spmi_regulator_init_registers(vreg, &data); | |
1565 | if (ret) { | |
1566 | dev_err(dev, "common initialization failed, ret=%d\n", ret); | |
1567 | return ret; | |
1568 | } | |
e92a4047 | 1569 | |
2cf7b99c SB |
1570 | switch (vreg->logical_type) { |
1571 | case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: | |
1572 | case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: | |
1573 | case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: | |
1574 | case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: | |
1575 | ret = spmi_regulator_init_slew_rate(vreg); | |
e92a4047 SB |
1576 | if (ret) |
1577 | return ret; | |
2cf7b99c SB |
1578 | default: |
1579 | break; | |
e92a4047 SB |
1580 | } |
1581 | ||
1582 | if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS) | |
1583 | vreg->ocp_irq = 0; | |
1584 | ||
1585 | if (vreg->ocp_irq) { | |
1586 | ret = devm_request_irq(dev, vreg->ocp_irq, | |
1587 | spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp", | |
1588 | vreg); | |
1589 | if (ret < 0) { | |
1590 | dev_err(dev, "failed to request irq %d, ret=%d\n", | |
1591 | vreg->ocp_irq, ret); | |
1592 | return ret; | |
1593 | } | |
1594 | ||
1595 | INIT_DELAYED_WORK(&vreg->ocp_work, spmi_regulator_vs_ocp_work); | |
1596 | } | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | static const struct spmi_regulator_data pm8941_regulators[] = { | |
1602 | { "s1", 0x1400, "vdd_s1", }, | |
1603 | { "s2", 0x1700, "vdd_s2", }, | |
1604 | { "s3", 0x1a00, "vdd_s3", }, | |
c333dfe8 | 1605 | { "s4", 0xa000, }, |
e92a4047 SB |
1606 | { "l1", 0x4000, "vdd_l1_l3", }, |
1607 | { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, | |
1608 | { "l3", 0x4200, "vdd_l1_l3", }, | |
1609 | { "l4", 0x4300, "vdd_l4_l11", }, | |
1610 | { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, | |
1611 | { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, | |
1612 | { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, | |
1613 | { "l8", 0x4700, "vdd_l8_l16_l18_19", }, | |
1614 | { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, | |
1615 | { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, | |
1616 | { "l11", 0x4a00, "vdd_l4_l11", }, | |
1617 | { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, | |
1618 | { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, | |
1619 | { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, | |
1620 | { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, | |
1621 | { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, | |
1622 | { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, | |
1623 | { "l18", 0x5100, "vdd_l8_l16_l18_19", }, | |
1624 | { "l19", 0x5200, "vdd_l8_l16_l18_19", }, | |
1625 | { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, | |
1626 | { "l21", 0x5400, "vdd_l21", }, | |
1627 | { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, | |
1628 | { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, | |
1629 | { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, | |
1630 | { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, | |
1631 | { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, | |
1632 | { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, | |
93bfe79b SB |
1633 | { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, |
1634 | { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, | |
e92a4047 SB |
1635 | { } |
1636 | }; | |
1637 | ||
1638 | static const struct spmi_regulator_data pm8841_regulators[] = { | |
1639 | { "s1", 0x1400, "vdd_s1", }, | |
1640 | { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 }, | |
1641 | { "s3", 0x1a00, "vdd_s3", }, | |
1642 | { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 }, | |
1643 | { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 }, | |
1644 | { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 }, | |
1645 | { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 }, | |
1646 | { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 }, | |
1647 | { } | |
1648 | }; | |
1649 | ||
1650 | static const struct spmi_regulator_data pm8916_regulators[] = { | |
1651 | { "s1", 0x1400, "vdd_s1", }, | |
1652 | { "s2", 0x1700, "vdd_s2", }, | |
1653 | { "s3", 0x1a00, "vdd_s3", }, | |
1654 | { "s4", 0x1d00, "vdd_s4", }, | |
1655 | { "l1", 0x4000, "vdd_l1_l3", }, | |
1656 | { "l2", 0x4100, "vdd_l2", }, | |
1657 | { "l3", 0x4200, "vdd_l1_l3", }, | |
1658 | { "l4", 0x4300, "vdd_l4_l5_l6", }, | |
1659 | { "l5", 0x4400, "vdd_l4_l5_l6", }, | |
1660 | { "l6", 0x4500, "vdd_l4_l5_l6", }, | |
1661 | { "l7", 0x4600, "vdd_l7", }, | |
1662 | { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", }, | |
1663 | { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", }, | |
1664 | { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", }, | |
1665 | { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", }, | |
1666 | { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", }, | |
1667 | { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", }, | |
1668 | { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", }, | |
1669 | { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", }, | |
1670 | { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", }, | |
1671 | { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", }, | |
1672 | { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", }, | |
1673 | { } | |
1674 | }; | |
1675 | ||
50314e55 SB |
1676 | static const struct spmi_regulator_data pm8994_regulators[] = { |
1677 | { "s1", 0x1400, "vdd_s1", }, | |
1678 | { "s2", 0x1700, "vdd_s2", }, | |
1679 | { "s3", 0x1a00, "vdd_s3", }, | |
1680 | { "s4", 0x1d00, "vdd_s4", }, | |
1681 | { "s5", 0x2000, "vdd_s5", }, | |
1682 | { "s6", 0x2300, "vdd_s6", }, | |
1683 | { "s7", 0x2600, "vdd_s7", }, | |
1684 | { "s8", 0x2900, "vdd_s8", }, | |
1685 | { "s9", 0x2c00, "vdd_s9", }, | |
1686 | { "s10", 0x2f00, "vdd_s10", }, | |
1687 | { "s11", 0x3200, "vdd_s11", }, | |
1688 | { "s12", 0x3500, "vdd_s12", }, | |
1689 | { "l1", 0x4000, "vdd_l1", }, | |
1690 | { "l2", 0x4100, "vdd_l2_l26_l28", }, | |
1691 | { "l3", 0x4200, "vdd_l3_l11", }, | |
1692 | { "l4", 0x4300, "vdd_l4_l27_l31", }, | |
1693 | { "l5", 0x4400, "vdd_l5_l7", }, | |
1694 | { "l6", 0x4500, "vdd_l6_l12_l32", }, | |
1695 | { "l7", 0x4600, "vdd_l5_l7", }, | |
1696 | { "l8", 0x4700, "vdd_l8_l16_l30", }, | |
1697 | { "l9", 0x4800, "vdd_l9_l10_l18_l22", }, | |
1698 | { "l10", 0x4900, "vdd_l9_l10_l18_l22", }, | |
1699 | { "l11", 0x4a00, "vdd_l3_l11", }, | |
1700 | { "l12", 0x4b00, "vdd_l6_l12_l32", }, | |
1701 | { "l13", 0x4c00, "vdd_l13_l19_l23_l24", }, | |
1702 | { "l14", 0x4d00, "vdd_l14_l15", }, | |
1703 | { "l15", 0x4e00, "vdd_l14_l15", }, | |
1704 | { "l16", 0x4f00, "vdd_l8_l16_l30", }, | |
1705 | { "l17", 0x5000, "vdd_l17_l29", }, | |
1706 | { "l18", 0x5100, "vdd_l9_l10_l18_l22", }, | |
1707 | { "l19", 0x5200, "vdd_l13_l19_l23_l24", }, | |
1708 | { "l20", 0x5300, "vdd_l20_l21", }, | |
1709 | { "l21", 0x5400, "vdd_l20_l21", }, | |
1710 | { "l22", 0x5500, "vdd_l9_l10_l18_l22", }, | |
1711 | { "l23", 0x5600, "vdd_l13_l19_l23_l24", }, | |
1712 | { "l24", 0x5700, "vdd_l13_l19_l23_l24", }, | |
1713 | { "l25", 0x5800, "vdd_l25", }, | |
1714 | { "l26", 0x5900, "vdd_l2_l26_l28", }, | |
1715 | { "l27", 0x5a00, "vdd_l4_l27_l31", }, | |
1716 | { "l28", 0x5b00, "vdd_l2_l26_l28", }, | |
1717 | { "l29", 0x5c00, "vdd_l17_l29", }, | |
1718 | { "l30", 0x5d00, "vdd_l8_l16_l30", }, | |
1719 | { "l31", 0x5e00, "vdd_l4_l27_l31", }, | |
1720 | { "l32", 0x5f00, "vdd_l6_l12_l32", }, | |
1721 | { "lvs1", 0x8000, "vdd_lvs_1_2", }, | |
1722 | { "lvs2", 0x8100, "vdd_lvs_1_2", }, | |
1723 | { } | |
1724 | }; | |
1725 | ||
ca5cd8c9 RN |
1726 | static const struct spmi_regulator_data pmi8994_regulators[] = { |
1727 | { "s1", 0x1400, "vdd_s1", }, | |
1728 | { "s2", 0x1700, "vdd_s2", }, | |
1729 | { "s3", 0x1a00, "vdd_s3", }, | |
1730 | { "l1", 0x4000, "vdd_l1", }, | |
1731 | { } | |
1732 | }; | |
1733 | ||
e92a4047 SB |
1734 | static const struct of_device_id qcom_spmi_regulator_match[] = { |
1735 | { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, | |
1736 | { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, | |
1737 | { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, | |
50314e55 | 1738 | { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, |
ca5cd8c9 | 1739 | { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, |
e92a4047 SB |
1740 | { } |
1741 | }; | |
1742 | MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); | |
1743 | ||
1744 | static int qcom_spmi_regulator_probe(struct platform_device *pdev) | |
1745 | { | |
1746 | const struct spmi_regulator_data *reg; | |
1747 | const struct of_device_id *match; | |
1748 | struct regulator_config config = { }; | |
1749 | struct regulator_dev *rdev; | |
1750 | struct spmi_regulator *vreg; | |
1751 | struct regmap *regmap; | |
1752 | const char *name; | |
1753 | struct device *dev = &pdev->dev; | |
0caecaa8 IL |
1754 | struct device_node *node = pdev->dev.of_node; |
1755 | struct device_node *syscon; | |
1756 | int ret, lenp; | |
e92a4047 SB |
1757 | struct list_head *vreg_list; |
1758 | ||
1759 | vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL); | |
1760 | if (!vreg_list) | |
1761 | return -ENOMEM; | |
1762 | INIT_LIST_HEAD(vreg_list); | |
1763 | platform_set_drvdata(pdev, vreg_list); | |
1764 | ||
1765 | regmap = dev_get_regmap(dev->parent, NULL); | |
1766 | if (!regmap) | |
1767 | return -ENODEV; | |
1768 | ||
1769 | match = of_match_device(qcom_spmi_regulator_match, &pdev->dev); | |
1770 | if (!match) | |
1771 | return -ENODEV; | |
1772 | ||
0caecaa8 IL |
1773 | if (of_find_property(node, "qcom,saw-reg", &lenp)) { |
1774 | syscon = of_parse_phandle(node, "qcom,saw-reg", 0); | |
1775 | saw_regmap = syscon_node_to_regmap(syscon); | |
1776 | of_node_put(syscon); | |
1777 | if (IS_ERR(regmap)) | |
1778 | dev_err(dev, "ERROR reading SAW regmap\n"); | |
1779 | } | |
1780 | ||
e92a4047 | 1781 | for (reg = match->data; reg->name; reg++) { |
0caecaa8 IL |
1782 | |
1783 | if (saw_regmap && \ | |
1784 | of_find_property(of_find_node_by_name(node, reg->name), \ | |
1785 | "qcom,saw-slave", &lenp)) { | |
1786 | continue; | |
1787 | } | |
1788 | ||
e92a4047 SB |
1789 | vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); |
1790 | if (!vreg) | |
1791 | return -ENOMEM; | |
1792 | ||
1793 | vreg->dev = dev; | |
1794 | vreg->base = reg->base; | |
1795 | vreg->regmap = regmap; | |
e92a4047 SB |
1796 | if (reg->ocp) { |
1797 | vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); | |
1798 | if (vreg->ocp_irq < 0) { | |
1799 | ret = vreg->ocp_irq; | |
1800 | goto err; | |
1801 | } | |
1802 | } | |
e92a4047 SB |
1803 | vreg->desc.id = -1; |
1804 | vreg->desc.owner = THIS_MODULE; | |
1805 | vreg->desc.type = REGULATOR_VOLTAGE; | |
9d485332 AL |
1806 | vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE; |
1807 | vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK; | |
1808 | vreg->desc.enable_val = SPMI_COMMON_ENABLE; | |
e92a4047 SB |
1809 | vreg->desc.name = name = reg->name; |
1810 | vreg->desc.supply_name = reg->supply; | |
1811 | vreg->desc.of_match = reg->name; | |
1812 | vreg->desc.of_parse_cb = spmi_regulator_of_parse; | |
1813 | vreg->desc.of_map_mode = spmi_regulator_of_map_mode; | |
1814 | ||
1815 | ret = spmi_regulator_match(vreg, reg->force_type); | |
1816 | if (ret) | |
6ee5c044 | 1817 | continue; |
e92a4047 | 1818 | |
0caecaa8 IL |
1819 | if (saw_regmap && \ |
1820 | of_find_property(of_find_node_by_name(node, reg->name), \ | |
1821 | "qcom,saw-leader", &lenp)) { | |
1822 | spmi_saw_ops = *(vreg->desc.ops); | |
1823 | spmi_saw_ops.set_voltage_sel = \ | |
1824 | spmi_regulator_saw_set_voltage; | |
1825 | vreg->desc.ops = &spmi_saw_ops; | |
1826 | } | |
1827 | ||
e92a4047 SB |
1828 | config.dev = dev; |
1829 | config.driver_data = vreg; | |
9d485332 | 1830 | config.regmap = regmap; |
e92a4047 SB |
1831 | rdev = devm_regulator_register(dev, &vreg->desc, &config); |
1832 | if (IS_ERR(rdev)) { | |
1833 | dev_err(dev, "failed to register %s\n", name); | |
1834 | ret = PTR_ERR(rdev); | |
1835 | goto err; | |
1836 | } | |
1837 | ||
1838 | INIT_LIST_HEAD(&vreg->node); | |
1839 | list_add(&vreg->node, vreg_list); | |
1840 | } | |
1841 | ||
1842 | return 0; | |
1843 | ||
1844 | err: | |
1845 | list_for_each_entry(vreg, vreg_list, node) | |
1846 | if (vreg->ocp_irq) | |
1847 | cancel_delayed_work_sync(&vreg->ocp_work); | |
1848 | return ret; | |
1849 | } | |
1850 | ||
1851 | static int qcom_spmi_regulator_remove(struct platform_device *pdev) | |
1852 | { | |
1853 | struct spmi_regulator *vreg; | |
1854 | struct list_head *vreg_list = platform_get_drvdata(pdev); | |
1855 | ||
1856 | list_for_each_entry(vreg, vreg_list, node) | |
1857 | if (vreg->ocp_irq) | |
1858 | cancel_delayed_work_sync(&vreg->ocp_work); | |
1859 | ||
1860 | return 0; | |
1861 | } | |
1862 | ||
1863 | static struct platform_driver qcom_spmi_regulator_driver = { | |
1864 | .driver = { | |
1865 | .name = "qcom-spmi-regulator", | |
1866 | .of_match_table = qcom_spmi_regulator_match, | |
1867 | }, | |
1868 | .probe = qcom_spmi_regulator_probe, | |
1869 | .remove = qcom_spmi_regulator_remove, | |
1870 | }; | |
1871 | module_platform_driver(qcom_spmi_regulator_driver); | |
1872 | ||
1873 | MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver"); | |
1874 | MODULE_LICENSE("GPL v2"); | |
1875 | MODULE_ALIAS("platform:qcom-spmi-regulator"); |